51 CYM1851 1,024K x 32 Static RAM Module Features • High-density 32-megabit SRAM module • 32-bit Standard Footprint supports densities from 16K x 32 through 1M x 32 • High-speed SRAMs — Access time of 12 ns • Low active power — 8.36W (max.) at 12 ns • 72 pins • Available in ZIP, SIMM, or angled SIMM format Functional Description The CYM1851 is a high-performance 32-megabit static RAM module organized as 1,024K words by 32 bits. This module is constructed from eight 1,024K x 4 SRAMs in SOJ packages mounted on an epoxy laminate substrate. Four chip selects are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. The CYM1851 is designed for use with standard 72-pin SIMM sockets. The pinout is downward compatible with the 64-pin JEDEC ZIP/SIMM module family (CYM1821, CYM1831, CYM1836, and CYM1841). Thus, a single motherboard design can be used to accommodate memory depth ranging from 16K words (CYM1821) to 1,024K words (CYM1851). The CYM1851 is offered in vertical and angled SIMM configurations and both are available with either tin-lead or 10 micro-inches of gold flash on the edge contacts. Presence detect pins (PD0–PD3) are used to identify module memory density in applications where modules with alternate word depths can be interchanged. Logic Block Diagram Pin Configuration ZIP/SIMM Top View A0 –A19 OE PD0 PD1 PD2 PD3 - 20 GND OPEN GND OPEN NC PD3 PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 WE 1M x 4 SRAM 4 1M x 4 SRAM 4 I/O0 – I/O3 1M x 4 SRAM 4 I/O8 – I/O11 1M x 4 SRAM 4 I/O4– I/O7 CS1 I/O12– I/O15 CS2 1M x 4 SRAM 4 1M x 4 SRAM 4 I/O16 – I/O19 1M x 4 SRAM 4 1M x 4 SRAM 4 I/O20– I/O23 CS3 A16 GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND A19 NC CS3 I/O24 – I/O27 I/O28– I/O31 CS4 Cypress Semiconductor Corporation Document #: 38-05274 Rev. ** • 3901 North First Street • San Jose • 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 33 35 NC PD2 GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15 CS2 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 CS4 A17 OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 A18 NC 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 CA 95134 • 408-943-2600 Revised March 15, 2002 CYM1851 Selection Guide 1851-12 1851-15 1851-20 1851-25 1851-35 12 15 20 25 35 Maximum Operating Current (mA) 1520 1520 1200 1200 960 Maximum Standby Current (mA) 480 480 480 480 480 Maximum Access Time (ns) Maximum Ratings DC Voltage Applied to Outputs in High Z State.................................................–0.5V to +VCC (Above which the useful life may be impaired. For user guidelines, not tested.) DC Input Voltage ............................................–0.5V to +7.0V Storage Temperature ................................. –55°C to +125°C Operating Range Ambient Temperature with Power Applied............................................... –10°C to +85°C Range Ambient Temperature Supply Voltage to Ground Potential ............... –0.5V to +7.0V VCC Commercial 0°C to +70°C 5V ± 10% Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.3 V VIL Input LOW Voltage –0.5 0.8 V IIX Input Load Current GND < VI < VCC –16 +16 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, CSN < VIL ISB1 Automatic CS Power-Down Current[1] Max. VCC, CS > VIH, Min. Duty Cycle = 100% ISB2 Automatic CS Power-Down Current[1] Max. VCC, CS > VCC – 0.2V, VIN > VCC – 0.2V, or VIN < 0.2V +10 µA -20, -25, -35 1200 mA -12, -15 1520 mA 480 mA -20, -25, -35 80 mA -12, -15 240 mA –10 Capacitance[2] Parameter Description CINA Input Capacitance (WE, OE, A0–19) CINB Input Capacitance (CS) COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 80 pF 20 pF 20 pF Notes: 1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested on a sample basis. Document #: 38-05274 Rev. ** Page 2 of 9 CYM1851 AC Test Loads and Waveforms R1 481Ω R1 481 Ω 5V ALL INPUT PULSES 5V OUTPUT R2 255Ω 30 pF INCLUDING JIG AND SCOPE R2 255Ω 5 pF INCLUDING JIG AND SCOPE THÉVENIN OUTPUT 90% OUTPUT (a) Equivalent to: 3.0V 90% 10% GND 10% < 5 ns < 5 ns (b) EQUIVALENT 167Ω 1.73V Switching Characteristics Over the Operating Range[3] 1851-12 Parameter Description Min. 1851-15 Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACS CS LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z tLZCS CS LOW to Low Z 12 15 12 3 3 12 7 0 [4] 3 ns ns 15 ns 8 ns 0 7 [4, 5] ns 15 ns 8 3 ns ns tHZCS CS HIGH to High Z 7 8 ns tPD CS HIGH to Power-Down 12 15 ns [6] WRITE CYCLE tWC Write Cycle Time 12 15 ns tSCS CS LOW to Write End 9 10 ns tAW Address Set-Up to Write End 9 10 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 1 1 ns tPWE WE Pulse Width 10 12 ns tSD Data Set-Up to Write End 7 8 ns tHD Data Hold from Write End 1 1 ns tLZWE WE HIGH to Low Z 3 3 ns tHZWE [5] WE LOW to High Z 0 7 0 8 ns Notes: 3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested. 5. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage. 6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05274 Rev. ** Page 3 of 9 CYM1851 Switching Characteristics Over the Operating Range[3](continued) 1851-20 Parameter Description Min. Max. 1851-25 Min. Max. 1851-35 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACS CS LOW to Data Valid 20 25 35 ns tDOE OE LOW to Data Valid 12 15 18 ns tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z tLZCS CS LOW to Low Z 20 25 20 3 25 3 0 3 [4, 5] ns 35 3 0 10 [4] 35 ns 0 12 3 ns ns 15 3 ns ns tHZCS CS HIGH to High Z 10 12 15 ns tPD CS HIGH to Power-Down 20 25 35 ns WRITE CYCLE[6] tWC Write Cycle Time 20 25 35 ns tSCS CS LOW to Write End 17 20 30 ns tAW Address Set-Up to Write End 17 20 30 ns tHA Address Hold from Write End 3 3 3 ns tSA Address Set-Up to Write Start 2 2 2 ns tPWE WE Pulse Width 15 20 30 ns tSD Data Set-Up to Write End 12 15 20 ns tHD Data Hold from Write End 2 2 2 ns tLZWE WE HIGH to Low Z 3 3 3 ns tHZWE [5] WE LOW to High Z 0 12 0 12 0 15 ns Switching Waveforms Read Cycle No. 1 [7,8] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 7. WE is HIGH for read cycle. 8. Device is continuously selected, CS = VIL, and OE= VIL. Document #: 38-05274 Rev. ** Page 4 of 9 CYM1851 Switching Waveforms (continued) Read Cycle No. 2 [7,9] tRC CS tACS OE tHZOE tDOE tHZCS tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID DATA OUT tLZCS tPD tPU ICC V CC SUPPLY CURRENT 50% 50% Write Cycle No. 1 (WE Controlled) ISB [6] tWC ADDRESS tSCS CS tAW tSA tHA tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT tHD tLZWE HIGH IMPEDANCE DATA UNDEFINED Note: 9. Address valid prior to or coincident with CS transition LOW. Document #: 38-05274 Rev. ** Page 5 of 9 CYM1851 Switching Waveforms (continued) Write Cycle No. 2 (CS Controlled) [6,10] tWC ADDRESS tSCS tSA CS tAW tHA tPWE WE tSD DATA IN tHD DATA VALID tHZWE HIGH IMPEDANCE DATA OUT DATA UNDEFINED Note: 10. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Truth Table CS WE OE Inputs/Output Mode H X X High Z Deselect/Power-Down L H L Data Out Read L L X Data In Write L H H High Z Deselect Document #: 38-05274 Rev. ** Page 6 of 9 CYM1851 Ordering Information Speed (ns) 12 15 20 25 35 Ordering Code Package Type Package Type CYM1851PM-12C PM04 72-Pin Plastic SIMM Module CYM1851P8-12C PM04 72-Pin Plastic SIMM Module (gold contacts) CYM1851PN-12C PN04 72-Pin Plastic Angled SIMM Module CYM1851P6-12C PN04 72-Pin Plastic Angled SIMM Module (gold contacts) CYM1851PZ-12C PZ09 72-Pin Plastic ZIP Module CYM1851PM-15C PM04 72-Pin Plastic SIMM Module CYM1851P8-15C PM04 72-Pin Plastic SIMM Module (gold contacts) CYM1851PN-15C PN04 72-Pin Plastic Angled SIMM Module CYM1851P6-15C PN04 72-Pin Plastic Angled SIMM Module (gold contacts) CYM1851PZ-15C PZ09 72-Pin Plastic ZIP Module CYM1851PM-20C PM04 72-Pin Plastic SIMM Module CYM1851P8-20C PM04 72-Pin Plastic SIMM Module (gold contacts) CYM1851PN-20C PN04 72-Pin Plastic Angled SIMM Module CYM1851P6-20C PN04 72-Pin Plastic Angled SIMM Module (gold contacts) CYM1851PZ-20C PZ09 72-Pin Plastic ZIP Module CYM1851PM-25C PM04 72-Pin Plastic SIMM Module CYM1851P8-25C PM04 72-Pin Plastic SIMM Module (gold contacts) CYM1851PN-25C PN04 72-Pin Plastic Angled SIMM Module CYM1851P6-25C PN04 72-Pin Plastic Angled SIMM Module (gold contacts) CYM1851PZ-25C PZ09 72-Pin Plastic ZIP Module CYM1851PM-35C PM04 72-Pin Plastic SIMM Module CYM1851P8-35C PM04 72-Pin Plastic SIMM Module (gold contacts) CYM1851PN-35C PN04 72-Pin Plastic Angled SIMM Module CYM1851P6-35C PN04 72-Pin Plastic Angled SIMM Module (gold contacts) CYM1851PZ-35C PZ09 72-Pin Plastic ZIP Module Operating Range Commercial Commercial Commercial Commercial Commercial Package Diagrams 72-Pin Plastic SIMM Module PM04 Document #: 38-05274 Rev. ** Page 7 of 9 CYM1851 Package Diagrams (continued) 72-Pin Plastic Angled SIMM Module PN04 72-Pin Plastic ZIP Module PZ09 Document #: 38-05274 Rev. ** Page 8 of 9 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CYM1851 Document Title: CYM1851 1,024K x 32 Static RAM Module Document Number: 38-05274 REV. ECN NO. Issue Date Orig. of Change ** 114175 3/19/02 DSG Document #: 38-05274 Rev. ** Description of Change Change from Spec number: 38-M-00052 to 38-05274 Page 9 of 9