ISSI IS61LV12816 128K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY ® NOVEMBER 2000 FEATURES DESCRIPTION • • • • • The ISSI IS61LV12816 is a high-speed, 2,097,152-bit static RAM organized as 131,072 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns with low power consumption. High-speed access time: 8, 10, 12, and 15 ns CMOS low power operation TTL and CMOS compatible interface levels Single 3.3V ± 10% power supply Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial temperature available When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV12816 is packaged in the JEDEC standard 44-pin 400-mil SOJ, 44-pin TSOP, 44-pin LQFP, and 48-pin mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CE OE WE CONTROL CIRCUIT UB LB ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 11/30/00 1 ISSI IS61LV12816 ® PIN CONFIGURATIONS 44-Pin SOJ (K) 44-Pin TSOP (T) A4 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE A0 5 40 UB CE 6 39 LB I/O0 7 38 I/O15 I/O1 8 37 I/O14 I/O2 9 36 I/O13 I/O3 10 35 I/O12 Vcc 11 34 GND GND 12 33 Vcc I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A16 18 27 A8 A15 19 26 A9 A14 20 25 A10 A13 21 24 A11 A12 22 23 NC A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 48-Pin mini BGA (B) 2 3 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 44-Pin LQFP (LQ) 4 5 6 OE A0 A1 A2 N/C B I/O8 UB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 NC A7 I/O3 Vcc E Vcc I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 44 43 42 41 40 39 38 37 36 35 345 33 1 32 2 31 3 30 4 29 5 TOP VIEW 28 6 27 7 26 8 25 9 24 10 23 11 12 13 14 15 16 17 18 19 20 21 22 I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC WE A0 A1 A2 A3 A4 NC A5 A6 A7 A8 A LB A16 A15 A14 A13 A12 A11 A10 A9 OE UB LB 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 11/30/00 ISSI IS61LV12816 ® OPERATING RANGE PIN DESCRIPTIONS Range Ambient Temperature Commercial 0°C to + 70°C Industrial –40°C to + 85°C A0-A16 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection Vcc Power GND Ground VCC 3.3V ± 10% 3.3V ± 10% ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC VTERM TSTG TBIAS PT IOUT Parameter Power Supply Voltage Relative to GND Terminal Voltage with Respect to GND Storage Temperature Temperature Under Bias: Com. Ind. Power Dissipation DC Output Current Value –0.5 to 5.0 –0.5 to Vcc + 0.5 –65 to + 150 –10 to + 85 –45 to + 90 2.0 ±20 Unit V V °C °C °C W mA Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage(1) 2 VCC + 0.3 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND - VIN - VCC –1 1 µA ILO Output Leakage GND - VOUT - VCC, Outputs Disabled –1 1 µA Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns). VIH (max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width - 2.0 ns). Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 11/30/00 3 ISSI IS61LV12816 ® TRUTH TABLE Mode Not Selected Output Disabled Read Write WE CE OE LB UB X H X H H H L L L H L L L L L L L L X H X L L L X X X X X H L H L L H L X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN Vcc Current High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN ISB1, ISB2 ICC ICC ICC POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol -8 ns Min. Max. -10 ns Min. Max. -12 ns Min. Max. -15 ns Min. Max. Parameter Test Conditions Unit ICC Vcc Operating Supply Current VCC = Max., CE = VIL IOUT = 0 mA, f = Max. Com. Ind. — — 150 160 — — 125 135 — — 110 120 — — 90 100 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL CE • VIH, f = max Com. Ind. — — 50 60 — — 40 50 — — 35 45 — — 30 40 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., CE - VCC – 0.2V, VIN > VCC – 0.2V, or VIN - 0.2V, f = 0 Com. Ind. — — 10 20 — — 10 20 — — 10 20 — — 10 20 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 11/30/00 ISSI IS61LV12816 ® CAPACITANCE(1) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter -8 ns Min. Max -10 ns Min. Max. -12 ns Min. Max. -15 ns Min. Max. Unit tRC Read Cycle Time 8 — 10 — 12 — 15 — ns tAA Address Access Time — 8 — 10 — 12 — 15 ns tOHA Output Hold Time 3 — 3 — 3 — 3 — ns tACE CE Access Time 8 — — 10 — 12 — 15 ns OE Access Time — 3 — 4 — 5 — 6 ns (2) OE to High-Z Output — 3 — 4 — 5 0 6 ns (2) OE to Low-Z Output 0 — 0 — 0 — 0 — ns tHZCE(2) CE to High-Z Output 0 3 0 4 0 5 0 8 ns tLZCE(2) CE to Low-Z Output 3 — 3 — 3 — 3 — ns tDOE tHZOE tLZOE LB, UB Access Time — 3 — 4 — 5 — 6 ns (2) tHZB LB, UB to High-Z Output 0 3 0 4 0 5 0 6 ns tLZB(2) LB, UB to Low-Z Output 0 — 0 — 0 — 0 — ns tBA Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 3.3V OUTPUT OUTPUT 30 pF Including jig and scope Figure 1. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 11/30/00 319 Ω 319 Ω 3.3V 353 Ω 5 pF Including jig and scope 353 Ω Figure 2. 5 ISSI IS61LV12816 ® AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t ACE t HZCE t LZCE LB, UB DOUT HIGH-Z t LZB t BA t HZB DATA VALID UB_CEDR2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 11/30/00 ISSI IS61LV12816 ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter -8 ns Min. Max -10 ns Min. Max. -12 ns Min. Max. -15 ns Min. Max. Unit tWC Write Cycle Time 8 — 10 — 12 — 15 — ns tSCE CE to Write End 6.5 — 8 — 8 — 10 — ns tAW Address Setup Time to Write End 6.5 — 8 — 8 — 10 — ns tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — 0 — ns tPWB LB, UB Valid to End of Write 6.5 — 8 — 9 — 10 — ns tPWE1 WE Pulse Width (OE = HIGH) 5 — 7 — 8 — 10 — ns tPWE2 WE Pulse Width (OE = LOW) 6.5 — 8 — 10 — 11 — ns tSD Data Setup to Write End 4 — 5 — 6 — 7 — ns tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns tHZWE(3) WE LOW to High-Z Output — 3 — 4 — 5 — 6 ns tLZWE(3) WE HIGH to Low-Z Output 0 — 0 — 0 — 0 — ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 11/30/00 7 ISSI IS61LV12816 ® WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CEWR1.eps 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 11/30/00 ISSI IS61LV12816 ® WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA t PBW UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR2.eps WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CEWR3.eps Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 11/30/00 9 ISSI IS61LV12816 ® WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CE LOW t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 11/30/00 ISSI IS61LV12816 IS61LV12816 STANDARD VERSION ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part No. Package ® IS61LV12816 STANDARD VERSION ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 8 IS61LV12816-8B IS61LV12816-8K IS61LV12816-8LQ IS61LV12816-8T mini BGA (6mm x 8mm) 400-mil Plastic SOJ LQFP Plastic TSOP 8 IS61LV12816-8BI IS61LV12816-8KI IS61LV12816-8LQI IS61LV12816-8TI mini BGA (6mm x 8mm) 400-mil Plastic SOJ LQFP Plastic TSOP 10 IS61LV12816-10B IS61LV12816-10K IS61LV12816-10LQ IS61LV12816-10T mini BGA (6mm x 8mm) 400-mil Plastic SOJ LQFP Plastic TSOP 10 IS61LV12816-10BI IS61LV12816-10KI IS61LV12816-10LQI IS61LV12816-10TI mini BGA (6mm x 8mm) 400-mil Plastic SOJ LQFP Plastic TSOP 12 IS61LV12816-12B IS61LV12816-12K IS61LV12816-12LQ IS61LV12816-12T mini BGA (6mm x 8mm) 400-mil Plastic SOJ LQFP Plastic TSOP 12 IS61LV12816-12BI IS61LV12816-12KI IS61LV12816-12LQI IS61LV12816-12TI mini BGA (6mm x 8mm) 400-mil Plastic SOJ LQFP Plastic TSOP 15 IS61LV12816-15B IS61LV12816-15K IS61LV12816-15LQ IS61LV12816-15T mini BGA (6mm x 8mm) 400-mil Plastic SOJ LQFP Plastic TSOP 15 IS61LV12816-15BI IS61LV12816-15KI IS61LV12816-15LQI IS61LV12816-15TI mini BGA (6mm x 8mm) 400-mil Plastic SOJ LQFP Plastic TSOP ISSI ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: [email protected] www.issi.com Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 11/30/00 11