AD ADG1436 2â ¦ max on resistance, â±15 v/12 v/â±5 v icmosâ ¢ dual spdt switch Datasheet

Preliminary Technical Data
2Ω Max On Resistance,
±15 V/12 V/±5 V iCMOS™ Dual SPDT Switch
ADG1436
FEATURES
FUNCTIONAL BLOCK DIAGRAM
2Ω Max On Resistance
0.5Ω Max On Resistance Flatness
200mA continious current
33 V supply range
Fully specified at +12 V, ±15 V, ±5 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 16-lead LFCSP packages
ADG1436
S1A
D1
S1B
IN1
IN2
S2A
D2
S2B
APPLICATIONS
SWITCHES SHOWN FOR A LOGIC "1" INPUT
Automatic test equipment
Data aquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Communication systems
Relay Replacement
Figure 1.TSSOP package
ADG1436
S2A
S1A
D2
D1
S2B
S1B
LOGIC
IN1
IN2
EN
SWITCHES SHOWN FOR A “1” INPUT LOGIC
Figure 2.LFCSP package
GENERAL DESCRIPTION
The ADG1436 is a monolithic CMOS device containing two
independently selectable SPDT switches. An EN input on the
LFCSP package is used to enable or disable the device. When
disabled, all channels are switched off. Each switch conducts
equally well in both directions when on and has an input signal
range that extends to the supplies. In the off condition, signal
levels up to the supplies are blocked. Both switches exhibit
break-before-make switching action for use in multiplexer
applications.
It is designed on an iCMOS process. iCMOS (industrialCMOS) is a modular manufacturing process combining high
voltage CMOS (complementary metal-oxide semiconductor)
and bipolar technologies. It enables the development of a wide
range of high performance analog ICs capable of 33 V operation
in a footprint that no previous generation of high voltage parts
has been able to achieve. Unlike analog ICs using conventional
CMOS processes, iCMOS components can tolerate high supply
voltages, while providing increased performance, dramatically
lower power consumption, and reduced package size.
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. iCMOS construction ensures ultralow
power dissipation, making the part ideally suited for portable
and battery-powered instruments.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
2Ω Max On Resistance over temperature.
Minimum distortion
3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V.
No VL logic power supply required.
Ultralow power dissipation: <0.03 µW.
16-lead TSSOP and 16-lead 4 mm × 4mm LFCSP
packages.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2007 Analog Devices, Inc. All rights reserved.
ADG1436
Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Pin Configurations and Function Descriptions ............................8
Dual Supply ................................................................................... 3
Terminology .......................................................................................9
Single Supply ................................................................................. 4
Typical Performance Characteristics ........................................... 10
Absolute Maximum Ratings............................................................ 7
Test Circuits..................................................................................... 13
Truth Table For Switches ............................................................. 8
Outline Dimensions ....................................................................... 15
ESD Caution.................................................................................. 7
Ordering Guide .......................................................................... 15
REVISION HISTORY
Rev. PrC | Page 2 of 17
Preliminary Technical Data
ADG1436
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
25°C
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
-40°C to
+85°C
-40°C to
+125°C
VDD to VSS
1.5
2
On Resistance Match between
Channels (∆RON)
0.1
On Resistance Flatness (RFLAT(ON))
0.1
0.5
Ω max
Ω typ
Ω max
0.5
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
±0.01
±0.5
±0.01
±0.5
±0.04
±1
±2.5
±5
±2.5
±5
±2.5
±5
2.0
0.8
tON (EN)
tOFF (EN)
Break-before-Make Time Delay, tD
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
CS (Off)
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, Vs = ±10 V; Figure 23
VS = ±10 V, Vs = ±10 V;; Figure 23
VS = VD = ±10 V; Figure 23
5
120
150
ns typ
ns max
RL = 300 Ω, CL = 35 pF
VS = +10 V; Figure 25
ns typ
ns max
ns typ
ns max
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 25
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 25
ns typ
ns min
pC typ
dB typ
dB typ
% typ
MHz typ
pF typ
pF typ
pF typ
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = +10 V; Figure 27
VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 29
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 30
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 31
RL = 110Ω, 5 V rms, f = 20 Hz to 20 kHz
RL = 50 Ω, CL = 5 pF; Figure 32
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
VDD = +16.5 V, VSS = −16.5 V
Digital Inputs = 0 V or VDD
85
105
105
125
15
200
130
140
150
170
40
1
50
50
60
0.015
100
35
35
70
0.001
150
300
ISS
VS = −5 V/0 V/+5 V; IS = −10 mA
VIN = VINL or VINH
0.005
1
IDD
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = ±10 V, IS = −10 mA; Figure 23
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −10 mA
V min
V max
µA typ
µA max
pF typ
±0.5
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANS
V
Ω typ
Ω max
Ω typ
0.001
1.0
Rev. PrC| Page 3 of 17
µA typ
µA max
µA typ
µA max
µA typ
µA max
Digital Input = 5 V
Digital Inputs = 0 V, 5V or VDD
ADG1436
Preliminary Technical Data
25°C
-40°C to
+85°C
VDD/VSS
1
-40°C to
+125°C
±4.5/±16.5
V min/max
Gnd = 0V
Guaranteed by design, not subject to production test.
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
25°C
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match between
Channels (∆RON)
-40°C to
+85°C
-40°C to
+125°C
0 V to VDD
2.5
3
0.1
4
0.5
On Resistance Flatness (RFLAT(ON))
0.1
V
Ω typ
Ω max
Ω typ
VS = +10 V, IS = −10 mA
Ω max
Ω typ
VS = +3 V/+6 V/+9 V, IS = −10 mA
VS = +10 V, IS = −10 mA; Figure 23
0.5
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
±0.01
±0.5
±0.01
±0.5
±0.04
±1
±2.5
±5
±2.5
±5
±2.5
±5
2.0
0.8
0.001
±0.5
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANS
tON (EN)
tOFF (EN)
Break-before-Make Time Delay, tD
5
120
150
85
105
105
125
200
130
140
150
170
15
1
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
CS (Off)
CD (Off)
CD, CS (On)
30
50
60
0.015
100
35
35
70
Rev. PrC | Page 4 of 17
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
MHz typ
pF typ
pF typ
pF typ
VDD = 12 V
VS = 1 V/10 V, VD = 10 V/1 V; Figure 24
VS = 1 V/10 V, VD = 10 V/1 V; Figure 24
VS = VD = 1 V or 10 V, Figure 25
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 25
RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 25
RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 25
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; Figure 27
VS = 6 V, RS = 0 Ω, CL = 1 nF; Figure 29
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 30;
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 31
RL = 110Ω, 5 V rms, f = 20 Hz to 20 kHz
RL = 50 Ω, CL = 5 pF; Figure 32
f = 1 MHz; VS = 6V
f = 1 MHz; VS = 6V
f = 1 MHz; VS = 6 V
Preliminary Technical Data
ADG1436
25°C
POWER REQUIREMENTS
IDD
-40°C to
+85°C
-40°C to
+125°C
0.001
1.0
IDD
150
300
VDD
1
5/16.5
µA typ
µA max
µA typ
µA max
VDD = 13.2 V
Digital Inputs = 0 V or VDD
Digital Inputs = 5 V
V
min/max
Gnd = 0V, Vss = 0V
Unit
Test Conditions/Comments
VS = ±3.3V, IS = −10 mA; See figure x
VDD = +4.5 V, VSS = −4.5 V
VS = ±3.3 V , IS = −10 mA
Guaranteed by design, not subject to production test.
DUAL SUPPLY
VDD = 5 V ± 10%, VSS = -5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 3.
25°C
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
−40°C to
+85°C
−40°C to
+125°C
0 V to VDD
On Resistance Match Between
Channels (∆RON)
0.1
V
Ω typ
Ω max
Ω typ
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
0.1
Ω max
Ω typ
±0.01
nA typ
VS = ±4.5 V, VD = ∓4.5 V; See figure x
±2.5
±5
Drain Off Leakage, ID (Off)
±0.5
±0.01
nA max
nA typ
VS = ±4.5 V, VD = ∓4.5 V; See figure x
±0.5
±0.04
±1
±2.5
±5
VS = VD = ±4.5V; See figure x
±5
±5
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
VIN = VINL or VINH
3
4
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINLor IINH
2.0
0.8
0.001
±0.5
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANS
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
3
150
190
85
105
105
125
265
130
140
150
170
50
ns typ
ns max
ns typ
ns max
ns typ
ns max
Charge Injection
Off Isolation
50
50
ns typ
ns min
pC typ
dB typ
Channel-to-Channel Crosstalk
60
dB typ
10
Rev. PrC| Page 5 of 17
VS = −3 V/0 V/+3 V; IS = −10 mA
VDD = +5.5 V, VSS = −5.5 V
RL = 300 Ω, CL = 35 pF
VS = 3 V; Figure 25
RL = 300 Ω, CL = 35 pF
VS = 3 V; Figure 25
RL = 300 Ω, CL = 35 pF
VS = 3 V; Figure 25
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 3 V; See figure 25
VS = 0 V, RS = 0 Ω, CL = 1 nF; See figure x
RL = 50 Ω, CL = 5 pF, f = 1 MHz; See figure
x
RL = 50 Ω, CL = 5 pF, f = 1 MHz; See figure
x
ADG1436
Total Harmonic Distortion + Noise
−3 dB Bandwidth
CS (Off)
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
Preliminary Technical Data
25°C
0.002
200
35
35
150
−40°C to
+85°C
−40°C to
+125°C
0.001
1.0
ISS
0.001
1.0
VDD/VSS
1
±4.5/±16.5
Guaranteed by design, not subject to production test.
Rev. PrC | Page 6 of 17
Unit
% typ
MHz typ
pF typ
pF typ
pF typ
µA typ
µA max
µA typ
µA max
V
min/max
Test Conditions/Comments
RL = 110Ω, 5 V pp, f = 20 Hz to 20 kHz
RL = 50 Ω, CL = 5 pF; See figure x
Vs = 0V, f = 1 MHz
Vs = 0V, f = 1 MHz
Vs = 0V, f = 1 MHz
VDD = 5.5 V , Vss = -5.5V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
Gnd = 0V
Preliminary Technical Data
ADG1436
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Peak Current, S or D
Continuous Current, S or D
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
16-Lead TSSOP, θJA Thermal
Impedance
16-Lead LFCSP, θJA Thermal
Impedance
Reflow Soldering Peak
Temperature, Pb free
1
Ratings
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
300 mA (pulsed at 1 ms, 10%
duty cycle max)
200 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−40°C to +125°C
−65°C to +150°C
150°C
150.4°C/W
72.7°C/W
260°C
Over voltages at IN, S, or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrC| Page 7 of 17
ADG1436
Preliminary Technical Data
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
S1A IN1 NC NC
IN1 1
16
NC
S1A 2
15
NC
D1 3
14
NC
16 15 14 13
D1 1
S1B 2
ADG1236 13 VDD
TOP VIEW
VSS 5 (Not to Scale) 12 S2B
Vss 3
S1B 4
11
D2
NC 7
10
S2A
NC 8
9
IN2
NC = NO CONNECT
TOP VIEW
(Not to Scale)
Gnd 4
12 EN
11 Vdd
10 S2B
9 D2
5 6
7
8
NC IN2 NC S2A
04776-0-002
GND 6
ADG1436
EXPOSED PAD TIED TO SUBSTRATE, Vss
NC = NO CONNECT
Figure 3.TSSOP Pin Configuration
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
1
15
2
16
3
1
4
2
5
3
6
4
7, 8, 14–16
5,7,13,14
9
6
10
8
11
9
12
10
13
11
12
Mnemonic
IN1
S1A
D1
S1B
VSS
GND
NC
IN2
S2A
D2
S2B
VDD
EN
Function
Logic Control Input.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
No Connect.
Logic Control Input.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Positive Power Supply Potential.
Active High Digital Input. When low, the device is disabled and all switches are off. When
high, INx logic inputs determine the on switches.
TRUTH TABLE FOR SWITCHES
Table 6. ADG1436 TSSOP Truth Table
INx
0
1
Switch xA
Off
On
Switch xB
On
Off
Table 7. ADG1436 LFCSPTruth Table
EN
0
1
1
INx
X
0
1
SxA
Off
Off
On
SxB
Off
On
Off
Rev. PrC | Page 8 of 17
Preliminary Technical Data
ADG1436
TERMINOLOGY
CD (Off)
The off switch drain capacitance, measured with reference to
ground.
IDD
The positive supply current.
ISS
The negative supply current.
CD, CS (On)
The on switch capacitance, measured with reference to ground.
VD (VS)
The analog voltage on Terminals D and S.
CIN
The digital input capacitance.
RON
The ohmic resistance between D and S.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
IS (Off)
The source leakage current with the switch off.
tTRANS
The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one
address state to another.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
ID (Off)
The drain leakage current with the switch off.
ID, IS (On)
The channel leakage current with the switch on.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
VINL
The maximum input voltage for Logic 0.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
VINH
The minimum input voltage for Logic 1.
On Response
The frequency response of the on switch.
IINL (IINH)
The input current of the digital input.
Insertion Loss
The loss due to the on resistance of the switch.
CS (Off)
The off switch source capacitance, measured with reference to
ground.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
Rev. PrC| Page 9 of 17
ADG1436
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
Figure 6, On Resistance as a Function of VD (VS) for Single l Supply
Figure 9. Leakage Current as a Function of VD (VS)
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
Figure 10. Leakage Currents as a Function of VD (VS)
Rev. PrC | Page 10 of 17
Preliminary Technical Data
ADG1436
Figure 11. Leakage Current as a Function of VD (VS)
Figure 15. Charge Injection vs. Source Voltage
Figure 12. Leakage Currents as a Function of Temperature
Figure 16. tTRANSITION Times vs. Temperature
Figure 13. IDD vs. Logic Level
Figure 17. Off Isolation vs. Frequency
Figure 14. Logic Threshold Voltage vs Supply Voltage
Rev. PrC| Page 11 of 17
ADG1436
Preliminary Technical Data
Figure 18. Crosstalk vs. Frequency
Figure 20. THD + N vs. Frequency
Figure 211. Capacitance vs. Source Voltage for Dual Supply
Figure 222. Capacitance vs. Source Voltage for Single Supply
Figure 19. On Response vs. Frequency
Rev. PrC | Page 12 of 17
Preliminary Technical Data
ADG1436
TEST CIRCUITS
V
A
VDD
VSS
VD
D
NC = NO CONNECT
0.1µF
A
VD
Figure 25. On Leakage
VIN
50%
50%
VIN
50%
50%
VSS
SB
D
SA
VOUT
RL
50Ω
IN
VIN
S
NC
A
Figure 24. Off Resistance
VDD
VS
ID (ON)
ID (OFF)
VS
Figure 23. On Resistance
0.1µF
D
CL
35pF
90%
90%
VOUT
GND
tON
tOFF
04776-0-023
VS
04776-0-020
IDS
S
04776-0-022
IS (OFF)
D
04776-0-021
S
Figure 26. Switching Times
0.1µF
VS
VDD
VSS
VDD
VSS
SB
0.1µF
VIN
D
SA
VOUT
RL
50Ω
IN
VOUT
CL
35pF
80%
tBBM
tBBM
VIN
04776-0-024
GND
Figure 27. Break-before-Make Time Delay
3V
ENABLE
DRIVE (VIN)
50%
VDD
VSS
VDD
VSS
INx
50%
SA
0V
tOFF (EN)
0.9VO
OUTPUT
0.9VO
D
EN
VIN
50Ω
GND
100Ω
35pF
04861-025
tON (EN)
OUTPUT
VS
SB
Figure 28. . Enable Delay, tON (EN), tOFF (EN)
Rev. PrC| Page 13 of 17
ADG1436
Preliminary Technical Data
VDD
VSS
VDD
VSS
0.1µF
VIN (NORMALLY
CLOSED SWITCH)
SB
VS
D
VOUT
SA
CL
1nF
IN
VIN
ON
OFF
NC
VIN (NORMALLY
OPEN SWITCH)
VOUT
GND
∆VOUT
QINJ = CL × ∆VOUT
04776-0-025
0.1µF
Figure 29. Charge Injection
VDD
VSS
0.1µF
0.1µF
VSS
NETWORK
ANALYZER
0.1µF
VDD
NC
SA
IN
VOUT
NETWORK
ANALYZER
VSS
SB
VDD
VSS
SA
RL
50Ω
SB
50Ω
50Ω
VS
D
R
50Ω
IN
VS
D
GND
VIN
GND
OFF ISOLATION = 20 LOG
VOUT
04776-0-026
RL
50Ω
VOUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
04776-0-028
VDD
0.1µF
VOUT
VS
Figure 32. Bandwidth
VS
Figure 30. Off Isolation
VSS
VDD
0.1µF
VDD
NETWORK
ANALYZER
VSS
NC
IN
SB
SA
VSS
0.1µF
0.1µF
VDD
RS
50Ω
S
50Ω
IN
VS
INSERTION LOSS = 20 LOG
RL
50Ω
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
VIN
GND
04776-0-027
GND
VS
V p-p
D
D
VIN
AUDIO PRECISION
VSS
Figure 31. Channel-to-Channel Crosstalk
Rev. PrC | Page 14 of 17
RL
600Ω
Figure 33. THD + Noise
VOUT
04776-0-029
VDD
0.1µF
Preliminary Technical Data
ADG1436
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.20
0.09
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in inches and (millimeters
4.00
BSC SQ
PIN 1
INDICATOR
0.65 BSC
TOP
VIEW
12° MAX
1.00
0.85
0.80
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
13
12
16
1
EXPOSED
PAD
3.75
BSC SQ
0.75
0.60
0.50
(BOTTOM VIEW)
9
4
8
2.25
2.10 SQ
1.95
5
0.25 MIN
1.95 BSC
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 35. 16-Lead Lead Frame Chip Scale Package [VQ_LFCSP]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG1436YRUZ
ADG1436YRUZREEL
ADG1436YRUZREEL7
ADG1436YCPZ500RL7
ADG1436YCPZREEL7
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Package Option
RU-16
RU-16
−40°C to +125°C
Thin Shrink Small Outline Package (TSSOP)
RU-16
−40°C to +125°C
Lead Frame Chip Scale Package (LFCSP)
CP-16-4
−40°C to +125°C
Lead Frame Chip Scale Package (LFCSP)
CP-16-4
Rev. PrC| Page 15 of 17
ADG1436
Preliminary Technical Data
NOTES
Rev. PrC | Page 16 of 17
Preliminary Technical Data
ADG1436
NOTES
© 2007Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06817-0-5/07(PrC)
Rev. PrC| Page 17 of 17
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