CY8CLED16
EZ-Color™ HB LED Controller
Features
■
HB LED Controller
❐ Configurable dimmers support up to 16
Independent LED channels
❐ 8-to 32-bits of resolution per channel
❐ Dynamic reconfiguration Enables LED controller Plus Other
Features: CapSense®, battery charging, and motor control
■
Visual embedded design
❐ LED-based drivers
• Binning compensation
• Temperature feedback
• Optical feedback
• DMX512
■
PrISM modulation technology™
❐ Reduces radiated EMI
❐ Reduces low frequency blinking
■
Powerful Harvard-architecture Processor
❐ M8C processor speeds to 24 MHz
❐ 3.0 to 5.25 V operating voltage
❐ Operating voltages down to 1.0 V using
On-Chip switch mode pump (SMP)
❐ Industrial temperature range: –40 °C to +85 °C
■
■
Advanced peripherals (PSoC® Blocks)
❐ 16 Digital PSoC Blocks Provide:
• 8-to 32-bit timers, counters, and PWMs
• Up to 4 Full-Duplex UARTs
• Multiple SPI masters or slaves
• Connectable to all GPIO Pins
❐ 12 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable gain amplifiers
• Programmable filters and comparators
❐ Complex peripherals by combining blocks
■
Flexible on-chip memory
❐ 32K flash program storage 50,000 Erase/Write Cycles
❐ 2K SRAM Data Storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible Protection Modes
❐
■
Programmable pin configurations
❐ 25 mA sink, 10 mA source on all GPIO
❐ Pull-up, Pull-down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐ Up to eight analog Inputs on GPIO
❐ Configurable interrupt on all GPIO
electrically erasable programmable read-only memory
(EEPROM) emulation in flash
Complete development tools
❐ Free development software
• PSoC Designer™
❐ Full-featured, In-circuit emulator and programmer
❐ Full speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
EZ-Color HB LED Controller
Preliminary Data Sheet
Cypress Semiconductor Corporation
Document Number: 001-13105 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 24, 2011
CY8CLED16
Logic Block Diagram
Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Analog
Drivers
SYSTEM BUS
Global Digital Interconnect
SRAM
2K
Global Analog Interconnect
SROM
Flash 32K
PSoC CORE
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Digital
Block
Array
Digital
Clocks
Two
Multiply
Accums.
Analog
Block
Array
POR and LVD
Decimator
I 2C
System Resets
Analog
Input
Muxing
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
Document Number: 001-13105 Rev. *H
Page 2 of 53
CY8CLED16
Contents
EZ-Color™ Functional Overview ..................................... 4
Target Applications ...................................................... 4
The PSoC Core ........................................................... 4
The Digital System ...................................................... 4
The Analog System ..................................................... 5
Additional System Resources ..................................... 6
EZ-Color Device Characteristics ................................. 6
Getting Started .................................................................. 6
Application Notes ........................................................ 6
Development Kits ........................................................ 6
Training ....................................................................... 6
CYPros Consultants .................................................... 6
Solutions Library .......................................................... 6
Technical Support ....................................................... 6
Development Tools .......................................................... 7
PSoC Designer Software Subsystems ........................ 7
Designing with PSoC Designer ....................................... 8
Select User Modules ................................................... 8
Configure User Modules .............................................. 8
Organize and Connect ................................................ 8
Generate, Verify, and Debug ....................................... 8
Pin Information ................................................................. 9
Pinouts ........................................................................ 9
Register Reference ......................................................... 11
Register Conventions ................................................ 11
Register Mapping Tables .......................................... 11
Electrical Specifications ................................................ 14
Absolute Maximum Ratings ....................................... 15
Document Number: 001-13105 Rev. *H
Operating Temperature ............................................. 15
DC Electrical Characteristics ..................................... 16
AC Electrical Characteristics ..................................... 31
Packaging Information ................................................... 41
Packaging Dimensions .............................................. 41
Thermal Impedances ................................................. 42
Capacitance on Crystal Pins ..................................... 42
Solder Reflow Peak Temperature ............................. 42
Development Tool Selection ......................................... 43
Software .................................................................... 43
Evaluation Tools ........................................................ 43
Device Programmers ................................................. 44
Accessories (Emulation and Programming) .............. 44
Ordering Information ...................................................... 45
Key Device Features ................................................. 45
Ordering Code Definitions ......................................... 45
Acronyms ........................................................................ 46
Acronyms Used ......................................................... 46
Reference Documents .................................................... 46
Document Conventions ............................................. 47
Units of Measure ....................................................... 47
Numeric Conventions ................................................ 47
Glossary .......................................................................... 47
Document History Page ................................................. 52
Sales, Solutions, and Legal Information ...................... 53
Worldwide Sales and Design Support ....................... 53
Products .................................................................... 53
PSoC® Solutions ...................................................... 53
Page 3 of 53
CY8CLED16
EZ-Color™ Functional Overview
Cypress's EZ-Color family of devices offers the ideal control
solution for High Brightness LED applications requiring intelligent dimming control. EZ-Color devices combine the power and
flexibility of Programmable System-on-Chip (PSoC); with
Cypress's precise illumination signal modulation (PrISM)
modulation technology providing lighting designers a fully
customizable and integrated lighting solution platform.
The EZ-Color family supports a range of independent LED
channels from 4 channels at 32 bits of resolution each, up to 16
channels at 8 bits of resolution each. This enables lighting
designers the flexibility to choose the LED array size and color
quality. PSoC Designer software, with lighting specific drivers,
can significantly cut development time and simplify
implementation of fixed color points through temperature,
optical, and LED binning compensation. EZ-Color's virtually
limitless analog and digital customization allow for simple
integration of features in addition to intelligent lighting, such as
Battery Charging, Image Stabilization, and Motor Control during
the development process. These features, along with Cypress'
best-in-class quality and design support, make EZ-Color the
ideal choice for intelligent HB LED control applications.
Target Applications
■
LCD Backlight
■
Large Signs
■
General Lighting
■
Architectural Lighting
■
Camera/Cell Phone flash
■
flashlights
The PSoC Core
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a central processing unit (CPU), memory,
clocks, and configurable general purpose I/O (GPIO).
The M8C CPU core is a powerful processor with speeds up to 48
MHz, providing a four million instructions per second (MIPS) 8-bit
Harvard-architecture microprocessor. The CPU utilizes an
interrupt controller with 25 vectors, to simplify programming of
real time embedded events. Program execution is timed and
protected using the included Sleep and watchdog timers (WDT).
Memory encompasses 32 KB of flash for program storage, 2 KB
of SRAM for data storage, and up to 2 KB of EEPROM emulated
using the flash. Program flash utilizes four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
be doubled to 48 MHz for use by the digital system. A low power
32 kHz internal low speed oscillator (ILO) is provided for the
Sleep timer and WDT. If crystal accuracy is desired, the 32.768
kHz external crystal oscillator (ECO) is available for use as a
real time clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the EZ-Color device.
EZ-Color GPIOs provide connection to the CPU, digital and
analog resources of the device. Each pin’s drive mode may be
selected from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
The Digital System
The digital system is composed of 16 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user modules. Digital peripheral configurations include
those listed below.
■
PrISM (8-to 32-bit)
■
PWMs (8-to 32-bit)
■
PWMs with Dead band (8-to 32-bit)
■
Counters (8-to 32-bit)
■
Timers (8-to 32-bit)
■
UART 8 bit with selectable parity (up to 4)
■
SPI master and slave (up to 4 each)
■
I2C slave and multi-master (1 available as a System Resource)
■
Cyclical Redundancy Checker/Generator (8- to 32-bit)
■
IrDA (up to 4)
■
Generators (8-to 32-bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by EZ-Color device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in Table 1 on page 6.
The EZ-Color family incorporates flexible internal clock generators, including a 24 MHz internal main oscillator (IMO) accurate
to 2.5% over temperature and voltage. The 24 MHz IMO can also
Document Number: 001-13105 Rev. *H
Page 4 of 53
CY8CLED16
Figure 1. Digital System Block Diagram
Port 5
Port 6
Port 3
Port 4
Port 1
Port 2
To System Bus
Digital Clocks
From Core
DCB02
4
DCB03
4
8
8
DBB10
DBB11
DCB12
4
DCB13
4
Row 2
DBB20
DBB21
DCB22
4
DCB23
4
Row Output
Configuration
Row Input
Configuration
Row 1
Correlators
■
Peak Detectors
■
Many other topologies possible
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
8
Row Output
Configuration
Row Input
Configuration
8
■
Figure 2. Analog System Block Diagram
Row Output
Configuration
Row Input
Configuration
Digital PSoC Block Array
DBB01
Modulators
Analog blocks are provided in columns of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks, as shown in the figure below.
DIGITAL SYSTEM
DBB00
■
Port 0
To Analog
System
Row 0
DTMF Dialer
AGNDIn RefIn
Port 7
■
P2[3]
P2[6]
P2[4]
P2[1]
P2[2]
DBB30
DBB31
DCB32
4
DCB33
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
Row Output
Configuration
Row Input
Configuration
P2[0]
Row 3
Array Input Configuration
GOE[7:0]
GOO[7:0]
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
The Analog System
The Analog System is composed of 12 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common EZ-Color analog functions (most
available as user modules) are listed below.
■
Analog-to-digital converters (up to 4, with 6- to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
■
Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 4, with selectable gain to 48x)
■
Instrumentation amplifiers (up to 2, with selectable gain to 93x)
■
Comparators (up to 4, with 16 selectable thresholds)
■
DACs (up to 4, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 4, with 6- to 9-bit resolution)
■
High current output drivers (four with 40 mA drive as a core
resource)
■
1.3 V reference (as a System resource)
Document Number: 001-13105 Rev. *H
Block Array
ACB00
ACB01
ACB02
ACB03
ASC10
ASD11
ASC12
ASD13
ASD20
ASC21
ASD22
ASC23
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Page 5 of 53
CY8CLED16
Additional System Resources
System resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Resources include a multiplier, decimator, switch mode pump,
low-voltage detection, and power-onreset (POR). Statements
describing the merits of each system resource are presented
below.
■
■
■
The decimator provides a custom hardware filter for digital
signal, processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
Low-voltage-detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced power on
reset (POR) circuit eliminates the need for a system supervisor.
■
An internal 1.3-voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
Multiply accumulate (MAC) provides fast 8-bit multiplier with
32-bit accumulate, to assist in general math and digital filters.
■
An integrated switch-mode pump (SMP) generates normal
operating voltages from a single 1.2-V battery cell, providing a
low cost boost converter.
EZ-Color Device Characteristics
Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data
sheet is shown in the highlighted row of the table.
Analog
Blocks
SRAM
Size
1
4
8
0
2
4
256 Bytes
4K
No
56
1
4
48
2
2
6
1K
16K
Yes
Flash
Size
Digital
Blocks
16
4
Analog
Columns
Digital
Rows
2
CY8CLED04
Analog
Outputs
Digital
I/O
CY8CLED02
Part Number
Analog
Inputs
LED
Channels
CapSense
Table 1. EZ-Color Device Characteristics
CY8CLED08
8
44
2
8
12
4
4
12
256 Bytes
16K
No
CY8CLED16
16
44
4
16
12
4
4
12
2K
32K
No
Getting Started
The quickest way to understand the device is to read this data
sheet and then use the PSoC Designer Integrated development
environment (IDE). This data sheet is an overview of the
EZ-Color integrated circuit and presents specific pin, register,
and electrical specifications. For in depth information, along with
detailed programming information, see the Technical Reference
Manual for this PSoC device.
For up-to-date ordering, packaging, and electrical specification
information, see the latest device data sheets on the web at
http://www.cypress.com.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
CYPros Consultants
Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC
consultant go to the CYPros Consultants web site.
Solutions Library
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Development Kits
Technical Support
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Application Notes
Document Number: 001-13105 Rev. *H
Page 6 of 53
CY8CLED16
Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
■
Integrated source-code editor (C and assembly)
■
Free C compiler with no size restrictions or time limits
■
Built-in debugger
■
In-circuit emulation
■
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full-speed USB 2.0
❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this lets you to use more than 100 percent of
PSoC's resources for an application.
Document Number: 001-13105 Rev. *H
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also lets you to create a trace buffer of registers and memory
locations of interest.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an Online Support
Forum to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
Page 7 of 53
CY8CLED16
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed-function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and lowering inventory costs. These
configurable resources, called PSoC blocks, have the ability to
implement a wide variety of user-selectable functions. The PSoC
development process is:
1. Select user modules.
2. Configure user modules.
3. Organize and connect.
4. Generate, verify, and debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a pulse
with modulator (PWM) user module configures one or more
digital PSoC blocks, one for each eight bits of resolution. Using
these parameters, you can establish the pulse width and duty
cycle. Configure the parameters and properties to correspond to
your chosen application. Enter values directly or by selecting
values from drop-down menus. All of the user modules are
documented in datasheets that may be viewed directly in
PSoC Designer or on the Cypress website. These user module
datasheets explain the internal operation of the user module and
provide performance specifications. Each datasheet describes
Document Number: 001-13105 Rev. *H
the use of each user module parameter, and other information
that you may need to successfully implement your design.
Organize and Connect
Build signal chains at the chip-Level by interconnecting user
modules to each other and the I/O pins. Perform the selection,
configuration, and routing so that you have complete control over
all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides APIs with high-level functions to control
and respond to hardware events at run time, and interrupt
service routines that you can adapt as needed.
A complete code development environment lets you to develop
and customize your applications in C, assembly language, or
both.
The last step in the development process takes place inside
PSoC Designer's Debugger (accessed by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full-speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint, and watch-variable
features, the debug interface provides a large trace buffer. It lets
you to define complex breakpoint events that include monitoring
address and data bus values, memory locations, and external
signals.
Page 8 of 53
CY8CLED16
Pin Information
Pinouts
The CY8CLED16 device is available in three packages which are listed and illustrated in the following tables. Every port pin (labeled
with a “P”) is capable of Digital I/O. However, Vss, VDD, SMP, and XRES are not capable of Digital I/O.
28-Pin Part Pinout
Table 2. 28-Pin Part Pinout (SSOP)
Pin
No.
1
2
3
4
5
6
7
8
9
Type
Digital Analog
I/O
I
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I
I/O
I
Power
10
11
12
13
I/O
I/O
I/O
I/O
14
15
I/O
I/O
I/O
I/O
20
21
22
23
24
25
26
27
28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
SMP
P1[7]
P1[5]
P1[3]
P1[1]
Power
16
17
18
19
Pin
Name
Vss
P1[0]
P1[2]
P1[4]
P1[6]
XRES
Input
I
I
I
I/O
I/O
I
Power
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
VDD
Description
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
Switch mode pump (SMP) connection to
external components required.
I2C serial clock (SCL).
I2C serial data (SDA).
Figure 3. 28-Pin Device
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I,
A, I, P2[3]
P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VREF
P2[4], External AGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Crystal (XTALin), I2C serial clock (SCL),
ISSP-SCLK[1].
Ground connection.
Crystal (XTALout), I2C serial data (SDA),
ISSP-SDATA[1].
optional external clock input (EXTCLK).
Active high external reset with internal
pull- down.
Direct switched capacitor block input.
Direct switched capacitor block input.
External analog ground (AGND).
External voltage reference (VREF).
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
Note
1. These are the ISSP pins, which are not High Z at POR.
Document Number: 001-13105 Rev. *H
Page 9 of 53
CY8CLED16
Table 3. 48-Pin Part Pinout (QFN)[2]
I/O
P4[1]
SMP
8
I/O
P3[7]
9
I/O
P3[5]
10
I/O
P3[3]
11
I/O
P3[1]
12
I/O
P5[3]
13
I/O
P5[1]
14
I/O
P1[7]
15
I/O
P1[5]
16
I/O
P1[3]
17
I/O
P1[1]
18
Power
Switch mode pump (SMP) connection to external
components required.
I2C serial clock (SCL).
2
Crystal (XTALin), I2C serial clock (SCL),
ISSP-SCLK[1].
Vss
Ground connection.
I/O
P1[0]
Crystal (XTALout), I2C serial data (SDA),
ISSP-SDATA[1].
20
I/O
P1[2]
21
I/O
P1[4]
22
I/O
P1[6]
23
I/O
P5[0]
24
I/O
P5[2]
25
I/O
P3[0]
26
I/O
P3[2]
27
I/O
P3[4]
28
I/O
MLF
7
8
9
10
11
12
(Top View)
36
35
34
33
32
31
30
29
28
27
26
25
P2[4], External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
optional external clock input (EXTCLK).
P3[6]
Input
XRES
Active high external reset with internal pull-down.
30
I/O
P4[0]
31
I/O
P4[2]
32
I/O
P4[4]
33
I/O
34
I/O
I
P2[0]
Direct switched capacitor block input.
35
I/O
I
P2[2]
Direct switched capacitor block input.
36
I/O
P2[4]
external analog ground (AGND).
37
I/O
P2[6]
external voltage reference (VREF).
38
I/O
I
P0[0]
Analog column mux input.
39
I/O
I/O
P0[2]
Analog column mux input and column output.
40
I/O
I/O
P0[4]
Analog column mux input and column output.
41
I/O
I
P0[6]
Analog column mux input.
42
1
2
3
4
5
6
I C serial data (SDA).
19
29
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[0]
P5[2]
Power
P0[0], A, I
P2[6], External VREF
P4[3]
6
38
37
P4[5]
I/O
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
I/O
5
42
41
40
39
4
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
P4[7]
45
44
I/O
17
18
19
20
21
22
23
24
Direct switched capacitor block input.
3
I2C SCL, XTALin, P1[1]
Vss
I2C SDA, XTALout, P1[0]
P1[2]
EXTCLK, P1[4]
P1[6]
Direct switched capacitor block input.
P2[1]
15
16
P2[3]
I
I2C SDA, P1[5]
P1[3]
I
I/O
P2[5]
P2[7]
P0[1], A, I
I/O
2
48
47
46
1
7
Figure 4. 48-Pin Device
Description
43
Pin
Name
Analog
13
14
Type
Digital
P5[1]
I2C SCL, P1[7]
Pin
No.
P4[6]
Power
VDD
Supply voltage.
43
I/O
I
P0[7]
Analog column mux input.
44
I/O
I/O
P0[5]
Analog column mux input and column output.
45
I/O
I/O
P0[3]
Analog column mux input and column output.
46
I/O
I
P0[1]
Analog column mux input.
47
I/O
P2[7]
48
I/O
P2[5]
LEGEND: A = Analog, I = Input, and O = Output.
Note
2. The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
Document Number: 001-13105 Rev. *H
Page 10 of 53
CY8CLED16
Register Reference
Register Conventions
Register Mapping Tables
Abbreviations Used
This chapter lists the registers of the CY8CLED16 EZ-Color
device.
The register conventions specific to this section are listed in the
following table.
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 001-13105 Rev. *H
The device has a total register address space of 512 bytes. The
register space is referred to as I/O space and is divided into two
banks, Bank 0 and bank 1. The XOI bit in the Flag register
(CPU_F) determines which bank the user is currently in. When
the XOI bit is set the user is in Bank 1.
Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
Page 11 of 53
CY8CLED16
Table 4. Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
Addr (0,Hex)
00
01
02
Access
RW
RW
RW
Name
DBB20DR0
DBB20DR1
DBB20DR2
Addr (0,Hex)
40
41
42
Access
#
W
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
Addr (0,Hex)
80
81
82
Acces
Name
RW
RDI2RI
RW
RDI2SYN
RW
RDI2IS
Addr (0,Hex)
C0
C1
C2
Acces
RW
RW
RW
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DBB20CR0
DBB21DR0
DBB21DR1
DBB21DR2
DBB21CR0
DCB22DR0
DCB22DR1
DCB22DR2
DCB22CR0
DCB23DR0
DCB23DR1
DCB23DR2
DCB23CR0
DBB30DR0
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC12CR0
ASC12CR1
ASC12CR2
ASC12CR3
ASD13CR0
ASD13CR1
ASD13CR2
ASD13CR3
ASD20CR0
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI2LT0
RDI2LT1
RDI2RO0
RDI2RO1
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
RW
RW
RW
RW
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
PRT5DM2
PRT6DR
PRT6IE
PRT6GS
PRT6DM2
PRT7DR
PRT7IE
PRT7GS
PRT7DM2
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
DBB10DR0
DBB10DR1
DBB10DR2
DBB10CR0
DBB11DR0
DBB11DR1
DBB11DR2
DBB11CR0
DCB12DR0
DCB12DR1
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
DBB30DR1
DBB30DR2
DBB30CR0
DBB31DR0
DBB31DR1
DBB31DR2
DBB31CR0
DCB32DR0
DCB32DR1
DCB32DR2
DCB32CR0
DCB33DR0
DCB33DR1
DCB33DR2
DCB33CR0
AMX_IN
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
RW
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
ASD22CR0
ASD22CR1
ASD22CR2
ASD22CR3
ASC23CR0
ASC23CR1
ASC23CR2
ASC23CR3
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
STK_PP
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
RW
7A
7B
7C
7D
7E
7F
RW
RW
RW
RW
RW
RW
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
ACB02CR3
ACB02CR0
DCB12DR2
3A
RW
ACB02CR1
DCB12CR0
3B
#
ACB02CR2
DCB13DR0
3C
#
ACB03CR3
DCB13DR1
3D
W
ACB03CR0
DCB13DR2
3E
RW
ACB03CR1
DCB13CR0
3F
#
ACB03CR2
Blank fields are reserved and should not be accessed.
Document Number: 001-13105 Rev. *H
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
MUL1_X
MUL1_Y
MUL1_DH
MUL1_DL
ACC1_DR1
ACC1_DR0
ACC1_DR3
ACC1_DR2
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RDI1RI
RDI1SYN
RDI1IS
RDI1LT0
RDI1LT1
RDI1RO0
RDI1RO1
BA
BB
BC
BD
BE
BF
# Access is bit specific.
W
W
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI3RI
RDI3SYN
RDI3IS
RDI3LT0
RDI3LT1
RDI3RO0
RDI3RO1
CUR_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
CPU_F
RW
RW
RW
RW
RW
RW
RW
CPU_SCR1
CPU_SCR0
FA
FB
FC
FD
FE
FF
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
#
#
Page 12 of 53
CY8CLED16
Table 5. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
Addr(1,Hex)
00
Access
RW
Name
DBB20FN
Addr(1,Hex)
40
Access
RW
Name
ASC10CR0
Addr(1,Hex)
80
Access
RW
Name
RDI2RI
Addr(1,Hex)
C0
Access
RW
PRT0DM1
01
RW
DBB20IN
41
RW
ASC10CR1
81
RW
RDI2SYN
C1
RW
PRT0IC0
02
RW
DBB20OU
42
RW
ASC10CR2
82
RW
RDI2IS
C2
RW
PRT0IC1
03
RW
ASC10CR3
83
RW
RDI2LT0
C3
RW
PRT1DM0
04
RW
DBB21FN
44
RW
ASD11CR0
84
RW
RDI2LT1
C4
RW
PRT1DM1
05
RW
DBB21IN
45
RW
ASD11CR1
85
RW
RDI2RO0
C5
RW
PRT1IC0
06
RW
DBB21OU
46
RW
ASD11CR2
86
RW
RDI2RO1
C6
RW
PRT1IC1
07
RW
ASD11CR3
87
RW
PRT2DM0
08
RW
DCB22FN
48
RW
ASC12CR0
88
RW
RDI3RI
C8
RW
PRT2DM1
09
RW
DCB22IN
49
RW
ASC12CR1
89
RW
RDI3SYN
C9
RW
PRT2IC0
0A
RW
DCB22OU
4A
RW
ASC12CR2
8A
RW
RDI3IS
CA
RW
PRT2IC1
0B
RW
ASC12CR3
8B
RW
RDI3LT0
CB
RW
PRT3DM0
0C
RW
DCB23FN
4C
RW
ASD13CR0
8C
RW
RDI3LT1
CC
RW
PRT3DM1
0D
RW
DCB23IN
4D
RW
ASD13CR1
8D
RW
RDI3RO0
CD
RW
PRT3IC0
0E
RW
DCB23OU
4E
RW
ASD13CR2
8E
RW
RDI3RO1
CE
RW
PRT3IC1
0F
RW
ASD13CR3
8F
RW
PRT4DM0
10
RW
DBB30FN
50
RW
ASD20CR0
90
RW
GDI_O_IN
D0
RW
PRT4DM1
11
RW
DBB30IN
51
RW
ASD20CR1
91
RW
GDI_E_IN
D1
RW
PRT4IC0
12
RW
DBB30OU
52
RW
ASD20CR2
92
RW
GDI_O_OU
D2
RW
PRT4IC1
13
RW
ASD20CR3
93
RW
GDI_E_OU
D3
RW
PRT5DM0
14
RW
DBB31FN
54
RW
ASC21CR0
94
RW
D4
43
47
4B
4F
53
C7
CF
PRT5DM1
15
RW
DBB31IN
55
RW
ASC21CR1
95
RW
D5
PRT5IC0
16
RW
DBB31OU
56
RW
ASC21CR2
96
RW
D6
PRT5IC1
17
RW
ASC21CR3
97
RW
D7
PRT6DM0
18
RW
DCB32FN
58
RW
ASD22CR0
98
RW
D8
PRT6DM1
19
RW
DCB32IN
59
RW
ASD22CR1
99
RW
D9
PRT6IC0
1A
RW
DCB32OU
5A
RW
ASD22CR2
9A
RW
DA
PRT6IC1
1B
RW
ASD22CR3
9B
RW
DB
PRT7DM0
1C
RW
DCB33FN
5C
RW
ASC23CR0
9C
RW
PRT7DM1
1D
RW
DCB33IN
5D
RW
ASC23CR1
9D
RW
OSC_GO_EN
DD
RW
PRT7IC0
1E
RW
DCB33OU
5E
RW
ASC23CR2
9E
RW
OSC_CR4
DE
RW
PRT7IC1
1F
RW
ASC23CR3
9F
RW
OSC_CR3
DF
RW
DBB00FN
20
RW
CLK_CR0
60
RW
A0
OSC_CR0
E0
RW
DBB00IN
21
RW
CLK_CR1
61
RW
A1
OSC_CR1
E1
RW
DBB00OU
22
RW
ABF_CR0
62
RW
A2
OSC_CR2
E2
RW
AMD_CR0
63
RW
A3
VLT_CR
E3
RW
VLT_CMP
E4
R
23
57
5B
5F
DBB01FN
24
RW
64
A4
DBB01IN
25
RW
65
A5
DBB01OU
26
RW
27
DC
E5
AMD_CR1
66
RW
A6
ALT_CR0
67
RW
A7
DEC_CR2
E6
E7
RW
DCB02FN
28
RW
ALT_CR1
68
RW
A8
IMO_TR
E8
W
DCB02IN
29
RW
CLK_CR2
69
RW
A9
ILO_TR
E9
W
DCB02OU
2A
RW
6A
AA
BDG_TR
EA
RW
6B
AB
ECO_TR
EB
W
2B
DCB03FN
2C
RW
TMP_DR0
6C
RW
AC
EC
DCB03IN
2D
RW
TMP_DR1
6D
RW
AD
ED
DCB03OU
2E
RW
TMP_DR2
6E
RW
AE
EE
TMP_DR3
6F
RW
AF
2F
EF
DBB10FN
30
RW
ACB00CR3
70
RW
RDI0RI
B0
RW
F0
DBB10IN
31
RW
ACB00CR0
71
RW
RDI0SYN
B1
RW
F1
DBB10OU
32
RW
ACB00CR1
72
RW
RDI0IS
B2
RW
F2
ACB00CR2
73
RW
RDI0LT0
B3
RW
F3
33
DBB11FN
34
RW
ACB01CR3
74
RW
RDI0LT1
B4
RW
F4
DBB11IN
35
RW
ACB01CR0
75
RW
RDI0RO0
B5
RW
F5
DBB11OU
36
RW
ACB01CR1
76
RW
RDI0RO1
B6
RW
ACB01CR2
77
RW
37
B7
F6
CPU_F
F7
DCB12FN
38
RW
ACB02CR3
78
RW
RDI1RI
B8
RW
DCB12IN
39
RW
ACB02CR0
79
RW
RDI1SYN
B9
RW
DCB12OU
3A
RW
ACB02CR1
7A
RW
RDI1IS
BA
RW
ACB02CR2
7B
RW
RDI1LT0
BB
RW
FB
FC
3B
DCB13FN
3C
RW
ACB03CR3
7C
RW
RDI1LT1
BC
RW
DCB13IN
3D
RW
ACB03CR0
7D
RW
RDI1RO0
BD
RW
DCB13OU
3E
RW
ACB03CR1
7E
RW
RDI1RO1
BE
RW
ACB03CR2
7F
RW
3F
Blank fields are reserved and should not be accessed.
Document Number: 001-13105 Rev. *H
BF
RL
F8
F9
FLS_PR1
FA
RW
FD
CPU_SCR1
FE
#
CPU_SCR0
FF
#
# Access is bit specific.
Page 13 of 53
CY8CLED16
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8CLED16 EZ-Color device. For the most up-to-date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com.
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Refer to Table 20 for the electrical specifications
for the internal main oscillator (IMO) using SLIMO mode.
Figure 5. Voltage versus CPU Frequency, and IMO Frequency Trim Options
5.25
4.75
Vdd Voltage
Vdd Voltage
lid ng
Va rati n
e io
Op Reg
4.75
SLIMO Mode = 0
5.25
3.60
SLIMO
Mode=1
SLIMO
Mode=0
SLIMO
Mode=1
SLIMO
Mode=0
3.00
3.00
93 kHz
12 MHz
CPU Frequency
Document Number: 001-13105 Rev. *H
24 MHz
93 kHz
6 MHz
12 MHz
24 MHz
IMO Frequency
Page 14 of 53
CY8CLED16
Absolute Maximum Ratings
Symbol
TSTG
Description
Storage temperature
TBAKETEMP Bake temperature
Min
–55
Typ
25
Max
+100
Units
°C
–
125
C
–
See
package
label
72
TBAKETIME
Bake time
TA
VIO
Ambient temperature with power applied
Supply voltage on VDD relative to Vss
DC input voltage
See
package
label
–40
-0.5
Vss - 0.5
VIOZ
DC Voltage applied to Tri-state
Vss - 0.5
–
IMIO
IMAIO
Maximum current into any port pin
Maximum current into any port pin
configured as analog driver
Electro static discharge voltage
Latch up current
–25
–50
2000
–
VDD
ESD
LU
–
–
–
Notes
Higher storage temperatures
reduces data retention time.
Recommended storage
temperature is +25 °C ± 25 °C.
Extended duration storage
temperatures above 65 °C
degrade reliability.
Hours
–
–
+85
+6.0
VDD +
0.5
VDD +
0.5
+50
+50
°C
V
V
mA
mA
–
–
–
200
V
mA
V
Human body model ESD.
Operating Temperature
Symbol
TA
TJ
Description
Ambient temperature
Junction temperature
Document Number: 001-13105 Rev. *H
Min
–0
–0
Typ
–
–
Max
+85
+100
Units
°C
°C
Notes
The temperature rise from ambient to
junction is package specific. See
Thermal Impedances per Package on
page 42. The user must limit the
power consumption to comply with
this requirement.
Page 15 of 53
CY8CLED16
DC Electrical Characteristics
DC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40°C TA 85 °C, or 3.0 V to 3.6 V and -40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 6. DC Chip Level Specifications
Symbol
VDD
Description
Supply voltage
IDD
Supply current
–
8
14
mA
IDD3
Supply current
–
5
9
mA
IDDP
Supply current when IMO = 6 MHz using
SLIMO mode.
–
2
3
mA
ISB
Sleep (Mode) current with POR, LVD,
Sleep Timer, WDT, and internal slow
oscillator active.
Sleep (Mode) current with POR, LVD,
Sleep Timer, WDT, and internal slow
oscillator active.
Sleep (Mode) current with POR, LVD,
Sleep Timer, WDT, internal slow oscillator,
and 32 kHz crystal oscillator active.
Sleep (Mode) current with POR, LVD,
sleep timer, WDT, and 32 kHz crystal oscillator active.
Reference voltage (Bandgap)
–
3
10
A
–
4
25
A
–
4
12
A
–
5
27
A
1.28
1.3
1.32
V
ISBH
ISBXTL
ISBXTLH
VREF
Document Number: 001-13105 Rev. *H
Min
3.00
Typ
–
Max
5.25
Units
V
Notes
See DC POR and LVD
specifications, Table 3-15 on
page 27.
Conditions are 5.0 V, TA = 25 °C,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.366 kHz.
Conditions are VDD = 3.3 V,
TA = 25 °C, CPU = 3 MHz, SYSCLK
doubler disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.366 kHz.
Conditions are VDD = 3.3 V,
TA = 25 °C, CPU = 0.75 MHz,
SYSCLK doubler disabled,
VC1 = 0.375 MHz, VC2 = 23.44 kHz,
VC3 = 0.09 kHz.
Conditions are with internal slow
speed oscillator, VDD = 3.3 V,
–40°C TA 55 °C.
Conditions are with internal slow
speed oscillator, VDD = 3.3 V, 55 °C <
TA 85 °C.
Conditions are with properly loaded,
1 W max, 32.768 kHz crystal.
VDD = 3.3 V, –40 °C TA 55 °C.
Conditions are with properly loaded,
1 W max, 32.768 kHz crystal.
VDD = 3.3 V, 55 °C < TA 85 °C.
Trimmed for appropriate VDD.
Page 16 of 53
CY8CLED16
DC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and -40 °C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 7. DC GPIO Specifications
Symbol
RPU
RPD
VOH
Description
Pull-up Resistor
Pull-down Resistor
High output level
Min
4
4
VDD 1.0
Typ
5.6
5.6
–
Max
8
8
–
Units
k
k
V
VOL
Low output level
–
–
0.75
V
IOH
High level source current
10
–
–
mA
IOL
Low level sink current
25
–
–
mA
VIL
VIH
VH
IIL
CIN
Input low level
Input high level
Input hysterisis
Input leakage (Absolute Value)
Capacitive load on pins as input
–
2.1
–
–
–
–
–
60
1
3.5
0.8
–
–
10
V
V
mV
nA
pF
COUT
Capacitive load on pins as output
–
3.5
10
pF
Document Number: 001-13105 Rev. *H
Notes
IOH = 10 mA, VDD = 4.75 to 5.25 V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])). 80 mA maximum
combined IOH budget.
IOL = 25 mA, VDD = 4.75 to 5.25 V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])). 150 mA maximum
combined IOL budget.
VOH = VDD-1.0 V. See the limitations of the
total current in the Note for VOH.
VOL = 0.75 V. See the limitations of the total
current in the Note for VOL.
VDD = 3.0 to 5.25.
VDD = 3.0 to 5.25.
Gross tested to 1 A.
Package and pin dependent.
Temp = 25 °C.
Package and pin dependent.
Temp =25 °C.
Page 17 of 53
CY8CLED16
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and -40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
The operational amplifier is a component of both the Analog Continuous Time PSoC blocks and the analog switched capacitor PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5 V at
25 °C and are for design guidance only.
Table 8. 5-V DC Operational Amplifier Specifications
Symbol
Min
Typ
Max
Unit
Input offset voltage (absolute value)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = Medium, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
–
–
–
–
–
–
1.6
1.6
1.6
1.6
1.6
1.6
10
10
10
10
10
10
mV
mV
mV
mV
mV
mV
TCVOSOA
Average input offset voltage drift
–
4
23
µV/°C
I
EBOA
Input leakage current (port 0 analog pins)
–
200
–
pA
Gross tested to 1 µA
CINOA
Input capacitance (port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 °C
V
Common mode voltage range (All cases,
except Power = High, Opamp bias = High)
0
–
VDD
V
0.5
–
VDD – 0.5
V
The common-mode input voltage range
is measured through an analog output
buffer.
The specification includes the
limitations imposed by the
characteristics of the analog output
buffer.
VOSOA
CMOA
Description
Common mode voltage range (Power = High,
Opamp bias = High)
Notes
–
CMRROA
Common mode rejection ratio
60
–
–
dB
–
GOLOA
Open loop gain
80
–
–
dB
–
VDD – 0.01
–
–
V
–
–
–
0.1
V
–
VOHIGHOA High output voltage swing (internal signals)
VOLOWOA
Low output voltage swing (internal signals)
ISOA
Supply current (including associated
AGND buffer)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = Medium, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
µA
µA
µA
µA
µA
µA
Supply voltage rejection ratio
67
80
–
dB
PSRROA
Document Number: 001-13105 Rev. *H
–
VSS VIN (VDD – 2.25) or
(VDD – 1.25 V) VIN VDD.
Page 18 of 53
CY8CLED16
Table 9. 3.3-V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Min
Typ
Max
Unit
Input offset voltage (absolute value)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = Medium, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
–
–
–
–
–
–
1.4
1.4
1.4
1.4
1.4
–
10
10
10
10
10
–
mV
mV
mV
mV
mV
mV
TCVOSOA
Average input offset voltage drift
–
7
40
µV/°C
I
Notes
Power = High, Opamp bias = High
setting is not allowed for 3.3 V VDD
operation.
–
EBOA
Input leakage current (port 0 analog pins)
–
200
–
pA
Gross tested to 1 µA.
CINOA
Input capacitance (port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 °C
V
Common mode voltage range
0
–
VDD
V
The common-mode input voltage range
is measured through an analog output
buffer.
The specification includes the limitations
imposed by the characteristics of the
analog output buffer.
CMOA
CMRROA
Common mode rejection ratio
60
–
–
dB
–
GOLOA
Open loop gain
80
–
–
dB
–
VOHIGHOA
High output voltage swing (internal signals)
VDD – 0.01
–
–
V
–
VOLOWOA
Low output voltage swing (internal signals)
–
–
0.01
V
–
ISOA
Supply current
(including associated AGND buffer)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = Medium, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
–
–
–
–
–
–
150
300
600
1200
2400
–
200
400
800
1600
3200
–
µA
µA
µA
µA
µA
µA
Supply voltage rejection ratio
54
80
–
dB
PSRROA
Power = High, Opamp bias = High
setting is not allowed for 3.3 V VDD
operation.
VSS VIN (VDD – 2.25) or
(VDD – 1.25 V) VIN VDD
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and -40 °C TA 85 °C, respectively. Typical parameters apply to 5 V at 25 °C and are
for design guidance only.
Table 10. DC Low Power Comparator Specifications
Symbol
VREFLPC
ISLPC
VOSLPC
Description
Low power comparator (LPC) reference voltage
range
LPC supply current
LPC voltage offset
Document Number: 001-13105 Rev. *H
Min
0.2
Typ
–
Max
VDD - 1
Units
V
Notes
–
–
10
2.5
40
30
A
mV
–
–
–
Page 19 of 53
CY8CLED16
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and -40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 11. 5-V DC Analog Output Buffer Specifications
Symbol
Description
VOSOB
Input offset voltage (absolute value)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
TCVOSOB
Average input offset voltage drift
VCMOB
Common-mode input voltage range
ROUTOB
Output resistance
Power = Low
Power = High
VOHIGHOB
High output voltage swing
(Load = 32 ohms to VDD/2)
Power = Low
Power = High
VOLOWOB
Min
Typ
Max
Unit
–
–
–
–
3.2
3.2
3.2
3.2
18
18
18
18
mV
mV
mV
mV
Notes
–
–
5.5
26
µV/°C
–
0.5
–
VDD – 1.0
V
–
–
–
–
–
1
1
–
–
0.5 × VDD + 1.3
0.5 × VDD + 1.3
–
–
–
–
V
V
Low output voltage swing
(Load = 32 ohms to VDD/2)
Power = Low
Power = High
–
–
–
–
–
0.5 × VDD – 1.3
0.5 × VDD – 1.3
V
V
ISOB
Supply current including bias cell (no load)
Power = Low
Power = High
–
–
1.1
2.6
2
5
mA
mA
PSRROB
Supply voltage rejection ratio
40
64
CL
Load capacitance
–
–
Min
Typ
–
dB
–
200
pF
This specification
applies to the
external circuit
driven by the analog
output buffer.
Max
Unit
Table 12. 3.3-V DC Analog Output Buffer Specifications
Symbol
Description
VOSOB
Input offset voltage (absolute value)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
–
–
–
–
3.2
3.2
6
6
20
20
25
25
mV
mV
mV
mV
TCVOSOB
Average input offset voltage drift
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
–
–
–
–
8
8
12
12
32
32
41
41
µV/°C
µV/°C
µV/°C
µV/°C
0.5
–
VDD – 1.0
V
–
–
–
–
10
10
W
W
VCMOB
Common-mode input voltage range
ROUTOB
Output resistance
Power = Low
Power = High
VOHIGHOB
High output voltage swing
(Load = 32 ohms to VDD/2)
Power = Low
Power = High
VOLOWOB
Low output voltage swing
(Load = 32 ohms to VDD/2)
Power = Low
Power = High
Document Number: 001-13105 Rev. *H
Notes
High power setting
is not
recommended.
High power setting
is not
recommended.
–
–
–
0.5 × VDD + 1.0
0.5 × VDD + 1.0
–
–
–
–
V
V
–
–
–
–
–
0.5 × VDD – 1.0
0.5 × VDD – 1.0
V
V
Page 20 of 53
CY8CLED16
Table 12. 3.3-V DC Analog Output Buffer Specifications (continued)
Min
Typ
Max
Unit
ISOB
Symbol
Supply current including bias cell (no load)
Power = Low
Power = High
Description
–
–
0.8
2.0
1
5
mA
mA
PSRROB
Supply voltage rejection ratio
60
64
–
dB
CL
Load capacitance
–
–
200
pF
Notes
–
This specification
applies to the
external circuit
driven by the
analog output
buffer.
DC Switch Mode Pump Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 13. DC Switch Mode Pump (SMP) Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VPUMP 5V
5 V output voltage at VDD from Pump
4.75
5.0
5.25
V
Configured as in Note 3.
Average, neglecting ripple. SMP
trip voltage is set to 5.0 V.
VPUMP 3V
3 V output voltage at VDD from Pump
3.00
3.25
3.60
V
Configured as in Note 3.
Average, neglecting ripple. SMP
trip voltage is set to 3.25 V.
IPUMP
Available output current
VBAT = 1.5 V, VPUMP = 3.25 V
VBAT = 1.8 V, VPUMP = 5.0 V
8
5
–
–
–
–
mA
mA
Configured as in Note 3.
SMP trip voltage is set to 3.25 V.
SMP trip voltage is set to 5.0 V.
VBAT5V
Input voltage range from battery
1.8
–
5.0
V
Configured as in Note 3. SMP trip
voltage is set to 5.0 V.
VBAT3V
Input voltage range from battery
1.0
3–
3.3
V
Configured as in Note 3. SMP trip
voltage is set to 3.25 V.
VBATSTART
Minimum input voltage from battery to start
Pump
1.2
–
–
V
Configured as in Note 3. 0 °C
TA 100. 1.25 V at TA = -40 °C.
VPUMP_Line
Line regulation (over VBAT range)
–
5
–
%VO
Configured as in Note 3. VO is the
“VDD Value for PUMP Trip”
specified by the VM[2:0] setting in
Table 17, “DC POR, SMP, and
LVD Specifications,” on page 28.
VPUMP_Load
Load regulation
–
5
–
%VO
Configured as in Note 3. VO is the
“VDD Value for PUMP Trip”
specified by the VM[2:0] setting in
Table 17, “DC POR, SMP, and
LVD Specifications,” on page 28.
VPUMP_Rippl Output Voltage Ripple (depends on
capacitor/load)
e
–
100
–
mVpp
Configured as in Note 3. Load is
5 mA.
E3
Efficiency
35
50
–
%
Configured as in Note 3. Load is
5 mA. SMP trip voltage is set to
3.25 V.
FPUMP
Switching Frequency
–
1.4
–
MHz
–
DCPUMP
Switching Duty Cycle
–
50
–
%
–
Note
3. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 6.
Document Number: 001-13105 Rev. *H
Page 21 of 53
CY8CLED16
Figure 6. Basic Switch Mode Pump Circuit
D1
Vdd
L1
V BAT
+
V PUMP
C1
SMP
Battery
EZ-Color
Vss
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
The guaranteed specifications are measured through the analog continuous time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the analog reference control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 14. 5-V DC Analog Reference Specifications
Reference
ARF_CR[5:3]
Reference Power
Settings
Symbol
Reference
Description
Min
RefPower = High
Opamp bias = High
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.228
VDD/2 + 1.290 VDD/2 + 1.352
VAGND
AGND
VDD/2
VDD/2 – 0.078
VDD/2 – 0.007
VDD/2 + 0.063
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.336
VDD/2 – 1.295
VDD/2 – 1.250
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.224
VDD/2 + 1.293 VDD/2 + 1.356
V
VAGND
AGND
VDD/2
VDD/2 – 0.056
VDD/2 – 0.005
VDD/2 + 0.043
V
RefPower = High
Opamp bias = Low
0b000
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Typ
Max
Unit
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.338
VDD/2 – 1.298
VDD/2 – 1.255
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.226
V
VAGND
AGND
VDD/2
VDD/2 – 0.057
VDD/2 + 1.293 VDD/2 + 1.356
VDD/2 – 0.006 VDD/2 + 0.044
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.337
VDD/2 – 1.298
VDD/2 – 1.256
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.226
V
VAGND
AGND
VDD/2
VDD/2 – 0.047
VDD/2 + 1.294 VDD/2 + 1.359
VDD/2 – 0.004 VDD/2 + 0.035
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.338
VDD/2 – 1.299
V
Document Number: 001-13105 Rev. *H
VDD/2 – 1.258
V
Page 22 of 53
CY8CLED16
Table 14. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR[5:3]
Reference Power
Settings
Symbol
Reference
RefPower = High
Opamp bias = High
VREFHI
Ref High
RefPower = High
Opamp bias = Low
0b001
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b010
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Description
P2[4] + P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
Min
Typ
Max
Unit
P2[4] + P2[6] –
0.085
P2[4] + P2[6] –
0.016
P2[4] + P2[6]
+ 0.044
V
P2[4]
P2[4]
VAGND
AGND
VREFLO
Ref Low
P2[4] – P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] – P2[6] –
0.022
P2[4] – P2[6] + P2[4] – P2[6] +
0.010
0.055
V
VREFHI
Ref High
P2[4] + P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] + P2[6] –
0.077
P2[4] + P2[6] –
0.010
P2[4] + P2[6]
+ 0.051
V
P2[4]
P2[4]
P2[4]
P2[4]
–
VAGND
AGND
VREFLO
Ref Low
P2[4] – P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] – P2[6] –
0.022
P2[4] – P2[6] + P2[4] – P2[6] +
0.005
0.039
V
VREFHI
Ref High
P2[4] + P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] + P2[6] –
0.070
P2[4] + P2[6] –
0.010
P2[4] + P2[6]
+ 0.050
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] – P2[6] –
0.022
P2[4] – P2[6] + P2[4] – P2[6] +
0.005
0.039
V
VREFHI
Ref High
P2[4] + P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] + P2[6] –
0.070
P2[4] + P2[6] –
0.007
P2[4] + P2[6]
+ 0.054
V
P2[4]
P2[4]
P2[4]
P2[4]
VAGND
AGND
VREFLO
Ref Low
P2[4] – P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
VREFHI
Ref High
VDD
VAGND
AGND
P2[4]
VDD/2
P2[4]
P2[4]
P2[4] – P2[6] –
0.022
P2[4] – P2[6] + P2[4] – P2[6] +
0.002
0.032
–
–
V
VDD – 0.037
VDD – 0.009
VDD
V
VDD/2 – 0.061
VDD/2 – 0.006
VDD/2 + 0.047
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.007
VSS + 0.028
V
VREFHI
Ref High
VDD
VDD – 0.039
VDD – 0.006
VDD
V
VAGND
AGND
VDD/2 – 0.049
VDD/2 – 0.005
VDD/2 + 0.036
V
VDD/2
VREFLO
Ref Low
VSS
VSS
VSS + 0.005
VSS + 0.019
V
VREFHI
Ref High
VDD
VDD – 0.037
VDD – 0.007
VDD
V
VAGND
AGND
VDD/2 – 0.054
VDD/2 – 0.005
VDD/2 + 0.041
V
VDD/2
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.024
V
VREFHI
Ref High
VDD
VDD – 0.042
VDD – 0.005
VDD
V
VDD/2 – 0.046
VDD/2 – 0.004
VDD/2 + 0.034
V
VSS
VSS + 0.004
VSS + 0.017
V
VAGND
AGND
VREFLO
Ref Low
Document Number: 001-13105 Rev. *H
VDD/2
VSS
Page 23 of 53
CY8CLED16
Table 14. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR[5:3]
Reference Power
Settings
Symbol
Reference
RefPower = High
Opamp bias = High
VREFHI
Ref High
3 × Bandgap
RefPower = High
Opamp bias = Low
0b011
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b100
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Description
Min
Typ
Max
Unit
3.788
3.891
3.986
V
VAGND
AGND
2 × Bandgap
2.500
2.604
3.699
V
VREFLO
Ref Low
Bandgap
1.257
1.306
1.359
V
VREFHI
Ref High
3 × Bandgap
3.792
3.893
3.982
V
2 × Bandgap
2.518
2.602
2.692
V
Bandgap
1.256
1.302
1.354
V
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
3 × Bandgap
3.795
3.894
3.993
V
VAGND
AGND
2 × Bandgap
2.516
2.603
2.698
V
VREFLO
Ref Low
Bandgap
1.256
1.303
1.353
V
VREFHI
Ref High
3 × Bandgap
3.792
3.895
3.986
V
VAGND
AGND
2 × Bandgap
2.522
2.602
2.685
V
VREFLO
Ref Low
Bandgap
1.255
1.301
1.350
V
VREFHI
Ref High
2 × Bandgap +
P2[6] (P2[6] =
1.3 V)
2.495 – P2[6]
2.586 – P2[6]
2.657 – P2[6]
V
VAGND
AGND
2.502
2.604
2.719
V
VREFLO
Ref Low
2 × Bandgap –
P2[6] (P2[6] =
1.3 V)
2.531 – P2[6]
2.611 – P2[6]
2.681 – P2[6]
V
VREFHI
Ref High
2 × Bandgap +
P2[6] (P2[6] =
1.3 V)
2.500 – P2[6]
2.591 – P2[6]
2.662 – P2[6]
V
2 × Bandgap
VAGND
AGND
2.519
2.602
2.693
V
VREFLO
Ref Low
2 × Bandgap –
P2[6] (P2[6] =
1.3 V)
2.530 – P2[6]
2.605 – P2[6]
2.666 – P2[6]
V
VREFHI
Ref High
2 × Bandgap +
P2[6] (P2[6] =
1.3 V)
2.503 – P2[6]
2.592 – P2[6]
2.662 – P2[6]
V
2 × Bandgap
VAGND
AGND
2.517
2.603
2.698
V
VREFLO
Ref Low
2 × Bandgap –
P2[6] (P2[6] =
1.3 V)
2.529 – P2[6]
2.606 – P2[6]
2.665 – P2[6]
V
VREFHI
Ref High
2 × Bandgap +
P2[6] (P2[6] =
1.3 V)
2.505 – P2[6]
2.594 – P2[6]
2.665 – P2[6]
V
VAGND
AGND
2.525
2.602
2.685
V
VREFLO
Ref Low
2.528 – P2[6]
2.603 – P2[6]
2.661 – P2[6]
V
Document Number: 001-13105 Rev. *H
2 × Bandgap
2 × Bandgap
2 × Bandgap –
P2[6] (P2[6] =
1.3 V)
Page 24 of 53
CY8CLED16
Table 14. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR[5:3]
Reference Power
Settings
Symbol
Reference
RefPower = High
Opamp bias = High
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
RefPower = High
Opamp bias = Low
0b101
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b110
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b111
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Description
Min
Typ
Max
Unit
P2[4] + 1.222
P2[4] + 1.290
P2[4] + 1.343
V
P2[4]
P2[4]
P2[4]
–
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.331
P2[4] – 1.295
P2[4] – 1.254
V
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.226
P2[4] + 1.293
P2[4] + 1.347
V
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4]
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4]
P2[4] – 1.331
P2[4] – 1.298
P2[4] – 1.259
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.227
P2[4] + 1.294
P2[4] + 1.347
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4]
P2[4] – 1.331
P2[4] – 1.298
P2[4] – 1.259
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.228
P2[4] + 1.295
P2[4] + 1.349
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – 1.332
P2[4] – 1.299
P2[4] – 1.260
V
VREFHI
Ref High
VAGND
AGND
P2[4]
P2[4] – Bandgap
(P2[4] = VDD/2)
2 × Bandgap
2.535
2.598
2.644
V
Bandgap
1.227
1.305
1.398
V
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.009
VSS + 0.038
VREFHI
Ref High
2 × Bandgap
2.530
2.598
2.643
V
VAGND
AGND
Bandgap
1.244
1.303
1.370
V
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.005
VSS + 0.024
VREFHI
Ref High
2 × Bandgap
2.532
2.598
2.644
V
VAGND
AGND
Bandgap
1.239
1.304
1.380
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.026
V
VREFHI
Ref High
2 × Bandgap
2.528
2.598
2.645
V
Bandgap
1.249
1.302
1.362
V
VSS
VSS + 0.004
VSS + 0.018
V
4.155
4.234
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.041
1.6 × Bandgap
1.998
2.083
2.183
V
VSS
VSS + 0.010
VSS + 0.038
V
4.153
4.236
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.047
1.6 × Bandgap
2.012
2.082
2.157
V
VSS
VSS + 0.006
VSS + 0.024
V
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
3.2 × Bandgap
4.049
4.154
4.238
V
VAGND
AGND
1.6 × Bandgap
2.008
2.083
2.165
V
VREFLO
Ref Low
VSS
VSS + 0.006
VSS + 0.026
V
VREFHI
Ref High
3.2 × Bandgap
4.047
4.154
4.238
V
VAGND
AGND
1.6 × Bandgap
2.016
2.081
2.150
V
VREFLO
Ref Low
VSS
VSS + 0.004
VSS + 0.018
V
Document Number: 001-13105 Rev. *H
VSS
VSS
VSS
Page 25 of 53
CY8CLED16
Table 15. 3.3-V DC Analog Reference Specifications
Reference
ARF_CR[5:3]
Reference Power
Settings
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b000
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Symbol Reference
Description
Min
Typ
Max
Unit
VDD/2 + BandGap
VDD/2 + 1.225
VDD/2 + 1.292
VDD/2 + 1.361
V
VDD/2
VDD/2 – 0.067
VDD/2 – 0.002
VDD/2 + 0.063
V
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
VDD/2 – BandGap
VDD/2 – 1.35
VDD/2 – 1.293
VDD/2 – 1.210
V
VREFHI
Ref High
VDD/2 + BandGap
VDD/2 + 1.218
VDD/2 + 1.294
VDD/2 + 1.370
V
VAGND
AGND
VDD/2
VDD/2 – 0.038
VDD/2 – 0.001
VDD/2 + 0.035
V
VREFLO
Ref Low
VDD/2 – BandGap
VDD/2 – 1.329
VDD/2 – 1.296
VDD/2 – 1.259
V
VREFHI
Ref High
VDD/2 + BandGap
VDD/2 + 1.221
VDD/2 + 1.294
VDD/2 + 1.366
V
VAGND
AGND
VDD/2
VDD/2 – 0.050
VDD/2 – 0.002
VDD/2 + 0.046
V
VREFLO
Ref Low
VDD/2 – BandGap
VDD/2 – 1.331
VDD/2 – 1.296
VDD/2 – 1.260
V
VREFHI
Ref High
VDD/2 + BandGap
VDD/2 + 1.226
VDD/2 + 1.295
VDD/2 + 1.365
V
VAGND
AGND
VDD/2
VDD/2 – 0.028
VDD/2 – 0.001
VDD/2 + 0.025
V
VREFLO
Ref Low
VDD/2 – BandGap
VDD/2 – 1.329
VDD/2 – 1.297
VDD/2 – 1.262
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4]
= VDD/2, P2[6] =
P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] +
0.098
0.018
0.055
V
VAGND
AGND
VREFLO
Ref Low
P2[4] – P2[6] (P2[4] P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] +
= VDD/2, P2[6] =
0.055
0.013
0.086
VREFHI
Ref High
P2[4] + P2[6] (P2[4] P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] +
= VDD/2, P2[6] =
0.082
0.011
0.050
0.5 V)
RefPower = High
Opamp bias = High
P2[4]
P2[4]
P2[4]
P2[4]
–
V
0.5 V)
V
0.5 V)
RefPower = High
Opamp bias = Low
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
P2[4]
P2[4]
P2[4]
P2[4]
P2[4] – P2[6] (P2[4] P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] +
= VDD/2, P2[6] =
0.037
0.006
0.054
–
V
0.5 V)
0b001
P2[4] + P2[6] (P2[4] P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] +
= VDD/2, P2[6] =
0.079
0.012
0.047
V
0.5 V)
RefPower = Med
Opamp bias = High
P2[4]
P2[4]–P2[6] (P2[4]
= VDD/2, P2[6] =
P2[4]
P2[4]
P2[4]
–
P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] +
0.038
0.006
0.057
V
P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] +
0.080
0.008
0.055
V
0.5 V)
P2[4]+P2[6] (P2[4]
= VDD/2, P2[6] =
0.5 V)
RefPower = Med
Opamp bias = Low
P2[4]
P2[4]–P2[6] (P2[4]
= VDD/2, P2[6] =
P2[4]
P2[4]
P2[4]
P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] +
0.032
0.003
0.042
–
V
0.5 V)
Document Number: 001-13105 Rev. *H
Page 26 of 53
CY8CLED16
Table 15. 3.3-V DC Analog Reference Specifications (continued)
Reference
ARF_CR[5:3]
Reference Power
Settings
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b010
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Symbol Reference
Description
Min
Typ
Max
Unit
VDD – 0.06
VDD – 0.010
VDD
V
VDD/2 – 0.05
VDD/2 – 0.002
VDD/2 + 0.040
V
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
Vss
Vss
Vss + 0.009
Vss + 0.056
V
VREFHI
Ref High
VDD
VDD – 0.060
VDD – 0.006
VDD
V
VAGND
AGND
VDD/2 – 0.028
VDD/2 – 0.001
VDD/2 + 0.025
V
VREFLO
Ref Low
Vss
Vss
Vss + 0.005
Vss + 0.034
V
VREFHI
Ref High
VDD
VDD – 0.058
VDD – 0.008
VDD
V
VAGND
AGND
VDD/2 – 0.037
VDD/2 – 0.002
VDD/2 + 0.033
V
VREFLO
Ref Low
Vss
Vss
Vss + 0.007
Vss + 0.046
V
VREFHI
Ref High
VDD
VDD – 0.057
VDD – 0.006
VDD
V
VAGND
AGND
VDD/2 – 0.025
VDD/2 – 0.001
VDD/2 + 0.022
V
VDD
VDD/2
VDD/2
VDD/2
VDD/2
VREFLO
Ref Low
0b011
All power settings.
Not allowed for 3.3 V
–
–
–
Vss
–
Vss + 0.004
–
Vss + 0.030
–
V
–
0b100
All power settings.
Not allowed for 3.3 V
–
–
–
–
–
–
–
VREFHI
Ref High
P2[4] + 1.213
P2[4] + 1.291
P2[4] + 1.367
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
V
VREFLO
Ref Low
P2[4] – BandGap
(P2[4] = VDD/2)
P2[4] – 1.333
P2[4] – 1.294
P2[4] – 1.208
V
VREFHI
Ref High
P2[4] + BandGap
(P2[4] = VDD/2)
P2[4] + 1.217
P2[4] + 1.294
P2[4] + 1.368
V
P2[4]
P2[4]
P2[4]
V
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b101
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Vss
P2[4] + BandGap
(P2[4] = VDD/2)
P2[4]
VAGND
AGND
VREFLO
Ref Low
P2[4] – BandGap
(P2[4] = VDD/2)
P2[4] – 1.320
P2[4] – 1.296
P2[4] – 1.261
V
VREFHI
Ref High
P2[4] + BandGap
(P2[4] = VDD/2)
P2[4] + 1.217
P2[4] + 1.294
P2[4] + 1.369
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
V
VREFLO
Ref Low
P2[4] – BandGap
(P2[4] = VDD/2)
P2[4] – 1.322
P2[4] – 1.297
P2[4] – 1.262
V
VREFHI
Ref High
P2[4] + BandGap
(P2[4] = VDD/2)
P2[4] + 1.219
P2[4] + 1.295
P2[4] + 1.37
V
P2[4]
P2[4]
P2[4]
V
P2[4] – 1.324
P2[4] – 1.297
P2[4] – 1.262
V
VAGND
AGND
VREFLO
Ref Low
Document Number: 001-13105 Rev. *H
P2[4]
P2[4]
P2[4]
P2[4] – BandGap
(P2[4] = VDD/2)
Page 27 of 53
CY8CLED16
Table 15. 3.3-V DC Analog Reference Specifications (continued)
Reference
ARF_CR[5:3]
Reference Power
Settings
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b110
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
0b111
Symbol Reference
VREFHI
Ref High
VAGND
AGND
Description
Min
Typ
Max
Unit
2 × BandGap
2.507
2.598
2.698
V
BandGap
1.203
1.307
1.424
V
Vss
Vss + 0.012
Vss + 0.067
V
VREFLO
Ref Low
Vss
VREFHI
Ref High
2 × BandGap
2.516
2.598
2.683
V
VAGND
AGND
BandGap
1.241
1.303
1.376
V
VREFLO
Ref Low
Vss
Vss
Vss + 0.007
Vss + 0.040
V
VREFHI
Ref High
2 × BandGap
2.510
2.599
2.693
V
VAGND
AGND
BandGap
1.240
1.305
1.374
V
VREFLO
Ref Low
Vss
Vss
Vss + 0.008
Vss + 0.048
V
VREFHI
Ref High
2 × BandGap
2.515
2.598
2.683
V
BandGap
1.258
1.302
1.355
V
Vss
–
Vss + 0.005
–
Vss + 0.03
–
V
–
VAGND
AGND
VREFLO
Ref Low
–
–
All power settings.
Not allowed for 3.3 V.
Vss
–
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 16. DC Analog PSoC Block Specifications
Symbol
RCT
CSC
Description
Resistor Unit Value (Continuous Time)
Capacitor Unit Value (Switched Capacitor)
Min
–
–
Typ
12.2
80
Max
–
–
Units
k
fF
Notes
DC POR, SMP, and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 17. DC POR, SMP, and LVD Specifications
Symbol
Description
VPPOR0R
VPPOR1R
VPPOR2R
VDD Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VPPOR0
VPPOR1
VPPOR2
VDD Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VPH0
VPH1
VPH2
PPOR Hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
Min
Typ
Max
Units
–
2.91
4.39
4.55
–
V
V
V
–
2.82
4.39
4.55
–
V
V
V
–
–
–
92
0
0
–
–
–
mV
mV
mV
Notes
Notes
4. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
5. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
Document Number: 001-13105 Rev. *H
Page 28 of 53
CY8CLED16
Table 17. DC POR, SMP, and LVD Specifications (continued)
Symbol
Description
Min
Typ
Max
Units
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VDD Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.86
2.96
3.07
3.92
4.39
4.55
4.63
4.72
2.92
3.02
3.13
4.00
4.48
4.64
4.73
4.81
2.98[4]
3.08
3.20
4.08
4.57
4.74[5]
4.82
4.91
V
V
V
V
V
V
V
V
V
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
VDD Value for SMP Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.96
3.03
3.18
4.11
4.55
4.63
4.72
4.90
3.02
3.10
3.25
4.19
4.64
4.73
4.82
5.00
3.08
3.16
3.32
4.28
4.74
4.82
4.91
5.10
V
V
V
V
V
V
V
V
V
Document Number: 001-13105 Rev. *H
Notes
Page 29 of 53
CY8CLED16
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –-40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 18. DC Programming Specifications
Symbol
Description
VDDP
VDD for programming and erase
VDDLV
Low VDD for verify
VDDHV
High VDD for verify
VDDIWRITE
Supply voltage for flash write operation
IDDP
VILP
Min
Typ
Max
Units
Notes
4.5
5
5.5
V
This specification applies to the
functional requirements of external
programmer tools.
3.0
3.1
3.2
V
This specification applies to the
functional requirements of external
programmer tools.
5.1
5.2
5.3
V
This specification applies to the
functional requirements of external
programmer tools.
3.15
–
5.25
V
This specification applies to this
device when it is executing internal
flash writes.
Supply current during programming or verify
–
10
30
mA
Input Low-voltage during programming or verify
–
–
0.8
V
VIHP
Input High-voltage during programming or verify
2.2
–
–
V
IILP
Input Current when Applying VILP to P1[0] or P1[1]
During Programming or Verify
–
–
0.2
mA
Driving internal pull-down resistor.
IIHP
Input Current when Applying VIHP to P1[0] or P1[1]
During Programming or Verify
–
–
1.5
mA
Driving internal pull-down resistor.
VOLV
Output Low-voltage during programming or verify
–
–
Vss +
0.75
V
VOHV
Output High-voltage during programming or verify
VDD - 1.0
–
VDD
V
FlashENPB
flash endurance (per block)
50,000[6]
–
–
–
Erase/write cycles per block.
FlashENT
flash endurance (total)[7]
1,800,000
–
–
–
Erase/write cycles.
FlashDR
flash data retention
10
–
–
Years
DC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 19. DC I2C Specifications
Min
Typ
Max
Units
VILI2C[8]
Parameter
Input low level
Description
–
–
0.3 × VDD
V
Notes
–
–
0.25 × VDD
V
4.75 V VDD 5.25 V
VIHI2C[8]
Input high level
0.7 × VDD
–
–
V
3.0 V VDD 5.25 V
3.0 V VDD 3.6 V
Notes
6. The 50,000 cycle flash endurance per block is only guaranteed if the Flash is operating within one voltage range. Voltage ranges are 3.0 V to 3.6 V and
4.75 V to 5.25 V.
7. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block
ever sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (flashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
8. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO specifications sections.The I2C GPIO pins also meet the mentioned specs.
Document Number: 001-13105 Rev. *H
Page 30 of 53
CY8CLED16
AC Electrical Characteristics
AC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Note See the individual user module data sheets for information on maximum frequencies for user modules.
Table 20. AC Chip-Level Specifications
Symbol
FIMO24
Description
Internal main oscillator frequency for 24
MHz
Min
23.4
Typ
24
Max
24.6[9,10,11]
Units
MHz
FIMO6
Internal main oscillator frequency for 6
MHz
5.5
6
6.5[9,10,11]
MHz
FCPU1
FCPU2
F48M
CPU frequency (5 V Nominal)
CPU frequency (3.3 V Nominal)
Digital PSoC block frequency
0.0914
0.0914
0
24
12
48
24.6[9,10]
12.3[10,11]
49.2[9,10,12]
MHz
MHz
MHz
F24M
F32K1
F32K_U
Digital PSoC block frequency
Internal low speed oscillator frequency
Internal low speed oscillator untrimmed
frequency
0
15
5
24
32
–
24.6[10,12]
64
100
MHz
kHz
kHz
DCILO
F32K2
Internal low speed oscillator duty cycle
External crystal oscillator
20
–
50
32.768
80
–
%
kHz
FPLL
PLL frequency
–
23.986
–
MHz
TPLLSLEW
TPLLSLEWL
PLL lock time
PLL lock time for low gain setting
0.5
0.5
–
–
10
50
ms
ms
Notes
Trimmed for 5 V or 3.3 V operation
using factory trim values. See the
figure on page 19. SLIMO
Mode = 0.
Trimmed for 5 V or 3.3 V operation
using factory trim values. See the
figure on page 19. SLIMO
Mode = 1.
–
–
Refer to the AC Digital Block Specifications below.
–
–
After a reset and before the M8C
starts to run, the ILO is not
trimmed. See the System Resets
section of the PSoC Technical
Reference Manual for details on
timing this.
–
Accuracy is capacitor and crystal
dependent. 50% duty cycle.
A multiple (x732) of crystal
frequency.
–
–
OW
TOS
TOSACC
External crystal oscillator startup to 1%
External crystal oscillator startup to 100
ppm
–
–
250
300
500
600
ms
ms
TXRST
DC24M
Step24M
External reset pulse width
24 MHz duty cycle
24 MHz trim step size
10
40
–
–
50
50
–
60
–
s
%
kHz
–
The crystal oscillator frequency is
within 100 ppm of its final value by
the end of the Tosacc period.
Correct operation assumes a
properly loaded 1 W maximum
drive level 32.768 kHz crystal. 3.0V
VDD 5.5 V, –40 °C TA 85 °C.
–
–
–
Notes
9. 4.75 V < VDD < 5.25 V.
10. Accuracy derived from Internal Main Oscillator with appropriate trim for VDD range.
11. 3.0 V < VDD < 3.6 V.
12. See the individual user module data sheets for information on maximum frequencies for user modules.
13. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-13105 Rev. *H
Page 31 of 53
CY8CLED16
Table 20. AC Chip-Level Specifications (continued)
Symbol
Fout48M
Description
48 MHz Output Frequency
Min
46.8
Typ
48.0
Max
49.2[9, 11]
Units
MHz
FMAX
Maximum frequency of signal on row
input or row output.
Power Supply Slew Rate
–
–
12.3
MHz
–
–
250
V/ms
TPOWERUP
Time from End of POR to CPU Executing
Code
–
16
100
ms
tjit_IMO[13]
24 MHz IMO cycle-to-cycle jitter (RMS)
24 MHz IMO long term N cycle-to-cycle
jitter (RMS)
24 MHz IMO period jitter (RMS)
24 MHz IMO cycle-to-cycle jitter (RMS)
24 MHz IMO long term N cycle-to-cycle
jitter (RMS)
24 MHz IMO period jitter (RMS)
–
–
200
300
700
900
ps
–
–
–
100
200
300
400
800
1200
–
100
700
SRPOWER_
Notes
Trimmed. Utilizing factory trim
values.
–
VDD slew rate during power up.
UP
tjit_PLL [13]
Power up from 0V. See the System
Resets section of the PSoC
Technical Reference Manual.
N = 32
–
–
ps
N = 32
–
Figure 7. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 8. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 9. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Document Number: 001-13105 Rev. *H
Page 32 of 53
CY8CLED16
AC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 21. AC GPIO Specifications
Symbol
FGPIO
TRiseF
TFallF
TRiseS
TFallS
Description
GPIO operating frequency
Rise time, normal strong mode, Cload = 50 pF
Fall time, normal strong mode, Cload = 50 pF
Rise time, slow strong mode, Cload = 50 pF
Fall time, slow strong mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12.3
18
18
–
–
Units
MHz
ns
ns
ns
ns
Notes
Normal Strong Mode
VDD = 4.75 to 5.25 V, 10% - 90%
VDD = 4.75 to 5.25 V, 10% - 90%
VDD = 3 to 5.25 V, 10% - 90%
VDD = 3 to 5.25 V, 10% - 90%
Figure 10. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
Document Number: 001-13105 Rev. *H
TFallF
TFallS
Page 33 of 53
CY8CLED16
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 22. 5-V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising Settling Time to 0.1% for a 1 V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Settling Time to 0.1% for a 1 V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Rising Slew Rate (20% to 80%) of a 1 V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Slew Rate (20% to 80%) of a 1 V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
Min
Typ
Max
Units
–
–
–
–
–
–
3.9
0.72
0.62
s
s
s
–
–
–
–
–
–
5.9
0.92
0.72
s
s
s
0.15
1.7
6.5
–
–
–
–
–
–
V/s
V/s
V/s
0.01
0.5
4.0
–
–
–
–
–
–
V/s
V/s
V/s
0.75
3.1
5.4
–
–
–
–
100
–
–
–
–
MHz
MHz
MHz
nV/rt-Hz
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
s
s
–
–
–
–
5.41
0.72
s
s
0.31
2.7
–
–
–
–
V/s
V/s
0.24
1.8
–
–
–
–
V/s
V/s
0.67
2.8
–
–
–
100
–
–
–
MHz
MHz
nV/rt-Hz
Notes
–
–
–
–
–
–
Table 23. 3.3-V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising settling time to 0.1% of a 1 V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling settling time to 0.1% of a 1 V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Rising Slew Rate (20% to 80%) of a 1 V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling slew rate (20% to 80%) of a 1 V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Gain bandwidth product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
Document Number: 001-13105 Rev. *H
Notes
–
–
–
–
–
–
Page 34 of 53
CY8CLED16
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 11. Typical AGND Noise with P2[4] Bypass
nV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 12. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 001-13105 Rev. *H
0.01
0.1
Freq (kHz)
1
10
100
Page 35 of 53
CY8CLED16
AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and -40 °C TA 85 °C or 3.0 V to 3.6 V and -40 °C TA 85 °C, respectively. Typical parameters apply to 5 V at 25 °C and are for
design guidance only.
Table 24. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
s
Notes
50 mV overdrive comparator
reference set within VREFLPC.
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and -40 °C TA 85 °C, or 3.0 V to 3.6 V and -40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 25. AC Digital Block Specifications
Function
All functions
Timer
Description
Min
Typ
Max
Unit
VDD 4.75 V
–
–
49.2
MHz
VDD < 4.75 V
–
–
24.6
MHz
MHz
Input clock frequency
No capture, VDD 4.75 V
–
–
49.2
No capture, VDD < 4.75 V
–
–
24.6
MHz
With capture
–
–
24.6
MHz
50[14]
–
–
ns
Capture pulse width
Counter
Input clock frequency
No enable input, VDD 4.75 V
–
–
49.2
MHz
No enable input, VDD < 4.75 V
–
–
24.6
MHz
With enable input
–
–
24.6
MHz
[14]
–
–
ns
Enable input pulse width
Dead Band
Notes
Block input clock frequency
50
Kill pulse width
Asynchronous restart mode
20
–
–
ns
Synchronous restart mode
[14]
50
–
–
ns
Disable mode
50[14]
–
–
ns
Input clock frequency
CRCPRS
(PRS Mode)
VDD 4.75 V
–
–
49.2
MHz
VDD < 4.75 V
–
–
24.6
MHz
VDD 4.75 V
–
–
49.2
MHz
VDD < 4.75 V
–
–
24.6
MHz
Input clock frequency
CRCPRS
(CRC Mode)
Input clock frequency
–
–
24.6
MHz
SPIM
Input clock frequency
–
–
8.2
MHz
The SPI serial clock (SCLK) frequency is equal to the
input clock frequency divided by 2
SPIS
Input clock (SCLK) frequency
–
–
4.1
MHz
The input clock is the SPI SCLK in SPIS mode
Width of SS_negated between
transmissions
50[14]
–
–
ns
Note
14. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-13105 Rev. *H
Page 36 of 53
CY8CLED16
Table 25. AC Digital Block Specifications (continued)
Function
Transmitter
Receiver
Description
Min
Typ
Max
Unit
Input clock frequency
VDD 4.75 V, 2 stop bits
–
–
49.2
VDD 4.75 V, 1 stop bit
–
–
24.6
MHz
VDD < 4.75 V
–
–
24.6
MHz
VDD 4.75 V, 2 stop bits
–
–
49.2
MHz
VDD 4.75 V, 1 stop bit
–
–
24.6
MHz
VDD < 4.75 V
–
–
24.6
MHz
MHz
Input clock frequency
Notes
The baud rate is equal to the input clock frequency
divided by 8
The baud rate is equal to the input clock frequency
divided by 8
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and -40 °C TA 85 °C, or 3.0 V to 3.6 V and -40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 26. 5V AC Analog Output Buffer Specifications
Symbol
Description
TROB
Rising Settling Time to 0.1%, 1 V Step, 100pF
Load
Power = Low
Power = High
TSOB
Falling Settling Time to 0.1%, 1 V Step, 100pF
Load
Power = Low
Power = High
SRROB Rising Slew Rate (20% to 80%), 1 V Step,
100pF Load
Power = Low
Power = High
SRFOB
Falling Slew Rate (80% to 20%), 1 V Step,
100pF Load
Power = Low
Power = High
BWOB
Small Signal Bandwidth, 20mVpp, 3dB BW,
100pF Load
Power = Low
Power = High
BWOB
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF
Load
Power = Low
Power = High
Document Number: 001-13105 Rev. *H
Min
Typ
Max
Units
–
–
–
–
4
4
s
s
–
–
–
–
3.4
3.4
s
s
0.5
0.5
–
–
–
–
V/s
V/s
0.55
0.55
–
–
–
–
V/s
V/s
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Notes
Page 37 of 53
CY8CLED16
Table 27. 3.3V AC Analog Output Buffer Specifications
Symbol
Description
TROB
Rising Settling Time to 0.1%, 1 V Step, 100pF
Load
Power = Low
Power = High
TSOB
Falling Settling Time to 0.1%, 1 V Step, 100pF
Load
Power = Low
Power = High
SRROB
Rising Slew Rate (20% to 80%), 1 V Step,
100pF Load
Power = Low
Power = High
SRFOB
Falling Slew Rate (80% to 20%), 1 V Step,
100pF Load
Power = Low
Power = High
BWOB
Small Signal Bandwidth, 20mVpp, 3dB BW,
100pF Load
Power = Low
Power = High
BWOB
Large Signal Bandwidth, 1Vpp, 3dB BW,
100pF Load
Power = Low
Power = High
Min
Typ
Max
Units
–
–
–
–
4.7
4.7
s
s
–
–
–
–
4
4
s
s
.36
.36
–
–
–
–
V/s
V/s
.4
.4
–
–
–
–
V/s
V/s
0.7
0.7
–
–
–
–
MHz
MHz
200
200
–
–
–
–
kHz
kHz
Notes
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and -40 °C TA 85 °C, or 3.0 V to 3.6 V and -40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 28. 5V AC External Clock Specifications
Symbol
FOSCEXT
–
–
–
Description
Frequency
High Period
Low Period
Power Up IMO to Switch
Min
0.093
20.6
20.6
150
Typ
–
–
–
–
Max
24.6
5300
–
–
Units
MHz
ns
ns
s
Notes
Table 29. 3.3V AC External Clock Specifications
Symbol
FOSCEXT
Description
Frequency with CPU Clock Divide
by 1
Min
0.093
Typ
–
Max
12.3
Units
MHz
FOSCEXT
Frequency with CPU Clock Divide
by 2 or Greater
0.186
–
24.6
MHz
–
High Period with CPU Clock Divide
by 1
Low Period with CPU Clock Divide
by 1
Power Up IMO to Switch
41.7
–
5300
ns
Notes
Maximum CPU frequency is 12 MHz at 3.3V.
With the CPU clock divider set to 1, the
external clock must adhere to the maximum
frequency and duty cycle requirements.
If the frequency of the external clock is greater
than 12 MHz, the CPU clock divider must be
set to 2 or greater. In this case, the CPU clock
divider will ensure that the fifty percent duty
cycle requirement is met.
–
41.7
–
–
ns
–
150
–
–
s
–
–
–
Document Number: 001-13105 Rev. *H
Page 38 of 53
CY8CLED16
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and -40 °C TA 85 °C, or 3.0 V to 3.6 V and -40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 30. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
flash Erase Time (Block)
flash Block Write Time
Min
1
1
40
40
0
–
–
Typ
–
–
–
–
–
10
40
Max
20
20
–
–
8
–
–
Units
ns
ns
ns
ns
MHz
ms
ms
TDSCLK
TDSCLK3
TERASEALL
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
flash Erase Time (Bulk)
–
–
–
–
–
80
45
50
–
ns
ns
ms
TPROGRAM_HOT flash Block Erase + flash Block Write Time
TPROGRAM_COLD flash Block Erase + flash Block Write Time
–
–
–
–
100[15] ms
200[15] ms
Notes
–
–
–
–
–
–
–
VDD 3.6
3.0 VDD 3.6
Erase all blocks and protection
fields at once.
0°C TJ 100 °C
-40°C TJ 0 °C
Note
15. For the full industrial range, the user must employ a Temperature Sensor User Module (flashTemp) and feed the result to the temperature argument before writing.
Refer to the flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 001-13105 Rev. *H
Page 39 of 53
CY8CLED16
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and -40 °C TA 85 °C, or 3.0 V to 3.6 V and -40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 31. AC Characteristics of the I2C SDA and SCL Pins
Symbol
FSCLI2C
THDSTAI2C
TLOWI2C
THIGHI2C
TSUSTAI2C
THDDATI2C
TSUDATI2C
TSUSTOI2C
TBUFI2C
TSPI2C
Standard-Mode
Fast-Mode
Min
Max
Min
Max
SCL Clock Frequency
0
100
0
400
Hold Time (repeated) START Condition. After
4.0
–
0.6
–
this period, the first clock pulse is generated.
LOW Period of the SCL Clock
4.7
–
1.3
–
HIGH Period of the SCL Clock
4.0
–
0.6
–
Set-up Time for a Repeated START Condition
4.7
–
0.6
–
Data Hold Time
0
–
0
–
Data Set-up Time
250
–
100[16]
–
Set-up Time for STOP Condition
4.0
–
0.6
–
Bus Free Time Between a STOP and START
4.7
–
1.3
–
Condition
Pulse Width of spikes are suppressed by the
–
–
0
50
input filter.
Description
Units
Notes
kHz
s
–
–
s
s
s
s
ns
s
s
–
–
–
–
–
–
–
ns
–
Figure 13. Definition for Timing for Fast-/Standard-Mode on the I2C Bus
I2C_SDA
TSUDATI2C
THDSTAI2C
TSPI2C
THDDATI2CTSUSTAI2C
TBUFI2C
I2C_SCL
THIGHI2C TLOWI2C
S
START Condition
TSUSTOI2C
Sr
Repeated START Condition
P
S
STOP Condition
Note
16. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-13105 Rev. *H
Page 40 of 53
CY8CLED16
Packaging Information
This section illustrates the packaging specifications for the CY8CLED16 EZ-Color device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of
the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com.
Packaging Dimensions
Figure 14. 28-Pin (210-Mil) SSOP
51-85079 *E
Document Number: 001-13105 Rev. *H
Page 41 of 53
CY8CLED16
Figure 15. 48-Pin (7 × 7 × 1.0 mm) QFN (Sawn)
7239,(:
6,'(9,(:
s
%277209,(:
s
5()
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Important Note
For information on the preferred dimensions for mounting QFN packages, see the following Application Note "Application Notes for
Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages" available at http://www.amkor.com.
Pinned vias for thermal conduction are not required for the low-power device.
Thermal Impedances
Solder Reflow Peak Temperature
Table 32. Thermal Impedances per Package
Following is the minimum solder reflow peak temperature to
achieve good solderability.
Package
28 SSOP
48 QFN[18]
Typical JA [17]
94 °C/W
28 °C/W
Capacitance on Crystal Pins
Table 34. Solder Reflow Peak Temperature
Package
Maximum Peak
Temperature
Time at Maximum
Peak Temperature
28 SSOP
260 °C
30 s
48 QFN
260 °C
30 s
Table 33. Typical Package Capacitance on Crystal Pins
Package
28 SSOP
48 QFN
Package Capacitance
2.8 pF
1.8 pF
Notes
17. TJ = TA + POWER x JA
18. To achieve the thermal impedance specified for the QFN package, refer to "Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF)
Packages" available at http://www.amkor.com.
Document Number: 001-13105 Rev. *H
Page 42 of 53
CY8CLED16
Development Tool Selection
Software
Device Programmers
PSoC Designer™
All device programmers are sold at the Cypress Online Store.
At the core of the PSoC development software suite is PSoC
Designer, used to generate PSoC firmware applications. PSoC
Designer is available free of charge at http://www.cypress.com
and includes a free C compiler.
CY3216 Modular Programmer
PSoC Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
PSoC Programmer is flexible and used on the bench in development. It is also suitable for factory programming. PSoC
Programmer works either as a standalone programming application or operates directly from PSoC Designer. PSoC
Programmer software is compatible with both PSoC ICE Cube
In-Circuit Emulator and PSoC MiniProg. It is available free of
charge at http://www.cypress.com.
■
Modular Programmer Base
■
Three Programming Module cards
■
MiniProg programming unit
■
PSoC Designer software CD
■
Getting Started guide
Evaluation Tools
■
USB 2.0 cable
All evaluation tools are sold at the Cypress Online Store.
CY3207ISSP In-System Serial Programmer (ISSP)
CY3210-MiniProg1
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production programming environment.
Note that CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
MiniProg programming unit
■
MiniEval Socket Programming and Evaluation board
■
28-Pin CY8C29466-24PXI PDIP PSoC device sample
■
28-Pin CY8C27443-24PXI PDIP PSoC device sample
■
PSoC Designer software CD
■
Getting Started guide
■
USB 2.0 cable
■
CY3207 programmer unit
■
PSoC ISSP software CD
■
110 ~ 240V power supply, euro-plug adapter
■
USB 2.0 cable
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
■
Evaluation board with LCD module
■
MiniProg programming unit
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
PSoC Designer software CD
■
Getting Started guide
■
USB 2.0 cable
Document Number: 001-13105 Rev. *H
Page 43 of 53
CY8CLED16
Accessories (Emulation and Programming)
Table 35. Emulation and Programming Accessories
Part No.
Pin Package
Flex-Pod Kit[19]
CY8CLED16-28PVXI
28 SSOP
CY3250-LED16
CY8CLED16-48LFXI
48 QFN
CY3250-LED16QFN
Foot Kit[20]
Adapter[21]
CY3250-28SSOP-FK Adapters can be found at
CY3250-48QFN-FK http://www.emulation.com.
Notes
19. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
20. Foot kit includes surface mount feet that can be soldered to the target PCB.
21. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 001-13105 Rev. *H
Page 44 of 53
CY8CLED16
Ordering Information
Key Device Features
The following table lists the CY8CLED16 EZ-Color devices’ key package features and ordering codes.
RAM
(Bytes)
Switch Mode
Pump
Temperature
Range
Digital PSoC
Blocks
Analog PSoC
Blocks
Digital I/O
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
CY8CLED16-28PVXI
32 K
CY8CLED16-28PVXIT 32 K
2K
2K
Yes
Yes
–40 C to +85 C
–40 C to +85 C
16
16
12
12
24
24
12
12
4
4
Yes
Yes
CY8CLED16-48LTXI
CY8CLED16-48LTXIT
2K
2K
Yes
Yes
–40 C to +85 C
–40 C to +85 C
16
16
12
12
44
44
12
12
4
4
Yes
Yes
Package
Ordering
Code
Flash
(Bytes)
Table 36. Device Key Features and Ordering Information
28-Pin (210 Mil) SSOP
28-Pin (210 Mil) SSOP
(Tape and Reel)
48-Pin QFN (Sawn)
48-Pin QFN
(Tape and Reel) (Sawn)
32 K
32 K
Ordering Code Definitions
CY
8
C
LED
xx - xx
xxxx
Package Type:
Thermal Rating:
PX = PDIP Pb-free
C = Commercial
I = Industrial
SX = SOIC Pb-free
E = Extended
PVX = SSOP Pb-free
LFX/LKX/LTX/LQX/LCX = QFN Pb-free
AX = TQFP Pb-free
Pin Count
Part Number
LED Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 001-13105 Rev. *H
Page 45 of 53
CY8CLED16
Acronyms
Acronyms Used
Table 37 lists the acronyms that are used in this document.
Table 37. Acronyms Used in this Datasheet
Acronym
AC
ADC
API
CMOS
CPU
CRC
CT
DAC
DC
Description
Acronym
Description
alternating current
MAC
multiply-accumulate
analog-to-digital converter
MIPS
million instructions per second
application programming interface
PCB
printed circuit board
complementary metal oxide semiconductor
PDIP
plastic dual-in-line package
central processing unit
PLL
phase-locked loop
POR
power-on reset
cyclic redundancy check
continuous time
digital-to-analog converter
direct current
PPOR
PRS
PSoC®
precision power on reset
pseudo-random sequence
Programmable System-on-Chip
DTMF
dual-tone multi-frequency
PWM
ECO
external crystal oscillator
QFN
quad flat no leads
electrically erasable programmable read-only
memory
RTC
real time clock
general purpose I/O
SAR
EEPROM
GPIO
ICE
in-circuit emulator
IDE
integrated development environment
pulse-width modulator
successive approximation
SC
switched capacitor
SMP
switch mode pump
ILO
internal low speed oscillator
IMO
internal main oscillator
SRAM
SPI
static random access memory
serial peripheral interface
I/O
input/output
SROM
supervisory read only memory
IrDA
infrared data association
SSOP
shrink small-outline package
ISSP
in-system serial programming
UART
universal asynchronous reciever /
transmitter
LCD
liquid crystal display
USB
universal serial bus
LED
light-emitting diode
WDT
watchdog timer
LPC
low power comparator
XRES
external reset
LVD
low-voltage detect
Reference Documents
Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459)
Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503)
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com.
Document Number: 001-13105 Rev. *H
Page 46 of 53
CY8CLED16
Document Conventions
Units of Measure
Table 38 lists the units of measures.
Table 38. Units of Measure
Symbol
dB
°C
fF
kHz
k
MHz
µA
µs
mA
nA
pF
pA
rt-Hz
Unit of Measure
decibels
degree Celsius
femtofarad
kilohertz
kilohm
megahertz
microamperes
microseconds
milliamperes
nanoamperes
picofarad
pikoamperes
root hertz
Symbol
ms
mH
ns
µV
V
mV
µW
%
W
mm
ps
ppm
nV
Unit of Measure
milliseconds
millihenry
nanoseconds
microvolts
volts
millivolts
microwatts
percent
watt
millimeters
picosecond
parts per million
nanovolts
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimals.
Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are switched capacitor (SC) and continuous
time (CT) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain
stages, and much more.
analog-to-digital
(ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically,
an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs
the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and
lower level services and functions (for example, user modules and libraries). APIs serve as
building blocks for programmers that create software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with
the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally)
reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or
loss); it is sometimes represented more specifically as, for example, full width at half maximum.
Document Number: 001-13105 Rev. *H
Page 47 of 53
CY8CLED16
Glossary (continued)
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a
reference level to operate the device.
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital
PSoC block or an analog PSoC block.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring
data from one device to another. Usually refers to an area reserved for IO operations, into
which data is read, or from which data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as
it is received from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets
with similar routing patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented
using vector notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is
sometimes used to synchronize different logic blocks.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously
satisfy predetermined amplitude requirements.
compiler
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to
‘1’.
crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric
crystal is less sensitive to ambient temperature than other circuit components.
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear
check (CRC)
feedback shift register. Similar calculations may be used for a variety of other purposes such as
data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location
to the central processing unit and vice versa. More generally, a set of signals used to convey
data between digital functions.
debugger
A hardware and software system that allows you to analyze the operation of the system
under development. A debugger usually allows the developer to step through the firmware one
step at a time, set break points, and analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC
generator, pseudo-random number generator, or SPI.
Document Number: 001-13105 Rev. *H
Page 48 of 53
CY8CLED16
Glossary (continued)
digital-to-analog
(DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analogto-digital (ADC) converter performs the reverse operation.
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
emulator
Duplicates (provides an emulation of) the functions of one system with a different system, so that
the second system appears to behave like the first system.
External Reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and
blocks to stop and return to a pre-defined state.
flash
An electrically programmable and erasable, non-volatile technology that provides you the
programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means
that the data is retained when power is OFF.
flash block
The smallest amount of flash ROM space that may be programmed at one time and the smallest
amount of flash space that may be protected. A flash block holds 64 bytes.
frequency
The number of cycles or events per unit of time, for a periodic function.
gain
The ratio of output current, voltage, or power to input current, voltage, or power, respectively.
Gain is usually expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an
Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The
original system was created in the early 1980s as a battery control interface, but it was later used
as a simple internal bus system for building control electronics. I2C uses only two bi-directional
pins, clock and data, both running at +5 V and pulled high with resistors. The bus operates at 100
kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows you to test the project in a hardware environment, while
viewing the debugging device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event
external to that process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the M8C receives a hardware
interrupt. Many interrupt sources may each exist with its own priority and individual ISR code
block. Each ISR code block ends with the RETI instruction, returning the device to the point in
the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold.
(LVD)
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside
a PSoC by interfacing to the flash, SRAM, and register space.
Document Number: 001-13105 Rev. *H
Page 49 of 53
CY8CLED16
Glossary (continued)
master device
A device that controls the timing for data exchanges between two devices. Or when devices are
cascaded in width, the master device is the one that controls the timing for data exchanges
between the cascaded devices and an external interface. The controlled device is called the slave device.
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition
to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason
for this is to permit the realization of a controller with a minimal quantity of chips, thus
achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of
the controller. The microcontroller is normally not used for general-purpose computation as is a
microprocessor.
mixed-signal
The reference to a circuit containing both analog and digital techniques and components.
modulator
A device that imposes a signal on a carrier.
noise
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
A circuit that may be crystal controlled and is used to generate a clock frequency.
parity
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the
sum of all the digits of the binary data either always even (even parity) or always odd (odd parity).
Phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative
to a reference signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC
device and their physical counterparts in the printed circuit board (PCB) package. Pinouts
involve pin numbers as a link between schematic and PCB design (both being computer generated
files) and may also involve pin names.
port
A group of pins, usually eight.
Power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of
hardware reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-onChip™ is a trademark of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied measurand
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out
and new data can be written in.
register
A storage device with a specific capacity, such as a bit or byte.
reset
A means of bringing a system back to a know state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but
new data cannot be written in.
Document Number: 001-13105 Rev. *H
Page 50 of 53
CY8CLED16
Glossary (continued)
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one
value to another.
shift register
A memory storage device that sequentially shifts a word either left or right to output a stream of
serial data.
slave device
A device that allows another device to control the timing for data exchanges between two
devices. Or when devices are cascaded in width, the slave device is the one that allows another
device to control the timing of data exchanges between the cascaded devices and an external
interface. The controlling device is called the master device.
SRAM
An acronym for static random access memory. A memory device where you can store and
retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell,
it remains unchanged until it is explicitly altered or until power is removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the
device, calibrate circuitry, and perform flash operations. The functions of the SROM may be
accessed in normal user code, operating from flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next
character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does
not drive any value in the Z state and, in many respects, may be considered to be disconnected
from the rest of the circuit, allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data
and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and
configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high
level API (Application Programming Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified
during normal program execution and not just during initialization. Registers in bank 1 are most
likely to be modified only during the initialization phase of the program.
VDD
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually
5 V or 3.3 V.
VSS
A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified
period of time.
Document Number: 001-13105 Rev. *H
Page 51 of 53
CY8CLED16
Document History Page
Document Title: CY8CLED16 EZ-Color™ HB LED Controller
Document Number: 001-13105
ECN No
Origin of
Change
Submission
Date
**
1148504
SFVTMP3
See ECN
*A
2763950
DPT
09/29/2009
Added 48QFN package diagram (Sawn).
Added Saw Marketing part number in ordering information.
*B
2794355
XBM
10/28/2009
Added “Contents” on page 3
Updated “Development Tools” on page 7.
Corrected FCPU1 and FCPU2 parameters in “AC Chip-Level Specifications” on page 31.
*C
2850593
FRE
01/14/2010
Updated DC GPIO, AC Chip-Level, and AC Programming Specifications
as follows:
Replaced TRAMP (time) with SRPOWER_UP (slew rate) specification.
Added note to flash Endurance specification.
Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL,
TPROGRAM_HOT, and TPROGRAM_COLD specifications.
Corrected the Pod Kit part numbers.
Updated Development Tool Selection.
Updated copyright and Sales, Solutions, and Legal Information URLs.
Updated 28-Pin SSOP 48-Pin QFN (Punched), 48-Pin QFN (Sawn)
package diagrams.
Removed Preliminary for Final status.
*D
2896238
CGX
03/19/10
*E
2903043
NJF
04/01/2010
Updated Cypress website links
Added TBAKETEMP and TBAKETIME parameters
Removed reference to 2.4V
Removed sections “Third Party Tools” and “Build a PSoC Emulator”
*F
3054665
CGX
10/11/2010
Removed pruned parts CY8CLED16-48PVXI and CY8CLED16-48PVXIT
*G
3114959
NJF
12/19/10
Added DC I2C Specifications table.
Added F32K_U max limit.
Added Tjit_IMO specification, removed existing jitter specifications.
Updated DC Analog reference, DC operational amplifier specifications
and DC analog output buffer specifications tables.
Updated Units of Measure, Acronyms, Glossary, and References
sections.
Updated solder reflow specifications.
No specific changes were made to AC Digital Block Specifications table
and I2C Timing Diagram. They were updated for clearer understanding.
Updated Figure 12 since the labelling for y-axis was incorrect.
Removed footnote reference for “Solder Reflow Peak Temperature” table.
*H
3284932
SHOB
06/24/11
Updated Getting Started, Development Tools, and Designing with PSoC
Designer.
Removed drawings and references to 48-Pin QFN (Punched) and 48-Pin
SSOP.
Removed obsolete kits.
Removed reference to obsolete spec AN2012.
Revision
Document Number: 001-13105 Rev. *H
Description of Change
New document (revision **).
Updated ordering information table. Removed part numbers
CY8CLED16-48LFXI and CY8CLED16-48LFXIT
Updated copyright section.
Updated package diagram for spec 51-85061
Page 52 of 53
CY8CLED16
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC® Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-13105 Rev. *H
Revised June 24, 2011
Page 53 of 53
PSoC Designer™ and EZ-Color™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.