Cypress CY7C1345G-133BGI 4-mbit (128k x 36) flow through sync sram Datasheet

CY7C1345G
4-Mbit (128K x 36) Flow Through Sync SRAM
Features
Functional Description
■
128K x 36 common IO
■
3.3V core power supply (VDD)
■
2.5V or 3.3V IO supply (VDDQ)
■
Fast clock-to-output times
❐ 6.5 ns (133 MHz version)
■
Provide high performance 2-1-1-1 access rate
■
User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed write
■
Asynchronous output enable
■
Available in Pb-free 100-Pin TQFP package, Pb-free and
non-Pb-free 119-Ball BGA package
■
ZZ Sleep Mode option
The CY7C1345G is a 128K x 36 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. The maximum access delay from clock rise
is 6.5 ns (133 MHz version). A two-bit on-chip counter captures
the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are
gated by registers controlled by a positive edge triggered Clock
Input (CLK). The synchronous inputs include all addresses, all
data inputs, address pipelining Chip Enable (CE1), depth
expansion Chip Enables (CE2 and CE3), Burst Control inputs
(ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and
Global Write (GW). Asynchronous inputs include the Output
Enable (OE) and the ZZ pin.
The CY7C1345G enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) is active. Subsequent burst addresses
are internally generated as controlled by the Advance pin (ADV).
The CY7C1345G operates from a +3.3V core power supply
while all outputs operate with either a +2.5 or +3.3V supply. All
inputs and outputs are JEDEC standard JESD8-5 compatible.
For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Selection Guide
Parameter
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.0
ns
Maximum Operating Current
225
205
mA
Maximum Standby Current
40
40
mA
Cypress Semiconductor Corporation
Document Number: 38-05517 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 15, 2007
CY7C1345G
Logic Block Diagram
ADDRESS
REGISTER
A 0, A1, A
A [1:0]
MODE
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADV
CLK
ADSC
ADSP
DQ D , DQP D
BW D
BYTE
WRITE REGISTER
DQ C, DQP C
BW C
BYTE
WRITE REGISTER
DQ D , DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B , DQP B
BW B
DQ B , DQP B
BYTE
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQ s
DQP A
DQP B
DQP C
DQP D
WRITE REGISTER
DQ A , DQP A
BW A
BWE
DQ A , DQPA
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
GW
ENABLE
REGISTER
CE1
CE2
INPUT
REGISTERS
CE3
OE
ZZ
SLEEP
CONTROL
Document Number: 38-05517 Rev. *E
Page 2 of 20
CY7C1345G
Pin Configurations
A
A
81
82
83
84
BWE
GW
OE
ADSC
ADSP
ADV
85
86
87
CLK
89
88
VDD
VSS
91
90
BWA
CE3
93
92
BWC
BWB
94
96
95
CE2
BWD
97
A
CE1
98
34
35
36
37
38
39
40
41
42
43
45
46
47
48
49
50
A
A1
A0
NC/72M
NC/36M
VSS
VDD
NC/18M
NC/9M
A
A
A
A
A
A
A
Document Number: 38-05517 Rev. *E
44
A
99
31
VSSQ
VDDQ
DQD
DQD
DQPD
A
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
CY7C1345G
33
BYTE D
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
A
BYTE C
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
32
VDDQ
VSSQ
DQC
DQC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
DQPC
DQC
DQC
100
100-Pin TQFP Pinout
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
BYTE B
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
BYTE A
VSSQ
VDDQ
DQA
DQA
DQPA
Page 3 of 20
CY7C1345G
Pin Configurations (continued)
119-Ball BGA Pinout
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
C
NC/288M
NC/144M
CE2
A
A
A
ADSC
VDD
A
A
CE3
A
NC/576M
NC/1G
D
DQC
DQPC
VSS
NC
VSS
DQPB
DQB
E
F
DQC
VDDQ
DQC
DQC
VSS
VSS
CE1
OE
VSS
VSS
DQB
DQB
DQB
VDDQ
G
H
J
DQC
DQC
VDDQ
DQC
DQC
VDD
BWC
VSS
NC
ADV
GW
VDD
BWB
VSS
NC
DQB
DQB
VDD
DQB
DQB
VDDQ
K
DQD
DQD
VSS
CLK
VSS
DQA
DQA
NC
BWA
DQA
DQA
BWE
A1
VSS
VSS
DQA
DQA
VDDQ
DQA
L
DQD
DQD
BWD
M
N
VDDQ
DQD
DQD
DQD
VSS
VSS
P
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
R
T
NC
NC
A
VDD
A
NC
A
A
NC/72M
MODE
A
NC/36M
NC
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
Document Number: 38-05517 Rev. *E
Page 4 of 20
CY7C1345G
Pin Definitions
Name
IO
Description
A0, A1, A
Input
Address Inputs Used to Select One of the 128K Address Locations. Sampled at the rising edge
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed
the two-bit counter.
BWA, BWB
BWC, BWD
Input
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
GW
Input
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
BWE
Input
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal is asserted
Synchronous LOW to conduct a byte write.
CLK
Input Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
Input
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
CE2
Input
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external address is
loaded.
CE3
Input
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address is
loaded.
OE
Input
Output Enable, asynchronous Input, Active LOW. Controls the direction of the IO pins. When
Asynchronous LOW, the IO pins act as outputs. When deasserted HIGH, IO pins are tri-stated and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input
Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically increSynchronous ments the address in a burst cycle.
ADSP
Input
Address Strobe from Processor, sampled on the rising edge of CLK, Active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Input
Address Strobe from Controller, sampled on the rising edge of CLK, Active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ
Input
ZZ sleep Input, Active HIGH. When asserted HIGH places the device in a non-time critical sleep
Asynchronous condition with data integrity preserved. During normal operation, this pin is low or left floating. ZZ pin
has an internal pull down.
DQs
DQPA, DQPB
DQPC, DQPD
IO
Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the pins
is controlled by OE. When OE is asserted LOW, the pins act as outputs. When HIGH, DQs and
DQP[A:D] are placed in a tri-state condition.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the core of the device.
VDDQ
IO Power
Supply
Power supply for the IO circuitry.
VSSQ
IO Ground
Ground for the IO circuitry.
Document Number: 38-05517 Rev. *E
Page 5 of 20
CY7C1345G
Pin Definitions (continued)
Name
MODE
IO
Description
Input
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and must remain static during device
operation. Mode Pin has an internal pull up.
NC
NC/9M,
NC/18M,
NC/36M
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
No Connects. Not Internally connected to the die.
–
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/288M, NC/576M, and NC/1G are address expansion pins and are not internally connected to the
die.
Functional Overview
Single Write Accesses Initiated by ADSP
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t CO) is 6.5 ns (133 MHz device).
Single write access is initiated when the following conditions are
satisfied at clock rise:
1. CE1, CE2, and CE3 are all asserted active
2. ADSP is asserted LOW.
The CY7C1345G supports secondary cache in systems using
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486™ processors. The linear
burst sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable and is determined
by sampling the MODE input. Accesses are initiated with either
the Processor Address Strobe (ADSP) or the Controller Address
Strobe (ADSC). Address advancement through the burst
sequence is controlled by the ADV input. A two-bit on-chip wrap
around burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, and CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise:
1. CE1, CE2, and CE3 are all asserted active.
2. ADSP or ADSC is asserted LOW (if the access is initiated by
ADSC, the write inputs are deasserted during this first cycle).
The address presented to the address inputs is latched into the
address register and the burst counter or control logic and
presented to the memory core. If the OE input is asserted LOW,
the requested data is available at the data outputs a maximum
to tCDV after clock rise. ADSP is ignored if CE1 is HIGH.
Document Number: 38-05517 Rev. *E
The addresses presented are loaded into the address register
and the burst inputs (GW, BWE, and BWx) are ignored during this
first clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data is latched and
written into the device. Byte writes are allowed. During byte
writes, BWA controls DQA and BWB controls DQB, BWC controls
DQC, and BWD controls DQD. All IOs are tri-stated during a byte
write. Since this is a common IO device, the asynchronous OE
input signal is deasserted and the IOs are tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless of
the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise:
1. CE1, CE2, and CE3 are all asserted active.
2. ADSC is asserted LOW.
3. ADSP is deasserted HIGH
4. The write input signals (GW, BWE, and BWx) indicate a write
access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter or control logic and delivered to the
memory core. The information presented to DQ[D:A] is written
into the specified address location. Byte writes are allowed.
During byte writes, BWA controls DQA, BWB controls DQB, BWC
controls DQC, and BWD controls DQD. All IOs and even a byte
write are tri-stated when a write is detected. Since this is a
common IO device, the asynchronous OE input signal is
deasserted and the IOs are tri-stated prior to the presentation of
data to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.
Page 6 of 20
CY7C1345G
Burst Sequences
Table 2. Linear Burst Address Table (MODE = GND)
The CY7C1345G provides an on-chip two-bit wrap around burst
counter inside the SRAM. The burst counter is fed by A[1:0] and
follows either a linear or interleaved burst order. The burst order
is determined by the state of the MODE input. A LOW on MODE
selects a linear burst sequence. A HIGH on MODE selects an
interleaved burst order. Leaving MODE unconnected causes the
device to default to a interleaved burst sequence.
Table 1. Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. In this
mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device is
deselected prior to entering the sleep mode. CEs, ADSP, and
ADSC must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ Active to sleep current
This parameter is sampled
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
Document Number: 38-05517 Rev. *E
Min
Max
Unit
40
mA
2tCYC
ns
2tCYC
ns
2tCYC
0
ns
ns
Page 7 of 20
CY7C1345G
Truth Table
The truth table for CY7C1345G follows. [1, 2, 3, 4, 5]
Address
Used
CE1
CE2
CE3
ZZ
ADSP
ADSC
Deselected Cycle, Power
down
None
H
X
X
L
X
L
X
Deselected Cycle, Power
down
None
L
L
X
L
L
X
Deselected Cycle, Power
down
None
L
X
H
L
L
Deselected Cycle, Power
down
None
L
L
X
L
Deselected Cycle, Power
down
None
X
X
X
Sleep Mode, Power down
None
X
X
X
Cycle Description
ADV WRITE
OE
CLK
DQ
X
X
L-H
Tri-State
X
X
X
L-H
Tri-State
X
X
X
X
L-H
Tri-State
H
L
X
X
X
L-H
Tri-State
L
H
L
X
X
X
L-H
Tri-State
H
X
X
X
X
X
X
Tri-State
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L-H
Tri-State
Write Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L-H
Tri-State
Next
X
X
X
L
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
Tri-State
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Notes
1. X = “Do Not Care,” H = Logic HIGH, and L = Logic LOW.
2. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA,
BWB, BWC, BWD), BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE is driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a “Do Not Care” for
the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05517 Rev. *E
Page 8 of 20
CY7C1345G
Truth Table for Read or Write
The partial truth table for read or write follows. [1, 6]
Read
Function
GW
H
BWE
H
BWD
X
BWC
X
BWB
X
BWA
X
Read
H
L
H
H
H
H
Write Byte (A, DQPA)
H
L
H
H
H
L
Write Byte (B, DQPB)
H
L
H
H
L
H
Write Bytes (B, A, DQPA, DQPB)
H
L
H
H
L
L
Write Byte (C, DQPC)
H
L
H
L
H
H
Write Bytes (C, A, DQPC, DQPA)
H
L
H
L
H
L
Write Bytes (C, B, DQPC, DQPB)
H
L
H
L
L
H
Write Bytes (C, B, A, DQPC, DQPB, DQPA)
H
L
H
L
L
L
Write Byte (D, DQPD)
H
L
L
H
H
H
Write Bytes (D, A, DQPD, DQPA)
H
L
L
H
H
L
Write Bytes (D, B, DQPD, DQPA)
H
L
L
H
L
H
Write Bytes (D, B, A, DQPD, DQPB, DQPA)
H
L
L
H
L
L
Write Bytes (D, B, DQPD, DQPB)
H
L
L
L
H
H
Write Bytes (D, B, A, DQPD, DQPC, DQPA)
H
L
L
L
H
L
Write Bytes (D, C, A, DQPD, DQPB, DQPA)
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Note
6. This table is only a partial listing of the byte write combinations. Any combination of BWx is valid. Appropriate write is done based on the active byte write.
Document Number: 38-05517 Rev. *E
Page 9 of 20
CY7C1345G
Maximum Ratings
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Exceeding the maximum ratings may shorten the battery life of
the device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) .................................. >2001V
Latch up Current..................................................... >200 mA
Operating Range
Supply Voltage on VDD Relative to GND ........–0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD
DC Voltage Applied to Outputs
in tri-state............................................. –0.5V to VDDQ + 0.5V
Ambient
Temperature
Range
Commercial
Industrial
VDD
0°C to +70°C
VDDQ
3.3V
2.5V –5%
−5%/+10%
to VDD
–40°C to +85°C
Electrical Characteristics
Over the Operating Range [7, 8]
Parameter
Description
Test Conditions
Min
Max
Unit
VDD
Power Supply Voltage
3.135
3.6
V
VDDQ
IO Supply Voltage
2.375
VDD
V
VOH
Output HIGH Voltage
VOL
VIH
VIL
IX
Output LOW Voltage
Input HIGH Voltage
for 3.3V IO, IOH = –4.0 mA
2.4
V
for 2.5V IO, IOH = –1.0 mA
2.0
V
for 3.3V, IO, IOL= 8.0 mA
0.4
V
for 2.5V IO, IOL = 1.0 mA
0.4
V
for 3.3V IO
2.0
VDD + 0.3V
V
for 2.5V IO
1.7
VDD + 0.3V
V
for 3.3V IO
–0.3
0.8
V
for 2.5V IO
–0.3
0.7
V
Input Leakage Current except GND ≤ VI ≤ VDDQ
ZZ and MODE
−5
5
µA
Input Current of MODE
–30
Input LOW
Voltage[7]
Input = VSS
Input = VDD
Input Current of ZZ
Input = VSS
µA
µA
–5
Input = VDD
30
GND ≤ VI ≤ VDDQ, Output Disabled
µA
5
µA
7.5 ns cycle, 133 MHz
225
mA
10 ns cycle, 100 MHz
205
mA
Max VDD, Device Deselected, 7.5 ns cycle, 133 MHz
VIN ≥ VIH or VIN ≤ VIL, f = fMAX, 10 ns cycle, 100 MHz
inputs switching
90
mA
80
mA
Max VDD, Device Deselected, All speeds
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
40
mA
Automatic CE Power down
Current—CMOS Inputs
Max VDD, Device Deselected, 7.5 ns cycle, 133 MHz
VIN ≥ VDDQ – 0.3V or VIN ≤
10 ns cycle, 100 MHz
0.3V, f = fMAX, inputs switching
75
mA
65
mA
Automatic CE Power down
Current—TTL Inputs
Max VDD, Device Deselected, All speeds
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
45
mA
IOZ
Output Leakage Current
IDD
VDD Operating Supply Current VDD = Max, IOUT = 0 mA,
f = fMAX= 1/tCYC
ISB1
Automatic CE Power down
Current—TTL Inputs
ISB2
Automatic CE Power down
Current—CMOS Inputs
ISB3
ISB4
µA
5
–5
Notes
7. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
8. TPower up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05517 Rev. *E
Page 10 of 20
CY7C1345G
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CIO
Input or Output Capacitance
119 BGA
Max
Test Conditions
100 TQFP
Max
TA = 25°C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 3.3V
5
5
pF
5
5
pF
5
7
pF
Unit
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Test Conditions
100 TQFP
Package
119 BGA
Package
Unit
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per
EIA/JESD51.
30.32
34.1
°C/W
6.85
14.0
°C/W
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
VT = 1.5V
(a)
GND
5 pF
INCLUDING
JIG AND
SCOPE
2.5V I/O Test Load
2.5V
OUTPUT
R = 351Ω
VT = 1.25V
(a)
Document Number: 38-05517 Rev. *E
5 pF
INCLUDING
JIG AND
SCOPE
10%
≤ 1ns
≤ 1ns
(c)
R = 1667Ω
ALL INPUT PULSES
VDDQ
GND
R = 1538Ω
(b)
90%
10%
90%
(b)
OUTPUT
RL = 50Ω
Z0 = 50Ω
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
≤ 1 ns
≤ 1 ns
(c)
Page 11 of 20
CY7C1345G
Switching Characteristics
Over the Operating Range [9, 10]
Parameter
tPOWER
Description
VDD(Typical) to the first Access[11]
–133
Min
Max
–100
Min
Max
Unit
1
1
ms
Clock
tCYC
Clock Cycle Time
7.5
10
ns
tCH
Clock HIGH
2.5
4.0
ns
tCL
Clock LOW
2.5
4.0
ns
Output Times
tCDV
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
6.5
8.0
ns
2.0
2.0
ns
0
0
ns
Clock to Low
Z[12, 13, 14]
tCHZ
Clock to High
Z[12, 13, 14]
3.5
3.5
ns
tOEV
OE LOW to Output Valid
3.5
3.5
ns
tOELZ
OE LOW to Output Low Z[12, 13, 14]
tCLZ
tOEHZ
OE HIGH to Output High
0
Z[12, 13, 14]
0
3.5
ns
3.5
ns
Setup Times
tAS
Address Setup Before CLK Rise
1.5
2.0
ns
tADS
ADSP, ADSC Setup Before CLK Rise
1.5
2.0
ns
tADVS
ADV Setup Before CLK Rise
1.5
2.0
ns
tWES
GW, BWE, BWx Setup Before CLK Rise
1.5
2.0
ns
tDS
Data Input Setup Before CLK Rise
1.5
2.0
ns
tCES
Chip Enable Setup
1.5
2.0
ns
tAH
Address Hold After CLK Rise
0.5
0.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
ns
tWEH
GW, BWE, BWx Hold After CLK Rise
0.5
0.5
ns
tADVH
ADV Hold After CLK Rise
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
0.5
ns
Hold Times
Notes
9. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
10. Test conditions shown in (a) of Latch up Current >200 mA unless otherwise noted.
11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation is
initiated.
12. tCHLZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady state voltage.
13. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High
Z prior to Low Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
Document Number: 38-05517 Rev. *E
Page 12 of 20
CY7C1345G
Timing Diagrams
Figure 1 shows the read cycle timing. [15]
Figure 1. Read Cycle Timing
tCYC
CLK
t
t ADS
CH
t CL
tADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t
GW, BWE,BW
t
WES
WEH
[A:B]
t CES
Deselect Cycle
t CEH
CE
t
ADVS
t
ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t CDV
t OELZ
t CHZ
t DOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note:
15. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 38-05517 Rev. *E
Page 13 of 20
CY7C1345G
Timing Diagrams
(continued)
Figure 2 shows the write cycle timing. [15, 16]
Figure 2. Write Cycle Timing
t CYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW
[A:B]
t
WES
t
WEH
GW
t CES
tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note:
16. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWx LOW.
Document Number: 38-05517 Rev. *E
Page 14 of 20
CY7C1345G
Timing Diagrams
(continued)
Figure 3 shows the read and write timing. [16, 17, 18]
Figure 3. Read/Write Timing
tCYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
ADSC
t AS
ADDRESS
A1
tAH
A2
A3
A4
t
BWE, BW
WES
t
A5
A6
D(A5)
D(A6)
WEH
[A:B]
t CES
tCEH
CE
ADV
OE
t DS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
t OELZ
D(A3)
t CDV
Q(A2)
Back-to-Back READs
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes:
17. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
18. GW is HIGH.
Document Number: 38-05517 Rev. *E
Page 15 of 20
CY7C1345G
Timing Diagrams
(continued)
Figure 4 shows the ZZ mode timing. [19, 20]
Figure 4. ZZ Mode Timing
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
A LL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
19. Device must be deselected when entering ZZ mode. See “Truth Table” on page 8 for all possible signal conditions to deselect the device.
20. DQs are in high-Z when exiting ZZ sleep mode.
Document Number: 38-05517 Rev. *E
Page 16 of 20
CY7C1345G
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
133
Ordering Code
Part and Package Type
CY7C1345G-133AXC
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
CY7C1345G-133BGC
51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1345G-133BGXC
100
Package
Diagram
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
CY7C1345G-133BGI
51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1345G-133BGXI
119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1345G-100AXC
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
CY7C1345G-100BGC
51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
CY7C1345G-100BGI
51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)
Document Number: 38-05517 Rev. *E
lndustrial
Commercial
119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1345G-100AXI
CY7C1345G-100BGXI
Commercial
119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1345G-133AXI
CY7C1345G-100BGXC
Operating
Range
lndustrial
119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
Page 17 of 20
CY7C1345G
Package Diagrams
Figure 5. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
R 0.08 MIN.
0.20 MAX.
0.10
1.60 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
R 0.08 MIN.
0.20 MAX.
0°-7°
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
1.00 REF.
DETAIL
Document Number: 38-05517 Rev. *E
A
51-85050-*B
Page 18 of 20
CY7C1345G
Package Diagrams (continued)
Figure 6.119-Ball BGA (14 x 22 x 2.4 mm), 51-85115
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.75±0.15(119X)
Ø1.00(3X) REF.
1
2
3 4
5
6
7
7
6
5
4 3 2 1
A
A
B
B
C
D
1.27
C
D
E
E
F
F
H
19.50
J
K
L
20.32
G
H
22.00±0.20
G
J
K
L
M
10.16
M
N
P
N
P
R
R
T
T
U
U
1.27
0.70 REF.
A
3.81
7.62
30° TYP.
14.00±0.20
0.15(4X)
0.15 C
2.40 MAX.
B
0.90±0.05
0.25 C
12.00
C
Document Number: 38-05517 Rev. *E
60±0.10
0.56
SEATING PLANE
51-85115-*B
Page 19 of 20
CY7C1345G
Document History Page
Document Title: CY7C1345G, 4-Mbit (128K x 36) Flow Through Sync SRAM
Document Number: 38-05517
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
224365
See ECN
RKF
New datasheet
*A
278513
See ECN
VBL
Deleted 66 MHz
Changed TQFP package to Pb-free TQFP in Ordering Information section
Added BG Pb-free package
*B
333626
See ECN
SYT
Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA
Packages as per JEDEC standards and updated the Pin Definitions accordingly
Modified VOL, VOH test conditions
Replaced ‘Snooze’ with ‘Sleep’
Removed 117 MHz speed bin
Replaced TBDs for ΘJA and ΘJC to their respective values on the Thermal Resistance table
Removed comment on the availability of BG Pb-free package
Updated the Ordering Information by shading and unshading MPNs as per
availability
*C
418633
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Modified test condition from VIH < VDD to VIH < VDD.
Modified test condition from VDDQ < VDD to VDDQ < VDD
Modified Input Load to Input Leakage Current except ZZ and MODE in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
*D
480124
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Updated the Ordering Information table.
*E
1274724
See ECN
VKN
Corrected Write Cycle timing waveform
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05517 Rev. *E
Revised July 15, 2007
Page 20 of 20
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