ON LB1876 3-phase brushless motor driver Datasheet

Ordering number : EN6201B
LB1876
Monolithic Digital IC
For Polygon Mirror Motors
http://onsemi.com
3-phase Brushless Motor Driver
Overview
The LB1876 is a driver for polygon mirror motors such as used in laser printers and similar equipment.
It incorporates all necessary circuitry (speed control + driver) on a single chip. Direct PWM drive enables drive with
low power loss.
Features
• 3-phase bipolar drive
• Direct PWM drive technique
• Built-in lower side output diode
• Output current limiter
• Reference clock input circuit (FG frequency equivalent)
• PLL speed control circuit
• Phase lock detector output (with masking function)
• Built-in protection circuitry includes current limiter, restraint protection, overheat protection, low-voltage protection,
etc.
• Brake method switching circuit (free-run or reverse torque)
• 5V regulator output
• Power save function
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
VCC max
30
V
Maximum output current
IO max
t ≤ 500ms
2.5
A
Allowable power dissipation
Pd max1
Independent IC
0.9
W
Pd max2
Mounted on a specified board*
2.1
W
Operating temperature
Topr
-20 to +80
°C
Storage temperature
Tstg
-55 to +150
°C
*Specified board: 114.3mm × 76.1mm × 1.6mm, glass epoxy board.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
May, 2013
31109 MS/61202RM (OT)/62599RM (KI) No.6201-1/12
LB1876
Allowable Operating Ranges at Ta = 25°C
Parameter
Power supply voltage range
Symbol
Conditions
Ratings
Unit
VCC
9.5 to 28
V
5V regulated output current
IREG
0 to -20
mA
LD pin voltage
VLD
0 to 28
V
FGS pin voltage
VFGS
0 to 28
V
LD pin output current
ILD
0 to 15
mA
FGS pin output current
IFGS
0 to 10
mA
Electrical Characteristics at Ta = 25°C, VCC = VM = 24V
Parameter
Symbol
Ratings
Conditions
min
Current drain
typ
ICC1
ICC2
Quiescent Current
Unit
max
17
22
mA
3.6
5.0
mA
5V Regulated Output
Output voltage
VREG
5.0
5.35
V
Voltage fluctuation
ΔVREG1
VCC = 9.5 to 28V
4.65
50
100
mV
Load fluctuation
ΔVREG2
IO = -5 to -20mA
30
100
Temperature coefficient
ΔVREG3
Design target value*
VOsat1
IO = 1.0A, VO(SINK) + VO(SOURCE)
2.0
VOsat2
IO = 2.0A, VO(SINK) + VO(SOURCE)
2.6
0
mV
mV/°C
Output Block
Output saturation voltage
Output leak current
Lower side diode forward voltage
IOleak
2.5
V
3.2
V
100
μA
VD1
ID = -1.0A
1.2
1.5
V
VD2
ID = -2.0A
1.5
1.9
V
Hall Amplifier Block
-2
μA
Input bias current
IHB
Common mode input voltage range
VICM
-0.5
Hall input sensitivity
VIN(HA)
80
Hysteresis width
ΔVIN(HA)
15
Input voltage L → H
VSLH
12
mV
Input voltage H → L
VSHL
-12
mV
0
VREG-2.0
V
mVp-p
24
42
mV
FG/Schmitt Block
Input bias current
IB(FGS)
Common mode input voltage range
VICM(FGS)
-2
Input sensitivity
VIN(FGS)
80
Hysteresis width
ΔVIN(FGS)
15
μA
-0.5
0
VREG-2.0
V
mVp-p
24
42
mV
Input voltage L → H
VSLH(FGS)
12
mV
Input voltage H → L
VSHL(FGS)
-12
mV
PWM Oscillator
Output High level voltage
VOH(PWM)
2.5
2.8
3.1
V
Output Low level voltage
VOL(PWM)
1.2
1.5
1.8
V
-125
-95
-75
External capacitor charge current
ICHG
VPWM = 2V
Oscillator frequency
f(PWM)
C = 3000pF
Amplitude
V(PWM)
22
1.05
μA
kHz
1.27
1.50
Vp-p
0.15
0.5
V
10
μA
V
FGS Output
Output saturation voltage
VOL(FGS)
Output leak current
IL(FGS)
IFGS = 7mA
CSD Oscillator
Output High level voltage
VOH(CSD)
2.65
3.0
3.3
Output Low level voltage
VOLCSD)
0.75
0.9
1.1
V
Amplitude
V(CSD)
1.75
2.1
2.3
Vp-p
External capacitor charge current
ICHG1
-13.5
-9
-5.5
μA
9
13.5
μA
External capacitor discharge current
ICHG2
Oscillator frequency
f(CSD)
5.5
C = 0.068μF
30
Hz
*Design target value, Do not measurement.
Continued on next page.
No.6201-2/12
LB1876
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
min
typ
VREG-0.2
VREG-0.1
Unit
max
Phase Comparator Output
Output High level voltage
VPDH
IOH = -100μA
Output Low level voltage
VPDL
IOH = 100μA
Output source current
IPD+
VPD = VREG/2
Output sink current
IPD−
VPD = VREG/2
Output saturation voltage
VOL(LD)
ILD = 10mA
Output leak current
IL(LD)
VO = VCC
VIO(ER)
Design target value*
0.2
V
0.3
-0.5
1.5
V
mA
mA
Phase Lock Detector Output
0.15
0.5
V
10
μA
+10
mV
+1
μA
0.9
1.2
V
-5%
VREG/2
+5%
V
0.4
0.5
0.6
times
Error Amplifier
Input offset voltage
Input bias current
IB(ER)
Output High level voltage
VOH(ER)
IOH = -500μA
Output Low level voltage
VOL(ER)
IOL = 500μA
DC bias level
VB(ER)
-10
-1
VREG-1.2
VREG-0.9
V
Current Limiter
Drive gain
GDF1
In phase lock mode
GDF2
In unlock mode
0.8
1.0
1.2
times
Limiter voltage
VRF
VCC - VM
0.45
0.5
0.55
V
Operating temperature
TSD
Design target value* (junction temperature)
150
180
°C
Hysteresis width
ΔTSD
Design target value* (junction temperature)
40
°C
Thermal Shutdown Operation
Low Voltage Protection
Operating voltage
VSD
8.1
8.5
8.9
V
Hysteresis
ΔVSD
0.2
0.35
0.5
V
External capacitor charge current
ICLD
-6
-4.3
-3
V
Operating voltage
VH(CLD
3.25
3.5
3.75
V
CLD Circuit
CLK Pin
External input frequency
fI(CKIN)
0.1
10
High level input voltage
VIH(CKIN)
3.5
VREG
kHz
V
Low level input voltage
VIL(CKIN)
0
1.5
V
Input open voltage
VIO(CKIN)
VREG-0.5
VREG
V
Hysteresis width
VIS(CKIN)
High level input current
IIH(CKIN)
VCKIN = VREG
Low level input current
IIL(CKIN)
VCKIN = 0V
0.35
0.5
0.65
V
-10
0
+10
μA
-280
-210
μA
S/S Pin
High level input voltage
VIH(SS)
3.5
VREG
V
Low level input voltage
VIL(SS)
0
1.5
V
Input open voltage
VIO(SS)
VREG-0.5
VREG
V
Hysteresis width
VIS(SS)
High level input current
IIH(SS)
VS/S = VREG
Low level input current
IIL(SS)
VS/S = 0V
0.35
0.5
0.65
V
-10
0
+10
μA
-280
-210
μA
LDSEL Pin
High level input voltage
VIH(LDSEL)
3.5
VREG
V
Low level input voltage
VIL(LDSEL)
0
1.5
V
Input open voltage
VIO(LDSEL)
High level input current
IIH(LDSEL)
VLDSEL = VREG
Low level input current
IIL(LDSEL)
VLDSEL = 0V
VREG-0.5
-10
0
-280
-210
VREG
V
+10
μA
μA
BRSEL Pin
High level input voltage
VIH(BRSEL)
3.5
VREG
V
Low level input voltage
VIL(BRSEL)
0
1.5
V
Input open voltage
VIO(BRSEL)
High level input current
IIH(BRSEL)
Low level input current
IIL(BRSEL)
*Design target value, Do not measurement.
VREG-0.5
VBRSEL = VREG
VBRSEL = 0V
-10
0
-280
-210
VREG
V
+10
μA
μA
No.6201-3/12
LB1876
Package Dimensions
unit : mm (typ)
3235A
Pd max -- Ta
0.65
17.8
(6.2)
2.7
Allowable power dissipation, Pd max -- W
2.4
10.5
7.9
(4.9)
36
1
0.25
(0.5)
2.0
0.3
(2.25)
0.8
With specified board: 114.3×76.1×1.6mm3
glass epoxy board.
2.1
2.0
1.6
1.2
0.9
0.8
1.18
Independent IC
0.4
2.45max
0
-20
0
20
40
60
80
100
0.1
Ambient temperature, Ta -- °C
SANYO : HSOP36(375mil)
OUT3
NC
GND3
BRSEL
LDSEL
VREG
VCC
VM2
VM1
FRAME
CLK
S/S
LD
FGS
CLD
PD
EI
EO
TOC
Pin Assignment
36
35
34
33
32
31
30
29
28
FR
27
26
25
24
23
22
21
20
19
11
12
13
14
15
16
17
18
PWM
FC
FGFIL
CSD
PH
10
GND2
IN1−
FR
GND1
9
FGIN−
8
FGIN+
7
FRAME
6
IN1+
IN3+
5
IN2−
4
IN2+
3
IN3−
2
NC
OUT2
1
OUT1
LB1876
Top view
3-phase Logic Truth Table
IN1
IN2
IN3
OUT1
OUT2
OUT3
H
L
H
L
H
M
H
L
L
L
M
H
H
H
L
M
L
H
L
H
L
H
L
M
L
H
H
H
M
L
L
L
H
M
H
L
IN = "H" indicates the IN+ > IN− condition.
No.6201-4/12
LB1876
Block Diagram
VREG
FGFIL
VREG
FGS
LD
CLD
LDSEL
PD
FGIN+
LDSEL
FG
FILTER
FGIN−
LD
EI
VREG
EO
CLK
CLK
TOC
PLL
TSD
PWM
S/S
PWM
OSC
VREG
CONT
AMP
COMP
S/S
PEAK
HOLD
CURR
LIM
BRSEL
BRSEL
VREG
FC
PH
VCC
VCC
Rf
VM2
LOGIC
VM1
CSD
SD
OSC
COUNT
OUT1
HALL LOGIC
DRIVER
HALL
HYS AMP
IN1+ IN1− IN2+ IN2− IN3+ IN3− GND1
OUT3
OUT2
GND2
GND3
VREG
No.6201-5/12
LB1876
Pin Function
Pin No.
Pin name
Function
2
OUT1
Motor drive output pins.
1
OUT2
PWM controls duty cycle ratio by lower transistors.
36
OUT3
Connect Schottky diodes between the outputs and VCC.
Equivalent curcuit
VCC
VM2
300Ω
VM1
34
GND3
Output block ground.
28
VM1
Output block power supply and output current detection.
29
VM2
VM1 and VM2 are short-circuited and used.
29
28
1 2 36
Connect low-resistance resistors Rf between these pins and
VCC.
The output current is limited to the current value set by IOUT
= VREF/Rf.
3
NC
Since these are not connected internally, they can be used
35
NC
for wiring.
8
IN1+
IN1−
Hall device input pins.
9
6
7
4
5
10
11
IN2+
IN2−
IN3+
IN3−
FGIN+
FGIN−
34
VREG
These inputs return a high level when IN+ > IN− and a low
level when IN− > IN+.
A Hall signal amplitude of at least 100mVp-p (differential) is
desirable. Insert a capacitor between IN+ and IN− if noise on
the Hall signal is a problem.
300Ω
300Ω
5 7 9
4 6 8
FG comparator input pins.
VREG
If noise on the FG signal is a problem, insert either a
capacitor or a filter consisting of a capacitor and a resistor.
300Ω
300Ω
11
10
12
GND1
Control circuit block ground.
13
GND2
Sub-ground.
14
PWM
PWM oscillation frequency setting pin.
VREG
Connect a capacitor between this pin and ground.
A capacitance of 1800pF for C sets the frequency to
approximately 37kHz.
200Ω
14
2kΩ
15
FC
Current control circuit frequency characteristics
VREG
compensation pin.
Insert a capacitor (on the order of 0.01 to 0.1μF) between
this pin and ground.
The output duty is determined by the ratio of the voltage on
this pin and the PWM oscillator waveform.
300Ω
15
Continued on next page.
No.6201-6/12
LB1876
Continued from preceding page.
Pin No.
16
Pin name
FGFIL
Function
FG filter pin.
If noise on the FG signal is a problem, insert a capacitor
Equivalent curcuit
VREG
(under about 2200pF) between this pin and ground.
16
17
CSD
Restraint protection circuit operating time setting pin/reset
VREG
pulse setting pin.
A protection operating time of about 8 seconds can be set by
connecting a capacitor (about 0.068μF) between this pin
and ground. If the protection circuit is not used, connect a
300Ω
17
capacitor and resistor (about 4700pF, 220kΩ) in parallel
between this pin and ground.
18
PH
RF waveform smoothing pin.
VREG
If noise on the RF signal is a problem, insert a capacitor
between this pin and ground.
500Ω
18
19
TOC
Torque specifying input pin.
VREG
Normally, this pin is connected to the EO pin.
When the TOC voltage falls, the on duty of the lower side
transistor increases.
300Ω
19
20
EO
Error amplifier output pin.
VREG
20
40kΩ
21
EI
Error amplifier input pin.
VREG
300Ω
21
Continued on next page.
No.6201-7/12
LB1876
Continued from preceding page.
Pin No.
22
Pin name
PD
Function
Equivalent curcuit
Phase comparator output pin.
VREG
The phase error is converted to a pulse duty and output from
this pin.
300Ω
22
23
CLD
Phase lock signal mask time setting pin.
A mask time of about 90ms can be set by inserting a
VREG
capacitor (about 0.1μF) between this pin and ground. Leave
this pin open if there is no need to mask.
300Ω
23
24
FGS
FG Schmitt output pin.
Open collector output.
VREG
24
25
LD
Phase lock detection output pin.
Open collector output.
VREG
Turns on (goes low) when phase lock is detected.
25
26
S/S
Start/stop control pin.
Low: 0 to 1.5V
VREG
High: 3.5V to VREG
Hysteresis: About 0.5V
Apply a low level to start; this pin goes high when open.
22kΩ
2kΩ
26
27
CLK
Clock input pin.
Low: 0 to 1.5V
VREG
High: 3.5V to VREG
Hysteresis: About 0.5 V
fCLK = 10kHz maximum
If there is noise on the clock signal, remove that noise with a
capacitor.
30
VCC
22kΩ
2kΩ
27
Power supply pin
Insert a capacitor between this pin and ground to prevent
noise from entering the IC. (Use a value of 20 or 30μF or
higher.)
Continued on next page.
No.6201-8/12
LB1876
Continued from preceding page.
Pin No.
31
Pin name
VREG
Function
Equivalent curcuit
Stabilized power supply output (5V output) pin.
VCC
Insert a capacitor between this pin and ground for
stabilization. (About 0.1μF.)
31
32
LDSEL
Phase lock signal mask switching pin.
Low: 0 to 1.5V
VREG
High: 3.5V to VREG
When open, this pin goes to the high level.
When low, transient unlock signals (short high-level periods
30kΩ
on the LD output) are masked, and when high, transient lock
2kΩ
signals (short low-level periods on the LD output) are
32
masked.
33
BRSEL
Braking control pin.
Low: 0 to 1.5V
VREG
High: 3.5V to VREG
When open, this pin goes to the high level.
When low, reverse torque control is applied and when high,
the circuit operates in free-running mode. An external
Schottky barrier diode is required on the low side output
30kΩ
2kΩ
33
when reverse torque control is applied.
−
FRAME
The FRAME pin is connected internally to the metal frame at
the base of the IC. Electrically, both the FRAME pin and the
metal frame are left open. To improve thermal dissipation,
provide a corresponding land on the PCB and solder the
FRAME pin to that land.
No.6201-9/12
LB1876
LB1876 Overview
1. Speed control circuit
This IC provides high-precision, low-jitter, and stable motor rotation since it adopts a PLL speed control technique.
This PLL circuit compares the phases of the edges on the CLK signal (falling edges) and the FG signal (falling edges on
the FGIN+, FGS output) and controls the speed using that error output.
The FG servo frequency during control operation is the same as the clock frequency.
fFG(servo) = fCLK
2. Output drive circuit
To reduce power loss in the output, this IC adopts a direct PWM drive technique. The output transistors are always
saturated when on, and the motor drive power is controlled by changing the output on duty. Since the lower side
transistor is used for the output PWM switching, Schottky diodes must be inserted between the outputs and VCC. (This
is because if the diodes used do not have a short reverse recovery time, instantaneous through currents will flow when
the lower side transistor turns on.)
The diodes between the outputs and ground are built in. However, if problems (such as waveform disruption during
lower side kickback) occur for large output currents, attach external rectifying diodes or Schottky diodes. If reverse
control mode is selected for braking and problems such as incorrect operation or excess heat generation due to the
reverse recovery time of the lower side diode causes a problem, add an external Schottky diode.
3. Current control circuit
The current control circuit controls the current (limits the peak current) to the current determined by I = VRF/Rf (VRF
= 0.5V typ., Rf: current detection resistor). The limiting operation consists of reducing the output on duty to suppress
the current.
The current control circuit detects the diode reverse recovery current due to the PWM operation, and has an operating
delay (about 3μ s) to prevent incorrect current limiting operation. If the motor coils have a relatively low resistance, or
relatively low inductance, the changes in current flow at startup (the state where the motor presents no back
electromotive force) will be rapid. As a result, the current limiter may operate at currents in excess of the set current due
to this delay. In such cases, the current limit value must be set so as to take the current increase due to the delay into
account.
4. Power saving circuit
This IC goes to the power saving state, which reduces power consumption, in the stopped state. Power is reduced in the
power saving state by cutting the bias current to most of the circuit blocks in the IC. However, the 5 V regulator circuit
does operate and provide its output in the power saving state.
5. Reference clock
The externally input clock signal must be free of chattering and other noise. The input circuit does have hysteresis, but
if problems occur, the clock signal must be input through a capacitor or other noise reduction circuit.
If the IC is set to the start state with no reference clock input, and if the constraint protection circuit is operated, after the
motor rotates a certain amount, the drive will be turned off. However, if the constraint protection circuit is not operated,
and furthermore, if reverse control mode is selected during braking, the motor will run backwards at increasing speed.
A workaround will be required in this case. (This problem occurs because the constraint protection circuit oscillator
signal is used for clock cutoff protection.)
6. PWM frequency
The PWM frequency is determined by the capacitor C (F) connected to the PWM pin.
fPWM ≈ 1/(15000 × C)
If an 1800pF capacitor is used, the frequency will be about 37kHz. If the PWM frequency is too low, the motor will
emit audible switching noise, and if it is too high, the power loss will increase. A frequency in the range 15 to 50kHz is
desirable. The capacitor ground must be connected as close as possible to the IC control block ground (the GND1 pin)
to minimize the influence of the output on this circuit.
7. Hall sensor input signals
Input signals with amplitudes greater than the input circuit hysteresis (42mV maximum) must be provided to the Hall
inputs. Input amplitudes of over 100mV are desirable to minimize the influence of noise. If the output waveform is
disturbed by noise (at phase switching), insert capacitors across the input to prevent this.
No.6201-10/12
LB1876
8. FG input signal
Normally, one of the Hall sensor signals is input as an FG signal. If noise on the FG input is a problem, insert either a
capacitor or a filter consisting of a capacitor and a resistor. Although it is possible to exclude noise from the FG signal
by inserting a capacitor between the FGFIL pin and ground, if this pin's waveform is smoothed excessively, the circuit
may not be able to operate normally. Therefore, if a capacitor is used here, its value must be held to under 2200pF. If
the position of the capacitor's ground lead is inappropriate, problems due to noise may become more likely to occur.
Select the position carefully.
9. Constraint protection circuit
This IC includes a built-in constraint protection circuit to protect the IC and the motor during motor constraint. In the
start state, when the LD output is high for a fixed period (the unlocked state), the lower side transistor turns off. The
time is set by the capacitor connected to the CSD pin.
Set time (seconds) ≈ 120 × C (μF)
If a 0.068μF capacitor is used, the protection time will be about 8 seconds. The set time must have a value that provides
an adequate margin relative to the motor start time. The protection circuit does not operate during braking implemented
by switching the clock frequency. Either switch to the stop state or turn off the power and restart to clear the constraint
protection state.
Since the CSD pin also functions as the initial reset pulse generation pin, if connected to ground the logic circuits will
be reset and speed control operation will not be possible. Therefore, if constraint protection is not used, connect CSD to
ground through a resistor of about 220kΩ and a capacitor of about 4700pF in parallel.
10. Phase lock signal
(1) Phase lock range
Since this IC does not have a counter in the speed control system, the speed error range in the phase locked state
cannot be determined solely by the IC's characteristics. (This is because of the influence of the acceleration of the
changes in the FG frequency.) If it is necessary to stipulate this for the motor, it will be necessary to measure this with
the actual motor. Since it is easier for speed errors to occur in the state where the FG acceleration is large, the largest
speed errors are thought to occur during lock pull-in at startup and when unlocked due to clock frequency switching.
(2) Phase lock signal mask function
When the LDSEL pin is set high or left open, transient lock signals (short low-level periods on the LD output) is
masked. This function masks short low-level periods due to hunting during pull-in and allows a stable lock signal to
be output. However, the lock signal is delayed by amount of masking time.
When the LDSEL pin is set low, transient unlock signals (short high-level periods on the LD output) is masked.
This function prevents short period high-level signals from being output.
The mask time is set with the capacitor connected between the CLD pin and ground.
Mask time (seconds) ≈ 0.9 × C (μF)
A mask time of about 90ms can be set by using a capacitor of about 0.1µF. If complete masking is required, the mask
time must be set large enough to provide ample margin. If masking is not required, leave the CLD pin open.
11. Power supply stabilization
Since this IC provides a large output current and adopts a switching drive technique, it can easily disrupt the power
supply line voltage. Therefore, capacitors with ample capacitance must be inserted between the VCC pins and ground.
If reverse control mode is selected during braking, the circuit will return current to the power supply. This means that
the power supply lines are even more susceptible to disruption. Since the power supply is most easily influenced during
lock pull-in at high motor speeds, this case requires particular care. Select capacitor values that are fully adequate for
this case.
If diodes are inserted in the power supply lines to prevent damage if the power supply is connected with reverse
polarity, the power supply voltage will be even more susceptible to disruption, and even larger capacitors must be used.
12. VREG stabilization
Insert a capacitor of at least 0.1μF to stabilize VREG, which is the control circuit power supply. The capacitor ground
must be connected as close as possible to the IC control block ground (the GND1 pin).
13. Error amplifier circuit components
Locate the error amplifier components as close to the IC as possible to minimize the influence of noise on this circuit.
Locate this circuit as far from the motor as possible.
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