BOARDCOM AC208KQM 2.5v 10/100-tx 8-port repeater/71 uplink port with integrated bridge Datasheet

PRELIMINARY DATA SHEET
AC208
2.5V 10/100-TX 8-Port Repeater/7+1 Uplink Port with Integrated Bridge
GENERAL DESCRIPTION
FEATURES
The AC208 is an unmanaged eight-port 10/100 Mbps
repeater with an integrated bridge. The AC208 provides a
low-cost and integrated solution for unmanaged repeater
applications.
The AC208 is a Class II Repeater. In addition, the eighth
port supports 10/100 TX interface for uplink function.
The AC208 provides 10/100 Mbps auto-negotiation and
parallel detection for all ports. In addition, the option to
configure each transceiver port via the EEPROM interface
is available. The AC208 provides two internal repeater state
machines, one operating at 10 Mbps and the other at
100 Mbps. Once the technology is set, the device
automatically connects each port to the appropriate
repeater segment.
The AC208 provides two back-planes for expansion, one
operates at 10 Mbps and the other operates at 100 Mbps.
Up to 32 ports can logically be connected into one repeater
using back-plane buses.
The AC208 integrates repeater and bridge technologies
with store-and-forward mechanisms.
FEATURES
• Low-power (less than 1A total current consumption when
used with 1.25:1 transformer) eight-port 10/100 Mbps
repeater with built-in bridge function.
• MDC/MDIO for control/status of transceiver components.
• Eight integrated 10/100 Mbps IEEE 802.3u compliant
transceivers.
• IEEE 802.3u-compliant auto-negotiation.
• Fully integrated adaptive equalizer provides phase/
amplitude compensation for various cable lengths up to
30 dB at 100 MHz.
• Patent-pending DC restoration technique reduces offset/
baseline wander.
• Unique scrambler seed for all ports for better EMI.
• Cascadable backplanes compatible with AC206.
• Non-blocking 10/100M bridge with MAC and bridge. One
segment of a bridge is fixed to 100 Mbps, while the other
segment can be configured for 10 or 100 Mbps.
• Bridge functions include:
- Embedded 32 KB of memory for address table and
packet buffer.
- Local MAC address filtering.
- XOR hashing scheme.
- Short routing decision time.
- Forwarding schemes: store-and-forward.
- Address table up to 1K entries.
• Programmable LED display for activity, link, speed,
partition, utilization, and collision rate.
• Advanced power management includes:
- Each transceiver port can be turned off
independently.
- Standby mode, which reduces power when the port
is not connected.
• Low-power 2.5V 0.25 µm CMOS implementation with
128-pin QFP package.
• Input tolerance to 3.3V.
256Kbits
RAM
Bridge
MII
MII
10M RBP
100M RBP
R_100
R_10
...
10M RBP
...
10M
RBP
100M
MUX
100M RBP
Figure 1:
P
H
Y
P
H
Y
P
H
Y
P
H
Y
P
H
Y
P
H
Y
P
H
Y
TX0
TX1
TX2
TX3
TX4
TX5
TX6
P
H
Y
TX7
Up Link
Functional Block Diagram
AC208-DS04-405-R
16215 Alton Parkway • P.O. Box 57013 • Irvine, California 92619-7013 • Phone: 949-450-8700 • Fax: 949-450-8710
07/08/02
REVISION HISTORY
Revision
Date
Change Description
AC208-DS04405-R
07/08/02
Incorporate MDC/MDIO changes.
AC208-DS03-R
06/07/02
General technical revision.
AC208-DS02-R
06/20/01
Updated the following tables:
• “LED Connections”
• “Power and Ground”
• “Register Set”
• “Bridge Control Register”
• “BT Control Register”
• “LED Effect with Partition/Isolation Event”
• “EEPROM”
AC208-DS01-R
02/08/01
• Updated “Scrambler” in the “Functional Description” section to: When the BT Control
register 23.11 is set to 1 the data scrambling function is disabled, the 5-bit data stream
is clocked directly to the device’s PMA sublayer.
• Added pin #114 to DGND in the “Power and Ground” table.
• Added pins # 28, 29, 30, 31, 33, 34, 35, 38 to the “No Connects” table.
• Updated the “Electrical Characteristics” section (replaced the Digital Input Voltage
–0.5V to Vcc with –0.5V to 3.3V)
• Updated the “Digital Timing Characteristics” section
• Various text changes throughout the whole document.
• Added the “Mechanical Information” section, outlining the packaging specifications.
• Updated “LED Timing.”
AC208-DS00-R
10/9/00
Initial release.
Altima Communications, Inc.
A Broadcom Company
Broadcom Corporation
P.O. Box 57013
16215 Alton Parkway
Irvine, CA 92619-7013
© 2002 by Altima Communications, Inc.
All Rights Reserved
Printed in the U.S.A.
Broadcom® and the pulse logo® are trademarks of Broadcom Corporation and/or its subsidiaries in the United States and
certain other countries. All other trademarks are the property of their respective owners.
This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended, or
certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous
substances management, or other high risk application. BROADCOM PROVIDES THIS DATA SHEET "AS-IS", WITHOUT
WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING,
WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, AND NON-INFRINGEMENT.
Preliminary Data Sheet
AC208
07/08/02
TABLE OF CONTENTS
Section 1: Functional Description...................................................................................... 1
Functional Description ................................................................................................................................ 1
Clocks, Reset, and Power Management Functions .................................................................................. 1
Media Independent Interface .................................................................................................................. 2
Scrambler................................................................................................................................................ 2
Parallel to Serial and NRZ—NRZI to MLT-3 Conversion ........................................................................ 2
PLL Clock Synthesizer............................................................................................................................ 3
Receive Function ......................................................................................................................................... 3
Adaptive Equalizer .................................................................................................................................. 3
Link Monitor ............................................................................................................................................ 4
Baseline Wander Compensation ............................................................................................................ 4
Clock/Data Recovery .............................................................................................................................. 4
Decoder/Descrambler ............................................................................................................................. 4
Auto-Negotiation and Miscellaneous Functions ....................................................................................... 5
Parallel Detection.................................................................................................................................... 5
Carrier Sense/RXDV for MII Port Only.................................................................................................... 5
Cable Length Monitor .................................................................................................................................. 5
Media Independent Interface .................................................................................................................. 6
Forwarding Scheme ................................................................................................................................ 6
Address Recognition............................................................................................................................... 6
Reset and Restart ................................................................................................................................... 6
Media Access Control ............................................................................................................................. 6
Hardware Configuration .......................................................................................................................... 7
Software Configuration ........................................................................................................................... 7
LEDs ....................................................................................................................................................... 7
Address Table ......................................................................................................................................... 9
Routing Decision................................................................................................................................... 10
Learning Process .................................................................................................................................. 10
Aging Time ............................................................................................................................................ 10
Forwarding Scheme .............................................................................................................................. 11
Bridge Buffer Management and Queues .............................................................................................. 11
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Section 2: Pins................................................................................................................... 12
Pin Descriptions .........................................................................................................................................12
Section 3: Register Descriptions ..................................................................................... 18
Register Description...................................................................................................................................18
Bridge Configuration Register ...............................................................................................................22
PHY Configuration Register ..................................................................................................................23
PHY Identifier 2 Register .......................................................................................................................25
Auto-Negotiation Advertisement Register .............................................................................................25
Auto-Negotiation Expansion Register....................................................................................................26
Cable Length Register...........................................................................................................................30
Power Management Register ................................................................................................................31
LED Effect with Partition/Isolation Event ...............................................................................................33
LED Effect with Link Event ....................................................................................................................33
LED Effect with Auto-Negotiating Event ................................................................................................34
LED Register Control Mode...................................................................................................................35
LED Display Matrix .....................................................................................................................................38
System Considerations..........................................................................................................................38
Section 4: Electrical Characteristics ............................................................................... 39
Absolute Maximum Ratings.......................................................................................................................39
Operating Range .........................................................................................................................................39
REFCLK Pins ........................................................................................................................................40
I/O Characteristics—LED Pins ..............................................................................................................40
10BASE-T Transceiver Characteristics .................................................................................................41
Section 5: Digital Timing Characteristics ....................................................................... 42
Power on Reset ...........................................................................................................................................42
PHY MDC/MDIO Interface ...........................................................................................................................43
100 MBPS Repeater BackPlane Receive/Transmit Timing .....................................................................44
10 MBPS Repeater BackPlane Receive/Transmit Timing .......................................................................45
EEPROM Interface Timing .........................................................................................................................46
LED Timing ..................................................................................................................................................47
TX Application Termination .......................................................................................................................48
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Preliminary Data Sheet
AC208
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Section 6: Mechanical Information................................................................................... 49
Section 7: Ordering Information.......................................................................................50
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LIST OF TABLES
Table 1:
LED Connections............................................................................................................................. 8
Table 2:
Content of Address Lookup Table ................................................................................................... 9
Table 3:
Embedded Memory Structure........................................................................................................11
Table 4:
Media Dependent Interface Pins (TX) ...........................................................................................12
Table 5:
EEPROM Interface ........................................................................................................................13
Table 6:
MDC/MDIO Interface .....................................................................................................................13
Table 7:
100 Mbps Internal Repeater ..........................................................................................................14
Table 8:
10 Mbps Internal Repeater Bus .....................................................................................................15
Table 9:
LED Pins........................................................................................................................................16
Table 10:
Configuration and Setup................................................................................................................17
Table 11:
Clock Reset ...................................................................................................................................17
Table 12:
Power and Ground ........................................................................................................................17
Table 13:
No Connects..................................................................................................................................17
Table 14:
Register Set...................................................................................................................................18
Table 15:
PHY Port Status Register ..............................................................................................................20
Table 16:
PHY Port Status ............................................................................................................................20
Table 17:
Initial Device Configuration Register .............................................................................................21
Table 18:
Bridge Configuration Register .......................................................................................................22
Table 19:
PHY Configuration Register 0 .......................................................................................................23
Table 20:
PHY Status Register 1...................................................................................................................24
Table 21:
PHY Identifier 1 Register ...............................................................................................................25
Table 22:
PHY Identifier 2 Register ...............................................................................................................25
Table 23:
Auto-Negotiation Advertisement Register .....................................................................................25
Table 24:
Auto-Negotiation Link Partner Ability Register ..............................................................................26
Table 25:
Register 6: Auto-Negotiation Expansion Register .........................................................................26
Table 26:
Auto-Negotiation Next Page Transmit Register.............................................................................27
Table 27:
PHY 10BASE-T Configuration Register ........................................................................................28
Table 28:
PHY Interrupt Control/Status Register...........................................................................................29
Table 29:
Diagnostic Register .......................................................................................................................30
Table 30:
Cable Length Register ...................................................................................................................30
Table 31:
Receive Error Count ......................................................................................................................31
Table 32:
Power Management Register ........................................................................................................31
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AC208
07/08/02
Table 33:
Transceiver Mode Register ........................................................................................................... 32
Table 34:
LED Effect with Partition/Isolation Event....................................................................................... 33
Table 35:
LED Effect with Link Event............................................................................................................ 33
Table 36:
LED Effect with Activity (CRS) Event ............................................................................................ 34
Table 37:
LED Effect with Auto-Negotiating Event........................................................................................ 34
Table 38:
LED Effect with Speed100 Event .................................................................................................. 35
Table 39:
LED Register Control Mode .......................................................................................................... 35
Table 40:
EEPROM....................................................................................................................................... 36
Table 41:
4B/5B Code-Group Table.............................................................................................................. 37
Table 42:
Total Power Consumption............................................................................................................. 39
Table 43:
TTL I/O Characteristics ................................................................................................................. 40
Table 44:
REFCLK Pins ................................................................................................................................ 40
Table 45:
I/O Characteristics—LED Pins ...................................................................................................... 40
Table 46:
100BASE-TX Transceiver Characteristics .................................................................................... 41
Table 47:
10BASE-T Transceiver Characteristics......................................................................................... 41
Table 48:
Power on Reset............................................................................................................................. 42
Table 49:
PHY MDC/MDIO Interface ............................................................................................................ 43
Table 50:
100 Mbps Repeater BackPlane Receive/Transmit Timing............................................................ 44
Table 51:
10 Mbps Repeater BackPlane Receive/Transmit Timing.............................................................. 45
Table 52:
EEPROM Interface Timing............................................................................................................ 46
Table 53:
LED Timing ................................................................................................................................... 47
Table 54:
Package Dimensions for the AC208 ............................................................................................. 49
Table 55:
Ordering Information ..................................................................................................................... 50
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LIST OF FIGURES
Figure 1:
Functional Block Diagram................................................................................................................. i
Figure 2:
Exclusive or Hashing Algorithm .....................................................................................................10
Figure 3:
Address Learning and Recognition ...............................................................................................10
Figure 4:
Basic Memory Management Concept ...........................................................................................11
Figure 5:
LED Display Matrix ........................................................................................................................38
Figure 6:
Power on Reset .............................................................................................................................42
Figure 7:
PHY MDC/MDIO Interface.............................................................................................................43
Figure 8:
100 Mbps RBP Receive/Transmit Timing......................................................................................44
Figure 9:
10 Mbps RBP Receive/Transmit Timing........................................................................................45
Figure 10: EEPROM Interface Timing ............................................................................................................46
Figure 11: LED Timing....................................................................................................................................47
Figure 12: Application Termination .................................................................................................................48
Figure 13: 128-Pin PQFP ...............................................................................................................................49
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Preliminary Data Sheet
AC208
07/08/02
S e c ti o n 1 : Fu nc t io na l D e s c r i pt i on
FUNCTIONAL DESCRIPTION
The AC208 is an unmanaged 10/100 Mbps repeater with integrated bridge functions. The device provides eight
10/100BASE-TX twisted pair interface ports. The AC208 also includes a built-in two-segment bridge for 10/100 Mbps
connection. The AC208 provides the highest integration chip solution for dual speed hub systems. The result is ultra low
power consumption that consumes less than 1A maximum when all ports are running 100BASE-TX full-speed. The built-in
function powers down when not used (no cable detected). This reduces power consumption and improves long-term
reliability.
CLOCKS, RESET, AND POWER MANAGEMENT FUNCTIONS
The AC208 requires a single 25-MHz clock signal at the CLK input pin. An internal PLL generates all of the clock frequencies
needed by the device from the single clock input.
The AC208 can be reset in two ways:
•
During initial power on.
•
Hardware reset: A logic low signal of 10 µs pulse width applies to RST pin.
During reset, all mode pins latch in, the internal address table is initialized, and the internal state machine is reset to known
states. At the completion of the reset sequence, all ports are enabled for frame reception and transmission.
The AC208 offers the following power management:
•
Power down mode: This can be achieved by writing to register 0.11 plus port based address.
Example: Port 1 has a based address of Hex 00. During power down, the device is able to respond through the MDC/
MDIO interface.
•
Energy detect mode: The device powers down all of the unused circuitry when the cable is not installed. The Energy
Detect (ED) circuit stays on to monitor incoming signals from the media. The MDC/MDIO interface is turned on in
response to any access transaction. The transmit circuit sends out a link pulse with minimum power consumption. If a
valid signal is received from the media, the device is powered up and resumes normal transmit/receive operation.
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Functional Description
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Preliminary Data Sheet
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TRANSCEIVER AND TRANSMIT FUNCTION
In 100BASE-TX mode, the Transceiver transmits MLT-3 signal to the cable via isolation transformer. MLT-3 data is a three
level signal data. This data is scrambled when transmitted to the media. The MLT-3 data is synchronous to the 25-MHz clock.
In 10BASE-T mode, Manchester code is generated by the 10BASE-T core logic, which synthesizes through the output
waveshaping driver. This helps reduce any EMI emission, which eliminates the need for an external filter.
MEDIA INDEPENDENT INTERFACE
The Media Independent Interface (MII) is for direct connection of an external device to the repeater. The transmit data on
the MII interface is 4-bit nibbles at 25/2.5 MHz rate. This MII interface is connected to the repeater via the MII TXD lines. The
external device asserts TX_EN during transmission, or forces an error in the encoded data using TX_ER.
SCRAMBLER
In 100BASE-TX mode, the internal 5-bit transmit data stream is scrambled as defined by the TP-PMD Stream Cipher
function in order to reduce radiated emissions on the twisted pair cable. The scrambler encodes a plain text NRZ bit stream
using a key stream periodic sequence of 2047 bits generated by the recursive linear function:
X [n] = X [n-11] + X [n-9] (modulo 2)
The scrambler reduces peak emissions by randomly spreading the signal energy over the transmit frequency range, thus
eliminating peaks at a single frequency. EMI emission can be further reduced by assigning a unique scrambled seed to each
port. When the BASE-T Control register 23.11 is set to 1 the data scrambling function is disabled, the 5-bit data stream is
clocked directly to the device’s PMA sublayer.
PARALLEL TO SERIAL AND NRZ—NRZI TO MLT-3 CONVERSION
The internal 5-bit NRZ data is clocked into transceiver’s shift register with a 25 MHz clock, and clocked out with a 125 MHz
clock to convert it into a serial bit stream. Both clocks are generated by an on-chip clock synthesizer, and they are in sync
to each other. The serialized data is further converted from NRZ to NRZI format, which produces a transition on every logic 1
and no transition on logic 0. To further reduce EMI emission, the NRZI data is converted to MLT-3 signal. The effect offers
a 3 dB to 6 dB reduction in EMI emissions over an un-converted NRZI signals, thus increases the output signals’ margin of
operating within the FCC Class B limit.
When there is a transition occurring in NRZI data, there is a corresponding transition for MLT-3 data. For NRZI data, it
changes the count up/down direction after every single transition. For MLT-3 data, it changes the count up/down direction
after every two transitions. The NRZI to MLT-3 data conversion is implemented without reference to the bit timing or clock
information. The conversion requires detecting transition of the incoming NRZI data and set up the count up/down direction
for the MLT-3 data. Asserting FX_SEL high bypasses this encoding.
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Transceiver and Transmit Function
Document
AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
MULTIMODE TRANSMIT DRIVER
The multimode driver transmits MLT-3 coded signal in 100BASE-TX mode and Manchester coded signal in 10BASE-T
mode.
The slew rate of the transmitted MLT-3 signal can be controlled to eliminate high frequency EMI component. The MLT-3
signal after the magnetic has a typical rise/fall time of approximately 4 ns, which is within the target range specified in the
ANSI TP- PMD standard.
In 10BASE-T mode, high frequency pre-emphasis is performed which extends the cable-driving distance without the need
of an external filter. FLP/NLP also drives signals through the 10BASE-T driver. The 10BASE-T and 100BASE-TX transmit
signals are multiplexed to the transmit output driver. This arrangement results in using the same external transformer for
both the 10BASE-T and the 100BASE-TX. The driver output level is set by a built-in bandgap reference and an external
resistor connected to the RIBB output pin. The resistor sets the output current for all modes of operation. Each of the TXOP/
N outputs is an open drain device which has a source resistance of 10Ω maximum and a current rating of 40 mA for the 2
Vp-p MLT-3 signal, 100 mA for 5Vp-p Manchester signal when used 1:1 transformer.
PLL CLOCK SYNTHESIZER
The Transceiver also includes on-chip PLL clock synthesizer that generates a 125-MHz and a 25-MHz clock for the
100BASE-TX, or a 100-MHz and 20-MHz clock for the 10BASE-T and auto-negotiation operations. The PLL clock generator
uses a fully differential VCO cell that induces a very low jitter. The Zero Dead Zone Phase Detection method implemented
in this design provides excellent phase tracking. A charge pump with charge sharing compensation is also included to further
reduce jitter at different loop filter voltages. On-chip loop filter eliminates the need for external components and avoids
external noise pickup. Only one external 25-MHz crystal or a signal source is required as a reference clock.
RECEIVE FUNCTION
In 100BASE-TX mode, the receive function implements the reverse order function in the transmit path. It includes a receiver
with adaptive equalization and DC restoration, MLT-3 to NRZI conversion, data and clock recovery at 125 MHz, NRZI to NRZ
conversion, Serial-to-Parallel conversion, de-scrambling, and 5B to 4B decoding. The receiver circuit starts with a DC bias
for the differential RX± inputs, follows with a low-pass filter to filter out high frequency noise from the transmission channel
media. An energy detect circuit is also added to determine whether there is any signal energy on the media. This is useful
in the power-saving mode. The amplification ratio and slicer threshold is set by the on-chip bandgap reference.
In 10BASE-T mode, signal first passes through a third order lowpass filter, which filters all the noise from the cable, board,
and transformer. This eliminates the need for a 10BASE-T external filter. A Manchester decoder and a Serial-to Parallel
follows to generate the 4-bit data in MII mode.
ADAPTIVE EQUALIZER
Each of the eight transceivers is designed to accommodate for maximum cable length of 150m UTP CAT5 cable. A 150m
of UTP CAT-5 cable (such as AT&T 1061) has an attenuation of 31 dB at 100 MHz. A typical attenuation of a 100m cable is
20 dB. The worst case attenuation is around 24–26 dB defined by TP-PMD.
The amplitude and phase distortion from the cable causes inter-symbol interference (ISI) which makes clock and data
recovery impossible. Adaptive equalizer is done by matching the inverse transfer function of the twist-pair cable. This is a
variable equalizer that changes its equalizer frequency response in accordance to cable length. The cable length is
estimated based on comparisons of incoming signal strength against some the known cable characteristics. The equalizer
has a monotonically frequency response, and tunes itself automatically for any cable length to compensate for the amplitude
and phase distortion incurred from the cable.
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Receive Function
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Preliminary Data Sheet
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LINK MONITOR
Signal levels are detected through a squelch detection circuitry. A signal detect (SD) circuit follows the equalizer and is
asserted high when the peak detector detects a post-equalized signal with peak to ground voltage level larger than 400 mV.
This is approximately 40% of a normal signal voltage level. In addition, the energy level must be sustained longer than 2~3 µs
in order for the signal detects be asserted. It gets de-asserted approximately 1~2 µs after the energy level is consistently
less than 300 mV from peak to ground.
In 100BASE-TX mode, when no signal or invalid signal is detected on the receive pair, the link monitor enters in the link fail
state where only scrambled idle code is transmitted. When a valid signal is detected for a minimum period of time, the link
monitor enters a link pass state and transmit and receive functions are entered.
In 10BASE-T mode, a link-pulse detection circuit constantly monitors the RXIP/RXIN pins for the presence of valid link
pulses.
BASELINE WANDER COMPENSATION
The 100BASE-TX data stream is not always DC balanced. The transformer blocks the DC component of the incoming signal,
thus the DC offset of the differential receives inputs can wander. The shift in the signal levels, coupled with non-zero rise
and fall times of the serial stream can cause pulse-width distortion, creating jitter and possible increases in error rates.
Therefore, a DC restoration circuit is needed to compensate for the attenuation of DC component. The Transceiver
implemented is a patent-pending DC restoration circuit, unlike the traditional implementation; it does not need the feedback
information from the slicer and clock recovery. This not only simplifies the system/circuit design but also eliminates any
random/systematic offset on the receive path. In 10BASE-T mode, the baseline wander correction circuit is not required and
is bypassed.
CLOCK/DATA RECOVERY
The equalized MLT-3 signal passes through a slicer circuit that converts to NRZI format. The transceiver uses a mixed-signal
phase locked loop (PLL) to extract clock information of the incoming NRZI data. The extracted clock is used to re-time the
data stream and set the data boundaries. The transmit clock is locked to the 25-MHz clock input while the receive clock is
locked to the incoming data streams. When initial lock is achieved, the PLL switches to lock to the data stream, extracts a
125-MHz clock and uses that for bit framing to recover data. The recovered 125-MHz clock is also used to generate an
internal 25-MHz RX_CLK. The PLL requires no external components for its operation and has high noise immunity and low
jitter. It provides fast phase align (lock) to data in one transition and its data/clock acquisition time after power-on is less than
60 transitions. The PLL can maintain lock on run-lengths of up to 60 data bits in the absence of signal transitions. When no
valid data is present (like when the SD is de-asserted), the PLL switches back to lock with TX_CLK and provides a
continuously running RX_CLK.
DECODER/DESCRAMBLER
The descrambler detects the state of the transmit Linear Feedback Shift Register (LFSR) by looking for a sequence
representing consecutive idle codes. The descrambler acquires lock with the data stream by recognizing IDLE bursts of 30
or more bits and locking to its de-ciphering Linear Feedback Shift Register (LFSR).
Once lock is acquired, the device operates with the inter-packet-gap (IPG) as low as 40 ns. Before lock occurs, the descrambler requires a minimum of 720 nS of idle in between packet in order to acquire lock.
The deciphering logic also tracks the number of consecutive receive errors detected while RX_DV is asserted. Once the
error counter exceeds its limit (currently set to 64 consecutive errors), the logic assumes that lock has been lost, and the decipher circuit resets itself. The process of regaining lock begins again.
Stream cipher de-scrambler is not used in 10BASE-T mode.
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Receive Function
Document
AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
AUTO-NEGOTIATION AND MISCELLANEOUS FUNCTIONS
Each of the transceivers contain the ability to negotiate its mode of operation over the twisted pair using the auto-negotiation
mechanism defined in the clause 28 IEEE 802.3u specification. Auto-negotiation may be disabled by software via EEPROM.
The transceiver automatically chooses its mode of operation by detecting the incoming signal.
During auto-negotiation, the auto-negotiation advertisement register is sent to its link partner through a series of fast link
pulse (FLP). When auto-negotiation enabled, Transceiver sends FLP during the following conditions:
•
Power on
•
Link loss
•
Restart command
At the same time, the device monitors incoming data to determine its mode of operation. Parallel detection circuit is enabled
as soon as 10BASE-T idle or 100BASE-TX idle is detected. The mode of operation is configured based on the technology
of the incoming signal. When the device receives a burst of FLP from its link partner with three identical link code words
(ignoring acknowledge bit), it stores these code words in the auto-negotiation link partner ability register and waits for the
next three identical code words. Once the device detects the second code word, it configures itself to the highest technology
that is common to both ends. The technology priorities are:
1
100BASE-TX, half-duplex
2
10BASE-T half-duplex
Once auto-negotiation is complete, the status register reflects the actual speed that was chosen.
PARALLEL DETECTION
The Transceiver also checks for 10BASE-T NLP or 100BASE-TX idle symbols. If either is detected, the device automatically
configures to match the detected operating speed in half-duplex mode. This ability allows the device to communicate with
legacy 10BASE-T and 100BASE-TX systems.
CARRIER SENSE/RXDV FOR MII PORT ONLY
Carrier sense is asserted asynchronously on the CRS pins as soon as activity is detected on the receive data stream.
RX_DV is asserted as soon as a valid SSD (Start-of-Stream Delimiter) is detected. Carrier sense and RX_DV are deasserted synchronously upon detection of a valid end of stream delimiter or two consecutive idle code groups in the receive
data stream. If carrier sense is asserted and a valid SSD is not detected immediately, RX_ER is asserted instead of RX_DV.
In 10BASE-T mode, carrier sense is asserted asynchronously on the CRS pin when valid preamble activity is detected on
the RXIP/RXIN pins. In half-duplex mode, the CRS is activated during transmit and receive of data.
CABLE LENGTH MONITOR
The AC208 can also detect the length of the cable and display the result in the interrupt control/status register (such as, 0000
stands for less than 10m cable used, 0001 stands for ~ 10m of cable, and 1111 stands for 150m cable).
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AC208-DS04-405-R
Auto-Negotiation and Miscellaneous Functions
Page 5
AC208
Preliminary Data Sheet
07/08/02
BRIDGE FUNCTION
MEDIA INDEPENDENT INTERFACE
The bridge supports MII for 10/100 Mbps. Port 0 of bridge can support either 10 or 100, while port 1 supports only at
100 Mbps. Refer to the mode pin table to configure port 0.
FORWARDING SCHEME
The bridge supports the store-and-forward scheme only. It does not support cut-through-mode. With store-and-forward, the
incoming packet should be completely received to the buffer without error before it can be sent out.
ADDRESS RECOGNITION
The self-learning bridge function is based on source address field of packets. The bridge uses the XOR hashing algorithm
to address look-up table. Programmable aging time and fast aging control is supported.
RESET AND RESTART
At power on, the bridge initially goes to the SRAM self-test mode. It generates eight patterns to evaluate SRAM status.
MEDIA ACCESS CONTROL
The bridge media access control (MAC) complies with certain IEEE 802.3 MAC protocols such as frame formatting and
collision handling, but does not generate CRC codes. It generates a 56-bit preamble and start of frame delimiter while a
packet is sending. In half-duplex mode, the device listens before transmitting, to prevent traffic jam. During collision, a packet
is retransmitted at a random time.
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Bridge Function
Document
AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
INITIALIZATION AND SETUP
HARDWARE CONFIGURATION
Several different states of operation can be chosen through hardware configuration. External pins may be pulled high or low
at reset time. The combination of high and low values determines the power on state of the device.
Many of these pins are multi-function pins which change their meaning when reset ends.
SOFTWARE CONFIGURATION
Several different states of transceiver operation may be chosen through the MDC/MDIO interface. For details, see “Register
Descriptions” on page 18.
LEDS
Using an LED display matrix with a refresh technique, only 16 pins are required to drive up to 48 LEDs with unique
information. On, Off, and Flash states are used to indicate different information. With a reduced number of signals, the LED
display is easier to route on the board, and less costly. The active-low LED data is driven out of LED_D[0:7] pins for each
port and the corresponding LED functions are LED_LN[5:0] pin. For details, see “LED Display/Configuration/PROM
Interface” on page 16 and “LED Display Matrix” on page 38.
The AC208 supports two LEDs per port. The following table describes how each of the LED is connected.
Signals LED_D[0:7] are indicators of port 1 through 8. Signals LED_LN[0:5] are events driven of port 1 through 8.
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Initialization and Setup
Page 7
AC208
Preliminary Data Sheet
07/08/02
Table 1: LED Connections
Signals
Events
Descriptions
LED_LN[0]
Link Status/Activity
Active low indicates 100M link is good. Blinking indicates 100M activity.
LED_LN[1]
Speed/Partition
Active low indicates 10M link is good. Blinking indicates 10M activity.
LED_LN[2]
Display utilization
on bridge segment
A (100 Mbps)
LED_LN[2] is active low, indicating 100M utilization. Utilization indicator is not per
port basis, but rather per segment basis. The LED_D[0:7] indicates percentage of
utilization.
LED_LN[3]
LED_LN[4]
LED_LN[5]
Display utilization
on bridge segment
B (10 Mbps)
Display collision on
bridge segment A
(100 Mbps)
Display collision on
bridge segment B
(10 Mbps)
LED_D[0:7]
7
6
5
4
3
2
1
0
Percent Util.
non
non
85%
65%
45%
25%
12%
1%
LED_LN[3] is active low, indicating 10M utilization. Utilization indicator is not per
port basis, but rather per segment basis. The LED_D[0:7] indicates percentage of
utilization.
LED_D[0:7]
7
6
5
4
3
2
1
0
Percent Util.
non
non
non
65%
45%
25%
12%
1%
LED_LN[4] is active low, indicating collision. Collision indicator is not per port
basis, but rather per segment basis. The LED_D[1:7] indicates percentage of
collision. However, LED_D0 only indicates collision occurrence.
LED_D[0:7]
7
6
5
4
3
2
1
0
Percent Col.
66%
32%
16%
8%
4%
2%
1%
Col.
LED_LN[5] is active low, indicating collision. Collision indicator is not per port
basis, but rather per segment basis. The LED_D[1:7] indicates percentage of
collision. However, LED_D0 only indicates collision occurrence.
LED_D[0:7]
7
6
5
4
3
2
1
0
Percent Col.
66%
32%
16%
8%
4%
2%
1%
Col.
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Initialization and Setup
Document
AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
ADDRESSING ALGORITHM, ROUTING, LEARNING, AND AGING
ADDRESS TABLE
The address table can store up to 1K entries and each entry consists of 48-bit MAC address, 8-bit port identifier, 1-bit
indication flag and 6-bit aging timer.
Table 2: Content of Address Lookup Table
3130
0
V
Timer
MAC#3
Port#
MAC#1
MAC#2
MAC#4
MAC#5
MAC#6
Bit 30: Entry valid/empty indication, 1 = valid entry, 0 = empty entry.
Bit 29-24: Aging timer.
Bit 23-16: Port number
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AC208-DS04-405-R
Addressing Algorithm, Routing, Learning, and Aging
Page 9
AC208
Preliminary Data Sheet
07/08/02
ADDRESS RECOGNITION
The exclusive or addressing algorithm is used for address lookup table addressing (see the following figure).
MAC#6
xor
MAC#4
xor
MAC#2
=
Hashed address[15:0]
MAC#5
xor
MAC#3
xor
MAC#1
=
Figure 2: Exclusive or Hashing Algorithm
The final address of address lookup table is the hashed address[9:0].
ROUTING DECISION
If a record is empty, the packet is broadcast and treated as an unknown frame. Otherwise, the record is read, and compared
with the current DA. If two addresses are the same, the port number is decided, and the packet is forwarded to the assigned
port. If address collision occurred, different MAC address, the incoming packet is considered an unknown packet.
LEARNING PROCESS
The address learning process is composed of the SA packets and the addressing algorithm described above. The bridge
checks each incoming packets integrity and buffers availability. If a packet is error-free and the buffer is available, the SA/
port number pair of the packet is written into the address lookup table. The following figure describes the general operations
of address learning and recognition.
DA or SA
Xor Hashing Function
[9:0]
Address
Entry Point
AAA-1
AAA
AAA+1
Address Lookup
T bl
Figure 3: Address Learning and Recognition
AGING TIME
The switch automatically examines the status of address lookup table. The round robin speed and checking timer are
dependent on the aging time. The switch aging time is set at 300s. When the aging timer is started after power on, the switch
guaranties that free spaces can be released from occupied address entries.
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AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
FORWARDING SCHEME
The store-and-forward algorithm is used. The incoming packet has to be completely stored in the buffer and verified errorfree before forwarding operations take place.
BRIDGE BUFFER MANAGEMENT AND QUEUES
The bridge buffering management continues to store received packets into memory. The buffer size for 100M port is 16K
bytes, and 8K bytes for 10M port.
Start Address
Read Point
Write Point
Free buffer
End Address
Per Port Buffer Management
Figure 4: Basic Memory Management Concept
The bridge uses the six pointers to control per port buffer status. Start Address point is the beginning of memory address for
each port and the End Address point is the last address of memory for each port. The Read/Write and shadow Read/Write
pointers are dynamically changed depending on the current outgoing and incoming packets in the storage. If the Write
pointer reaches the Read pointer and the size between write and read pointers is smaller than 2K bytes, buffer is full. On the
other hand, when read/write pointers are equal, the buffer is empty.
Table 3: Embedded Memory Structure
31
0x0000
0
2K x 32 for address lookup table
0x07FF
0x0800
4K x 32 for 100M Bridge Port
0x17FF
0x1800
2K x 32 for 10M Bridge Port
0x1FFF
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AC208-DS04-405-R
Addressing Algorithm, Routing, Learning, and Aging
Page 11
AC208
Preliminary Data Sheet
07/08/02
S e c t i o n 2 : Pi n s
PIN DESCRIPTIONS
Many of these device pins have multiple functions. The separate descriptions of each pin are listed in the proper sections.
Designers must assure that they have identified all modes of operation prior to final design.
The media dependent interface (MDI) pin assignment shown below and in the pin description table is subject to change
without notice. The user is advised to contact Altima Communications, Inc. before implementing any design based on the
information provided in this data sheet.
Signals types:
•
I = Input
•
O = Output
•
Z = High impedance
•
U = Pull up with 10 kΩ
•
D = Pull down with 10 kΩ
•
S = Schimitt Trigger
•
A = Analog signal
•
P = Power
•
G = Ground
•
* = Active low signal
Table 4: Media Dependent Interface Pins (TX)
Pin Name
Pin #
Type
Description
RXIP_7
RXIP_6
RXIP_5
RXIP_4
RXIP_3
RXIP_2
RXIP_1
RXIP_0
107
96
95
84
83
72
71
60
AI
AI
AI
AI
AI
AI
AI
AI
Receiver Input Positive for both 10BASE-T and 100BASE-TX.
RXIN_7
RXIN_6
RXIN_5
RXIN_4
RXIN_3
RXIN_2
RXIN_1
RXIN_0
106
97
94
85
82
73
70
61
AI
AI
AI
AI
AI
AI
AI
AI
Receiver Input Negative for both 10BASE-T and 100BASE-TX.
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Document
AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
Table 4: Media Dependent Interface Pins (TX) (Cont.)
Pin Name
Pin #
Type
Description
TXOP_7
TXOP_6
TXOP_5
TXOP_4
TXOP_3
TXOP_2
TXOP_1
TXOP_0
104
99
92
87
80
75
68
63
AO
AO
AO
AO
AO
AO
AO
AO
Transmitter Output Positive for both 10BASE-T and 100BASE-TX.
TXON_7
TXON_6
TXON_5
TXON_4
TXON_3
TXON_2
TXON_1
TXON_0
103
100
91
88
79
76
67
64
AO
AO
AO
AO
AO
AO
AO
AO
Transmitter Output Negative for both 10BASE-T and 100BASE-TX.
Table 5: EEPROM Interface
Pin Name
Pin #
Type
Description
PROM_CS
127
O
PROM chip select. Connected to Chip Select pin of 93C46 serial
EEPROM
PROM_CLK LED_D[6]
124
O
PROM Clock. Connected to CLK pin of 93C46 serial EEPROM
PROM_OUT LED_D[5]
123
O
PROM Data Out. Connected to Data_In pin of 93C46 serial
EEPROM
PROM_IN LED_D[7]
125
I,D
PROM Data In. Connected to Data_Out pin of 93C46 serial
EEPROM
Table 6: MDC/MDIO Interface
Pin Name
Pin #
Type
Description
MDC (PROM_CS)
127
I,U
Clock signal between the external device and PHY registers for
communication synchronization
MDIO
128
I/O,D
Data Input/Output. It is a bi-directional data interface used by the
external device to access only the internal PHY registers within
the AC208. This pin has internal pull-down register.
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Pin Descriptions
Page 13
AC208
Preliminary Data Sheet
07/08/02
Table 7: 100 Mbps Internal Repeater
Pin Name
Pin #
Type
Description
M100COL_LOCAL*
3
I/O, U
100M Local Collision. Input when ChipID = 00. Active low to
indicate collision on all other ChipIds.
M100ACTO*
4
O, U
Output to ChipID=00 for ChipID≠00 to signal local activity. This
signal is pure combinational logic and is not in sync with any
clock source. (Refer to next 3 signals).
M100ACTI_0*
(M100ACTO*)
4
I,U
Input for ChipID=00 from ChipID≠00 M100ACTO* pins to
indicate activities. Open on all other ChipIDs.
M100ACTI_1*
6
I,U
Connected from ChipID=00 to ChipID=10 M100ACTO* to sense
activities. Open on all other ChipIDs.
M100ACTI_2*
7
I,U
Connected from ChipID=00 to ChipID=11 M100ACTO* to sense
activities. Open on all other ChipIDs.
M100COL_SYS*
2
I/O,U
ChipID=00 drives this pin the same as 100COLBP* to indicate
local collision.
M100CRS_SYS*
8
I/O,U
ChipID=00 drives this pin the same as 100CRSBP* to indicate
local activity.
MS100D4
MS100D3
MS100D2
MS100D1
MS100D0
14
13
12
11
9
I/O,D
I/O,D
I/O,D
I/O,D
I/O,D
Multiple/Stacked Data Group. Transmit and receive data in descrambled 5B data groups for multiple devices. Data is sampled
at the rising edge of MS100D_CLK and driven out on falling edge
of MS100D_CLK.
MS100D_EN*
1
I/O,U
Multiple/Stacked Data Enable. Active-low when data is valid.
Signal is driven out on the falling edge of MS100D_CLK, and
sampled at the rising edge of MS100D_CLK.
MS100D_CLK
16
I/O, U,
S
Multiple/Stacked Data Clock. The bi-directional non-continuous
25 MHz recovered clock for synchronizing with MS100D[4:0],
and MS100D_EN*.
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AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
Table 8: 10 Mbps Internal Repeater Bus
Pin Name
Pin #
Type
Description
M10COL_LOCAL*
18
I/O, U
10M Local Collision. Input when ChipID = 00. Active low to
indicate collision on all other ChipIds. M10COL_LOCAL# ≠
(local_collision).
M10ACTO*
19
O, U
Output to ChipID = 00 for ChipID ≠ 00 to signal local activity.
(Refer to next 3 signals).
M10ACTI_0*
(M10ACTO*)
19
I,U
Connected from ChipID = 00 from ChipID = 01 M10ACTO* to
sense activities. Open on all other ChipIDs.
M10ACTI_1*
20
I,U
Connected from ChipID 00 to ChipID 10 M10ACTO* to sense
activities. Open on all other ChipIDs.
M10ACTI_2*
21
I,U
Connected from ChipID 00 to ChipID 11 M10ACTO* to sense
activities. Open on all other ChipIDs.
M10COL_SYS*
27
I/O,U
ChipID 00 drives this pin the same as 10COLBP* to indicate
system collision.
M10CRS_SYS*
22
I/O,U
ChipID 00 drives this pin the same as 10CRSBP* to indicate
system activity.
MS10D
25
I/O,D
Multiple/Stacked Data Group. Transmit and receive data in
10BASE-T for multiple devices. Data is sampled at the rising
edge of MS10D_CLK and driven out on falling edge of
MS10D_CLK.
MS10D_EN*
26
I/O,U
Multiple/Stacked Data Enable. Active when data is valid.
MS10D_CLK
24
I/O, U,
S
Multiple/Stacked Data Clock. The bi-directional non-continuous
10 MHz recovered clock for synchronizing with MS10D and
MS10D_EN*.
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Pin Descriptions
Page 15
AC208
Preliminary Data Sheet
07/08/02
LED DISPLAY/CONFIGURATION/PROM INTERFACE
The LED pins are shared with reset-read configuration pins, test pins and EEPROM interface. The value applied on the
reset-read pins is only valid at the end of the reset cycle. The EEPROM interface is active after the reset cycle. Once the
data in the EEPROM is read, the same pins are used for LED display. Forty-eight LED outputs are available through an 6x8
matrix.
Table 9: LED Pins
Pin Name
Pin #
Type
Description
LED_LN[5]
LED_LN[4]
LED_LN[3]
LED_LN[2]
LED_LN[1]
LED_LN[0]
50
51
52
53
54
55
O
48 mA
Enable corresponding LED display line in the display matrix, active low
output. The detail of how to program and connect the LEDs is in the LED
Setup section.
LED_LN*[5] = Display 10BASE-T Collision rate and segment collision
status.
LED_LN*[4] = Display 100 Mbps Collision rate and segment collision
status
LED_LN*[3] = Display 10M segment utilization rate
LED_LN*[2] = Display 100M segment utilization rate
LED_LN*[1] = Programmable LED display. The default is to display 10M
Link/Activity information of each port.
LED_LN*[0] = Programmable LED display. The default is to display 100M
Link/Activity information of each port.
LED_D[7]
LED_D[6]
LED_D[5]
LED_D[4]
LED_D[3]
LED_D[2]
LED_D[1]
LED_D[0]
125
124
123
122
121
120
119
118
I/O, D
Output for LED display information of each column in the display matrix.
Active high output.
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AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
Table 10: Configuration and Setup
Pin Name
Pin #
Type
Description
Mode[3]
Mode[2] (LED_D[4])
Mode[1] (LED_D[1])
Mode[0] (LED_D[0])
37
122
119
118
I,D
Mode[1:0]
00
01
10
11
Domain A
100M Rptr
100M Rptr
100M
100M Rptr
Mode[3:2]
Reserved
MII
Domain B
10M Rptr (Master)
10M Rptr (Slave, Bridge disable)
Port 7
10M Rptr (Slave, Bridge, enable
and 10M disable)
TP125
36
I
1:select 1:1.25 xformer
ChipID[0] (LED_D[3])
ChipID[1] (LED_D[2])
120
121
I,D
To assign chip ID for four devices in a single box. One device
in the box must be assigned with ChipID = 0.
RBP
112
I
Reference bias resistor. Connected to analog ground through
a 10K (1%) resistor.
Table 11: Clock Reset
Pin Name
Pin #
Type
Description
1 RESET*
1 47
1 I,U
1 Reset to initial and defaulted state. Pulse must be greater than 10 ns.
1 CLK
1 48
1 I
1 25-MHz system clock reference input. This pin shall be connected to an
external 25-MHz clock source. Multiple devices should be synchronous to
the same external clock source.
Table 12: Power and Ground
Pin Name
Pin #
Type
Description
DVCC
115, 126, 10, 23, 39, 46
P
2.5V power for digital circuit, total of 9 pins.
DGND
114, 116, 117, 5, 15, 32,
45, 49
G
Ground for digital circuit, total 10 pins.
AVCC
108, 109, 110, 57, 58, 59
P
2.5V power for analog circuit, total 16 pins.
AGND
105, 62, 65, 66, 69, 74,
77, 78, 81, 86, 89, 90, 93,
98, 101, 102
G
Ground for analog circuit, total 16 pins
GAVDD
113
P
2.5V power supply for common analog circuit
GAGND
111, 56
G
Ground for common analog circuit
Table 13: No Connects
Pin Name
Pin #
Type
Description
N/C
17, 28, 29, 30, 31, 33, 34,
35, 38, 40, 41, 42, 43, 44
N/C
No Connects
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AC208-DS04-405-R
Pin Descriptions
Page 17
AC208
Preliminary Data Sheet
07/08/02
Section 3 : R egis ter De scr iptions
The following standard registers are supported. (Register numbers are in Decimal format, the values are in Hex format).
Note When writing to registers, it is recommended that a read/modify/write operation be performed, as
unintended bits may get set to unwanted states. This applies to all registers, including those with reserved
bits.
REGISTER DESCRIPTION
The following table lists the AC208 register sets. Each register contains 16-bit data. The addresses in the following table are
hexadecimal.
Table 14: Register Set
PHY Addr
Offset Addr
Definition
Type
Default
8
0–4
PHY Port Status Registers
8
0
PHY Port Link Status
RO
8
1
PHY Port Polarity Status
RO
8
2
PHY Port Partition Status for 100 Mb
RO
8
3
PHY Port Partition Status for 10 Mb
RO
8
4
PHY Port Speed Status
RO
8
5
PHY Port Isolation Status
RO
8
6
Initial Device Configuration Register
R/W
8
7
Bridge Configuration Register
R/W
8
8
Device Revision Number
RO
0
0–31
PHY 1 Registers
0
0
PHY Control Register
R/W
3000
0
1
PHY Status Register
RO
2849
0
2
PHY Identifier 1 Register
RO
0022
0
3
PHY Identifier 2 Register
RO
5541
0
4
Auto-Negotiation Advertisement Register
RO
00A1
0
5
Auto-Negotiation Link Partner Ability Register
RO
0001
0
6
Auto-Negotiation Expansion Register
RO
0004
0
7
Auto Negotiation Next Page Transmit Register
RO
2001
0
8–15
Reserved
0
16
PHY 10BASE-T Configuration Register Control Register
0
17
PHY Interrupt Control/Status Register
0
18
Diagnostic Register
0000
R/W
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AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
Table 14: Register Set (Cont.)
PHY Addr
Offset Addr
Definition
Type
0
19
Reserved
RO
0
20
Cable Length Register
RO
0
21
Receive Error Count
0
22
Power Management Register
0
23
Transceiver Mode Register
0
24–31
Reserved
1
0–31
PHY 2 Registers
2
0–31
PHY 3 Registers
3
0–31
PHY 4 Registers
4
0–31
PHY 5 Registers
5
0–31
PHY 6 Registers
6
0–31
PHY 7 Registers
7
0–31
PHY 8 Registers
8
0–31
LED Effect Registers
8
16
Reserved
8
17
Reserved
RO
8
18
LED Effect with Partition/Isolation Event
R/W
8
19
LED Effect with Link Event
R/W
8
20
LED Effect with Activity (CRS) Event
R/W
8
21
LED Effect with AutoNeg Event
R/W
8
22
LED Effect with Speed100 Event
R/W
8
23
LED Register Control Mode
R/W
Default
0000
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Register Description
Page 19
AC208
Preliminary Data Sheet
07/08/02
PHY PORT STATUS REGISTER
Table 15: PHY Port Status Register
Name
Type
Address
Description
PHY Port Link Status
R
00
1 = Link good
0 = Default
PHY Port Polarity Status
R
01
1 = The polarity has been crossed
0 = Default
PHY Port Partition Status for 100 Mb
R
02
1 = The port has been partitioned
0 = Default
PHY Port Partition Status for 10 Mb
R
03
1 = The port has been partitioned
0 = Default
PHY Port Speed Status
R
04
1 = 100M
0 = 10M
0 = Default
PHY Port Isolation Status (Fast Ethernet Only)
R
05
1 = The port has been isolated
0 = Default
Table 16: PHY Port Status
15:9
8
7
6
5
4
3
2
1
0
RSV
MII
RSV
Port 5
Port 4
Port 3
Port 2
Port 1
RSV
RSV
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AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
INITIAL DEVICE CONFIGURATION REGISTER
Table 17: Initial Device Configuration Register
Name
Type
Address
Description
MII Configuration
R/W
06
Used to give the status of MII port. Default is set by pin.
Bit
Name
Type
Description
15:12
Mode
RO
Mode[3:2]
Default
Must be 00.
MODE pins
Mode[1:0]
00
Master mode, Bridge enable.
01
Slave mode, Bridge disable.
10
Slave mode, Uplink.
Port 7 is connected to the bridge
port in this mode. The other bridge
port is connected to 100 segment.
11
Slave mode, Bridge enable (mulitbridge mode).
11
Reserved
(Write clear enable)
RO
10
Reserved
(MIB enable)
RO
Reserved.
0
9
Disable partition
R/W
1:disable partition function of MII interface.
0
8
External transform
selection
R/W
1:external transform 1:1.25, 0:external transform
1:1.
Ext pin
7
MIIB Speed Select
R/W
1:100M interface, 0:10M interface.
Ext Pin
6:2
Switch debug
R/W
Selection control for debugging signals.
00000
1
100M repeater
Partition Alternative
R/W
0 = normal, un-partition a port only when data can
be transmitted out from the port for 560 bit-time
without a collision.
1 = alternate, un-partition a port when data can be
either transmitted from the port or received from the
port for 560 bit-time without a collision.
0
0
10M repeater Partition
Alternative
R/W
0 = normal, un-partition a port when data can be
either transmitted from the port or received from the
port for 560 bit-time without a collision.
1 = alternate, un-partition a port only when data can
be received from the port for 560 bit-time without a
collision
0
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AC208-DS04-405-R
Register Description
Page 21
AC208
Preliminary Data Sheet
07/08/02
BRIDGE CONFIGURATION REGISTER
Table 18: Bridge Configuration Register
Name
Type
Address
Description
Bridge Configuration
Register
R/W
07
Used to configure Bridge.
Bit
Name
Type
Description
Default
15
Watch Dog Reset
R/W
1 = reset when WDOG even occur
0 = does not reset when WDOG even occur
1
14
Loose Length
R/W
1 = receives frame with length from 1519 to 1548
0 = rejects frame with length over 1518
1
13
Dribble Error
R/W
1 = enable, 0:disable receive dribble error packets
0
12
Address Table
Initialization Disable
R/W
1 = disable, 0:enable address table init.
While this bit is 1, the address table only contains few entries
for speed up function verification.
0
11
Aging Speed Up
R/W
1 = enable, 0:disable aging speed up
0
10
10M Back Pressure
R/W
1 = enable, 0:disable 10M back pressure function
0
9
100M Back Pressure
R/W
1 = enable, 0:dieable 100M back pressure function
0
8
Collision Test
R/W
1 = enable, 0:disable collision test
0
7:0
Reserved
R
00
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Document
AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
PHY REGISTERS
The following registers are defined for each PHY port. The base addresses of PHY 1 to PHY 8 are 0, 1, 2, 3, 4, 5, 6, and 7,
respectively.
PHY CONFIGURATION REGISTER
Table 19: PHY Configuration Register 0
Bit
Name
Definition
Mode
Default
0.15
Reset
1 = PHY reset
This bit is self-clearing.
RW/SC
0
0.14
Loopback
1 = Loopback mode. Because it internally loops the transmit of
AC208 to its receive, it ignores all the activity on the cable media.
0 = Normal operation.
RW
0
0.13
Speed Select
1 = 100 Mbps
0 = 10 Mbps. This bit is ignored if auto-negotiation is enabled.
It no longer reflects auto-negotiation results.
RW
1
0.12
Auto-Neg Enable
1 = Enable auto-negotiate process (overrides 0.13 and 0.8)
0 = Disable auto-negotiate process.
In force mode, speed is selected via bit 0.13.
RW
1
0.11
Power Down
1 = Power down mode, puts AC208 in low-power stand-by mode,
only reacts to access transaction.
0 = Normal operation.
RW
0
0.10
Isolate
1 = Electrical isolation of PHY from MII and cable media.
0 = Normal operation.
RW
0
0.9
Restart AutoNegotiation
1 = Restart auto-negotiation process.
0 = Normal operation.
RW/
SC
0
0.8
Duplex Mode
1 = Full-duplex.
0 = Half-duplex.
Full-duplex is not supported on this chip.
It no longer reflects auto-negotiation results.
RO
0
0.7
Collision Test
1 = Enable collision test, which issues the COL signal in
response to the assertion of TX_EN signal.
0 = Disable COL test.
RW
0
0.6:0
Reserved
RO
000000
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PHY Registers
Page 23
AC208
Preliminary Data Sheet
07/08/02
PHY STATUS REGISTER
Table 20: PHY Status Register 1
Bit
Name
Definition
Mode
Default
1.15
100BASE-T4
Tied to 0 indicates no 100BASE-T4 capability.
RO
0
1.14
100BASE-TX
Full-duplex
Tied to 0 indicates no 100BASE-TX full-duplex support.
RO
0
1.13
100BASE-TX
Half-duplex
1 = 100BASE-TX with half-duplex.
0 = No TX half-duplex ability.
RO
1
1.12
10BASE-T Fullduplex
Tied to 0 indicates no 10BASE-T full-duplex support.
RO
0
1.11
10BASE-T Halfduplex
1 = 10BASE-T with half-duplex.
0 = No 10BASE-T half-duplex ability.
RO
1
1.10:6
Reserved
RO
00001
1.5
Auto-Negotiate
Complete
1 = Auto-negotiate process completed, indicates Reg. 4, 5, 6 are
valid.
0 = Auto-negotiate process not completed.
RO
N/A
1.4
Remote Fault
1 = Remote fault condition detected.
0 = No remote fault.
After this bit is set, it remains set until it is cleared by reading
register 1 via the MDC/MDIO interface.
SC/LH
N/A
1.3
Auto-Negotiate
Ability
1 = Able to perform auto-negotiation function, its value is
determined by ANEGA pin.
0 = Unable to perform auto-negotiation function.
RO
1
1.2
Link Status
1 = Link is established. If AC208 link fails, this bit becomes
cleared and remains cleared until register is read via the MDC/
MDIO interface.
0 = Link is down, or has been dropped.
SC/LL
0
1.1
Jabber Detect
1 = Jabber condition detect.
0 = No Jabber condition detected.
SC/LH
0
1.0
Extended
Capability
1 = Extended register capable. This bit is tied permanently to
one.
RO
1
1.15
100BASE-T4
Tied to 0 indicates no 100BASE-T4 capability.
RO
0
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AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
PHY IDENTIFIER 1 REGISTER
Table 21: PHY Identifier 1 Register
Register
Bit
Name
Description
Mode
Default
2.15:0
OUI*
Assigned to the third through eighteenth bits of the Organizationally
Unique Identifier (OUI).
RO
0022
(HEX)
PHY IDENTIFIER 2 REGISTER
Table 22: PHY Identifier 2 Register
Register
Bit
Name
Description
Mode
Default
3.15:10
OUI
Assigned to the nineteenth through twenty-fourth bits of the OUI.
RO
010101
3.9:4
Model
Number
Six bit manufacturer’s model number; 101 is encoded as 010001.
RO
010100
3.3:0
Revision
Number
Four bits manufacturer’s revision number. 0001 stands for Rev. A,
and so on.
RO
0001
AUTO-NEGOTIATION ADVERTISEMENT REGISTER
Table 23: Auto-Negotiation Advertisement Register
Bit
Name
Definition
Mode
Default
4.15
Next Page
1 = Desire Next Page.
0 = Next Page is not desired.
RW
0
4.14
Acknowledge
This bit is set internally after receiving three consecutive and
consistent FLP bursts.
RO
0
4.13
Remote Fault
1 = Remote fault detected.
0 = No remote fault.
RW
0
4.12:10
Reserved
For future technology.
RW
000
4.9
100BASE-T4
Tied to 0 indicates no 100BASE-T4 support.
RO
0
4.8
100BASE-TX
Full-duplex
1 = 100BASE-TX with full-duplex.
0 = No 100BASE-TX full-duplex ability.
RO
0
4.7
100BASE-TX
1 = 100BASE-TX capable.
0 = No 100BASE-TX capability.
RW
1
4.6
10BASE-T Fullduplex
1 = 10 Mbps with full-duplex.
0 = No 10 Mbps with full-duplex capability.
RO
0
4.5
10BASE-T
1 = 10 Mbps capable.
0 = No 10 Mbps capability.
RW
1
4.4:0
Selector Field
[00001] = IEEE 802.3.
RO
00001
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PHY Registers
Page 25
AC208
Preliminary Data Sheet
07/08/02
AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER
Table 24: Auto-Negotiation Link Partner Ability Register
Register
Bit
Name
Description
Mode
Default
5.15:0
Technology
Technology capability field, which indicates the technology capability
of link partner. The bit definition is the same as Reg. 4.15:0.
RO
0001(H)
AUTO-NEGOTIATION EXPANSION REGISTER
Table 25: Register 6: Auto-Negotiation Expansion Register
Register
Bit
Name
6.15:5
Reserved
6.4
Parallel
Detection Fault
6.3
Link Partner Next
Page Able
6.2
Next Page Able
6.1
Page Received
6.0
Link Partner
Auto-Negotiation
Able
Description
Mode
Default
RO
0000
0000
000
1 = Fault detected by parallel detection logic. This is caused by
unstable link, or concurrent link up condition.
0 = No fault detected by parallel detection logic.
SC/LH
0
1 = Link partner supports next page function.
0 = Link partner does not support next page function.
RO
0
RO
1
1 = A new link code word has been received. The contains of the
received link code word is located in Register 5.
SC/LH
0
1 = Link partner is auto-negotiation able.
1 = Link partner is not auto-negotiation able.
RO
0
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AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
AUTO-NEGOTIATION NEXT PAGE TRANSMIT REGISTER
Table 26: Auto-Negotiation Next Page Transmit Register
Register
Bit
Name
Description
Mode
Default
7.15
NP
1 = Another Next Page is desired.
RW
0
7.14
Reserved
RO
0
7.13
Message
Page
1 = Message page.
0 = Un-formatted Page.
RW
1
7.12
ACK2
Acknowledge2.
1 = Complies with message.
0 = Can not comply with message.
RW
0
7.11
Toggle
1 = Previous value of transmitted Link Code Word equal to 0.
0 = Previous value of transmitted Link Code Word equal to 1.
RO
N/A
7:10:0
Code
Message/Un-formatted Code Field.
RW
0001
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PHY Registers
Page 27
AC208
Preliminary Data Sheet
07/08/02
PHY 10BASE-T CONFIGURATION REGISTER
Table 27: PHY 10BASE-T Configuration Register
Register
Bit
Name
Description
Mode
Default
16.15
Repeater
1 = Repeater mode. Full-duplex is inactive, and CES only
responses to receive activity. SEQ test function is also
disabled.
0 = DTE mode.
RW
1
16.14
Reserved
RO
0
16.13
TXJAM
1=Force CIM to send jam pattern.
0=Normal operation mode
RO
0
16.12
CIM Disable
1 = Disable carrier integrity monitor function.
0 = Enable carrier integrity monitor function.
Default is ‘0’.
RW
1
16.11
SEQ Test Inhibit
1 = Disable 10BASE-T SEQ testing.
0 = Enable 10BASE-T SEQ testing. Generates a COL pulse
following the completion of a packet transmission.
RW
0
16.10
BASE-T Normal Loop
Back
1 = Enable 10BASE-T normal loop back.
0 = Disable 10BASE-T normal loop back.
RW
0
16.[9:6]
Reserved
RO
0
16:5
Auto polarity disable
1 = Disable auto polarity detection/correction.
0 = Enable auto polarity detection/correction.
RW
0
16.4
Reverse Polarity
When Reg16.5 is set to 0, this bit sets to 1. If Reverse
Polarity is detected on the media, it is set to 0. When
Reg16.5 is set to 1, writing a one to the bit reverses the
polarity of the transmitter.
Note: The reverse polarity is detected either through 8
inverted NLP or through a burst of inverted FLP.
RW
0
16:[3:0]
Reserved
RO
0
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AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
PHY INTERRUPT CONTROL/STATUS REGISTER
Table 28: PHY Interrupt Control/Status Register
Register
Bit
Name
Description
Mode Default
17.15
Jabber_IE
Jabber Interrupt Enable.
RW
0
17.14
Rx_Er_IE
Receive Error Interrupt Enable.
RW
0
17.13
Page_Rx_IE
Page Received Interrupt Enable.
RW
0
17.12
PD_Fault_IE
Parallel Detection Fault Interrupt Enable.
RW
0
17.11
LP_Ack_IE
Link Partner Acknowledge Interrupt Enable.
RW
0
17.10
Link_Schange_ IE
Link Status Changed Interrupt Enable.
RW
0
17.9
R_Fault_IE
Remote Fault Interrupt Enable.
RW
0
17.8
Aneg_Comp_IE
Auto-Neg Complete Interrupt Enable.
RW
0
17.7
Jabber_Int
This bit is set when a jabber event is detected.
RC
0
17.6
Rx_Er_Int
This bit is set when RX_ER transitions high.
RC
0
17.5
Page_Rx_Int
This bit is set when a new page is received from link partner during
Auto-Negotiation.
RC
0
17.4
PD_Fault_Int
This bit is set when parallel detect fault is detected.
RC
0
17.3
LP_Ack_Int
This bit is set when the FLP with acknowledge bit set is received.
RC
0
17.2
Link_Schanged Int
This bit is set when link status is changed.
RC
0
17.1
R_Fault_Int
This bit is set when remote fault is detected.
RC
0
17.0
A_Neg_Comp Int
This bit is set when Auto-Neg is completed.
RC
0
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AC208-DS04-405-R
PHY Registers
Page 29
AC208
Preliminary Data Sheet
07/08/02
DIAGNOSTIC REGISTER
Table 29: Diagnostic Register
Register
Bit
Name
Description
Mode
Default
18.15
Lp_lpbk
Link pulse loopback.
1 = loopback the link pulse for auto-negotiation testing
RW
0
18.14
Send_nlp
1 = force link pulse generator to send nlp event in auto-negotiation
mode.
RW
0
18.13
Force link
pass bt
1 = force 10BASE-T link pass
RW
0
18.12
Force link
pass tx
1 = force 100 TX link pass
RW
0
18.11
DPLX
This bit indicates the result of the Auto-Neg for duplex arbitration.
RO
0
18.10
Speed
This bit indicates the result of the Auto-Neg for data speed arbitration.
RO
X
18.9
RX_PASS
In 10BASE-T mode, this bit indicates that Manchester data has been
detected.
In 100BASE-T mode, it indicates valid signal has been received but
not necessarily locked on to.
RC
X
18.8
RX_LOCK
Indicates the receive PLL has locked onto the received signal for the
selected speed of operation (10BASE-T or 100BASE-TX). This bit is
set whenever a cycle-slip occurs, and will remain set until it is read.
RC
X
18.[7:4]
ARB_STATE
HIGHEST
Highest state of Auto-Negotiation state machine since reset on last
read operation.
RC
TBD
18.[3:0]
ARB_STATE
LOWEST
Lowest state of Auto-Negotiation state machine since reset on last
read operation.
RC
TBD
CABLE LENGTH REGISTER
Table 30: Cable Length Register
Register
Bit
Name
20.[15:9]
Reserved
20.8
Adaptation
disable
20.[7:4]
20.[3:0]
Description
Mode
Default
RO
0000000
1 = Disable adaptation
RW
0
Cable
Length
Indication
These bits indicate cable length from 0 to 150m. Each bit represents
10m. For example, if the cable length is 100m then bits [7:4] = 1010.
These bits are only applicable to 100TX mode.
RW
XXXX
Adaptation
Low limit
Adaptation setting, when SD signal is first detected.
RO
XXXX
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AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
RECEIVE ERROR COUNT
Table 31: Receive Error Count
Register
Bit
Name
Description
Mode
Default
21.[15:0
]
Receive Error
Count
Count number of receiving packets with error. This register can
only be cleared by reset (software or hardware).
RO
0000
POWER MANAGEMENT REGISTER
Table 32: Power Management Register
Register Bit Name
Description
Mode
Default
RO
00
22.[15:14]
Reserved
22.13
PD_PLL
1=Power down PLL circuit
RO
X
22.12
PD_EQUAL
1=Power down equalizer circuit
RO
X
22.11
PD_BT_RCVR
1=Power down 10BASE-T receiver
RO
X
22.10
PD_LP
1=Power down link pulse receiver
RO
X
22.9
PD_EN_DET
1=Power down energy detect circuit
RO
X
22.8
PD_FX
1=Power down FX circuit
RO
X
22.[7:6]
Reserved
RW
00
22.5
MSK_PLL
0=Force power up PLL circuit
RW
X
22.4
MSK_EQUAL
0=Force power up equalizer circuit
RW
X
22.3
MSK_BT_RCVR
0=Force power up 10BASE-T receiver
RW
X
22.2
MSK_LP
0=Force power up link pulse receiver
RW
X
22.1
MSK_EN_DET
0=Force power up energy detect circuit
RW
X
22.0
MSK_FX
0=Force power up FX circuit
RW
X
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PHY Registers
Page 31
AC208
Preliminary Data Sheet
07/08/02
TRANSCEIVER MODE REGISTER
Table 33: Transceiver Mode Register
Register
Bit
Name
23.15
Description
Mode
Default
Reserved
RO
0
23.14
Reserved
RO
0
23.13
Clk_rclk_save
RW
0
23.12
Reserved
RO
0
23.11
Scramble
disable
1 = disable scrambler
RW
0
23.10
Serial bt
enable
1 = enable serial bt mode
RW
0
23.9
Pcsbp
1 = enable PCS bypass mode
RW
0
23:8
Age timer en
1 = enable age timer in adaptation
0 = disable age timer in adaptation.
RW
0
23.7
Reserved
RO
0
23:6
Reserved
RO
0
23.5
Force re-adapt
1 = force adaptation to re-adapt
Writing a 1 to this bit forces adaptation to re-adapt. This bit is
always read as 0.
RO
0
23.[4:0]
Dlock drop
counter
D lock drop counter
RO
XXXXX
1 = set rclk save mode. Rclk is hut off after 64 cycles of each
packet
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AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
TEST AND LED EFFECT REGISTER
This set of the registers is defined for the whole chip. The base address is hex 08.
LED EFFECT WITH PARTITION/ISOLATION EVENT
Table 34: LED Effect with Partition/Isolation Event
Register
Bit
Name
Description
Mode
Default
15:12
Blink Rate [7:4]
Set the blink rate bits [7:0] with LED Effect with Partition/Isolation
Event Register (PHY Addr = 8; Reg Addr = 18), abbreviated as
REG_LED_EFFECT in the following equation.
Blink Rate = 1 / (16 ms x {REG_LED_EFFECT[15:12],
4‘b0000} x 2)
RW
0001
11:10
Reserved
RO
00
9:8
LED On with
Part/ISO Event
RW
00
7:6
Reserved
RO
00
5:4
LED Blink with
Part/ISO Event
RW
00
3:2
Reserved
RO
00
1:0
LED Off with
Part/ISO Event
RW
00
Mode
Default
RO
00000
RW
11
RO
00
RW
11
RO
00
RW
00
When Partition/Isolation, turn on corresponding LED 1:0.
When Partition/Isolation, blink corresponding LED 1:0.
When Partition/Isolation, turn off corresponding LED 1:0.
LED EFFECT WITH LINK EVENT
Table 35: LED Effect with Link Event
Register
Bit
Name
15:10
Reserved
9:8
LED On with Link
Event
7:6
Reserved
5:4
LED Blink with Link
Event
3:2
Reserved
1:0
LED Off with Link
Event
Description
When Link Up, turn on corresponding LED 1:0.
When Link Up, blink corresponding LED 1:0.
When Link Up, turn off corresponding LED 1:0.
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AC208-DS04-405-R
Test and LED Effect Register
Page 33
AC208
Preliminary Data Sheet
07/08/02
LED EFFECT WITH ACTIVITY (CRS) EVENT
Table 36: LED Effect with Activity (CRS) Event
Register
Bit
Name
15:10
Reserved
9:8
LED On with
Activity Event
7:6
Reserved
5:4
LED Blink with
Activity Event
3:2
Reserved
1:0
LED Off with
Activity Event
Description
When Activity, turn on corresponding LED 1:0.
When Activity, blink corresponding LED 1:0.
When Activity, turn off corresponding LED 1:0.
Mode
Default
RO
00000
RW
00
RO
00
RW
11
RO
00
RW
00
Mode
Default
RO
00000
RW
00
RO
00
RW
00
RO
00
RW
00
LED EFFECT WITH AUTO-NEGOTIATING EVENT
Table 37: LED Effect with Auto-Negotiating Event
Register
Bit
Name
15:10
Reserved
9:8
LED On with Autonegotiating Event
7:6
Reserved
5:4
LED Blink with
Auto-negotiating
Event
3:2
Reserved
1:0
LED Off with Autonegotiating Event
Description
When Auto-negotiating, turn on corresponding LED 1:0.
When Auto-negotiating, blink corresponding LED 1:0.
When Auto-negotiating, turn off corresponding LED 1:0.
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AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
LED EFFECT WITH SPEED100 EVENT
Table 38: LED Effect with Speed100 Event
Register
Bit
Name
15:10
Reserved
9:8
LED On with
Speed100 Event
7:6
Reserved
5:4
LED Blink with
Speed100 Event
3:2
Reserved
1:0
LED Off with
Speed100 Event
Description
When Speed100, turn on corresponding LED 1:0.
When Speed100, blink corresponding LED 1:0.
When Speed100, turn off corresponding LED 1:0.
Mode
Default
RO
00000
RW
01
RO
00
RW
01
RO
00
RW
10
LED REGISTER CONTROL MODE
Table 39: LED Register Control Mode
Register
Bit
Name
Description
Mode
Default
15:8
LED Data
Set value shown on the LED_D[7:0].
RW
000000
7:6
Reserved
RO
00
5:0
LED Column
RW
000000
Control which lane of the LED_D should be turned on.
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AC208-DS04-405-R
Test and LED Effect Register
Page 35
AC208
Preliminary Data Sheet
07/08/02
EEPROM TABLE
EEPROM is used to configure the initial setting of Bridge, Repeater, and Transceiver.
Table 40: EEPROM
Address
Description
Default
Assign to
0
First Word
5A3C
1
Test Configuration Register0
0080
PHY=8, Reg=28
2
Initial Repeater Configuration Register
0180
PHY=8, Reg=6
3
Bridge Configuration Register
D000
PHY=8, Reg=7
4
Initialize Port 0 Configuration Register
3000
PHY=0, Reg=0
5
Initialize Port 1 Configuration Register
3000
PHY=1, Reg=0
6
Initialize Port 2 Configuration Register
3000
PHY=2, Reg=0
7
Initialize Port 3 Configuration Register
3000
PHY=3, Reg=0
8
Initialize Port 4 Configuration Register
3000
PHY=4, Reg=0
9
Initialize Port 5 Configuration Register
3000
PHY=5, Reg=0
10
Initialize Port 6 Configuration Register
3000
PHY=6, Reg=0
11
Initialize Port 7 Configuration Register
3000
PHY=7, Reg=0
12
LED Effect with Partition/Isolation Event
1000
PHY=8, Reg=18
13
LED Effect with Link Event
0330
PHY=8, Reg=19
14
LED Effect with Activity (CRS) Event
0030
PHY=8, Reg=20
15
LED Effect with AutoNeg Event
0000
PHY=8, Reg=21
16
LED Effect with Speed100 Event
0200
PHY=8, Reg=22
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AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
4B/5B CODE-GROUP TABLE
Table 41: 4B/5B Code-Group Table
PCS Code Group[4:0] Symbol Name
MII (TXD/RXD [3:0])
Description
11110
0
0000
Data 0
01001
1
0001
Data 1
10100
2
0010
Data 2
10101
3
0011
Data 3
01010
4
0100
Data 4
01011
5
0101
Data 5
01110
6
0110
Data 6
01111
7
0111
Data 7
10010
8
1000
Data 8
10011
9
1001
Data 9
10110
A
1010
Data A
10111
B
1011
Data B
11010
C
1100
Data C
11011
D
1101
Data D
11100
E
1110
Data E
11101
F
1111
Data F
Idle and Control Code
11111
I
0000
Inter-Packet Idle; used as inter-stream fill code.
11000
J
0101
Start of stream delimiter, part 1 of 2; always use
in pair with K symbol.
10001
K
0101
Start of stream delimiter, part 2 of 2; always use
in pair with J symbol.
01101
T
Undefined
End of stream delimiter, part 1 of 2; always use
in pair with R symbol.
00111
R
Undefined
End of stream delimiter, part 2 of 2; always use
in pair with T symbol.
00100
H
Undefined
Transmit Error; used to send HALT code-group
00000
V
Undefined
Invalid code
00001
V
Undefined
Invalid code
00010
V
Undefined
Invalid code
00011
V
Undefined
Invalid code
00101
V
Undefined
Invalid code
00110
V
Undefined
Invalid code
01000
V
Undefined
Invalid code
01100
V
Undefined
Invalid code
10000
V
Undefined
Invalid code
11001
V
Undefined
Invalid code
Invalid Code
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Document
AC208-DS04-405-R
EEPROM Table
Page 37
AC208
Preliminary Data Sheet
07/08/02
LED DISPLAY MATRIX
The LED Display uses refresh technique. By using the LED display matrix, the number of ports to drive the LED can be
significantly reduced. Two LEDs are assigned for each port. On, Off, and Flash states are used to indicate different
information. With reduced LED counts, and reduced number of signals, the LED display will be easier to route on the board,
and less costly.
LED_D[7]
LED_D[6]
LED_D[5]
LED_D[4]
LED_D[3]
LED_D[2]
LED_D[1]
LED_D[0]
330 OHM
330 OHM
330 OHM
330 OHM
330 OHM
330 OHM
330 OHM
330 OHM
D?
D
D
D?
D
D
D?
D
LE
LE
LE
LE
LE
LE
LE
LE
D?
D
D
D?
D
D
D?
D
LE
LE
LE
LE
LE
LE
LE
LE
D?
D
D
D?
D
D
D?
D
LE
LE
LE
LE
LE
LE
LE
LE
D?
D
D
D?
D
D
D?
D
LE
LE
LE
LE
LE
LE
LE
LE
D?
D
D
D?
D
D
D?
D
LE
LE
LE
LE
LE
LE
LE
LE
D?
D
D
D?
D
D
D?
D
LE
LE
LE
LE
LE
LE
LE
LE
LED_LN[5]
LED_LN[4]
LED_LN[3]
LED_LN[2]
LED_LN[1]
LED_LN[0]
Figure 5: LED Display Matrix
SYSTEM CONSIDERATIONS
The design of the chip is optimized for low cost 10/100 Mb unmanaged repeater applications. It also provides flexibility for
systems that require multiple LAN ports within the same unmanaged repeater domain.
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Page 38 LED Display Matrix
Document
AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
Se ction 4: Electr ic al C ha rac te ristics
The following electrical characteristics are design goals rather than characterized numbers.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature............................... –55oC to +150oC
Vcc Supply Referenced to GND............. –0.5V to 2.5V
Digital Input Voltage............................... –0.5V to 3.3V
DC Output Voltage.................................. –0.5V to Vcc
OPERATING RANGE
Operating Temperature (Ta)........................... 0oC to 70oC
Vcc Supply Voltage Range (Vcc).................. 2.375V to 2.625V
Table 42: Total Power Consumption
Parameter
Symbol
Conditions
Supply Current
(per port)
Icc
10BASE-T, Idle
10BASE-T, Normal activity
100BASE-TX
10/100BASE-TX, low power without
cable
Power down
Supply Current
(dual speed
hub)
Icc
Mode 00
Mode 01
Mode 10
Mode 11
Minimum Typical
Master
Slave, Bridge disabled
Slave, Uplink
Slave, Bridge enabled
53
Maximum
Units
53
153
103
44
44
mA
mA
mA
mA
mA
mA
mA
mA
680
620
680
680
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AC208-DS04-405-R
Electrical Characteristics
Page 39
AC208
Preliminary Data Sheet
07/08/02
Table 43: TTL I/O Characteristics
Parameter
Symbol
Conditions
Input Voltage High
Vih
Input Voltage Low
Vil
Input Current
Ii
–10
Output Voltage High
Voh
2.0
Output Voltage Low
Vol
Output Current High
Ioh
8
mA
Output Current Low
Iol
-8
mA
Input Capacitance
Ci
Typical
Maximum
Units
2.0
V
0.8
V
10
mA
V
0.4
Output Transition Time
Tristate Leakage
Current
Minimum
3.15V < VCC < 3.45V
V
10
pF
5
ns
|Ioz|
10
uA
REFCLK PINS
Table 44: REFCLK Pins
Parameter
Symbol
Input Voltage Low
Vil
Input Voltage High
Vih
Input Clock Frequency Tolerance
F
Input Clock Duty Cycle
Tdc
Input Capacitance
Cin
Conditions
Minimum
Typical
Maximum Units
0.8
V
2.0
V
100
ppm
40
60
%
3.0
pF
I/O CHARACTERISTICS—LED PINS
Table 45: I/O Characteristics—LED Pins
Parameter
Symbol
Output Low Voltage
Vol
Output High Voltage
Voh
Input Current
Ii
Output Current
Io
Conditions
Minimum
Typical
Maximum
Units
0.4
V
V
27
mA
mA
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Page 40 Operating Range
Document
AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
100BASE-TX TRANSCEIVER CHARACTERISTICS
Table 46: 100BASE-TX Transceiver Characteristics
Parameter
Symbol
Conditions
Minimum
Typical
Maximum Units
Peak to Peak Differential
Output Voltage
Vp
Note 1
1.9
2.0
2.1
V
Output Voltage Symmetry
Vss
Note 1
0.98
1.02
mV
Signal Rise/Fall Time
Trf
Note 1
3.0
5.0
ns
Rise/Fall Time Symmetry
Trfs
Note 1
0
0.5
ns
Duty Cycle Distortion
Dcd
0
0.5
ps
Overshoot/Undershoot
Vos
5
%
1.4
ns
4
ns
Output Jitter
Scrambled Idle
Receive Jitter Tolerance
Output Current High
Ioh
1:1 Transformer
40
mA
Output Current High
Ioh
1.25:1
Transformer
32
mA
Common Mode Input Voltage
1.25
V
Differential Input Resistance
4
kΩ
Note 1: 50Ω (± 1%) resistor to VCC on each output
10BASE-T TRANSCEIVER CHARACTERISTICS
Table 47: 10BASE-T Transceiver Characteristics
Parameter
Symbol
Conditions
Minimum
Typical
Maximum
Units
Peak to Peak Differential
Output Voltage
Vop
Note 1
4.4
5
5.6
V
350
ns
Output Jitter
1.4
ns
Receive Jitter Tolerance
32
ns
500
mV
Start of Idle Pulse Width
Differential Squelch Threshold
300
Vds
300
Common Mode Rejection
400
25
V
Note 1: 50Ω (± 1%) resistor to VCC on each output
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Document
AC208-DS04-405-R
Operating Range
Page 41
AC208
Preliminary Data Sheet
07/08/02
S e c t io n 5 : Di gi t a l T i m i ng C ha r a c t e r i s t i c s
POWER ON RESET
Table 48: Power on Reset
Minimu
m
Typical
Maximu
m
Units
tRST
150
-
-
µs
tCONF
100
-
-
ns
Parameter
Symbol
RST* Low Period
Configuration
Conditions
tRST
RST*
All
Configuration
Pins
tCONF
Figure 6: Power on Reset
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Page 42 Digital Timing Characteristics
Document
AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
PHY MDC/MDIO INTERFACE
Table 49: PHY MDC/MDIO Interface
Parameter
Symbol
MDC CLOCK
Conditions
Minimum
Typical
Maximum Units
tMDCL
-
300
-
ns
MDC CLOCK
tMDCH
-
300
-
ns
Receive Data Setup
Time
tRDS
Setup on Read Cycle
10
-
-
ns
Receive Data Hold
Time
tRDH
Hold on Read Cycle
10
-
-
ns
Transmit Data Delay
Time
tTDD
Delay on Write Cycle
3
-
18
ns
tM D C L
tM D C H
M DC
tR D S
M D IO
(I N )
tR D H
tT D D
M D IO
(O )
Figure 7: PHY MDC/MDIO Interface
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Document
AC208-DS04-405-R
PHY MDC/MDIO Interface
Page 43
AC208
Preliminary Data Sheet
07/08/02
100 MBPS REPEATER BACKPLANE RECEIVE/TRANSMIT TIMING
Table 50: 100 Mbps Repeater BackPlane Receive/Transmit Timing
Parameter
Symbol
Minimum
Typical
Maximum
MS100D_CLK Period
tCK
MS100D_CLK High period
tCKH
18
22
ns
MS100D_CLK Low period
tCKL
18
22
ns
RXIP/N to Control Assert
tJC
180
ns
RXIP/N to Control De-assert
tTC
180
ns
RXIP/N to M100COL_SYS* Assert
tCCS
200
ns
Control Falling to MS100CRS_SYS*/
MS100D_EN Falling Delay Time
tCSC
30
ns
MS100D to MS100D_CLK Rising Setup Time
tDS
12
ns
MS100D to MS100D_CLK Rising Hold Time
tDH
5
ns
Control Assert to TXOP/N Valid
tCLT
300
Control De-assert to TXOP/N Invalid
tCHT
200
40
Units
ns
ns
Control is the combination of the following signals:
M100ACT0*, M100ACT1_0*, M100ACT1_1*, M100ACT1_2*
Start of Packet
End of Packet
RXIP/N
tJC
tTC
Control*
tCCS
M100COL_SYS*
MS100CRS_SYS*/
MS100D_EN*
tCSC
tCK
tCKH
tCKL
MS100D_CLK
tDS
tDH
MS100D
tCLT
tCHT
TXOP/N
Figure 8: 100 Mbps RBP Receive/Transmit Timing
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Page 44 100 MBPS Repeater BackPlane Receive/Transmit Timing
Document
AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
10 MBPS REPEATER BACKPLANE RECEIVE/TRANSMIT TIMING
Table 51: 10 Mbps Repeater BackPlane Receive/Transmit Timing
Parameter
Symbol
Minimum
Typical
Maximum Units
MS10D_CLK Period
tCK
MS10D_CLK High Period
tCKH
40
60
ns
MS10D_CLK Low Period
tCKL
40
60
ns
RXIP/N to Control Assert
tJC
280
ns
RXIP/N to Control De-assert
tTC
280
ns
RXIP/N to C10COL_SYS* Assert
tCCS
300
ns
Control Falling to MS10CRS_SYS*/MS10D_EN*
Falling Delay Time
tCD
30
ns
MS10D to M10D_CLK Rising Setup Time
tDS
20
ns
MS10D to MS10D_CLK Rising Hold Time
tDH
5
ns
Control Assert to TXOP/N Valid
tCLT
720
ns
Control De-assert to TXOP/N Invalid
tCHT
4000
ns
100
ns
Control is the combination of the following signals:
M10ACT0*, M10ACT1_0*, M10ACT1_1*, M10ACT1_2*
SOP
EOP
RXIP/N
tJC
tTC
Control*
tCCS
M10COL_SYS*
MS10CRS_SYS*/
MS10D_EN*
tCSC
tCK
tCKH
tCKL
MS10D_CLK
tDS
tDH
MS10D
tCLT
tCHT
TXOP/N
Figure 9: 10 Mbps RBP Receive/Transmit Timing
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Document
AC208-DS04-405-R
10 MBPS Repeater BackPlane Receive/Transmit Timing
Page 45
AC208
Preliminary Data Sheet
07/08/02
EEPROM INTERFACE TIMING
Table 52: EEPROM Interface Timing
Parameter
Symbol
Conditions
Minimum
Typical
Maximum
PROM_CLK Period
tECK
-
5120
-
ns
PROM_CLK Low Period
tECKL
2550
-
2570
ns
PROM_CLK High Period
tECKH
2550
-
2570
ns
PROM_IN to PROM_CLK Rising Hold Time
tERDS
10
-
-
ns
PROM_IN to PROM_CLK Rising Hold Time
tERDH
10
-
-
ns
PROM_CLK Falling to PROM_OUT Output
Delay Time
tEWDD
-
-
20
PROM_CS
tECKH
tECKL
PROM_CLK
tEWDD
tECK
PROM_OUT
tERDS
tERDH
PROM_IN
Figure 10: EEPROM Interface Timing
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Page 46 EEPROM Interface Timing
Document
AC208-DS04-405-R
Preliminary Data Sheet
AC208
07/08/02
LED TIMING
Table 53: LED Timing
Parameter
Symbol
Conditions
Minimum
Typical
Maximum Units
Pulse Width
tPW
2
ms
LED_D[n] Falling to
LED_D[n+1] Falling
tPP
2
ms
LED_D[n] Falling to
LED_D[n] Falling
tPD
16
ms
LED_LN[5:0]
LED_D[7]
tPW
LED_D[6]
tPP
LED_D[5]
tPD
LED_D[4]
LED_D[3]
LED_D[2]
LED_D[1]
LED_D[0]
Figure 11: LED Timing
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AC208-DS04-405-R
LED Timing
Page 47
Preliminary Data Sheet
AC208
07/08/02
TX APPLICATION TERMINATION
49.9 Ω 1%
49.9 Ω 1%
2.5V
0.1 µF
AC208
RJ45
Transformer
TXON
TXOP
IBREF
TXC_P
TX+_P
TX-_P
TXC_S
TX+_S
TX-_S
RX+_P
RX-_P
RXC_P
RX+_S
RX-_S
RXC_S
1 TX+
2 TX3 RX+
4 Unused
5 Unused
6 RX7 Unused
8 Unused
10 KΩ
1%
0.1 µF
75 Ω X 4
RXIP
110 Ω 1%
RXIN
1000 pF
3 KV
Chassis GND
Figure 12: Application Termination
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Document
AC208-DS04-405-R
TX Application Termination
Page 48
Preliminary Data Sheet
AC208
07/08/02
Sec t ion 6 : M echa nica l Info rm ation
Table 54: Package Dimensions for the AC208
N
A
A1
A2
B
D
D1
D2
E
E1
E2
e
L
L1
128
3.40
Max
0.25 Min
2.70 ±
0.2
0.200 ±
0.1
23.20 ±
0.25
20.00 ±
0.10
18.5 ±
0.10
17.20 ±
0.25
14.00 ±
0.10
12.50 ±
0.10
0.50
0.88 ±
0.2
1.60 ±
0.12
65
103
E2
E1
E
39
1
D2
D1
D
L
B
A2
L1
A
e
A1
Figure 13: 128-Pin PQFP
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Document
AC208-DS04-405-R
Mechanical Information
Page 49
AC208
Preliminary Data Sheet
07/08/02
S e c t i on 7: O rd e r i n g I nfo r m a t io n
Table 55: Ordering Information
Part Number
Package
Ambient Temperature
AC208KQM
128-pin PQFP
0° to 70° C
Broadcom
Altima Communications, Inc.
A Wholly Owned Subsidiary of
Broadcom Corporation
P.O. Box 57013
16215 Alton Parkway
Irvine, CA 92619-7013
Broadcom® Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design.
Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation
does not assume any liability arising out of the application or use of this information, nor the application or use of any product or
circuit described herein, neither does it convey any license under its patent rights nor the rights of others.
Document AC208-DS04-405-R