AD AD9461-LVDS/PCB 16-bit, 130 msps if sampling adc Datasheet

16-Bit, 130 MSPS IF Sampling ADC
AD9461
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD1 AVDD2
DRGND DRVDD
DFS
AD9461
DCS MODE
BUFFER
VIN+
VIN–
CLK+
CLK–
PIPELINE
ADC
T/H
16
CMOS
OR
LVDS
OUTPUT
STAGING
2
32
OUTPUT MODE
OR
D15 TO D0
2
CLOCK
AND TIMING
MANAGEMENT
DCO
REF
VREF SENSE REFT REFB
06011-001
130 MSPS guaranteed sampling rate
78.7 dBFS SNR/90 dBc SFDR with 10 MHz input
(3.4 V p-p input, 130 MSPS)
77.7 dBFS SNR with 170.3 MHz input
(4.0 V p-p input, 130 MSPS)
77.0 dBFS SNR/84 dBc SFDR with 170 MHz input
(3.4 V p-p input, 130 MSPS)
76.3 dBFS SNR/86 dBc SFDR with 225 MHz input
(3.4 V p-p input, 125 MSPS)
89 dBFS two-tone SFDR with 169 MHz and 170 MHz
(130 MSPS)
60 fsec rms jitter
Excellent linearity
DNL = ±0.6 LSB typical
INL = ±5.0 LSB typical
2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output clock available
Figure 1.
APPLICATIONS
MRI receivers
Multicarrier, multimode, cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Communications instrumentation
Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
and output data mode.
The AD9461 is available in a Pb-free, 100-lead, surface-mount,
plastic package (100-lead TQFP_EP) specified over the industrial
temperature range −40°C to +85°C.
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION
1.
True 16-bit linearity.
The AD9461 is a 16-bit, monolithic, sampling, analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit. It is
optimized for performance, small size, and ease of use. The
AD9461 operates up to 130 MSPS, providing a superior signalto-noise ratio (SNR) for instrumentation, medical imaging, and
radar receivers using baseband (<100 MHz) and IF frequencies.
2.
High performance: outstanding SNR performance for
baseband IFs in data acquisition, instrumentation,
magnetic resonance imaging, and radar receivers.
3.
Ease of use: on-chip reference and high input impedance
track-and-hold with adjustable analog input range and an
output clock simplifies data capture.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are CMOS or LVDS compatible
(ANSI-644 compatible) and include the means to reduce the
overall current needed for short trace distances.
4.
Packaged in a Pb-free, 100-lead TQFP_EP.
5.
Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths.
6.
Out-of-range (OR) outputs indicate when the signal is
beyond the selected input range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD9461
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configurations and Function Descriptions ............................8
Functional Block Diagram .............................................................. 1
Equivalent Circuits......................................................................... 12
Applications....................................................................................... 1
Typical Performance Characteristics ........................................... 13
General Description ......................................................................... 1
Terminology .................................................................................... 16
Product Highlights ........................................................................... 1
Theory of Operation ...................................................................... 17
Revision History ............................................................................... 2
Analog Input and Reference Overview ................................... 17
Specifications..................................................................................... 3
Clock Input Considerations...................................................... 18
DC Specifications ......................................................................... 3
Power Considerations................................................................ 19
AC Specifications.......................................................................... 4
Digital Outputs ........................................................................... 20
Digital Specifications ................................................................... 5
Timing ......................................................................................... 20
Switching Specifications .............................................................. 5
Operational Mode Selection ..................................................... 20
Timing Diagrams.......................................................................... 6
Evaluation Board ............................................................................ 21
Absolute Maximum Ratings............................................................ 7
Outline Dimensions ....................................................................... 28
Thermal Resistance ...................................................................... 7
Ordering Guide .......................................................................... 28
ESD Caution.................................................................................. 7
REVISION HISTORY
4/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD9461
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.4 V p-p differential input, internal
trimmed reference (1.0 V mode), AIN = −1.0 dBFS, DCS on, SFDR = AGND, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Temp
Full
Full
Full
25°C
Full
25°C
Full
25°C
Differential Nonlinearity (DNL) 1
Integral Nonlinearity (INL)1
VOLTAGE REFERENCE
Output Voltage VREF = 1.7 V
Load Regulation @ 1.0 mA
Reference Input Current (External VREF = 1.7 V)
INPUT REFERRED NOISE
ANALOG INPUT
Input Span
VREF = 1.7 V
VREF = 1.0 V
Internal Input Common-Mode Voltage
External Input Common-Mode Voltage
Input Resistance 2
Input Capacitance2
POWER SUPPLIES
Supply Voltage
AVDD1
AVDD2
DRVDD—LVDS Outputs
DRVDD—CMOS Outputs
Supply Current1
AVDD1
AVDD21, 3
IDRVDD1—LVDS Outputs
IDRVDD1—CMOS Outputs
PSRR
Offset
Gain
POWER CONSUMPTION
LVDS Outputs
CMOS Outputs (DC Input)
−4.2
−3
−3.4
−1.0
−1.0
−7
AD9461BSVZ
Typ
Max
16
Guaranteed
±0.1
+4.2
±0.5
+3
+3.4
±0.6
+1.0
+1.3
±5.0
+7
Unit
Bits
mV
% FSR
% FSR
LSB
LSB
LSB
Full
Full
Full
25°C
+1.7
±2
350
2.6
V
mV
μA
LSB rms
Full
Full
Full
Full
Full
Full
3.4
2.0
3.5
V p-p
V p-p
V
V
kΩ
pF
Full
Full
Full
Full
1
Min
3.2
3.9
1
6
3.14
4.75
3.0
3.0
3.3
5.0
3.3
Full
Full
Full
Full
405
131
72
14
Full
Full
1
0.2
Full
Full
2.2
2.0
3.46
5.25
3.6
3.6
V
V
V
V
426
143
81
mA
mA
mA
mA
mV/V
%/V
2.4
W
W
Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.
3
For SFDR = AVDD1, IAVDD2 decreases by ~8 mA, decreasing power dissipation.
2
Rev. 0 | Page 3 of 28
AD9461
AC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 3.4 V p-p differential input, internal
trimmed reference (1.7 V mode), AIN = −1.0 dBFS, DCS on, SFDR = AGND, unless otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 10 MHz
fIN = 170 MHz 1
fIN = 225 MHz
fIN = 225 MHz @125 MSPS
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 10 MHz
fIN = 170 MHz1
fIN = 225 MHz
fIN = 225 MHz @125 MSPS
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 170 MHz1
fIN = 225 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR, SECOND OR THIRD HARMONIC)
fIN = 10 MHz
fIN = 170 MHz1
fIN = 225 MHz
fIN = 225 MHz @125 MSPS
WORST SPUR EXCLUDING SECOND OR THIRD HARMONICS
fIN = 10 MHz
fIN = 170 MHz1
fIN = 225 MHz
fIN = 225 MHz @ 125 MSPS
TWO-TONE SFDR
fIN = 169.6 MHz @ −7 dBFS, 170.6 MHz @ −7 dBFS
ANALOG BANDWIDTH
1
Temp
Min
25°C
Full
25°C
Full
25°C
25°C
76.3
76.0
74.2
73.8
25°C
Full
25°C
Full
25°C
25°C
74.0
74.0
71.9
68.3
SFDR = high (AVDD1). See the Operational Mode Selection section.
Rev. 0 | Page 4 of 28
77.7
76.0
74.4
75.3
25°C
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
82
80
77
71
25°C
Full
25°C
Full
25°C
25°C
88
86
89
85
25°C
Full
AD9461BSVZ
Typ
Max
76.7
Unit
dB
dB
dB
dB
dB
dB
73.5
74.6
dB
dB
dB
dB
dB
dB
12.5
12.2
11.9
Bits
Bits
Bits
90
dBc
dBc
dBc
dBc
dBc
dBc
75.1
84
82
86
96
91
93
dBc
dBc
dBc
dBc
dBc
dBc
89
615
dBFS
MHz
95
AD9461
DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDS_BIAS = 3.74 kΩ, unless otherwise noted.
Table 3.
Parameter
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUT BITS—CMOS MODE (D0 to D15, OTR) 1
High Level Output Voltage
Low Level Output Voltage
DIGITAL OUTPUT BITS—LVDS MODE (D0 to D15, OTR)
VOD Differential Output Voltage 2
VOS Output Offset Voltage
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage
Common-Mode Voltage
Input Resistance
Input Capacitance
1
2
Temp
Min
Full
Full
Full
Full
Full
2.0
AD9461BSVZ
Typ
Max
0.8
200
+10
−10
2
Full
Full
3.25
Full
Full
247
1.125
Full
Full
Full
Full
0.2
1.3
1.1
1.5
1.4
2
Unit
V
V
μA
μA
pF
0.2
V
V
545
1.375
mV
V
1.6
1.7
V
V
kΩ
pF
Output voltage levels measured with 5 pF load on each output.
LVDS RTERM = 100 Ω.
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High 1 (tCLKH)
CLK Pulse Width Low1 (tCLKL)
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (tPD) 2 (Dx, DCO+)
Output Propagation Delay—LVDS (tPD) 3 (Dx+), (tCPD)3 (DCO+)
Pipeline Delay (Latency)
Aperture Uncertainty (Jitter, tJ)
1
Temp
Min
Full
Full
Full
Full
Full
130
Full
Full
Full
Full
With duty cycle stabilizer (DCS) enabled.
Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.
3
LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
2
Rev. 0 | Page 5 of 28
AD9461BSVZ
Typ
Max
1
7.7
3.1
3.1
2.3
3.35
3.6
13
60
4.8
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
Cycles
fsec rms
AD9461
TIMING DIAGRAMS
N–1
N + 15
N
N + 14
N+1
AIN
N + 13
tCLKL
tCLKH
1/fS
CLK+
CLK–
tPD
N
N – 12
N – 13
DATA OUT
N+1
13 CLOCK CYCLES
DCO+
06011-002
DCO–
tCPD
Figure 2. LVDS Mode Timing Diagram
N–1
N
N+1
VIN
N+2
tCLKL
tCLKH
CLK–
CLK+
tPD
DX
13 CLOCK CYCLES
N – 13
N – 12
N–1
N
06011-003
DCO+
DCO–
Figure 3. CMOS Timing Diagram
Rev. 0 | Page 6 of 28
AD9461
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
ELECTRICAL
AVDD1 to AGND
AVDD2 to AGND
DRVDD to DGND
AGND to DGND
AVDD1 to DRVDD
AVDD2 to DRVDD
AVDD2 to AVDD
D0± through D15± to DGND
CLK+/CLK− to AGND
OUTPUT MODE, DCS MODE, and
DFS to AGND
VIN+, VIN− to AGND
VREF to AGND
SENSE to AGND
REFT, REFB to AGND
ENVIRONMENTAL
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
THERMAL RESISTANCE
Rating
−0.3 V to +4 V
−0.3 V to +6 V
−0.3 V to +4 V
−0.3 V to +0.3 V
−4 V to +4 V
−4 V to +6 V
−4 V to +6 V
−0.3 V to DRVDD + 0.3 V
–0.3 V to AVDD1 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
The heat sink of the AD9461 package must be soldered to
ground.
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces through holes, ground, and power planes reduces
the θJA. It is required that the exposed heat sink be soldered to
the ground plane.
Table 6.
Package Type
100-Lead TQFP_EP
1
−0.3 V to AVDD2 + 0.3 V
−0.3 V to AVDD1 + 0.3 V
−0.3 V to AVDD1 + 0.3 V
−0.3 V to AVDD1 + 0.3 V
2
3
θJA 1
19.8
θJB 2
8.3
θJC 3
2
Unit
°C/W
Typical θJA = 19.8°C/W (heat sink soldered) for multilayer board in still air.
Typical θJB = 8.3°C/W (heat sink soldered) for multilayer board in still air.
Typical θJC = 2°C/W (junction to exposed heat sink) represents the thermal
resistance through heat sink path.
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 7 of 28
AD9461
DRVDD
D11–
D11+
D12–
D12+
D13–
D13+
D14–
D14+
D15–
D15+ (MSB)
DRGND
DRVDD
OR–
OR+
AGND
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND
SFDR
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DCS MODE
1
DNC
2
PIN 1
OUTPUT MODE 3
75
DRGND
74
D10+
73
D10–
DFS
4
72
D9+
LVDS_BIAS
5
71
D9–
AVDD1
6
70
D8+
SENSE
7
69
D8–
VREF
8
68
DCO+
AGND
9
67
DCO–
66
D7+
65
D7–
AVDD2 12
64
DRVDD
AVDD2 13
63
DRGND
AVDD2 14
62
D6+
AVDD2 15
61
D6–
AVDD2 16
60
D5+
AVDD2 17
59
D5–
AVDD1 18
58
D4+
AVDD1 19
57
D4–
AVDD1 20
56
D3+
AGND 21
55
D3–
VIN+ 22
54
D2+
VIN– 23
53
D2–
AGND 24
52
D1+
AVDD2 25
51
D1–
AD9461
LVDS MODE
REFT 10
TOP VIEW
(Not to Scale)
REFB 11
06011-004
D0+
D0– (LSB)
DRVDD
DRGND
AGND
AVDD1
AVDD1
AVDD1
AGND
CLK–
CLK+
AGND
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
AVDD2
DNC = DO NOT CONNECT
Figure 4. 100-Lead TQFP_EP Pin Configuration in LVDS Mode
Table 7. Pin Function Descriptions—100-Lead TQFP_EP in LVDS Mode
Pin No.
1
Mnemonic
DCS MODE
2
3
DNC
OUTPUT MODE
4
DFS
5
6, 18 to 20, 32 to 34, 36,
38, 43 to 45, 92 to 97
7
LVDS_BIAS
AVDD1
8
VREF
9, 21, 24, 39, 42, 46, 91, 98,
99, Exposed Heat Sink
AGND
SENSE
Description
Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible.
DCS = low (AGND) to enable DCS (recommended).
DCS = high (AVDD1) to disable DCS.
Do Not Connect. This pin should float.
CMOS-Compatible Output Logic Mode Control Pin.
OUTPUT MODE = 0 for CMOS mode.
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
Data Format Select Pin. CMOS control pin that determines the format of the output data.
DFS = high (AVDD1) for twos complement.
DFS = low (ground) for offset binary format.
Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.
3.3 V (±5%) Analog Supply.
Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog
input range); connect to AVDD1 for external reference.
1.7 V Reference I/O. The function is dependent on the SENSE pin and external programming
resistors. Decouple to ground with 0.1 μF and 10 μF capacitors.
Analog Ground. The exposed heat sink on the bottom of the package must be connected to
AGND.
Rev. 0 | Page 8 of 28
AD9461
Pin No.
10
Mnemonic
REFT
11
REFB
12 to 17, 25 to 31, 35, 37
22
23
40
41
47, 63, 75, 87
48, 64, 76, 88
49
50
51
52
53
54
55
56
57
58
59
60
61
62
65
66
67
68
69
70
71
72
73
74
77
78
79
80
81
82
83
84
85
86
89
90
100
AVDD2
VIN+
VIN−
CLK+
CLK−
DRGND
DRVDD
D0− (LSB)
D0+
D1−
D1+
D2−
D2+
D3−
D3+
D4−
D4+
D5−
D5+
D6−
D6+
D7−
D7+
DCO−
DCO+
D8−
D8+
D9−
D9+
D10−
D10+
D11−
D11+
D12−
D12+
D13−
D13+
D14−
D14+
D15−
D15+ (MSB)
OR−
OR+
SFDR
Description
Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB
(Pin 11) with 0.1 μF and 10 μF capacitors.
Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT
(Pin 10) with 0.1 μF and 10 μF capacitors.
5.0 V Analog Supply (±5%).
Analog Input—True.
Analog Input—Complement.
Clock Input—True.
Clock Input—Complement.
Digital Output Ground.
3.3 V Digital Output Supply (3.0 V to 3.6 V).
D0 Complement Output Bit (LVDS Levels).
D0 True Output Bit.
D1 Complement Output Bit.
D1 True Output Bit.
D2 Complement Output Bit.
D2 True Output Bit.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
D5 Complement Output Bit.
D5 True Output Bit.
D6 Complement Output Bit.
D6 True Output Bit.
D7 Complement Output Bit.
D7 True Output Bit.
Data Clock Output—Complement.
Data Clock Output—True.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
D10 Complement Output Bit.
D10 True Output Bit.
D11 Complement Output Bit.
D11 True Output Bit.
D12 Complement Output Bit.
D12 True Output Bit.
D13 Complement Output Bit.
D13 True Output Bit.
D14 Complement Output Bit.
D14 True Output Bit.
D15 Complement Output Bit.
D15 True Output Bit.
Out-of-Range Complement Output Bit.
Out-of-Range True Output Bit.
SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the
AD9461 analog front end. Connecting SFDR to AGND optimizes SFDR performance for
applications with analog input frequencies <40 MHz or >215 MHz. For applications with
analog inputs from 40 MHz to 215 MHz, connect this pin to AVDD1 for optimum SFDR
performance; power dissipation from AVDD2 decreases by ~40 mW.
Rev. 0 | Page 9 of 28
DRVDD
D5+
D6+
D7+
D8+
D9+
D10+
D11+
D12+
D13+
D14+
DRGND
DRVDD
D15+ (MSB)
OR+
AGND
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND
SFDR
AD9461
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DCS MODE
1
DNC
2
PIN 1
OUTPUT MODE 3
75
DRGND
74
D4+
73
D3+
DFS
4
72
D2+
LVDS_BIAS
5
71
D1+
AVDD1
6
70
D0+ (LSB)
SENSE
7
69
DNC
VREF
8
68
DCO+
AGND
9
67
DCO–
66
DNC
65
DNC
AVDD2 12
64
DRVDD
AVDD2 13
63
DRGND
AVDD2 14
62
DNC
AVDD2 15
61
DNC
AVDD2 16
60
DNC
AVDD2 17
59
DNC
AVDD1 18
58
DNC
AVDD1 19
57
DNC
AVDD1 20
56
DNC
AGND 21
55
DNC
VIN+ 22
54
DNC
VIN– 23
53
DNC
AGND 24
52
DNC
AVDD2 25
51
DNC
AD9461
CMOS MODE
REFT 10
TOP VIEW
(Not to Scale)
REFB 11
06011-005
DNC
DNC
DRVDD
DRGND
AGND
AVDD1
AVDD1
AVDD1
AGND
CLK–
CLK+
AGND
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
AVDD2
DNC = DO NOT CONNECT
Figure 5. 100-Lead TQFP_EP, Pin Configuration in CMOS Mode
Table 8. Pin Function Descriptions—100-Lead TQFP_EP in CMOS Mode
Pin No.
1
Mnemonic
DCS MODE
2, 49 to 62, 65 to 66, 69
3
DNC
OUTPUT MODE
4
DFS
5
6, 18 to 20, 32 to 34, 36,
38, 43 to 45, 92 to 97
7
LVDS_BIAS
AVDD1
8
VREF
9, 21, 24, 39, 42, 46, 91, 98,
99, Exposed Heat Sink
10
AGND
SENSE
REFT
Description
Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible.
DCS = low (AGND) to enable DCS (recommended).
DCS = high (AVDD1) to disable DCS.
Do Not Connect. These pins should float.
CMOS-Compatible Output Logic Mode Control Pin.
OUTPUT MODE = 0 for CMOS mode.
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
Data Format Select Pin. CMOS control pin that determines the format of the output data.
DFS = high (AVDD1) for twos complement.
DFS = low (ground) for offset binary format.
Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.
3.3 V (±5%) Analog Supply.
Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog
input range); connect to AVDD1 for external reference.
1.7 V Reference I/O. The function is dependent on the SENSE pin and external programming
resistors. Decouple to ground with 0.1 μF and 10 μF capacitors.
Analog Ground. The exposed heat sink on the bottom of the package must be connected to
AGND.
Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB
(Pin 11) with 0.1 μF and 10 μF capacitors.
Rev. 0 | Page 10 of 28
AD9461
Pin No.
11
Mnemonic
REFB
12 to 17, 25 to 31, 35, 37
22
23
40
41
47, 63, 75, 87
48, 64, 76, 88
67
68
70
71
72
73
74
77
78
79
80
81
82
83
84
85
86
89
90
100
AVDD2
VIN+
VIN−
CLK+
CLK−
DRGND
DRVDD
DCO−
DCO+
D0+ (LSB)
D1+
D2+
D3+
D4+
D5+
D6+
D7+
D8+
D9+
D10+
D11+
D12+
D13+
D14+
D15+ (MSB)
OR+
SFDR
Description
Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT
(Pin 10) with 0.1 μF and 10 μF capacitors.
5.0 V Analog Supply (±5%).
Analog Input—True.
Analog Input—Complement.
Clock Input—True.
Clock Input—Complement.
Digital Output Ground.
3.3 V Digital Output Supply (3.0 V to 3.6 V).
Data Clock Output—Complement.
Data Clock Output—True.
D0 True Output Bit (CMOS Levels).
D1 True Output Bit.
D2 True Output Bit.
D3 True Output Bit.
D4 True Output Bit.
D5 True Output Bit.
D6 True Output Bit.
D7 True Output Bit.
D8 True Output Bit.
D9 True Output Bit.
D10 True Output Bit.
D11 True Output Bit.
D12 True Output Bit.
D13 True Output Bit.
D14 True Output Bit.
D15 True Output Bit.
Out-of-Range True Output Bit.
SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the
AD9461 analog front end. Connecting SFDR to AGND optimizes SFDR performance for
applications with analog input frequencies <40 MHz or >215 MHz. For applications with
analog inputs from 40 MHz to 215 MHz, connect this pin to AVDD1 for optimum SFDR
performance; power dissipation from AVDD2 decreases by ~40 mW.
Rev. 0 | Page 11 of 28
AD9461
EQUIVALENT CIRCUITS
AVDD2
VIN+
6pF
1kΩ
DRVDD
T/H
X1
3.5V
AVDD2
1kΩ
DX
6pF
06011-009
06011-006
VIN–
Figure 6. Equivalent Analog Input Circuit
Figure 9. Equivalent CMOS Digital Output Circuit
VDD
DRVDD
DRVDD
K
3.74kΩ
ILVDSOUT
30kΩ
06011-010
LVDSBIAS
DCS MODE,
OUTPUT MODE,
DFS
06011-007
1.2V
Figure 7. Equivalent LVDS_BIAS Circuit
Figure 10. Equivalent Digital Input Circuit,
DFS, DCS MODE, OUTPUT MODE
AVDD1
DRVDD
3kΩ
V
DX–
DX+
V
V
CLK+
CLK–
2.5kΩ
2.5kΩ
06011-011
06011-008
V
3kΩ
Figure 8. Equivalent LVDS Digital Output Circuit
Figure 11. Equivalent Sample Clock Input Circuit
Rev. 0 | Page 12 of 28
AD9461
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, rated sample rate, LVDS mode, DCS enabled, TA = 25°C, 3.4 V p-p differential
input, AIN = −1 dBFS, internal trimmed reference (nominal VREF = 1.7 V), unless otherwise noted.
0
5
130MSPS
10.3MHz @ –1.0dBFS
SNR = 77.7dB
ENOB = 12.6 BITS
SFDR = 90dBc
–10
–20
3
–40
2
–50
1
INL (LSB)
–60
–70
–80
–90
–1
–2
–100
06011-012
–120
0
16.25
32.50
48.75
06011-017
–3
–110
–130
0
–4
–5
65.00
0
8192
16384
24576
FREQUENCY (MHz)
Figure 12. 130 MSPS, 64k Point Single-Tone FFT, 10.3 MHz
57344
65536
SFDR = +85°C
90
–40
–50
85
–60
SFDR = +25°C
(dB)
AMPLITUDE (dBFS)
–30
49152
95
130MSPS
170.3MHz @ –1.0dBFS
SNR = 75.4dB
ENOB = 12.3 BITS
SFDR = 86dBc
–20
40960
Figure 15. 130 MSPS, INL Error vs. Output Code, 10.3 MHz
0
–10
32768
OUTPUT CODE
–70
SFDR = –40°C
80
–80
SNR = –40°C
–90
–100
75
–120
–130
SNR = +25°C
06011-015
–110
0
16.25
32.50
48.75
70
65.00
0
FREQUENCY (MHz)
50
SNR = +85°C
100
06011-018
AMPLITUDE (dBFS)
–30
4
150
200
ANALOG INPUT FREQUENCY (MHz)
Figure 13. 130 MSPS, 64k Point Single-Tone FFT,170.3 MHz
Figure 16. 130 MSPS, SNR/SFDR vs. Analog Input Frequency, 3.4 V p-p
0.6
95
SFDR = +85°C
0.4
90
85
SFDR = +25°C
(dB)
0
SFDR = –40°C
80
–0.2
SNR = –40°C
–0.6
0
8192
16384
24576
32768
40960
49152
57344
SNR = +85°C
70
65536
OUTPUT CODE
0
50
100
SNR = +25°C
150
200
ANALOG INPUT FREQUENCY (MHz)
Figure 14. 130 MSPS, DNL Error vs. Output Code, 10.3 MHz
Figure 17. 130 MSPS, SNR/SFDR vs. Analog Input Frequency,
3.4 V p-p, CMOS Output Mode
Rev. 0 | Page 13 of 28
06011-019
75
–0.4
06011-016
DNL (LSB)
0.2
AD9461
120
0
SFDR dBFS
–10
–20
100
SFDR dBc
–30
(dB)
SFDR AND IMD3 (dB)
SFDR dBc
80
60
SNR dBFS
40
–40
–50
WORST IMD3 dBc
–60
–70
–80
SFDR dBFS
–90
–100
20
–80
–70
–60
–50
–40
–30
–20
–10
06011-025
0
–90
–110
06011-020
SNR dB
–120
–130
–100
0
ANALOG INPUT AMPLITUDE (dB)
WORST IMD3 dBFS
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
ANALOG INPUT AMPLITUDE (dB)
Figure 18. 130 MSPS,170.3 MHz SNR/SFDR vs. Analog Input Amplitude
Figure 21. 130 MSPS, Two-Tone SFDR vs. Analog Input Amplitude,
169.6 MHz, 170.6 MHz
6000
95
5000
SFDR = +25°C
90
FREQUENCY
4000
(dB)
85
SFDR = –40°C
SFDR = +85°C
80
SNR = –40°C
3000
2000
75
SNR = +25°C
0
50
100
150
0
N–11
N–10
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N+0
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N+10
N+11
70
06011-028
06011-021
1000
SNR = +85°C
200
ANALOG INPUT FREQUENCY (MHz)
BIN
Figure 19. 125 MSPS, SNR/SFDR vs. Analog Input Frequency, 3.4 V p-p
Figure 22. 130 MSPS, Grounded Input Histogram
0
120
105MSPS
170.6MHz @ –7.0dBFS
169.6MHz @ –7.0dBFS
SFDR = 89dBFS
–20
SFDR dBFS
100
60
SFDR dBc
40
20
–60
–80
–100
06011-023
–120
SNR dB
0
–90
–40
–80
–70
–60
–50
–40
–30
–20
–10
06011-029
(dB)
AMPLITUDE (dBFS)
SNR dBFS
80
–140
0
0
15.625
31.250
46.875
62.500
FREQUENCY (MHz)
ANALOG INPUT AMPLITUDE (dB)
Figure 20. 130 MSPS, 170.3 MHz SNR/SFDR vs. Analog Input Amplitude,
CMOS Output Mode
Figure 23. 130 MSPS, 64k Point Two-Tone FFT, 169.6 MHz, 170.6 MHz
Rev. 0 | Page 14 of 28
AD9461
0.6
90
SFDR dBc
0.5
85
0.3
80
SNR dB
(dB)
GAIN ERROR (%FS)
0.4
0.2
75
0.1
0
06011-030
–0.2
–40
–20
0
20
40
60
65
2.9
80
TEMPERATURE (°C)
06011-046
70
–0.1
3.1
3.3
3.5
3.7
3.9
4.1
ANALOG INPUT COMMON-MODE VOLTAGE (V)
Figure 24. 130 MSPS, Gain vs. Temperature
Figure 27. 130 MSPS, SNR/SFDR vs. Analog Input Common Mode
97
90
170.3MHz SFDR dBc
SFDR dBc
85
87
80
SNR dB
(dB)
(dBc)
92
82
75
170.3MHz SNR dBFS
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
65
45
4.2
ANALOG INPUT RANGE (V p-p)
1.732
1.730
1.726
1.724
1.722
1.720
06011-032
VREF (V)
1.728
1.718
0
20
40
85
105
125
145
Figure 28. Single-Tone SNR/SFDR vs. Sample Rate 170.3 MHz
1.734
–20
65
SAMPLE RATE (MSPS)
Figure 25. 130 MSPS, SNR, SFDR vs. Analog Input Range
1.716
–40
06011-035
72
1.8
70
06011-047
77
60
80
TEMPERATURE (°C)
Figure 26. 130 MSPS, VREF vs. Temperature
Rev. 0 | Page 15 of 28
AD9461
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Aperture Delay (tA)
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Effective Number of Bits (ENOB)
The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured
SINAD using the following formula:
Aperture Uncertainty (Jitter, tJ)
The sample-to-sample variation in aperture delay.
ENOB =
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the
clock pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 16-bit resolution indicates that all 65,536
codes must be present over all operating ranges.
Integral Nonlinearity (INL)
INL is the deviation of each individual code from a line drawn
from negative full scale through positive full scale. The point
used as negative full scale occurs ½ LSB before the first code
transition. Positive full scale is defined as a level 1½ LSB beyond
the last code transition. The deviation is measured from the
middle of each particular code to the true straight line.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the rms input signal amplitude to the rms
value of the sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms input signal amplitude to the rms
value of the sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the rms signal amplitude to the rms value
of the peak spurious spectral component. The peak spurious
component may be a harmonic. SFDR can be reported in dBc (that
is, degrades as signal level is lowered) or dBFS (always related back
to converter full scale).
Total Harmonic Distortion (THD)
The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.
(SINAD − 1.76 )
6.02
Gain Error
The first code transition should occur at an analog value of
½ LSB above negative full scale. The last transition should occur
at an analog value of 1½ LSB below the positive full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Offset Error
The major carry transition should occur for an analog value of
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Output Propagation Delay (tPD)
The delay between the clock rising edge and the time when all
bits are within valid logic levels.
Power-Supply Rejection Ratio
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at the maximum
limit.
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at TMIN or TMAX.
Rev. 0 | Page 16 of 28
AD9461
THEORY OF OPERATION
The AD9461 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated, high bandwidth
track-and-hold circuit that samples the signal prior to quantization
by the 16-bit pipeline ADC core. The device includes an on-board
reference and input logic that accepts TTL, CMOS, or LVPECL
levels. The digital output logic levels are user selectable as standard
3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT
MODE pin.
ranges <2 V p-p. However, reducing the range can improve SFDR
performance in some applications. Likewise, increasing the
range up to 3.4 V p-p can improve SNR. Users are cautioned
that the differential nonlinearity of the ADC varies with the
reference voltage. Configurations that use <2.0 V p-p can
exhibit missing codes and, therefore, degraded noise and
distortion performance.
VIN+
ANALOG INPUT AND REFERENCE OVERVIEW
VIN–
A stable and accurate 0.5 V band gap voltage reference is built
into the AD9461. The input range can be adjusted by varying
the reference voltage applied to the AD9461, using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly.
REFT
ADC
CORE
0.1µF
0.1µF
+
10µF
REFB
0.1µF
VREF
10µF
+
0.1µF
SELECT
LOGIC
Internal Reference Connection
SENSE
A comparator within the AD9461 detects the potential at the
SENSE pin and configures the reference into three possible states,
summarized in Table 9. If SENSE is grounded, the reference
amplifier switch is connected to the internal resistor divider (see
Figure 29), setting VREF to ~1.7 V. If a resistor divider is
connected as shown in Figure 30, the switch again sets to the
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as
06011-036
0.5V
AD9461
Figure 29. Internal Reference Configuration
R2 ⎞
VREF = 0.5 V × ⎛⎜1 +
⎟
⎝ R1 ⎠
VIN+
VIN–
ADC
CORE
0.1µF
0.1µF
+
10µF
REFB
0.1µF
VREF
+
10µF
Internal Reference Trim
0.1µF
R2
The internal reference voltage is trimmed during the production
test; therefore, there is little advantage to the user supplying an
external voltage reference to the AD9461. The gain trim is
performed with the AD9461 input range set to 3.4 V p-p
nominal (SENSE connected to AGND). Because of this trim,
and the maximum ac performance provided by the 3.4 V p-p
analog input range, there is little benefit to using analog input
Rev. 0 | Page 17 of 28
SELECT
LOGIC
SENSE
R1
0.5V
AD9461
Figure 30. Programmable Reference Configuration
06011-037
In all reference configurations, REFT and REFB drive the
analog-to-digital conversion core and establish its input span.
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
REFT
AD9461
Table 9. Reference Configuration Summary
Selected Mode
External Reference
Programmable Reference
SENSE Voltage
AVDD
0.2 V to VREF
Resulting VREF (V)
N/A
Programmable Reference
(Set for 2 V p-p)
0.2 V to VREF
R2 ⎞ , R1 = R2 = 1 kΩ
0.5 × ⎛⎜ 1 +
⎟
R1 ⎠
⎝
2.0
Internal Fixed Reference
AGND to 0.2 V
1.7
3.4
R2 ⎞ , (See Figure 30)
0.5 × ⎛⎜ 1 +
⎟
R1 ⎠
⎝
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer continues to generate the positive
and negative full-scale references, REFT and REFB, for the
ADC core. The input span is always twice the value of the
reference voltage; therefore, the external reference must be
limited to a maximum of 2.0 V. See Figure 24 for gain variation vs.
temperature.
Analog Inputs
As with most new high speed, high dynamic range ADCs, the
analog input to the AD9461 is differential. Differential inputs
improve on-chip performance because signals are processed
through attenuation and gain stages. Most of the improvement
is a result of differential analog stages having high rejection of
even-order harmonics. There are also benefits at the PCB level.
First, differential inputs have high common-mode rejection of
stray signals, such as ground and power noise. Second, they
provide good rejection of common-mode signals, such as local
oscillator feedthrough. The specified noise and distortion of the
AD9461 cannot be realized with a single-ended analog input;
therefore, such configurations are discouraged. Contact sales for
recommendations of other 16-bit ADCs that support singleended analog input configurations.
With the 1.7 V reference, which is the nominal value (see the
Internal Reference Trim section), the differential input range of
the AD9461 analog input is nominally 3.4 V p-p or 1.7 V p-p on
each input (VIN+ or VIN−).
VIN+
1.7V p-p
3.5V
VIN–
DIGITAL OUT = ALL 0s
06011-038
DIGITAL OUT = ALL 1s
Figure 31. Differential Analog Input Range for VREF = 1.7 V
The AD9461 analog input voltage range is offset from ground
by 3.5 V. Each analog input connects through a 1 kΩ resistor to
the 3.5 V bias voltage and to the input of a differential buffer. The
internal bias network on the input properly biases the buffer for
maximum linearity and range (see the Equivalent Circuits section).
Therefore, the analog source driving the AD9461 should be accoupled to the input pins. The recommended method for driving
the analog input of the AD9461 is to use an RF transformer to
convert single-ended signals to differential (see Figure 32). Series
resistors between the output of the transformer and the AD9461
analog inputs help isolate the analog input source from switching
transients caused by the internal sample-and-hold circuit. The
series resistors, along with the 1 kΩ resisters connected to the
internal 3.5 V bias, must be considered in impedance matching
the transformer input. For example, if RT is set to 51 Ω, RS is set
to 33 Ω and there is a 1:1 impedance ratio transformer, the input
matches a 50 Ω source with a full-scale drive of 16.0 dBm. The
50 Ω impedance matching can also be incorporated on the
secondary side of the transformer, as shown in the evaluation
board schematic (see Figure 35).
ANALOG
INPUT
SIGNAL R
T
RS
ADT1–1WT
RS
VIN+
AD9461
VIN–
0.1µF
06011-039
External Reference Operation
Resulting Differential Span (V p-p)
2 × external reference
2 × VREF
Figure 32. Transformer-Coupled Analog Input Circuit
CLOCK INPUT CONSIDERATIONS
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock combines with the desired signal at the analog-todigital output. For that reason, considerable care was taken in
the design of the clock inputs of the AD9461, and the user is
advised to give careful thought to the clock source.
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, can be sensitive
to the clock duty cycle. Commonly a 5% tolerance is required on
the clock duty cycle to maintain dynamic performance characteristics. The AD9461 contains a clock duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal ~50% duty cycle. Noise and distortion performance are nearly flat for a 30% to 70% duty cycle with the DCS
Rev. 0 | Page 18 of 28
AD9461
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the duty cycle stabilizer,
and logic high (AVDD1 = 3.3 V) disables the controller.
The AD9461 input sample clock signal must be a high quality,
extremely low phase noise source to prevent degradation of performance. Maintaining 16-bit accuracy places a premium on the
encode clock phase noise. SNR performance can easily degrade
by 3 dB to 4 dB with 70 MHz analog input signals when using a
high jitter clock source. (See the AN-501 Application Note,
Aperture Uncertainty and ADC System Performance for more
information.) For optimum performance, the AD9461 must be
clocked differentially. The sample clock inputs are internally
biased to ~1.5 V, and the input signal is usually ac-coupled into
the CLK+ and CLK− pins via a transformer or capacitors.
Figure 33 shows one preferred method for clocking the
AD9461. The clock source (low jitter) is converted from singleended to differential using an RF transformer. The back-to-back
Schottky diodes across the secondary of the transformer limit
clock excursions into the AD9461 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9461 and
limits the noise presented to the sample clock inputs.
If a low jitter clock is available, it helps to band-pass filter the
clock reference before driving the ADC clock inputs. Another
option is to ac couple a differential ECL/PECL signal to the encode
input pins, as shown in Figure 34.
ADT1–1WT
CLK+
0.1µF
AD9461
CLK–
HSMS2812
DIODES
06011-040
CRYSTAL
SINE
SOURCE
VT
0.1µF
ENCODE
ECL/
PECL
0.1µF
AD9461
ENCODE
VT
06011-041
formance are nearly flat for a 30% to 70% duty cycle with the DCS
enabled. The DCS circuit locks to the rising edge of CLK+ and
optimizes timing internally. This allows for a wide range of input
duty cycles at the input without degrading performance. Jitter in
the rising edge of the input is still of paramount concern and is
not reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates of less than 30 MHz
nominally. The loop is associated with a time constant that
should be considered in applications where the clock rate can
change dynamically, requiring a wait time of 1.5 μs to 5 μs after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the time that the
loop is not locked, the DCS loop is bypassed, and the internal
device timing is dependent on the duty cycle of the input clock
signal. In such an application, it can be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
Figure 34. Differential ECL for Encode
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (fINPUT) and rms amplitude due only to aperture jitter
(tJ) can be calculated using the following equation:
SNR = −20 log[2πfINPUT × tJ]
In the equation, the rms aperture jitter represents the root-meansquare of all jitter sources including the clock input, analog input
signal, and ADC aperture jitter specification. IF undersampling
applications are particularly sensitive to jitter
The clock input should be treated as an analog signal in cases
where aperture jitter can affect the dynamic range of the AD9461.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
synchronized by the original clock during the last step.
POWER CONSIDERATIONS
Care should be taken when selecting a power source. The use of
linear dc supplies is highly recommended. Switching supplies
tend to have radiated components that can be received by the
AD9461. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1 μF chip capacitors.
The AD9461 has separate digital and analog power supply pins.
The analog supplies are denoted AVDD1 (3.3 V) and AVDD2
(5 V), and the digital supply pins are denoted DRVDD. Although
the AVDD1 and DRVDD supplies can be tied together, best performance is achieved when the supplies are separate. This is
because the fast digital output swings can couple switching
current back into the analog supplies. Note that both AVDD1
and AVDD2 must be held within 5% of the specified voltage.
The DRVDD supply of the AD9461 is a dedicated supply for the
digital outputs in either LVDS or CMOS output mode. When in
LVDS mode, the DRVDD should be set to 3.3 V. In CMOS mode,
the DRVDD supply can be connected from 2.5 V to 3.6 V for
compatibility with the receiving logic.
Figure 33. Crystal Clock Oscillator, Differential Encode
Rev. 0 | Page 19 of 28
AD9461
DIGITAL OUTPUTS
TIMING
LVDS Mode
The AD9461 provides latched data outputs with a pipeline delay
of 13 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of CLK+. Refer to Figure 2 and
Figure 3 for detailed timing diagrams.
The off-chip drivers on the chip can be configured to provide
LVDS-compatible output levels via Pin 3 (OUTPUT MODE).
LVDS outputs are available when OUTPUT MODE is CMOS
logic high (or AVDD1 for convenience) and a 3.74 kΩ RSET
resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic
performance, including both SFDR and SNR, maximizes when
using the AD9461 in LVDS mode; designers are encouraged to
take advantage of this mode. The AD9461 outputs include
complementary LVDS outputs for each data bit (Dx+/Dx−), the
overrange output (OR+/OR−), and the output data clock output
(DCO+/DCO−). The RSET resistor current is multiplied on-chip,
setting the output current at each output equal to a nominal
3.5 mA (11 × IRSET). A 100 Ω differential termination resistor
placed at the LVDS receiver inputs results in a nominal 350 mV
swing at the receiver. LVDS mode facilitates interfacing with
LVDS receivers in custom ASICs and FPGAs that have LVDS
capability for superior switching performance in noisy
environments. Single point-to-point net topologies are
recommended, with a 100 Ω termination resistor located as
close to the receiver as possible. It is recommended to keep the
trace length less than two inches and to keep differential output
trace lengths as equal as possible.
CMOS Mode
In applications that can tolerate a slight degradation in dynamic
performance, the AD9461 output drivers can be configured to
interface with 2.5 V or 3.3 V logic families by matching
DRVDD to the digital supply of the interfaced logic. CMOS
outputs are available when OUTPUT MODE is CMOS logic
low (or AGND for convenience). In this mode, the output data
bits, Dx, are single-ended CMOS, as is the overrange output,
OR+. The output clock is provided as a differential CMOS
signal, DCO+/DCO−. Lower supply voltages are recommended
to avoid coupling switching transients back to the sensitive
analog sections of the ADC. The capacitive load to the CMOS
outputs should be minimized, and each output should be
connected to a single gate through a series resistor (220 Ω) to
minimize switching transients caused by the capacitive loading.
OPERATIONAL MODE SELECTION
Data Format Select
The data format select (DFS) pin of the AD9461 determines
the coding format of the output data. This pin is 3.3 V CMOS
compatible, with logic high (or AVDD1, 3.3 V) selecting twos
complement and DFS logic low (AGND) selecting offset binary
format. Table 10 summarizes the output coding.
Output Mode Select
The OUPUT MODE pin controls the logic compatibility,
as well as the pinout of the digital outputs. This pin is a CMOScompatible input. With OUTPUT MODE = 0 (AGND), the
AD9461 outputs are CMOS compatible, and the pin assignment
for the device is as defined in Table 8. With OUTPUT MODE = 1
(AVDD1, 3.3 V), the AD9461 outputs are LVDS compatible, and
the pin assignment for the device is as defined in Table 7.
Duty Cycle Stabilizer
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the DCS, and logic
high (AVDD1, 3.3 V) disables the controller.
SFDR Enhancement
Under certain conditions, the SFDR performance of the AD9461
improves by decreasing the power of the core of the ADC. The
SFDR control pin (Pin 100) is a CMOS-compatible control pin
to optimize the configuration of the AD9461 analog front end.
Connecting SFDR to AGND optimizes SFDR performance for
applications with analog input frequencies <40 MHz or >215 MHz.
For applications with analog inputs from 40 MHz to 215 MHz,
connect this to AVDD1 for optimum SFDR performance; power
dissipation from AVDD2 decreases by ~40 mW.
Table 10. Digital Output Coding
Code
65,536
32,768
32,767
0
VIN+ − VIN−
Input Span = 3.4 V p-p (V)
+1.700
0
−0.000058
−1.70
VIN+ − VIN−
Input Span = 2 V p-p (V)
+1.000
0
−0.0000305
−1.00
Digital Output
Offset Binary (D15•••D0)
1111 1111 1111 1111
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
Rev. 0 | Page 20 of 28
Digital Output
Twos Complement (D15•••D0)
0111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0000
AD9461
EVALUATION BOARD
Evaluation boards are offered to configure the AD9461 in either
CMOS mode or LVDS mode only. This design represents a
recommended configuration for using the device over a wide
range of sampling rates and analog input frequencies. These
evaluation boards provide all the support circuitry required to
operate the ADC in its various modes and configurations.
Complete schematics are shown in Figure 35 through Figure 38.
Gerber files are available from engineering applications
demonstrating the proper routing and grounding techniques
that should be applied at the system level.
The LVDS mode evaluation boards include an LVDS-to-CMOS
translator, making them compatible with the high speed ADC
FIFO evaluation kit (HSC-ADC-EVALA-SC). The kit includes a
high speed data capture board that provides a hardware solution
for capturing up to 32 kB samples of high speed ADC output
data in a FIFO memory chip (user upgradeable to 256 kB
samples). Software is provided to enable the user to download
the captured data to a PC via the USB port. This software also
includes a behavioral model of the AD9461 and many other
high speed ADCs.
It is critical that signal sources with very low phase noise
(<60 fsec rms jitter) are used to realize the ultimate
performance of the converter. Proper filtering of the input
signal to remove harmonics and lower the integrated noise at
the input is also necessary to achieve the specified noise
performance.
Behavioral modeling of the AD9461 is also available at
www.analog.com/ADIsimADC. The ADIsimADC™ software
supports virtual ADC evaluation using ADI proprietary behavioral
modeling technology. This allows rapid comparison between the
AD9461 and other high speed ADCs with or without hardware
evaluation boards.
The evaluation boards are shipped with a 115 V ac to 6 V dc
power supply. The evaluation boards include low dropout
regulators to generate the various dc supplies required by the
AD9461 and its support circuitry. Separate power supplies are
provided to isolate the DUT from the support circuitry. Each
input configuration can be selected by proper connection of
various jumpers (see Figure 35).
The user can choose to remove the translator and terminations
to access the LVDS outputs directly.
Rev. 0 | Page 21 of 28
TINB
06011-042
R1
DNP
GND
4
3
SEC
6
2
1
5
PRI
NC
TOUT
TOUTB
TOUTB
CT
E26
GND
E41
E24
GND
C12
0.1µF
TOUT
E15
SEC
CT
PRI
5
4
2
3
T5
ADT1-1WT
TINB
1
VCC
EXTREF
GND
T1
ETC1-1-13
R2
GND DNP
GND
C5
0.1µF
GND
ANALOG
L1
10nH
E2
E3
E9
E10
R3
3.74kΩ
E14
E1
E5
DNP = DO NOT POPULATE
J4
SMBMST
R5
DNP
GND
GND
VCC
GND
VCC
GND
E4
E6
E18
VCC
E25
E27
GND
4
3
2
5
1
GND
T2
GND
C98
DNP GND
C39
10µF
PRI
SEC
E19
ETC1-1-13
E36
GND
C8
0.1µF
R6
25Ω
R4
25Ω
C7
0.1µF
GND
C40
0.1µF
GND
C86
0.1µF
C51
10µF
VCC
R28
33Ω
R35
33Ω
R9
DNP
C9
0.1µF
C3
0.1µF
C91
0.1µF
VCC
C13
DNP
SCLK 1
2
3
4
5
6
VCC
7
8
9
GND
10
11
12
5V
C2
13
5V
0.1µF
14
5V
5V 15
16
5V
17
5V
18
VCC
19
VCC
20
VCC
21
GND
22
23
24
GND
25
5V
R11
1kΩ GND
GND
DCS MODE
DNC
OUTPUT MODE
DFS
LVDSBIAS
AVDD1
SENSE
VREF
AGND
REFT
REFB
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AGND
VIN+
VIN–
AGND
AVDD2
5V
GND
OPTIONAL
101
EPAD
H4
MTHOLE6
D11_T/D7_Y
D11_C/D6_Y
DRVDD
H3
MTHOLE6
DRGND
H2
MTHOLE6
AD9461
DRGND
D10_T
D10_C
D9_T
D9_C
D8_T
D8_C
DCO
DCOB
D7_T
D7_C
DRVDD
DRGND
D6_T
D6_C
D5_T
D5_C
D4_T
D4_C
D3_T
D3_C
D2_T
D2_C
D1_T
D1_C
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
5V
GND
VCC
GND
GND
H1
MTHOLE6
GND
VCC
VCC
VCC
VCC
VCC
VCC
GND
DOR_T/DOR_Y
DOR_C
DRVDD
DRGND
(MSB) D15_T/D15_Y
D15_C/D14_Y
D14_T/D13_Y
D14_C/D12_Y
D13_T/D11_Y
D13_C/D10_Y
D12_T/D9_Y
D12_C/D8_Y
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
SFDR
AGND
AGND
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
OR_T
OR_C
DRVDD
DRGND
D15_T
D15_C
D14_T
D14_C
D13_T
D13_C
D12_T
D12_C
D11_T
D11_C
DRVDD
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1
AGND
ENC
ENCB
AGND
AVDD1
AVDD1
AVDD1
AGND
DRGND
DRVDD
D0_C
D0_T
Rev. 0 | Page 22 of 28
VCC
VCC
VCC
5V
VCC
5V
VCC
GND
ENC
ENCB
Figure 35. Evaluation Board Schematic
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
+
GND
VCC
VCC
VCC
GND
DRGND
DRVDD
D0_C (LSB)
D0_T
D5_T
D5_C
D4_T
D4_C
D3_T
D3_C
D2_T
D2_C
D1_T
D1_C
D7_T
D7_C
DRVDD
DRGND
D6_T
D6_C
D8_T/D1_Y
D8_C/D0_Y
DR
DRB
D10_T/D5_Y
D10_C/D4_Y
D9_T/D3_Y
D9_C/D2_Y
DRGND
DRVDD
DRGND
EXTREF
XTALPWR
4
P4
3
P3
2
P2
1
P1
4
P4
3
P3
2
P2
1
P1
P22
P21
PTMICRO4 PTMICRO4
AD9461
GND
R8
50Ω
Rev. 0 | Page 23 of 28
Figure 36. Evaluation Board Schematic, Encode, Optional Encode, and Power Options
1
C33
10µF
GND
+
GND
06011-043
DNP = DO NOT POPULATE
1
3
3
2
VIN
GND
C89
10µF
OUT
5V
2
PJ-002A
+
L3
FERRITE
L4
FERRITE
L5
FERRITE
C42
0.1µF
IN
OUT1
GND
ADP3338-5
5V
VCC
DRVDD
4
4
6
2
PRI SEC
3
NC 5
1
T3
ADT1-1WT
3
2
1
1
C34
10µF
VIN
5VX
GND
5VX
VCCX
GND
+
2
DRVDDX
GND
CR2
DNP
3
3
VCCX
1
2
OUT
C87
10µF
GND
+
4
U7
VXTAL
3.3V
IN
OUT1
GND
ADP3338-3.3
ENC
ENCB
CR1
CR2 TO MAKE LAYOUT AND PARASITIC
LOADING SYMMETRICAL
ENCODE
U14
5VX
C26
0.1µF
C36
DNP
R39
0Ω
GND
P4
POWER OPTIONS
XTALINPUT
J1
SMBMST
J5
SMBMST
R7
DNP
GND
3
2
1
C6
10µF
GND
+
VIN
VCCX
GND
GND
GND
VEE
VCC
DRVDDX
L2
0Ω
7
14
+
U3
3.3V
IN
OUT1
GND
+
C4
10µF
VIN
DRVDDX
DRGND
DRGND
3
2
1
XTALINPUT
C41
0.1µF
DNP
ADP3338-3.3
1
8
C1
10µF
DNP
OUT
C88
10µF
DRGND
+
4
DRGND
~OUT
OUT
U2
ECLOSC
GND
XTALPWR
5V
C44
10µF
DNP
GND
+
E30
VXTAL
E20
E31
VXTAL
OPTIONAL ENCODE CIRCUITS
AD9461
AD9461
BYPASS CAPACITORS
VCC
+
C64
10µF
C43
0.1µF
C35
0.1µF
C32
0.1µF
C14
DNP
C17
DNP
C30
0.01µF
C28
0.1µF
C27
0.1µF
C90
0.1µF
C50
0.1µF
C60
0.1µF
C10
0.1µF
C61
DNP
C75
DNP
GND
VCC
C11
0.1µF
C16
DNP
C15
0.1µF
C31
DNP
C38
0.1µF
C29
DNP
C19
DNP
C69
DNP
C70
DNP
C45
DNP
C37
DNP
C48
0.1µF
C18
0.1µF
GND
DRVDD
DRVDD
+
C65
10µF
C47
0.1µF
C23
0.1µF
C21
0.1µF
C20
0.1µF
DRGND
C49
DNP
DRGND
5V
EXTREF
+
C56
10µF
C85
0.1µF
C53
0.1µF
C52
0.1µF
C58
0.01µF
GND
+
GND
C55
10µF
DNP
5V
C72
DNP
C73
DNP
C94
0.1µF
C95
0.1µF
C108
DNP
C109
DNP
C110
DNP
C59
0.1µF
C93
DNP
C96
0.1µF
GND
5V
C22
0.1µF
C97
0.1µF
C46
0.1µF
06011-044
GND
C84
0.1µF
DNP = DO NOT POPULATE
Figure 37. Evaluation Board Schematic, Bypass Capacitors
Rev. 0 | Page 24 of 28
Rev. 0 | Page 25 of 28
Figure 38. Evaluation Board Schematic
06011-045
DRGND
D0_T
D1_T
D2_T
D3_T
D4_T
D5_T
D6_T
D7_T
DR
D8_T/D1_Y
D9_T/D3_Y
D10_T/D5_Y
D11_T/D7_Y
D12_T/D9_Y
D13_T/D11_Y
D14_T/D13_Y
D15_T/D15_Y
DOR_T/DOR_Y
DRGND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
D0_C
DRGND
P3 3
P1 1
GND
GND
D5_C
P13 13
D1_C
D6_C
P15 15
P5 5
D7_C
P17 17
D2_C
DRB
P19 19
P7 7
D8_C/DO_Y
P21 21
D3_C
D9_C/D2_Y
P23 23
P9 9
D10_C/D4_Y
P25 25
D4_C
D11_C/D6_Y
P27 27
P11 11
D12_C/D8_Y
D14_C/D12_Y
P33 33
P29 29
D15_C/D14_Y
P35 35
D13_C/D10_Y
DOR_C
P37 37
P31 31
DRGND
P6
C40MS
P2
P4
P6
P8
P10
P12
P14
P16
P18
P20
P22
P24
P26
P28
P30
P32
P34
P36
P38
P40
P39 39
C76
0.1µF
D15_T/D14_Y
D15_C/D14_Y
D14_T/D13_Y
D14_C/D12_Y
D13_T/D11_Y
D13_C/D10_Y
D12_T/D9_Y
D12_C/D8_Y
D11_T/D7_Y
D11_C/D6_Y
D10_T/D5_Y
D10_C/D4_Y
D9_T/D3_Y
D9_C/D2_Y
D8_T/D1_Y
D8_C/D0_Y
D7_T
D7_C
D6_T
D6_C
D5_T
D5_C
D4_T
D4_C
D3_T
D3_C
D2_T
D2_C
D1_T
D1_C
D0_T
D0_C
DRO_T/DOR_Y
DOR_C
DR
DRB
C82
0.1µF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
EN_1_2
1Y
2Y
VCC
GND
3Y
4Y
EN_3_4
C77
0.1µF
A1A
A1B
A2A
A2B
A3A
A3B
A4A
A4B
B1A
B1B
B2A
B2B
B3A
B3B
B4A
B4B
C1A
C1B
C2A
C2B
C3A
C3B
C4A
C4B
D1A
D1B
D2A
D2B
D3A
D3B
D4A
D4B
C78
0.1µF
GND
VCC1
VCC2
GND1
ENA
A1Y
A2Y
A3Y
A4Y
ENB
B1Y
B2Y
B3Y
B4Y
GND2
VCC3
VCC4
GND3
C1Y
C2Y
C3Y
C4Y
ENC
D1Y
D2Y
D3Y
D4Y
END
GND4
VCC5
VCC6
GND5
U8
SN75LVDT386
1A
1B
2A
2B
3A
3B
4A
4B
U15
SN75LVDT390
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
16
15
14
13
12
11
10
9
R19
0Ω
DRVDD
DRGND
DRVDD
DRVDD
DRGND
DRVDD
DRGND
DRVDD
DRVDD
DRGND
DRVDD
DRGND
DRVDD
DRVDD
DRGND
DRVDD
DRVDD
DRVDD
DRGND R10
0Ω
DRVDD
ORO
DRO
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
RZ4
R8
R7
R6
R5
R4
R3
R2
R1
9
10
11
12
13
14
15
16
220
RSO16ISO
R8
R7
R6
R5
R4
R3
R2
R1
RZ5
220
RSO16ISO
D0O
D1O
D2O
D3O
D4O
D5O
D6O
D7O
D8O
D9O
D10O
D11O
D12O
D13O
D14O
D15O
DRGND
ORO
DRGND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
P1 1
P3 3
P5 5
P7 7
P9 9
P11 11
P13 13
P15 15
P17 17
P19 19
P21 21
P23 23
P25 25
P27 27
P29 29
P31 31
P33 33
P35 35
P37 37
P39 39
P7
C40MS
P2
P4
P6
P8
P10
P12
P14
P16
P18
P20
P22
P24
P26
P28
P30
P32
P34
P36
P38
P40
DRGND
D0O
D1O
D2O
D3O
D4O
D5O
D6O
D7O
D8O
D9O
D10O
D11O
D12O
D13O
D14O
D15O
GND
DRO
DRGND
AD9461
AD9461
Table 11. AD9461 Customer Evaluation Board Bill of Material
Item
1
Qty.
7
Reference Designator
C4, C6, C33, C34, C87, C88, C89
Description
Capacitor
Package
TAJD
Value 1
10 μF
2
44
Capacitor
402
0.1 μF
3
2
C2, C3, C5, C7, C8, C9, C10, C11, C12,
C15, C20, C21, C22, C23, C26, C27,
C28, C32, C35, C38, C40, C42, C43,
C46, C47, C48, C50, C52, C53, C59,
C60, C76, C77, C78, C82, C84, C85,
C86, C90, C91, C94, C95, C96, C97
C30, C58
Capacitor
201
0.01 μF
4
4
C39, C56, C64, C65
Capacitor
TAJD
10 μF
5
1
C51
Capacitor
805
10 μF
6
1
CR1
Diode
SOT23M5
7
1
CR21
Diode
SOT23M5
8
20
Header
EHOLE
9
2
E1, E2, E3, E4, E5, E6, E9, E10, E14, E18,
E19, E20, E24, E25, E26, E27, E30, E31,
E36, E41
J1, J4
SMA
SMA
10
1
L1
Inductor
0603A
11
3
L3, L4, L5
1206MIL
12
1
P4
EMIFIL®
BLM31PG500SN1L
Power jack
13
1
P7
Header
C40MS
14
1
R3
Resistor
402
3.74 kΩ
15
1
R8
Resistor
402
50 Ω
16
4
R10, R19, R39, L2
Resistor
402
0Ω
17
1
R11
BRES402
402
1 kΩ
18
2
R28, R35
Resistor
402
33 Ω
19
2
RZ4, RZ5
Resistor array
16-pin
22 Ω
20
21
1
1
T3
U1
Transformer
AD9461BSVZ-105/130
ADT1-1WT
SV-100-3
22
1
U14
ADP3338-5
SOT-223HS
23
2
U3, U7
ADP3338-3.3
SOT-223HS
24
1
U8
SN75LVDT386
TSSOP64
25
1
U15
SN75LVDT390
SOIC16PW
26
2
R4, R6
Resistor
402
Rev. 0 | Page 26 of 28
DNP
10 nH
Manufacturer
Digi-Key
Corporation
Digi-Key
Corporation
Mfg. Part No.
478-1699-2
Digi-Key
Corporation
Digi-Key
Corporation
Digi-Key
Corporation
Digi-Key
Corporation
Digi-Key
Corporation
Mouser
Electronics
445-1796-1-ND
Digi-Key
Corporation
Coilcraft, Inc.
ARFX1231-ND
Mouser
Electronics
Digi-Key
Corporation
Samtec, Inc.
PJ-002A
25 Ω
Digi-Key
Corporation
Digi-Key
Corporation
Digi-Key
Corporation
Digi-Key
Corporation
Digi-Key
Corporation
Digi-Key
Corporation
Mini-Circuits
Analog
Devices, Inc.
Analog
Devices, Inc.
Analog
Devices, Inc.
Arrow
Electronics,
Inc.
Arrow
Electronics,
Inc.
Digi-Key
Corporation
PCC2146CT-ND
478-1699-2
490-1717-1-ND
MA3X71600LCTND
MA3X71600LCTND
517-6111TG
0603CS10NXGBU
81-BLM31P500S
CP-002A-ND
TSW-120-08-LD-RA
P3.74KLCT-ND
P49.9LCT-ND
P0.0JCT-ND
P1.0KLCT-ND
P33JCT-ND
742C163220JCTND
ADT1-1WT
AD9461BSVZ
ADP3338-5
ADP3338-3.3
SN75LVDT386
SN75LVDT390
P36JCT-ND
AD9461
Manufacturer
Digi-Key
Corporation
Mfg. Part No.
478-1699-2
402
Value 1
10 μF,
DNP
DNP
Capacitor
805
DNP
490-1717-1-ND
E151
Header
EHOLE
DNP
31
J51
SMA
SMA
DNP
32
P61
Header
C40MS
DNP
Digi-Key
Corporation
Mouser
Electronics
Digi-Key
Corporation
Samtec, Inc.
R1, R21
R5, R7, R91
U21
H1, H2, H3, H41
T1, T21
T51
P21, P221
BRES402
BRES402
ECLOSC
MTHOLE6
Balun transformer
Transformer
Term strip
402
402
DIP4(14)
MTHOLE6
SM-22
ADT1-1WT
PTMICRO4
DNP
DNP
DNP
DNP
DNP
DNP
DNP
M/A-COM
Mini-Circuits
Newark
Electronics
ETC1-1-13
ADT1-WT
Item
27
Qty.
2
Reference Designator
C1, C44, C551
Description
Capacitor
Package
TAJD
28
23
CAP402
29
1
C13, C14, C16, C17, C18, C19, C29,
C31, C36, C37, C41, C45, C49, C61,
C69, C70, C72, C73, C75, C93, C108,
C109, C1101
C981
30
33
34
35
36
37
38
39
1
2
3
1
4
2
1
2
DNP = do not populate. All items listed in this category are not populated.
Rev. 0 | Page 27 of 28
517-6111TG
ARFX1231-ND
TSW-120-08-LD-RA
AD9461
OUTLINE DIMENSIONS
0.75
0.60
0.45
16.00 BSC SQ
1.20
MAX
14.00 BSC SQ
100
1
76
75
76
75
100
1
PIN 1
EXPOSED
PAD
TOP VIEW
(PINS DOWN)
0° MIN
1.05
1.00
0.95
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
25
26
51
50
BOTTOM VIEW
(PINS UP)
51
25
50
26
0.50 BSC
LEAD PITCH
VIEW A
9.50 SQ
0.27
0.22
0.17
VIEW A
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
NOTES
1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
040506-A
ROTATED 90° CCW
Figure 39. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9461BSVZ 1
AD9461-LVDS/PCB
1
Temperature Range
–40°C to +85°C
Package Description
100-Lead TQFP_EP
AD9461-100 LVDS Mode Evaluation Board
Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06011–0–4/06(0)
Rev. 0 | Page 28 of 28
Package Option
SV-100-3