TI1 LMP7300MAX/NOPB Micropower precision comparator and precision reference Datasheet

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LMP7300
SNOSAT7G – AUGUST 2007 – REVISED OCTOBER 2015
LMP7300 Micropower Precision Comparator and Precision Reference
With Adjustable Hysteresis
1 Features
3 Description
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The LMP7300 is a combination comparator and
reference with ideal specifications for precision
threshold detecting. The precision 2.048-V reference
comes with a 0.25% maximum error. The comparator
features micropower (35 µW), low offset voltage
(0.75-mV maximum), and independent adjustable
positive and negative hysteresis.
1
(For VS = 5 V, typical unless otherwise noted)
Supply Current 13 μA
Propagation Delay 4 μs
Input Offset Voltage 0.3 mV
CMRR 100 dB
PSRR 100 dB
Positive and Negative Hysteresis Control
Adjustable Hysteresis 1 mV/mV
Reference Voltage 2.048 V
Reference Voltage Accuracy 0.25%
Reference Voltage Source Current 1 mA
Wide Supply Voltage Range 2.7 V to 12 V
Operating Temperature Range Ambient −40°C to
125°C
Hysteresis control for the comparator is accomplished
through two external pins. The HYSTP pin sets the
positive hysteresis, and the HYSTN pin sets the
negative hysteresis. The comparator design isolates
the VIN source impedance and the programmable
hysteresis components. This isolation prevents any
undesirable interaction allowing the IC to maintain a
precise threshold voltage during level detection.
2 Applications
The combination of low offset voltage, external
hysteresis control, and precision voltage reference
provides an easy-to-use micropower precision
threshold detector.
•
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The LMP7300 open collector output is ideal for
mixed-voltage system designs. The output voltage
upper rail is unconstrained by VCC and can be pulled
above VCC to a maximum of 12 V. The LMP7300 is a
member of the LMP precision amplifier family.
Precision Threshold Detection
Battery Monitoring
Battery Management Systems
Zero Crossing Detectors
Device Information(1)
PART NUMBER
LMP7300
PACKAGE
BODY SIZE (NOM)
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
3.91 mm × 4.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
VBATT = (TRIP @ .9V x 3 CELL)
Propagation Delay vs Overdrive Voltage
30
R1
318.4 k:
1%
R2
1 M:
1%
+
INP
INN
HYSTP
HYSTN
V
LED
+
-
GND
OUT
VREF
R3
9.86 k:
1%
R4
1 M:
1%
R5 ADJUST
FOR LED
BRIGHTNESS
+
V = 12V
PROPAGATION DELAY (Ps)
0.1 PF
CL = 10 pF
25
20
15
10
-40°C
25°C
85°C
5
0
0
125°C
20
40
60
80
100
OVERDRIVE VOLTAGE (mV)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMP7300
SNOSAT7G – AUGUST 2007 – REVISED OCTOBER 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: 2.7-V ................................
Electrical Characteristics: 5-V ...................................
Electrical Characteristics: 12-V ................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Applications ................................................ 16
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
11.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (March 2013) to Revision G
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision E (March 2013) to Revision F
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 19
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5 Pin Configuration and Functions
DGK or D Package
8-Pin VSSOP or SOIC
Top View
+IN
-IN
GND
OUT
1
8
2
7
3
6
4
5
+
V
REF
HYSTP
HYSTN
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
+IN
1
I
Noninverting Comparator Input. The +IN has a common-mode voltage range from 1 V above
the negative rail to, and including, the positive rail. Internal ESD diodes, connected from the
+IN pin to the rails, protect the input stage from overvoltage. If the input voltage exceeds the
rails, the diodes turn on and clamp the input to a safe level.
-IN
2
I
Inverting Comparator Input. The −IN has a common-mode voltage range from 1 V above the
negative rail to, and including, the positive rail. Internal ESD diodes, connected from the −IN
pin to the rails, protects the input stage from overvoltage. If the input voltage exceeds the
rails, the diodes turn on and clamp the input to a safe level.
GND
3
G
Ground. This pin may be connected to a negative DC voltage source for applications
requiring a dual supply. If connected to a negative supply, decouple this pin with 0.1-µF
ceramic capacitor to ground. The internal reference output voltage is referenced to this pin.
GND is the die substrate connection.
OUT
4
O
Comparator Output. The output is an open-collector. It can drive voltage loads by using a
pullup resistor, or it can drive current loads by sinking a maximum output current. This pin
may be taken to a maximum of +12 V with respect to the ground pin, irrespective of supply
voltage.
HYSTN
5
I
Negative Hysteresis pin. This pin sets the lower trip voltage VIL. The common mode range is
from 1V above the negative rail to VCC. The input signal must fall below VIL for the
comparator to switch from high to low state.
HYSTP
6
I
Positive Hysteresis pin. This pin sets the upper trip voltage VIH. The common mode range is
from 1V above the negative rail to VCC. The input signal must rise above VIH for the
comparator to switch from low to high state.
REF
7
O
Reference Voltage Output pin. This is the output pin of a 2.048-V band gap precision
reference.
V+
8
P
Positive Supply Terminal. The supply voltage range is 2.7 V to 12 V. Decouple this pin with
0.1-μF ceramic capacitor to ground.
(1)
P= Power, G=Ground, I=Input, O=Output, A=Analog
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
±VS
V
13.6
V
VIN differential
+
−
Supply voltage (VS = V – V )
V− − 0.3
V
Infrared or convection (20 s)
235
°C
Wave soldering lead temperature (10 s)
260
°C
150
°C
150
°C
V+ + 0.3
Voltage at input/output pins
Soldering information
Junction temperature, TJ (3)
Storage temperature, Tstg
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±250
Machine model
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Temperature (2)
+
MAX
UNIT
–40
125
°C
2.7
12
V
−
Supply Voltage (VS = V – V )
(1)
(2)
NOM
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature
is PD = (TJ(MAX) – TA)/θJA. All numbers apply for packages soldered directly onto a PC Board.
6.4 Thermal Information
LMP7300
THERMAL METRIC (1)
DGK (VSSOP)
D (SOIC)
UNIT
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance (2)
175.5
121.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
66.1
67.5
°C/W
RθJB
Junction-to-board thermal resistance
95.6
61.5
°C/W
ψJT
Junction-to-top characterization parameter
10
18.3
°C/W
ψJB
Junction-to-board characterization parameter
94.2
61
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953..
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
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6.5 Electrical Characteristics: 2.7-V
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 2.7 V, V− = 0 V, and VCM = V+/2, RPULLUP = 100 kΩ,
CLOAD = 10 pF.
PARAMETER
IS
Supply Current
TEST CONDITIONS
MIN
TA = 25°C
RPULLUP = Open
TYP
MAX
9
12
TJ = TA
17
UNIT
μA
COMPARATOR
VCM = V+/2 SOIC
VOS
Input Offset Voltage
VCM = V+/2 VSSOP
TA = 25°C
±0.07
TJ = TA
±0.75
±2
TA = 25°C
±0.07
TJ = TA
±1
±2.2
mV
mV
TCVOS
Input Offset Average
Drift
See (1)
IB
Input Bias Current (2)
|VID| < 2.5 V
IOS
Input Offset Current
CMRR
Common Mode
Rejection Ratio
1 V < VCM < 2.7 V
80
100
dB
PSRR
Power Supply Rejection +
V = 2.7 V to 12 V
Ratio
80
100
dB
VOL
Output Low Voltage
ILOAD = 10 mA
ILEAK
Output Leakage
Current
Comparator Output in High State
HCLIN
Hysteresis Control
Voltage Linearity
0 < Ref-HYSTP,N < 25 mV
IHYS
Hysteresis Leakage
Current
TA = 25°C
TPD
Propagation Delay
(High to Low)
Overdrive = 10 mV, CL = 10 pF
12
17
Overdrive = 100 mV, CL = 10 pF
4.5
7.6
μV/°C
1.8
TA = 25°C
1.2
TJ = TA
3
4
0.15
TA = 25°C
0.25
TJ = TA
0.5
0.4
0.5
1
1.2
V
mV/V
0.950
TJ = TA
nA
pA
1
25 mV < Ref-HYSTP,N < 100 mV
nA
3
4
nA
μs
REFERENCE
VO
Reference Voltage
Line Regulation
SOIC
2.043
2.048
2.053
V
VSSOP
2.043
2.048
2.056
V
14
80
0.2
mV/m
0.5
A
VCC = 2.7 V to 12 V
Load Regulation
IOUT = 0 to 1 mA
Temperature
Coefficient
−40°C to 125°C
C
VN
Output Noise Voltage
TCVREF/°
(1)
(2)
55
μV/V
ppm/°
C
0.1 Hz to 10 Hz
80
μVPP
10 Hz to 10 kHz
100
μVRMS
Offset voltage average drift determined by dividing the change in VOS at temperature extremes, by the total temperature change.
Positive current corresponds to current flowing into the device.
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6.6 Electrical Characteristics: 5-V
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5 V, V− = 0 V, and VCM = V+/2, RPULLUP = 100 kΩ,
CLOAD = 10 pF. (1)
PARAMETER
IS
Supply Current
TEST CONDITIONS
RPULLUP = Open
MIN (2)
TA = 25°C
TYP (3)
MAX (2)
10
13
TJ = TA
18
UNIT
μA
COMPARATOR
VOS
VCM = V+/2
SOIC
VCM = V+/2
VSSOP
Input Offset Voltage
TA = 25°C
±0.07
TJ = TA
±0.75
±2
TA = 25°C
±0.07
TJ = TA
±1
±2.2
mV
mV
TCVOS
Input Offset Average Drift
See (4)
IB
Input Bias Current (5)
|VID| < 2.5 V
IOS
Input Offset Current
CMRR
Common Mode Rejection
Ratio
1 ≤ VCM ≤ 5 V
80
100
dB
PSRR
Power Supply Rejection
Ratio
V+ = 2.7 V to 12 V
80
100
dB
VOL
Output Voltage Low
ILOAD = 10 mA
ILEAK
Output Leakage Current
Comparator Output in High State
HCLIN
Hysteresis Control Voltage 0 < Ref-VHYSTP,N < 25 mV
Linearity
25 mV < Ref-VHYSTP,N < 100 mV
IHYS
Hysteresis Leakage
Current
TA = 25°C
TPD
Propagation Delay
(High to Low)
Overdrive = 10 mV, CL = 10 pF
12
15
Overdrive = 100 mV, CL = 10 pF
4
7
μV/°C
1.8
TA = 25°C
1.2
TJ = TA
3
4
0.15
0.25
0.5
0.4
1
V
mV/V
0.950
1.2
nA
pA
1
TJ = TA
nA
3
4
nA
μs
REFERENCE
VO
Reference Voltage
TCVREF/°
SOIC
2.043
2.048
2.053
VSSOP
2.043
V
2.048
2.056
Line Regulation
VCC = 2.7 V to 12 V
14
80
V
Load Regulation
IOUT = 0 to 1 mA
0.2
0.5 mV/mA
Temperature Coefficient
−40°C to 125°C
μV/V
55 ppm/°C
C
VN
(1)
(2)
(3)
(4)
(5)
6
Output Noise Voltage
0.1 Hz to 10 Hz
80
μVPP
10 Hz to 10 kHz
100
μVRMS
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Offset voltage average drift determined by dividing the change in VOS at temperature extremes, by the total temperature change.
Positive current corresponds to current flowing into the device.
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6.7 Electrical Characteristics: 12-V
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 12 V, V− = 0 V, and VCM = V+/2, RPULLUP = 100 kΩ,
CLOAD = 10 pF. (1)
PARAMETER
IS
Supply Current
TEST CONDITIONS
RPULLUP = Open
MIN
TA = 25°C
TYP
MAX
11
14
TJ = TA
20
UNIT
µA
COMPARATOR
VCM = V+/2 SOIC
VOS
Input Offset Voltage
VCM = V+/2 VSSOP
TA = 25°C
±0.08
TJ = TA
±0.75
±2
TA = 25°C
±0.08
TJ = TA
±1
±2.2
TCVOS
Input Offset Average Drift
See (2)
IB
Input Bias Current (3)
|VID| > 2.5 V
IOS
Input Offset Current
CMRR
Common Mode Rejection Ratio
1 V ≤ VCM ≤ 12 V
80
100
PSRR
Power Supply Rejection Ratio
V+ = 2.7 V to 12 V
80
100
VOL
Output Voltage Low
ILOAD = 10 mA
ILEAK
Output Leakage Current
Comparator Output in High State
HCLIN
Hysteresis Control Voltage
Linearity
0 < Ref-V+HYSTP, N < 25 mV
IHYS
Hysteresis Leakage Current
TPD
Propagation Delay
(High to Low)
1.2
TJ = TA
3
4
0.15
0.25
0.5
dB
TJ = TA
V
pA
1
1.2
nA
0.4
mV/V
0.95
TA = 25°C
nA
dB
1
25 mV < Ref-V+HYSTP, N < 100 mV
mV
μV/°C
1.8
TA = 25°C
mV
3
4
Overdrive = 10 mV, CL = 10 pF
11
15
Overdrive = 100 mV, CL = 10 pF
3.5
6.8
nA
μs
REFERENCE
VO
Reference Voltage
TCVREF/°
TJ = 25°C
SOIC
2.043
2.048
2.053
TJ = 25°C
VSSOP
2.043
2.048
2.056
(1)
(2)
(3)
V
Line Regulation
VCC = 2.7 V to 12 V
14
80
μV/V
Load Regulation
IOUT = 0 to 1 mA
0.2
0.5
mV/m
A
Temperature Coefficient
−40°C to 125°C
55
ppm/°
C
C
VN
V
Output Noise Voltage
0.1 Hz to 10 Hz
80
μVPP
10 Hz to 10 kHz
100
μVRMS
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
Offset voltage average drift determined by dividing the change in VOS at temperature extremes, by the total temperature change.
Positive current corresponds to current flowing into the device.
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6.8 Typical Characteristics
20
0.5
+
OUTPUT LOW VOLTAGE (V)
SUPPLY CURRENT (PA)
V = 12V
125°C
15
85°C
25°C
10
-40°C
5
0
2
4
6
8
10
0.4
125°C
0.3
85°C
0.2
-40°C
0.1
25°C
0
0
12
2
SUPPLY VOLTAGE (V)
Figure 1. Supply Current vs Supply Voltage
+
OUTPUT LOW VOLTAGE (V)
OUTPUT LOW VOLTAGE (V)
10
V = 2.7V
0.4
125°C
0.3
85°C
0.2
-40°C
0.1
25°C
0
2
4
6
8
0.4
125°C
0.3
85°C
0.2
-40°C
0.1
25°C
0
0
10
2
LOAD CURRENT (mA)
4
6
8
10
LOAD CURRENT (mA)
Figure 3. Output Low Voltage vs Load Current
Figure 4. Output Low Voltage vs Load Current
2.052
2.050
+
VREF UNLOADED
V = 12V
2.050
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
8
0.5
+
V = 5V
-40°C
25°C
2.048
85°C
125°C
2.046
2.044
2
4
6
8
10
12
-40°C
25°C
2.049
2.048
85°C
2.047
125°C
2.046
0
SUPPLY VOLTAGE (V)
0.5
1
1.5
2
SOURCE CURRENT (mA)
Figure 5. Reference Voltage vs Supply Voltage
8
6
Figure 2. Output Low Voltage vs Load Current
0.5
0
4
LOAD CURRENT (mA)
Figure 6. Reference Voltage vs Source Current
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Typical Characteristics (continued)
2.050
2.050
+
+
V = 2.7V
-40°C
25°C
2.049
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
V = 2.7V
2.048
85°C
2.047
125°C
2.049
-40°C
25°C
2.048
85°C
2.047
125°C
2.046
0
50
100
150
200
2.046
250
0
SINK CURRENT (PA)
0.5
1
1.5
SOURCE CURRENT (mA)
Figure 7. Reference Voltage vs Sink Current
Figure 8. Reference Voltage vs Source Current
30
30
+
V = 5V
+
25
20
15
-40°C
25°C
85°C
5
0
25
PROPAGATION DELAY (Ps)
PROPAGATION DELAY (Ps)
V = 2.7V
10
20
15
10
-40°C
20
40
60
80
25°C
85°C
5
125°C
0
2
0
100
125°C
20
40
0
60
80
100
OVERDRIVE VOLTAGE (mV)
OVERDRIVE VOLTAGE (mV)
Figure 9. Propagation Delay vs Overdrive Voltage
Figure 10. Propagation Delay vs Overdrive Voltage
30
+
PROPAGATION DELAY (Ps)
V = 12V
CL = 10 pF
25
20
15
10
-40°C
25°C
85°C
5
0
0
125°C
20
40
60
80
100
OVERDRIVE VOLTAGE (mV)
Figure 11. Propagation Delay vs Overdrive Voltage
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7 Detailed Description
7.1 Overview
The LMP7300 device is a unique combination of micropower and precision. The open collector comparator has
low offset, high CMRR, high PSRR, programmable hysteresis and microamp supply current. The precision 2.048V reference provides a DAC or ADC with an accurate binary divisible voltage. The comparator and reference
combination forms an ideal single IC solution for low power sensor or portable applications.
7.2 Functional Block Diagram
V+
INP
+
OUT
INN
HYSTP
GND
V+
2.048 V
VREF
HYSTN
GND
7.3 Feature Description
7.3.1 Voltage Reference
The reference output voltage is a band gap derived 2.048 V that is trimmed to achieve typically 0.2% accuracy
over the full operating temperature range of −40°C to 125°C. The trim procedure employs a curvature correction
algorithm to compensate for the base emitter thermal nonlinearity inherent in band gap design topologies. The
reference accuracy and the set resistor tolerance determine the magnitude and precision of the programmable
hysteresis. In situations where reference noise filtering is required, TI recommends a 5-µF capacitor in series
with a 190-Ω resistor to ground.
7.3.2 Comparator
7.3.2.1 Output Stage
The comparator employs an open collector output stage that can switch microamp loads for micropower
precision threshold detection to applications requiring activating a solenoid, a lamp, or an LED. The wired-OR
type output easily interfaces to TTL, CMOS, or multiple outputs, as in a window comparator application, over a
range of 0.5 V to 12 V. The output is capable of driving greater than 10-mA output current and yet maintaining a
saturation voltage less than 0.4 V over temperature. The supply current increases linearly when driving heavy
loads, so TI recommends a pullup resistor of 100 kΩ or greater for micropower applications.
7.3.2.2 Fault Detection Rate
The user’s choice of a pullup resistor and capacitive load determines the minimum response time and the event
detection rate. By optimizing overdrive, the pullup resistor and capactive load fault update rates of 200 kHz to
250 kHz or greater can be achieved.
10
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Feature Description (continued)
7.3.3 Hysteresis
False triggering on noise coupled into the signal path is a common problem for comparator based threshold
detectors. One of the most effective solutions is to add hysteresis. Hysteresis is a circuit signal path
characteristic where an amplitude delay is introduced to the normal input. Positive hysteresis forces the signal to
pass the normal switch point before the output makes a low to high transition while negative hysteresis does the
opposite. This is a memory effect. The comparator behaves differently based on which direction the signal is
going.
The LM7300 has been designed with a unique way of introducing hysteresis. The set points are completely
independent of each other, the power supply, and the input or output conditions. The HYSTP pin sets positive
hysteresis and the HYSTN pin sets the negative hysteresis in a simple way using two resistors. The pins can be
tied together for the same hysteresis or tied to separate voltage taps for asymmetric hysteresis, or tied to the
reference for no hysteresis. When the precision reference is used to drive the voltage tap resistor divider precise,
stable threshold levels can be obtained. The maximum recommended hysteresis is about 130 mV. This places
the HYSTP and HYSTN pin voltages at VREF – 130 mV, which is approximately the center of their input common
mode range at 2.7 V. For the typical example, a differential input signal voltage, VIN, is applied between INP and
INN, the noninverting and inverting inputs of the comparator. A DC switch or threshold voltage, VTH, is set on the
negative input to keep the output off when the signal is above and on when it goes below this level. For a
precision threshold tie the INN pin to VREF. With the output, off the circuit is in the minimum power state.
Figure 13 through Figure 21 demonstrate the different configurations for setting the upper threshold VIH and the
lower threshold VIL and their relationship to the input trip point VREF, by the following formulas.
æ R1 ö
VIL = VREF - VREF ç
÷
è R1 + R2 ø
æ R1 ö
VIH = VREF + VREF ç
÷
è R1 + R2 ø
(1)
+
V
INP
+
-
VIN
INN
RPULLUP
1 M:
+
OUT
-
HYSTP
HYSTN
VREF
RP1
1.47 k:
1%
RP2
1 M:
1%
GND
+
V
2.048V
RN1
4.91 k:
1%
RN2
1 M:
1%
GND
Figure 12. Typical Micropower Application to Set Asymmetric Positive and
Negative Hysteresis of −10 mV, 3 mV
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Feature Description (continued)
VOUT
1
OUTPUT
STATE
-10 mV
+3 mV
VIN
0
VIL
VIH
VREF
VIL = VREF -10 mV
VIH = VREF +3 mV
Figure 13. Typical Micropower Application to Set Asymmetric Positive and
Negative Hysteresis of −10 mV, 3 mV
When VID = 0, INN = INP = VTH
Figure 15 shows the configuration with no hysteresis when the HYSTP and HYSTN pins are connected together
to VREF. TI does not recommend this configuration because it has the highest level of false triggers due to the
system noise.
+
V
INP
+
-
VIN
INN
RPULLUP
1 M:
+
OUT
-
HYSTP
HYSTN
VREF
GND V+
2.048V
GND
Figure 14. Typical Configuration for No Hysteresis
VOUT
1
OUTPUT
STATE
0
VIN
VREF
Figure 15. Typical Configuration for No Hysteresis
Figure 17 shows the configuration with symmetric hysteresis when the HYSTP and HYSTN pins are connected
to the same voltage that is less than VREF. The two trip points set a hysteresis band around the input threshold
voltage VREF, such that the positive band is equal to the negative band.
This configuration controls the false triggering mentioned in Figure 15. For precise level detection applications, TI
recommends symmetric hysteresis values less than 5 mV to 10 mV.
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Feature Description (continued)
+
V
INP
+
-
VIN
RPULLUP
1 M:
+
OUT
INN
-
HYSTP
GND
HYSTN
VREF
V
+
2.048V
R1
2.45 k:
1%
R2
1 M:
1%
GND
Figure 16. Symmetric Hysteresis ±5 mV
VOUT
1
OUTPUT
STATE
10 mV
0
VIN
VIL
VREF
VIH
Figure 17. Symmetric Hysteresis ±5 mV
Figure 19 shows the case for negative hysteresis by biasing only the HYSN pin to a voltage less than VREF.
+
V
INP
+
-
VIN
INN
RPULLUP
1 M:
+
OUT
-
HYSTP
HYSTN
VREF
GND
+
V
2.048V
RN1
4.91 k:
1%
RN2
1 M:
1%
GND
Figure 18. Typical Configuration for Negative Hysteresis = −10 mV
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Feature Description (continued)
VOUT
1
OUTPUT
STATE
0
VIN
VREF
VIL
Figure 19. Typical Configuration for Negative Hysteresis = −10 mV
The case for setting only a positive hysteresis is demonstrated in Figure 21.
+
V
INP
+
-
VIN
RPULLUP
1 M:
+
OUT
INN
-
HYSTP
GND
HYSTN
VREF
+
V
2.048V
RP1
4.91 k:
1%
GND
RP2
1 M:
1%
Figure 20. Connections for Positive Hysteresis = 10 mV
VOUT
1
OUTPUT
STATE
0
VIN
VREF
VIH
Figure 21. Connections for Positive Hysteresis = 10 mV
In the general case, as demonstrated with both positive and negative hysteresis bands in Figure 22, noise within
these bands has no effect on the state of the comparator output. In Example 1 the noise is well behaved and in
band. The output is clean and well behaved. In Example 2, a significant amount of out of band noise is present;
however, due to hysteresis no false triggers occur on the rising positive or falling negative edges. The hysteresis
forces the signal level to move higher or lower before the output is set to the opposite state.
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Feature Description (continued)
VOUT
V
POSITIVE
TRIP POINTS
+
VOUT
VIH
VHYSTP
VTH
VHYSTN
VIL
HYSTERESIS
(DEAD) BAND
GND
TIME
VIN
NEGATIVE
TRIP POINTS
EXAMPLE 1
EXAMPLE 2
Figure 22. Output Response With Input Noise Less than Hysteresis Band
7.3.3.1 How Much Hysteresis Is Correct?
An effective way of determining the minimum hysteresis necessary for clean switching is to decrease the amount
of hysteresis until false triggering is observed, and then use a multiple of say three times that amount of
hysteresis in the final circuit. This is most easily accomplished in the breadboard phase by making R1 and R2
potentiometers. For applications near or above 100°C, TI recommends a minimum of 5-mV hysteresis due to
peaking of the LMP7300 noise sensitivity at high temperatures.
7.4 Device Functional Modes
The LMP7300 device may be used as a voltage reference or as a comparator with HIGH and LOW output states.
A LOW output will occur when the noninverting input (INP) is less than the inverting input (INN). A HIGH output
will occur when the noninverting input (INP) is greater than the inverting input (INN).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMP7300 device may be used in a variety of applications including precision threshold detection, battery
monitoring, battery management systems, and zero crossing detectors. The externally controlled hysteresis
functionality allows the user to determine how robust the device is against noise and false triggering.
8.2 Typical Applications
8.2.1 Window Comparator
Figure 23 shows two LMP7300s configured as a micropower window detector in a temperature level detection
application.
USB POWER SOURCE
4.3V to 5.5V
RT*
0.1 PF
R2
19.6 k:
1%
1 M:
INP
INN
HYSTP
+
-
VHIGH
TEMPERATURE
FAULT
OUT
HYSTN C1
LMP7300
VREF
2.32 k:
1%
R3
15.4 k:
1%
* NTC Thermistor
Such as: OMEGA #44008
30 k: @ 25°C
19.74 k: @ 35°C
46.67 k: @ 15°C
205 k:
1%
0.1 PF
+
INP
R1
61.9 k:
1%
R4
46.4 k:
1%
V
1 M:
+
INN
HYSTP
HYSTN C2
OUT
VLOW
TEMPERATUE
FAULT
LMP7300
VREF
2.32 k:
1%
205 k:
1%
Figure 23. Temperature-Controlled Window Detector to Monitor Ambient Temperature
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Typical Applications (continued)
8.2.1.1 Design Requirements
Figure 23 monitors the ambient temperature change. If the temperature rises outside the 15°C to 35°C window,
either comparator 1 for high temperature, or comparator 2 for low temperature, sets low, indicating a fault
condition has occurred. The open collector outputs are pulled up separately but can be wire-OR’d for a single
fault indication. If the temperature returns inside the window, it must overcome the 22-mV asymmetric hysteresis
band established on either comparator. For the high side, the temperature must drop below 34°C, and for the low
side the temperature must rise above 16°C for the outputs to reset high and remove the fault indication. The
temperature is sensed by a 30 kΩ @ 25°C Omega Precision NTC Thermistor #44008 (±0.2% tol).
8.2.1.2 Detailed Design Procedure
To set a fixed temperature threshold, the thermistor resistance ( RT*) must first be approximated at the specified
temperatures. For a temperature of 35°C, RT* =19.74 kΩ from Figure 23. A resistor divider with R1 =61.9 kΩ and
VREF can be formed on INN of comparator 1 to set the high side tripping voltage according to Equation 1. An
equivalent resistor divider must be formed on INP of comparator 1 by using the nearest 1% matching resistors of
R2=19.6 kΩ and a combination of R3=15.4 kΩ and R4=46.4 kΩ.
NOTE
a combination of resistors was chosen with R4=46.4 kΩ to set the low side tripping
threshold where RT* = 46.67 kΩ at 15°C .
A similar technique can be applied for comparator 2 to set the low side temperature of 15°C. The total change in
Volts can be computed by subtracting the two tripping thresholds to get a range of approximately 390 mV. Given
a total temperature change of 20°C, the hysteresis should be set to 19.5 mV to give an equivalent hysteresis of
1°C. A hysteresis value of 22.9 mV is calculated through the resistor divider of VREF, 2.32 kΩ, and 205 kΩ.
8.2.1.3 Application Curve
The results of the circuit shown in Figure 23 above can be plotted for various temperatures. A temperature
change of ±100°C/hour was chosen to demonstrate the functionality. Figure 24 shows that when the temperature
drops to 15°C the output of comparator 2 trips, which signifies a low temperature fault. When the temperature
returns and crosses the 22-mV hysteresis, comparator 2 returns to its normally high-output state. Similarly, when
the temperature reaches 35°C, comparator 1 trips and signifies a high temperature fault. When the temperature
returns below the hysteresis, comparator 1 returns to its normally high-output state.
Figure 24. Window Detector Output Response
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Typical Applications (continued)
8.2.2 Precision High-Temperature Switch
The LMP7300 brings accuracy and stability to simple sensor switch applications. Figure 26 shows the LMP7300
setup in a high temperature switch configuration. The input bridge is used to establish the temperature at which
the LMP7300 will trip and the temperature at which it resets.
VREF
VCC (2.7V ± 12V)
RTH
RADJ
3.24 k:
0.1 PF
T
VREF
RSET
78.7 k:
C1
6.8 PF
RSET
78.7 k:
RH1
1.44 k:
+
-
1 M:
VCC
LMP7300
HYSTN
HYSTP
GND
RH2
205 k:
Figure 25. Precision High-Temperature Switch
8.2.2.1 Design Requirements
In Figure 25, the input bridge establishes the trip point at 85°C and the reset temperature at 80°C. The
comparator is set up with positive hysteresis of 14.3 mV and no negative hysteresis. When the temperature is
rising, it trips at 85°C. The 14.3-mV hysteresis allows the temperature to drop to 80°C before reset.
The temperature sensor used is an Omega 44008 Precision NTC Thermistor. The 44008 has an accuracy of
±0.2°C. The resistance at 85°C is 3270.9 Ω and at 80°C is 3840.2 Ω. The trip voltage threshold is established by
one half of the bridge, which is the ratio of RADJ and RSET. The input signal bias is set by the second half, which
is the ratio of the thermistor resistance RTH and RSET. The resistance values are chosen for approximately 50-µA
bridge current to minimize the power in the thermistor. The thermistor specification states it has a 1°C/mW
dissipation error. The reference voltage establishes the supply voltage for the bridge to make the circuit
independent of supply voltage variation. Capacitor C1 establishes a low-frequency pole at FCORNER = 1/(2πC1 ×
2(RSET//RADJ)). With the resistance values chosen C1 should be selected for Fc < 10 Hz. This will limit the
thermal noise in the bridge.
The accuracy of the circuit can be calculated from the nearest resistance values chosen. For 1% resistors RADJ
is 3.24 kΩ, and RSET is 78.7 kΩ. The bridge gain becomes 2.488 mV/C at 85°C. In general, the higher the bridge
current is allowed to be, the higher the bridge gain will be. The actual trip point found during simulation is 85.3°C
and the reset point is 80.04°C. With the values chosen the worst case trip temperature uncertainty is ±1.451°C
and the reset uncertainty is ±1.548°C. Accuracy could be maximized with resistors chosen to 0.1% values, 0.1%
tolerance and by using the 0.1% model of the Omega 44008 thermistor.
8.2.3 Micropower Precision-Battery Low-Voltage Detector
The ability of the LMP7300 device to operate at very low supply voltages makes it an ideal choice for low battery
detection application in portable equipment. The circuit in Figure 26 performs the function of low voltage
threshold detection in a battery monitor application.
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Typical Applications (continued)
VBATT
The LED turns on when VBATT x
R2
1 M:
1%
so, if
+
INP
INN
HYSTP
HYSTN
V
LED
+
-
GND
OUT
VREF
VBATT
R2
R1 + R2
d VREF,
= D and R2 is known,
§
¨¨
©
R1
318.4 k:
1%
R5
§
¨
©
0.1 PF
§ VBATT - VREF
§1 - D
= R2 ¨
then, R1 = R2 ¨ D
©
VREF
©
VREF
As an example:
R3
9.86 k:
1%
VREF = 2.048V, VBATTLOW = +2.7V, R2 = 1 M:
then R1 = 318.4 k:
R4
1 M:
1%
Figure 26. Battery Voltage Monitor for 3-Cell Discharge Voltage
8.2.3.1 Design Requirements
The circuit in Figure 26 is configured to detect the low voltage threshold detection in a 3 cell, 0.9-V discharge
voltage, battery monitor application. R1 and R2 are chosen to set the inverting input voltage equal to the
noninverting input voltage when the battery voltage is equal to the minimum operating voltage of the system.
Here, the very precise reference output voltage is directly connected to the noninverting input on the comparator
and sets an accurate threshold voltage. The hysteresis is set to 0-mV negative and 20-mV positive. The output is
off for voltages higher than the minimum VBATT, and turns on when the circuit detects a minimum battery voltage
condition.
9 Power Supply Recommendations
Even in low-frequency applications, the LMP7300 can have internal transients which are extremely quick. For
this reason, bypassing the power supply with 1-μF to ground will provide improved performance; the supply
bypass capacitor should be placed as close as possible to the supply pin and have a solid connection to ground.
The bypass capacitors should have a low ESR.
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10 Layout
10.1 Layout Guidelines
A good PCB layout is always important to reduce output to input coupling. Positive feedback noise reduces
performance. For the LMP7300, output coupling is minimized by the unique package pinout. The output is kept
away from the noninverting and inverting inputs, the reference and the hysteresis pins.
10.2 Layout Example
The following section shows an example schematic and layout for the LMP7300MA 8-pin SOIC package.
J3
TP1
R1
1 M:
VIN
BNC
VCC
VOH
JP2
8
1
+
-
6
J4
JP3
JP4
HYSTP
5
HYSTN
J2
4
VREF
TP4
HYSTN
TP3
R8
OPEN
C4
0.1 PF
VCC
VCC
OUT
BNC
TP5
VOH
VOH
J5
LMP7300
7
HYSTP
TP2
R9
1 M:
GND
2
3
R3
OPEN
C2
OPEN
5 PF
C1
0.1 PF
VCC
JP1
R4
50 k:
VREF
R2
1 M:
R6
50 k:
R7
50 k:
R5
1 M:
R10
1 M:
CREF
OPEN
J6
GND
JP5
JP6
J1
VEE
VEE
VEE
C6
OPEN
5 PF
Figure 27. LMP7300MA-EVAL Schematic
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Layout Example (continued)
Figure 28. LMP7300MA-EVAL Layout Top View
Figure 29. LMP7300MA-EVAL Layout Bottom View
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Boards
Texas Instruments provides the following PCB boards as an aid in evaluating the LMP7300 performance in the 8pin SOIC package. For more information on the evaluation board, LMP7300MA-EVAL, of the LMP7300MA
device option, see AN-1639 LMP7300 Single Precision Comparator With Reference Evaluation Boards (SOIC
and VSSOP), SNOA491.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMP7300MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP73
00MA
LMP7300MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP73
00MA
LMP7300MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
C31A
LMP7300MME/NOPB
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
C31A
LMP7300MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
C31A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jul-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMP7300MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMP7300MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP7300MME/NOPB
VSSOP
DGK
8
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP7300MMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMP7300MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMP7300MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMP7300MME/NOPB
VSSOP
DGK
8
250
210.0
185.0
35.0
LMP7300MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
Pack Materials-Page 2
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