Gennum GS9025ACQM Serial digital receiver Datasheet

GENLINX ™II GS9025A
Serial Digital Receiver
DATA SHEET
DESCRIPTION
• SMPTE 259M compliant
The GS9025A provides automatic cable equalization and
high performance clock and data recovery for serial digital
signals. The GS9025A receives either single-ended or
differential serial digital data and outputs differential clock
and retimed data signals at PECL levels (800mV). The onboard cable equalizer provides up to 40dB of gain at
200MHz which typically results in equalization of greater
than 350m of high quality cable at 270Mb/s.
• operational to 540Mb/s
• automatic cable equalization (typically greater than
350m of high quality cable at 270Mb/s)
• adjustment-free operation
• auto-rate selection (5 rates) with manual override
• single external VCO resistor for operation with five
input data rates
The GS9025A operates in either auto or manual data rate
selection mode. In both modes, the GS9025A requires only
one external resistor to set the VCO centre frequency and
provides adjustment free operation.
• data rate indication output
• serial data outputs muted and serial clock remains
active when input data is lost
• operation independent of SAV/EAV sync signals
• signal strength indicator output
• carrier detect with programmable threshold level
• power savings mode (output serial clock disable)
• Pb-free and Green
APPLICATIONS
Cable equalization plus clock and data recovery for all high
speed serial digital interface applications involving SMPTE
259M and other data standards.
The GS9025A has dedicated pins to indicate signal
strength/carrier detect, LOCK and data rate. Optional
external resistors allow the carrier detect threshold level to
be customized to the user's requirement. In addition, the
GS9025A provides an 'Output Eye Monitor Test'
(OEM_TEST) for diagnostic testing of signal integrity after
equalization, prior to reslicing. The serial clock outputs can
also be disabled to reduce power. The GS9025A operates
from a single +5 or -5 volt supply.
ORDERING INFORMATION
PART NUMBER
PACKAGE
TEMPERATURE
Pb-FREE AND GREEN
GS9025ACQM
44 pin MQFP Tray
0°C to 70°C
No
GS9025ACTM
44 pin MQFP Tape
0°C to 70°C
No
GS9025ACQME3
44 pin MQFP Tray
0°C to 70°C
Yes
GS9025ACTME3
44 pin MQFP Tape
0°C to 70°C
Yes
COSC
A/D
DDI
LOCK
ANALOG
DIGITAL
MUX
DDI
CARRIER DETECT
PHASELOCK
HARMONIC
LOGIC
MUTE
SDO
SDI
+
SDI
--
FREQUENCY
ACQUISITION
VARIABLE
GAIN EQ
STAGE
SDO
CLK_EN
PHASE
DETECTOR
SCO
SCO
OEM_TEST
EYE
MONITOR
3 BIT
COUNTER
DIVISION
AUTO EQ
CONTROL
SMPTE
AUTO/MAN
+
AGC CAP CD_ADJ
SSI/CD
CHARGE
PUMP
LF+ LFS LF-
VCO
DECODER
SS0
SS1
SS2
CBG RVCO
BLOCK DIAGRAM
Revision Date: August 2005
Document No. 522 - 75 - 05
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
GS9025A
FEATURES
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
Supply Voltage (VS)
5.5V
Input Voltage Range (any input)
VCC + 0.5 to VEE - 0.5V
0°C ≤ TA ≤ 70°C
Operating Temperature Range
GS9025A
-65°C ≤ TS ≤ 150°C
Storage Temperature Range
Lead Temperature (soldering, 10 sec)
260°C
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, TA = 0° to 70°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF
TEST
LEVEL
MIN
TYPICAL1
MAX
UNITS
4.75
5
5.25
V
3
CLK_EN = 0
-
115
mA
9
CLK_EN = 1
-
125
mA
3
-
2.4
-
V
3
DDI Common Mode Input
Voltage Range
VEE+(VDIFF/2)
0.4 to 4.6
VCC-(VDIFF/2)
V
DDI Differential Input Drive
200
800
2000
mV
3
HIGH, 100m,
143Mb/s, ΙOH=-10µA
-
4.2
-
V
3
HIGH, 300m,
143Mb/s, ΙOH=-10µA
-
3.7
-
LOW, ΙOL=1mA
-
0.4
0.8
V
1
OEM_TEST Bias Potential
RL=50Ω
-
4.75
-
V
A/D
High
2.3
-
-
V
3
Low
-
-
0.8
High
2.0
-
-
V
3
Low
-
-
0.8
High
2.5
-
-
V
3
Low
-
-
0.8
LOCK Output Low Voltage
ΙOL=500µA
-
0.25
0.4
V
SS[2:0] Output Voltage
HIGH, ΙOH=-180µA,
Auto Mode
4.4
4.8
-
V
-
0.3
0.4
PARAMETER
CONDITION
Supply Voltage
Supply Current
SDI Common Mode Voltage
SSI/CD Output Current
AUTO/MAN, SMPTE, SS[2:0]
Input Voltage
CLK_EN Input Voltage
LOW, ΙOL=600µA,
Auto Mode
NOTES
2
5
3
3
3
1
1
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DC ELECTRICAL CHARACTERISTICS (Continued)
VCC = 5.0V, TA = 0° to 70°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF
PARAMETER
SS[2:0] Input Voltage
MIN
TYPICAL
HIGH, Manual Mode
2
LOW, Manual Mode
Low, VIL = 0V
1
NOTES
TEST
LEVEL
MAX
UNITS
-
-
V
3
-
-
0.8
-
26
55
µA
1
NOTES
TEST LEVELS
1. TYPICAL - measured on EB9025A board.
1. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature
ranges.
2. VDIFF is the differential input signal swing.
3. LOCK is an open collector output and requires an external pull-up
resistor.
4. Pins SS[2:0] are outputs in AUTO mode and inputs in MANUAL mode.
5. If OEM_TEST is permanently enabled, operating temperature range is
limited from 0°C to 60°C inclusive.
2. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature
ranges using correlated test.
3. Production test at room temperature and nominal supply
voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization
data of similar product.
9. Indirect test.
AC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VEE = 0V, TA = 0° to 70°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF
PARAMETER
CONDITIONS
Serial Data Rate
SDI
Maximum Equalizer Gain
Additive Jitter
MIN
TYPICAL
1
MAX
UNITS
NOTES
TEST
LEVEL
143
-
540
Mb/s
3
@ 200MHz
-
40
-
dB
6
270Mb/s, 300m
(Belden 8281)
-
300
-
ps p-p
2, 8
9
540Mb/s, 100m
(Belden 8281)
-
275
-
270Mb/s
-
185
see Figure 12
ps p-p
2, 7
4
540Mb/s
-
164
270Mb/s
-
462
see Figure 13
ps p-p
2, 7
3
360Mb/s
-
308
540Mb/s
-
260
270Mb/s
0.40
0.56
-
UI p-p
3, 7
9
540Mb/s
0.32
0.43
-
tswitch < 0.5µs, 270Mb/s
-
1
-
µs
4
7
0.5µs< tswitch <10ms
-
1
-
ms
tswitch > 10 ms
-
4
-
ms
Lock Time -
Loop Bandwidth
-
10
-
ms
5
7
Asynchronous Switch
= 6MHz @ 540Mb/s
23
[Pseudorandom (2
-1)]
Intrinsic Jitter
23
[Pseudorandom (2
-1)]
Intrinsic Jitter
[Pathological (SDI checkfield)]
Input Jitter Tolerance
Lock Time Synchronous Switch
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GS9025A
CLK_EN Source Current
CONDITION
AC ELECTRICAL CHARACTERISTICS (Continued)
VCC = 5.0V, VEE = 0V, TA = 0° to 70°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF
PARAMETER
CONDITIONS
SDO Mute Time
SDO to SCO Synchronization
MAX
UNITS
NOTES
TEST
LEVEL
1
2
µs
6
7
-200
0
200
ps
7
MIN
TYPICAL
0.5
1
75Ω DC load
600
800
1000
mV p-p
1
SDO, SCO Rise & Fall times
20%-80%
200
300
400
ps
7
SDI/SDI Input Resistance
-
10
-
kΩ
8
6
SDI/SDI Input Capacitance
-
1.0
-
pF
8
6
Carrier Applied,
-
3
-
µs
8, 9
6
Carrier Removed,
-
30
-
Carrier Detect Response Time
NOTES
TEST LEVELS
1. TYPICAL - measured on CB9025A board.
1. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature
ranges.
2. Characterized 6 sigma rms.
3. IJT measured with sinusoidal modulation beyond Loop
Bandwidth (at 6.5MHz).
4. Synchronous switching refers to switching the input data from
one source to another source which is at the same data rate (ie.
line 10 switching for component NTSC).
5. Asynchronous switching refers to switching the input data from
one source to another source which is at a different data rate.
2. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature ranges
using correlated test.
3. Production test at room temperature and nominal supply
voltage.
4. QA sample test.
6. SDO Mute Time refers to the response of the SDO outputs from
valid re-clocked input data to mute mode when the input signal
is removed.
5. Calculated result based on Level 1,2, or 3.
7. Using the DDI input, A/D=0.
8. Not tested. Based on existing design/characterization data
of similar product.
8. Using the SDI input, A/D=1.
9. Carrier detect response time refers to the response of the SSI/CD
output from a logic high to logic low state when the input signal is
removed or its amplitude drops below the threshold set by the
CD_ADJ PIN. SSI/CD PIN loading CL<50pF, RL = open cct.
DATA
TEKTRONIX
GigaBERT
1400
TRANSMITTER
DATA
GS9028
CABLE
DRIVER
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
9. Indirect test.
BELDEN 8281
CABLE
CB9025A
BOARD
TEKTRONIX
GigaBERT
1400
ANALYZER
CLOCK
TRIGGER
Fig. 1 Test Setup for Figures 6 - 13
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GS9025A
SDO, SCO Output Signal
Swing
COSC
39
38 37
36
35 34
VEE
LOCK
40
VCC
SSI/CD
41
CLK_EN
A/D
42
VEE
SMPTE
43
31
SDO
VCC
4
30
VEE
VEE
5
GS9025A
29
SCO
SDI
6
TOP VIEW
28
SCO
SDI
7
27
VEE
VCC
8
26
AUTO/MAN
VEE
9
25
SS0
CD_ADJ
10
24
SS1
AGC-
11
23
SS2
13
14
15
16
17
18 19
20
21 22
VCC
12
CBG
3
RVCO
VCC_75
RVCO_RTN
SDO
VEE
32
LF-
2
LFS
DDI
LF+
VEE
VEE
33
VCC
1
AGC+
DDI
GS9025A
44
OEM_TEST
VCC_75
PIN CONNECTIONS
PIN DESCRIPTIONS
NUMBER
SYMBOL
TYPE
DESCRIPTION
1, 2
DDI/DDI
I
Digital data inputs (Differential ECL/PECL).
3, 44
VCC_75
I
Power supply connection for internal 75Ω pull-up resistors connected to DDI/DDI.
4, 8, 13, 22, 35
VCC
I
Most positive power supply connection.
5, 9, 14, 18, 27,
30, 33, 34, 37
VEE
I
Most negative power supply connection.
6, 7
SDI/SDI
I
Differential analog data inputs.
10
CD_ADJ
I
Carrier detect threshold adjust.
11, 12
AGC-, AGC+
I
External AGC capacitor. VCOMMON MODE=2.7V TYP.
15
LF+
I
Loop filter component connection.
16
LFS
I
Loop filter component connection.
17
LF-
I
Loop filter component connection.
19
RVCO_RTN
I
Frequency setting resistor return connection.
20
RVCO
I
Frequency setting resistor connection.
21
CBG
I
Internal bandgap voltage filter capacitor.
23, 24, 25
SS[2:0]
I/O
26
AUTO/MAN
I
Data rate indication (auto mode) or data rate select (manual mode). TTL/CMOS
compatible I/O. In auto mode, these pins can be left unconnected.
Auto or manual mode select. TTL/CMOS compatible input.
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PIN DESCRIPTIONS (Continued)
SYMBOL
TYPE
DESCRIPTION
28, 29
SCO/SCO
O
Serial clock output. SCO/SCO are differential current mode outputs and require
external 75Ω pull-up resistors.
31, 32
SDO/SDO
O
Equalized and reclocked serial digital data outputs. SDO/SDO are differential current
mode outputs and require external 75Ω pull-up resistors.
36
CLK_EN
I
Clock enable. When HIGH, the serial clock outputs are enabled.
38
COSC
I
Timing control capacitor for internal system clock.
39
LOCK
O
Lock indication. When HIGH, the GS9025A is locked. LOCK is an open collector output
and requires an external 10kΩ pull-up resistor.
40
SSI/CD
O
Signal strength indicator/Carrier detect.
41
A/D
I
Analog/Digital select.
42
SMPTE
I
SMPTE/Other data rate select. TTL/CMOS compatible input.
43
OEM_TEST
O
Output ‘Eye’ monitor test. Single-ended current mode output that requires an external
50Ω pull-up resistor. This feature is recommended for debugging purposes only. If
enabled during normal operation, the maximum operating temperature is rated to
60°C. For maximum cable length performance OEM_TEST must be disabled.
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GS9025A
NUMBER
TYPICAL PERFORMANCE CURVES
(VS = 5V, TA = 25°C unless otherwise shown)
j1
j2
j0.5
j5
SSI/CD OUTPUT VOLTAGE (V)
4.50
270
3000
4.00
1620
-j0.2
3.50
-j5
810
3.00
-j0.5
-j2
2.50
0
50
100
150
200
250
300
350
400
450
500
-j1
Frequencies in MHz, impedances normalized to 50Ω
CABLE LENGTH (m)
Fig. 2 SSI/CD Voltage vs. Cable Length
(Belden 8281) (CD_ADJ = 0V)
Fig. 5 Input Impedance
50
450
45
400
40
JITTER (ps p-p)
GAIN (dB)
35
30
25
20
15
540Mb/s
300
250
200
270Mb/s
150
100
10
50
5
0
(Characterized)
350
1
10
100
0
1000
0
50
100
150
200
250
300
350
400
CABLE LENGTH (m)
FREQUENCY (MHz)
Fig. 3 Equalizer Gain vs. Frequency
Fig. 6 Typical Additive Jitter vs. Input Cable Length (Belden 8281)
Pseudorandom (223-1)
450
5.0
400
CABLE LENGTH (m)
CD_ADJ VOLTAGE (V)
4.5
4.0
3.5
3.0
350
300
250
200
2.5
150
2.0
200
250
300
350
100
400
200
300
400
500
600
DATA RATE (Mb/s)
CABLE LENGTH (m)
Fig. 4 Carrier Detect Adjust Voltage Threshold Characteristics
Fig. 7 Typical Error Free Cable Length
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GS9025A
j0.2
5.00
GS9025A
23
Fig. 8 Intrinsic Jitter (2
Fig. 11 Intrinsic Jitter (2
- 1 Pattern) 30Mb/s
23
- 1 Pattern) 540Mb/s
2000
1800
1600
JITTER (ps)
1400
1200
1000
800
600
Typical Range, Characterized
400
Max
Typical
Min
200
0
100
200
300
400
500
600
SDI DATA RATE (Mb/s)
TA=0 to 70˚C, VCC=4.75 to 5.25V for the typical range
Fig. 9 Intrinsic Jitter (223 - 1 Pattern) 143Mb/s
Fig. 12 Intrinsic Jitter - Pseudorandom (2
23
- 1)
2000
1800
1600
JITTER (ps p-p)
1400
1200
1000
800
600
400
Max
Typical
Min
200
Typical Range, Characterized
0
100
200
300
400
500
600
SDI DATA RATE (Mb/s)
TA = 0 to 70˚C, VCC = 4.75 to 5.25V for the typical range
Fig. 10 Intrinsic Jitter (2
23
Fig. 13 Intrinsic Jitter - Pathological SDI Checkfield
- 1 Pattern) 270Mb/s
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0.5
IJT (UI)
0.4
0.3
0.2
0.1
0
100
200
300
400
500
600
The edge energy of the equalized signal is monitored by a
detector circuit which produces an error signal
corresponding to the difference between the desired edge
energy and the actual edge energy. This error signal is
integrated by an external differential AGC filter capacitor
(AGC+/AGC-) providing a steady control voltage for the
gain stage. As the frequency response of the gain stage is
automatically varied by the application of negative
feedback, the edge energy of the equalized signal is kept
at a constant level which is representative of the original
edge energy at the transmitter.
DATA RATE (Mb/s)
TA = 0 to 70˚C, VCC = 4.75 to 5.25V
Fig. 14 Typical Input Jitter Tolerance (Characterized)
0.600
143Mb/s
0.550
177Mb/s
270Mb/s
0.500
360Mb/s
0.400
The equalized signal is DC restored, effectively restoring
the logic threshold of the equalized signal to its corrective
level irrespective of shifts due to AC coupling.
540Mb/s
0.350
0.300
1.1
0.250
0.200
0
10
20
30
40
50
60
70
TEMPERATURE (C˚)
Fig. 15 Typical IJT vs. Temperature (VCC = 5.0V) (Characterized)
DETAILED DESCRIPTION
The GS9025A Serial Digital Receiver is a bipolar integrated
circuit containing a built-in cable equalizer and reclocker.
Serial digital signals are applied to either the analog
SDI/SDI or digital DDI/DDI inputs. Signals applied to the
SDI/SDI inputs are equalized and then passed to a
multiplexer. Signals applied to the DDI/DDI inputs bypass
the equalizer and go directly to the multiplexer. The
analog/digital select pin (A/D) determines which signal is
then passed to the reclocker.
Signal Strength Indication/Carrier Detect
The GS9025A incorporates an analog signal strength
indicator/carrier detect (SSI/CD) output indicating both the
presence of a carrier and the amount of equalization
applied to the signal. The voltage output of this pin versus
cable length (signal strength) is shown in Figures 2 and 16.
With 0m of cable (800mV input signal levels), the SSI/CD
output voltage is approximately 4.5V. As the cable length
increases, the SSI/CD voltage decreases linearly providing
accurate correlation between the SSI/CD voltage and cable
length.
Packaged in a 44 pin MQFP, the receiver operates from a
single 5V supply to data rates of 540Mb/s. Typical power
consumption is 575mW.
5
SSI/CD OUTPUT VOLTAGE (V)
IJT (UI)
0.450
4
3
CD_ADJ
CONTROL RANGE
2
1
1. CABLE EQUALIZER
The automatic cable equalizer is designed to equalize
serial digital data signals from 143Mb/s to 540Mb/s.
0
0
50
100
150
200
250
300
350
400
450
500
CABLE LENGTH (m)
Fig. 16 SSI/CD Voltage vs. Cable Length
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GS9025A
The serial data signal is connected to the input pins
(SDI/SDI) either differentially or single-ended. An input
return loss of 20dB at 270 Mb/s has typically been achieved
on the CB9025A characterization board. The input signal
then passes through a variable gain equalizing stage
whose frequency response closely matches the inverse
cable loss characteristic. The variation of the frequency
response with control voltage imitates the variation of the
inverse cable loss characteristic with cable length. The gain
stage provides up to 40dB of gain at 200MHz which
typically results in equalization of greater than 350m at
270Mb/s of Belden 8281 cable.
0.6
When the signal strength decreases to the level set at the
"Carrier Detect Threshold Adjust" pin, the SSI/CD voltage
goes to a logic "0" state (0.8 V) and can be used to drive
other TTL/CMOS compatible logic inputs. When loss of
carrier is detected, the SDO/SDO outputs are muted (set to
a known static state). Additional SSI/CD output source
current can be obtained in applications with a pull-up
resistor. An external 5k pull-up resistor with less than 50pF
capacitor loading is recommended.
SDO
SCO
1.2 Carrier Detect Threshold Adjust
GS9025A
50%
Fig. 17 Output and Clock Signal Timing
Carrier Detect Threshold Adjust is designed for applications
such as routers where signal crosstalk and circuit noise
cause the equalizer to output erroneous data when no input
signal is present. The GS9025A solves this problem with a
user adjustable threshold which meets the unique
conditions that exist in each application. Override and
internal default settings are provided to give the user total
flexibility.
The threshold level at which loss of carrier is detected is
adjustable via external resistors at the CD_ADJ pin. The
control voltage at the CD_ADJ pin is set by a simple resistor
divider circuit (see Typical Application Circuit). The
threshold level is adjustable from 200m to 350m. By default
(no external resistors), the threshold is typically 320m. In
noisy environments, it is not recommended to leave this pin
floating. Connecting this pin to VEE disables the SDO/SDO
muting function and allows for maximum possible cable
length equalization.
The reclocker contains four main functional blocks: the
Phase Locked Loop, Frequency Acquisition, Logic Circuit,
and Auto/Manual Data Rate Select.
2.1 Phase Locked Loop (PLL)
The Phase Locked Loop locks the internal PLL clock to the
incoming data rate. A simplified block diagram of the PLL is
shown below. The main components are the VCO, the
Phase Detector, the Charge Pump, and the Loop Filter.
DDI/DDI
2
PHASE
DETECTOR
INTERNAL
PLL CLOCK
DIVISION
1.3 Output Eye Monitor Test
The GS9025A provides an 'Output Eye Monitor Test'
(OEM_TEST) which allows the verification of signal integrity
after equalization, prior to reslicing. The OEM_TEST pin is
an open collector current output that requires an external
50Ω pull-up resistor. When the pull-up resistor is not used,
the OEM_TEST block is disabled and the internal
OEM_TEST circuit is powered down. The OEM_TEST
provides a typical 100mVp-p signal when driving a 50Ω
oscilloscope input. Due to additional power consumed by
this diagnostic circuit, it is not recommended for continuous
operation.
NOTE: For maximum cable length performance the
OEM_TEST block should be disabled.
2. RECLOCKER
The reclocker receives a differential serial data stream from
the internal multiplexer. It locks an internal clock to the
incoming data. It outputs the differential PECL retimed data
signal on SDO/SDO. It outputs the recovered clock on
SCO/SCO. The timing between the output and clock signals
is shown in Figure 17.
CHARGE
PUMP
LF+
LFS
RLF CLF1
VCO
LF-
RVCO
LOOP
FILTER
CLF2
Fig. 18 Simplified Block Diagram of the PLL
2.1.1 VCO
The VCO is a differential low phase noise, factory trimmed
design that provides increased immunity to PCB noise and
precise control of the VCO centre frequency. The VCO
operates between 30 and 540Mb/s and has a pull range of
±15% about the centre frequency. A single low impedance
external resistor, RVCO, sets the VCO centre frequency (see
Figure 19). The low impedance RVCO minimizes thermal
noise and reduces the PLL's sensitivity to PCB noise.
For a given RVCO value, the VCO can oscillate at one of two
frequencies. When SMPTE = SS0 = logic 1, the VCO centre
frequency corresponds to the ƒL curve. For all other
SMPTE/SS0 combinations, the VCO centre frequency
corresponds to the ƒH curve (ƒH is approximately 1.5 x ƒL).
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2.1.4 Loop Filter
800
The loop filter integrates the charge pump packets and
produces a VCO control voltage. The loop filter is
comprised of three external components which are
connected to pins LF+, LFS, and LF-. The loop filter design
is fully differential which increases the GS9025’s immunity to
PCB board noise.
600
500
400
ƒH
300
SMPTE=1
SSO=1
100
0 0
The loop filter components are critical in determining the
loop bandwidth and damping of the PLL. Choosing these
component values is discussed in detail in section 2.9, PLL
Design Guidelines. Recommended values for SMPTE 259M
applications are shown in the Typical Application Circuit.
ƒL
200
200
400
600
800
1000
1200 1400
1600
1800
RVCO (Ω)
Fig. 19 RVCO vs. VCO Centre Frequency
2.2 Frequency Acquisition
The recommended RVCO value for auto rate SMPTE 259M
applications is 365Ω.
The VCO and an internal divider generate the PLL clock.
Divider moduli of 1, 2, and 4 allow the PLL to lock to data
rates from 143Mb/s to 540Mb/s. The divider modulus is set
by the AUTO/MAN, SMPTE, and SS[2:0] pins (for further
details, see section 2.4, Auto/Manual Data Rate Select). In
addition, a manually selectable modulus 8 divider allows
operation at data rates as low as 30Mb/s.
The core PLL is able to lock if the incoming data rate and
the PLL clock frequency are within the PLL capture range
(which is slightly larger than the loop bandwidth). To assist
the PLL to lock to data rates outside of the capture range,
the GS9025A uses a frequency acquisition circuit.
The frequency acquisition circuit sweeps the VCO control
voltage so that the VCO frequency changes from -10% to
+10% of the centre frequency. Figure 20 shows a typical
sweep waveform.
When the input data stream is removed for an excessive
period of time (see AC Electrical Characteristics table), the
VCO frequency can drift from the previously locked
frequency to the limits shown in Table1.
tsys
tswp
VLF
TABLE 1: Frequency Drift Range (when PLL loses lock)
A
LOSES LOCK FROM
MIN (%)
MAX(%)
143Mb/s lock
-21
21
177Mb/s lock
-12
26
Fig. 20 Typical Sweep Waveform
270Mb/s lock
-13
28
360 Mb/s lock
-13
24
540 Mb/s lock
-13
28
The VCO frequency starts at point A and sweeps up
attempting to lock. If lock is not established during the up
sweep, the VCO is then swept down. The probability of
locking within one cycle period is greater than 0.999. If the
system does not lock within one cycle period, it will attempt
to lock in the subsequent cycle. In manual mode, the
divider modulus is fixed for all cycles. In auto mode, each
subsequent cycle is based on a different divider moduli as
determined by the internal 3-bit counter.
Tcycle
Tcycle = tswp + tsys
2.1.2 Phase Detector
The phase detector compares the phase of the PLL clock
with the phase of the incoming data signal and generates
error correcting timing pulses. The phase detector design
provides a linear transfer function which maximizes the
input jitter tolerance of the PLL.
The average sweep time, tswp, is determined by the loop
filter component, CLF1, and the charge pump current, ΙCP:
2.1.3 Charge Pump
The charge pump takes the phase detector output timing
pulses and creates a charge packet that is proportional to
the system phase error. A unique differential charge pump
design ensures that the output phase does not drift when
data transitions are sparse. This makes the GS9025A ideal
for SMPTE 259M applications where pathological signals
have data transition densities of 0.05.
4C LF1
t SWP = --------------3I CP
The nominal sweep time is approximately 121µs when
CLF1 = 15nF and ΙCP = 165µA (RVCO = 365Ω).
An internal system clock determines tsys (see section 2.3,
Logic Circuit).
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GS9025A
VCO FREQUENCY (MHz)
700
2.3 Logic Circuit
2.4.2 Manual Mode (AUTO/MAN = 0)
The GS9025A is controlled by a finite state logic circuit
which is clocked by an asynchronous system clock. In other
words, the system clock is completely independent of the
incoming data rate. It runs at low frequencies, relative to the
incoming data rate, thereby reducing interference to the
PLL. The period of the system clock is set by the COSC
capacitor and is
In manual mode, the GS9025A divider moduli is fixed. In
this mode, the SS[2:0] pins are inputs and set the divider
moduli according to Table 3.
TABLE 3.
4
t sys = 9.6 × 10 × C OSC [ sec onds ]
The recommended value for tsys is 450µs (COSC = 4.7nF).
2.4 Auto/Manual Data Rate Select
SMPTE
SS[2:0]
DIVIDER
MODULI
PLL CLOCK
1
000
4
ƒH/4
1
001
2
ƒL/2
The GS9025A can operate in either auto or manual data
rate select mode. The mode of operation is selected by a
single input pin (AUTO/MAN).
1
010
2
ƒH/2
1
011
1
ƒL
1
100
1
ƒH
2.4.1 Auto Mode (AUTO/MAN = 1)
1
101
8
ƒL/8
In auto mode, the GS9025A uses a 3-bit counter to
automatically cycle through five (SMPTE=1) or three
(SMPTE=0) different divider moduli as it attempts to acquire
lock. In this mode, the SS[2:0] pins are outputs and indicate
the current value of the divider moduli according to Table 2.
1
110
8
ƒH/8
1
111
-
-
0
000
4
ƒH/4
0
001
4
ƒH/4
0
010
2
ƒH/2
0
011
2
ƒH/2
0
100
1
ƒH
0
101
1
ƒH
0
110
8
ƒH/8
0
111
-
-
NOTE: For SMPTE = 0 and divider moduli of 2 and 4, the
PLL can correctly lock for two values of SS[2:0].
TABLE 2.
AUTO/MAN = 1 (AUTO MODE)
ƒH, ƒL = VCO centre frequency as per Figure 19.
SMPTE
SS[2:0]
DIVIDER
MODULI
PLL CLOCK
1
000
4
ƒH/4
1
001
2
ƒL/2
1
010
2
ƒH/2
1
011
1
ƒL
1
100
1
ƒH
1
101
-
-
1
110
-
-
1
111
-
-
0
000
4
ƒH/4
0
001
4
ƒH/4
0
010
2
ƒH/2
0
011
2
ƒH/2
0
100
1
ƒH
0
101
-
-
0
110
-
-
0
111
-
-
2.5 LOCKING
The GS9025A indicates lock when three conditions are
satisfied:
1. Input data is detected.
2. The incoming data signal and the PLL clock are phase
locked.
3. The system is not locked to a harmonic.
The GS9025A defines the presence of input data when at
least one data transition occurs every 1µs.
The GS9025A assumes that it is NOT locked to a harmonic
if the pattern ‘101’ or ‘010’ (in the reclocked data stream)
occurs at least once every tsys/3 seconds. Using the
recommended component values, this corresponds to
approximately 150µs. In a harmonically locked system, all
bit cells are double clocked and the above patterns
become ‘110011’ and ‘001100’, respectively.
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GS9025A
AUTO/MAN = 1 (MANUAL MODE)
ƒH, ƒL = VCO centre frequency as per Figure 19.
2.6 Output Data Muting
The lock time of the GS9025A depends on whether the
input data is switching synchronously or asynchronously.
Synchronous switching means that the input data is
changed from one source to another source which is at the
same data rate (but different phase). Asynchronous
switching means that the input data is changed from one
source to another source which is at a different data rate.
The GS9025A internally mutes the SDO and SDO outputs
when the device is not locked. When muted, SDO/SDO are
latched providing a logic state to the subsequent circuit
and avoiding a condition where noise could be amplified
and appear as data.
The output data muting timing is shown in Figure 21.
When input data to the GS9025A is removed, the GS9025A
latches the current state of the counter (divider modulus).
Therefore, when data is reapplied, the GS9025A begins the
lock procedure at the previous locked data rate. As a result,
in synchronous switching applications, the GS9025A locks
very quickly. The nominal lock time depends on the
switching time and is summarized in Table 4.
NO DATA TRANSITIONS
DDI
LOCK
SDO
VALID
DATA
OUTPUTS MUTED
VALID
DATA
TABLE 4.
SWITCHING TIME
LOCK TIME
<0.5µs
10µs
0.5µs - 10ms
2tsys
>10ms
2Tcycle + 2tsys
Fig. 21 Output Data Muting Timing
2.7 Clock Enable
In asynchronous switching applications, including power
up, the lock time is determined by the frequency acquisition
circuit (see section 2.2, Frequency Acquisition).
To acquire lock in manual mode, the frequency acquisition
circuit may have to sweep over an entire cycle depending
on initial conditions. Maximum lock time is 2Tcycle + 2tsys.
To acquire lock in auto tune mode, the frequency
acquisition circuit may have to cycle through 5 possible
counter states depending on initial conditions. Maximum
lock time is 6Tcycle + 2tsys.
The nominal value of Tcycle for the GS9025A operating in a
typical SMPTE 259M application is approximately 1.3ms.
The GS9025A has a dedicated LOCK output (pin 39)
indicating when the device is locked.
NOTE: In synchronous switching applications where the
switching time is less than 0.5µs, the LOCK output will NOT
be de-asserted and the data outputs will NOT be muted.
2.5.2 DVB-ASI
When CLK_EN is high, the GS9025A SCO/SCO outputs are
enabled. When CLK_EN is low, the SCO/SCO outputs are
set to a high Z state and float to VCC. Disabling the clock
outputs results in a power savings of 10%. It is
recommended that the CLK_EN input be hard wired to the
desired state. For applications which do not require the
clock output, connect CLK_EN to ground and connect the
SCO/SCO outputs to VCC.
2.8 Stressful Data Patterns
All PLL's are susceptible to stressful data patterns which
can introduce bit errors in the data stream. PLL's are most
sensitive to patterns which have long run lengths of 0's or
1's (low data transition densities for a long period of time).
The GS9025A is designed to operate with low data
transition densities such as the SMPTE 259M pathological
signal (data transition density = 0.05).
2.9 PLL Design Guidelines
The reclocking performance of the GS9025A is primarily
determined by the PLL. Thus, it is important that the system
designer is familiar with the basic PLL design equations.
A model of the GS9025A PLL is shown in Figure 22. The
main components are the phase detector, the VCO, and the
external loop filter components.
Design Note: For DVB-ASI applications having significant
instances of few bit transitions or when only K28.5 idle bits
are transmitted, the wide-band PLL in the GS9025A may
lock at 243MHz being the first 27MHz sideband below
270MHz. In this case, when normal bit density signals are
transmitted, the PLL will correctly lock onto the proper
270MHz carrier.
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GS9025A
2.5.1 Lock Time
PHASE
DETECTOR
+
ΙCP
KPD
VCO
2 π Kƒ
Ns
-
Øo
RLF
CLF2
CLF1
GS9025A
LOOP
FILTER
AMPLITUDE
Øi
Fig. 22 Model of the GS9025A
2.9.1
WZ
Transfer Function
WP2
Fig. 23 Transfer Function Bode Plot
The 3dB bandwidth
approximately:
sC LF1 R LF + 1
Øo
1
------- = ---------------------------------------------------------------- --------------------------------------------------------L
2
L
Øi
⎛
⎞
s C LF1 R LF – --------- + 1 s C LF2 L + s --------+1
⎝
R LF ⎠
R LF
of
the
transfer
function
is
w BW
w BW
w 3dB = ---------------------------------------------------------------------- ≈ -----------2 0.78
w BW ( w BW ⁄ w P2 )
1 – 2 ------------ + --------------------------------w P2
w BW
1 – 2 -----------w P2
Equation 1
N L = ------------------DI CP K ƒ
WBW
FREQUENCY
The transfer function of the PLL is defined as Øo/Øi and can
be approximated as:
where
WP1
and
N is the divider modulus
2.9.2
D is the data density (=0.5 for NRZ data)
Transfer Function Peaking
ICP is the charge pump current in amps
There are two causes of peaking in the PLL transfer function
given by Equation 1.
Kƒ is the VCO gain in Hz/V
The first is the quadratic:
This response has
(wP1,wBW,wP2) where:
1
zero
(wZ)
and
three
2
L
s C LF2 L + s --------- + 1
R LF
poles
which has:
1 w Z = ---------------------C LF1 R LF
1
w o = -------------------C LF2 L
1
w P1 = -------------------------------------L
C LF1 R LF – --------R LF
and
R LF2
Q = R LF ----------L
This response is critically damped for Q = 0.5.
Thus, to avoid peaking:
R LF
w BW = --------L
C LF2 1
- < --R LF -----------2
L
1 w P2 = ---------------------C LF2 R LF
The bode plot for this transfer function is plotted in
Figure 23.
or
1
L
------------------------- -------->4
R LF2 C LF2 R LF
Therefore,
wP2 > 4 wBW
To reduce the high frequency content on the loop filter, keep
wP2 as low as possible.
The second is the zero-pole combination:
s- + 1
-----sC LF1 R LF + 1
wZ
---------------------------------------------------------- = -------------------s-+1
1 -⎞ + 1
--------s ⎛ C LF1 R LF – -------⎝
w P1
R LF ⎠
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This causes lift in the transfer function given by:
2.9.4 SPICE Simulations
More detailed analysis of the GS9025A PLL can be done
using SPICE. A SPICE model of the PLL is shown below:
w P1
1
20 LOG ---------- = 20 LOG --------------------wZ
wZ
1 – ----------w BW
PHII
G1
IN+
To keep peaking to less than 0.05dB:
V1
E1
2 π Kƒ
IN-
Ns
RLF
2.9.3 Selection of Loop Filter Components
1
Based on the above analysis, the loop filter components
should be selected for a given PLL bandwidth, ƒ3dB, as
follows:
CLF1
Fig. 25 SPICE Model of the PLL
2N L = -------------I CP K ƒ
where:
ICP is the charge pump current and is a function of the
RVCO resistor and is obtained from Figure 24.
Kƒ = 90MHz/V for VCO frequencies corresponding to
the ƒL curve.
Kƒ = 140MHz/V for VCO frequencies corresponding to
the ƒH curve.
N is the divider modulus
(ƒL, ƒH and N can be obtained from Table 2 or Table 3)
2. Choose RLF = 2(3.14)ƒ3dB(0.78)L
3. Choose CLF1 = 174L/(RLF)2
4. Choose CLF2 = L/4(RLF)2
CHARGE PUMP CURRENT (µA)
400
350
300
250
200
150
100
50
0
200
CLF2
NOTE: PHII, PHIO, LF, and 1 are node names in the SPICE netlist.
1. Calculate
0
R2
400
600
800
1000
1200
1400
1600
1800
The model consists of a voltage controlled current source
(G1), the loop filter components (RLF, CLF1, and CLF2), a
voltage controlled voltage source (E1), and a voltage
source (V1). R2 is necessary to create a DC path to ground
for Node 1.
V1 is used to generate the input phase waveform. G1
compares the input and output phase waveforms and
generates the charge pump current, ΙCP. The loop filter
components integrate the charge pump current to establish
the loop filter voltage. E1 creates the output phase
waveform (PHIO) by multiplying the loop filter voltage by
the value of the Laplace transform (2πKƒ/Ns).
The net list for the model is given below. The .PARAM
statements are used to set values for ΙCP, Kƒ, N, and D. ΙCP
is determined by the RVCO resistor and is obtained from
Figure 24.
SPICE NETLIST * GS9025A PLL Model
.PARAM ICP = 165E-6 KF= 90E+6
.PARAM N = 1 D = 0.5
.PARAM PI = 3.14
.IC V(Phio) = 0
.ac dec 30 1k 10meg
RLF 1 LF 1000
CLF1 1 0 15n
CLF2 0 LF 15p
E_LAPLACE1 Phio 0 LAPLACE {V(LF)} {(2*PI*KF)/(N*s)}
G1 0 LF VALUE{D * ICP/(2*pi)*V(Phii, Phio)}
V1 2 0 DC 0V AC 1V
R2 0 1 1g
.END
RVCO (Ω)
Fig. 24 RVCO vs. Charge Pump Current
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GS9025A
wZ < 0.0057wBW
PHIO
LF
3. I/O DESCRIPTION
RSOURCE
ZO
DDI
3.1 High Speed Analog Inputs (SDI/SDI)
SDI/SDI are high impedance inputs
differential or single-ended input drive.
which
accept
113
10nF
SDI
75
ZO
Figure 29 shows the recommended interface when the
GS9025A digital inputs are driven single-endedly. In this case,
the input must be AC-coupled and a matching resistor (Zo)
must be used.
GS9025
SDI
DDI
ZO
GS9025
DDI
Fig. 26
3.2 High Speed Digital Inputs (DDI/DDI)
Fig. 29
DDI/DDI are high impedance inputs which accept
differential or single-ended input drive. Two conditions must
be observed when interfacing to these inputs:
1. Input signal amplitudes are between 200 and 2000mV.
When the DDI and the DDI inputs are not used, saturate one
input of the differential amplifier for improved noise immunity.
To saturate, connect either pins 44 and 1 or pins 2 and 3 to
VCC. Leave the other pair floating.
2. The common mode input voltage range is as specified
in the DC Characteristics table.
3.3 High Speed Outputs (SDO/SDO and SCO/SCO)
Commonly used interface examples are shown in Figures
27 to 29.
SDO/SDO and SCO/SCO are current mode outputs that
require external pullup resistors (see Figure 30). To
calculate the output sink current use the following
relationship:
Figure 27 illustrates the simplest interface to the GS9025A
digital inputs. In this example, the driving device generates
the PECL level signals (800mV amplitudes) having a
common mode input range between 0.4V and 4.6V. This
scheme is recommended when the trace lengths are less
than 1in. The value of the resistors depends on the output
driver circuitry.
Output Sink Current = Output Signal Swing / Pullup Resistor
A diode can be placed between Vcc and the pullup resistors to
reduce the common mode voltage by approximately 0.7 volts.
When the output traces are longer than 1in, controlled
impedance traces should be used. The pullup resistors should
be placed at the end of the output traces as they terminate the
trace in its characteristic impedance (75Ω).
VCC
DDI
GS9025
DDI
75
75
75
75
SDO
SDO
GS9025
SCO
SCO
Fig. 27
When trace lengths become greater than 1in, controlled
impedance traces should be used. The recommended
interface is shown in Figure 29. In this case, a parallel
resistor (RLOAD) is placed near the GS9025A inputs to
terminate the controlled impedance trace. The value of
RLOAD should be twice the value of the characteristic
impedance of the trace. In addition, place series resistors
(RSOURCE) near the driving chip to serve as source
terminations. They should be equal to the value of the trace
impedance. Assuming 800mV output swings at the driver,
RLOAD = 100Ω, RSOURCE = 50Ω and ZO = 50Ω.
VCC
Fig. 30 High Speed Outputs with External Pullups
4. OPTIMIZING GS9025A PERFORMANCE
For optimal device performance, implement loop filter
component values for the GS9025A as shown in Table 5.
TABLE 5: Recommended Loop Filter Component Values
COMPONENT
RLF
CLF1
CLF2
GS9025
1kΩ
15nF
5.6pF
GS9025A
1.8kΩ
15nF
3.3pF
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GS9025A
10nF
GS9025
DDI
Fig. 28
Figure 26 shows the recommended interface when a singleended serial digital signal is used.
75
RLOAD
RSOURCE
TYPICAL APPLICATION CIRCUIT
VCC
VCC
VCC VCC
4.7n
10k
VCC VCC
36
35
OEM_TEST
SMPTE
A/D
SSI/CD
LOCK
COSC
VEE
CLK_EN
VCC
31
4
VCC
VEE
30
5
VEE
SCO
29
6
SDI
SCO
28
7
SDI
VEE
27
AUTO/MAN
26
VCC
10n
8
GS9025A
TOP VIEW
VCC
23
12
13
14
15
16
17
18
100p
VCC
1.8k 15n
19
VCC
SS2
CBG
AGC-
RVCO
11
RVCO_RTN
24
VEE
SS1
LF-
CD_ADJ
LFS
10
LF+
25
VEE
SS0
VCC
VEE
AGC+
9
All resistors in ohms,
all capacitors in microfarads,
unless otherwise stated.
Power supply decoupling
capacitors are not shown.
34
VEE
37
VCC
20
21
22
4 x 75 see Note 2
To
GS9020
VCC
}
To LED
Driver
(optional)
VCC
365
(1%)
0.1µ 0.1µ
see Note 3
3.3p
NOTES
1. It is recommended that the DDI/DDI inputs are not driven when the SDI/SDI inputs are being used.
This minimizes crosstalk between the DDI/DDI and SDI/SDI inputs and maximizes performance.
2. These resistors are not needed if the internal pull-up resistors on the GS9020 are used.
3. It is recommended that for new designs VCO components should be returned to the RVCO_RTN pin
for improved ground bounce immunity. If replacing GS9025 with GS9025A connection to ground
can be maintained.
TABLE 6: RVCO = 365, ƒH = 540MHz, ƒL = 360MHz
SMPTE
SS[2:0]
DATA RATE (Mb/s)
LOOP BANDWIDTH (MHz)
1
000
143
1.2
1
001
177
1.9
1
010
270
3.0
1
011
360
4.5
1
100
540
6.0
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GS9025A
38
SDO
3
100k
Pot
(Optional)
39
VCC_75
VCC
VCC
40
32
DDI
75 10n
VCC
41
SDO
2
37.5
42
33
DDI
75
75
43
VEE
1
From
GS9024 see Note 1
44
VCC_75
VCC
PACKAGE DIMENSIONS
13.20 ±0.25
10.00 ±0.10
GS9025A
13.20
±0.25
10.00
±0.10
PIN 1
0.80 BSC
0.45 MAX
0.30 MIN
5˚ to 16˚
0.20 MIN
0˚ MIN
2.20 MAX
1.85 MIN
7˚ MAX
0˚ MIN
2.55 MAX
5˚ to 16˚
0.23
MAX.
0.35 MAX
0.15 MIN
0.3 MAX.
RADIUS
0.88
NOM.
0.13 MIN.
RADIUS
1.60
REF
All dimensions in millimetres
44 pin MQFP
REVISION NOTES:
Corrected input high level for A/D pin.
For latest product information, visit www.gennum.com
DOCUMENT IDENTIFICATION
CAUTION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes at any time to improve reliability, function or design, in order to
provide the best product possible.
GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
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970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
GENNUM JAPAN CORPORATION
Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku,
Shinjuku-ku, Tokyo, 160-0023 Japan
Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505
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25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright June 2000 Gennum Corporation. All rights reserved. Printed in Canada.
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