PD - 94272
IRFR3911
IRFU3911
®
SMPS MOSFET
HEXFET Power MOSFET
Applications
High frequency DC-DC converters
l
VDSS
100V
Benefits
l Low Gate-to-Drain Charge to Reduce
Switching Losses
l Fully Characterized Capacitance Including
Effective COSS to Simplify Design, (See
App. Note AN1001)
l Fully Characterized Avalanche Voltage
and Current
RDS(on) max
ID
0.115Ω
14A
D-Pak
IRFR3911
I-Pak
IRFU3911
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
Units
14
9.5
56
56
0.37
± 20
7.1
-55 to + 175
A
W
W/°C
V
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
Junction-to-Case
Junction-to-Ambient (PCB mount)*
Junction-to-Ambient
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Typ.
Max.
Units
–––
–––
–––
2.7
50
110
°C/W
1
01/22/02
IRFR3911/IRFU3911
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
V(BR)DSS
IDSS
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Min.
100
–––
–––
2.0
–––
–––
–––
–––
Typ.
–––
0.11
–––
–––
–––
–––
–––
–––
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
0.115
Ω
VGS = 10V, ID = 8.4A
4.0
V
VDS = VGS, ID = 250µA
20
VDS = 100V, VGS = 0V
µA
250
VDS = 80V, VGS = 0V, TJ = 150°C
100
VGS = 20V
nA
-100
VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Min.
9.6
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
21
4.3
6.6
7.9
26
52
25
740
110
18
700
61
130
Max. Units
Conditions
–––
S
VDS = 50V, ID = 8.4A
32
ID = 8.4A
6.5
nC
VDS = 80V
9.9
VGS = 10V
–––
VDD = 500V
–––
I
D = 8.4A
ns
–––
RG = 22Ω
–––
VGS = 10V
–––
VGS = 0V
–––
VDS = 25V
–––
pF
ƒ = 1.0MHz
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 80V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 80V
Avalanche Characteristics
Parameter
EAS
IAR
EAR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Typ.
Max.
Units
–––
–––
–––
68
8.4
0.0056
mJ
A
mJ
Diode Characteristics
IS
ISM
VSD
trr
Q rr
ton
2
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
14
––– –––
showing the
A
G
integral reverse
56
––– –––
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 8.4A, VGS = 0V
––– 86 –––
ns
TJ = 25°C, IF = 8.4A
––– 290 –––
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRFR3911/IRFU3911
100
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
10
ID , Drain-to-Source Current (A)
ID , Drain-to-Source Current (A)
TOP
4.5V
1
10
4.5V
1
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
0.1
0.1
0.1
1
10
0.1
100
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
100
Fig 2. Typical Output Characteristics
3.0
100.00
T J = 25°C
I D = 14A
2.5
T J = 175°C
10.00
VDS = 15V
20µs PULSE WIDTH
1.00
3.0
5.0
7.0
9.0
11.0
13.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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15.0
2.0
(Normalized)
R DS(on) , Drain-to-Source On Resistance
ID , Drain-to-Source Current (Α )
10
VDS , Drain-to-Source Voltage (V)
1.5
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
80
TJ , Junction Temperature
100 120 140 160 180
( ° C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFR3911/IRFU3911
10000
12
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
VGS, Gate-to-Source Voltage (V)
C, Capacitance(pF)
Ciss
Coss
100
Crss
7
5
2
10
0
1
10
0
100
10
15
20
25
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100.00
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
5
QG , Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
100
T J = 175°C
10.00
T J = 25°C
1.00
OPERATION IN THIS AREA
LIMITED BY R DS (on)
10
100µsec
1msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
10msec
0.1
0.10
0.0
0.5
1.0
1.5
VSD , Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
V DS = 80V
V DS = 50V
V DS = 20V
10
Coss = Cds + Cgd
1000
ID = 8.4A
2.0
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFR3911/IRFU3911
15
RD
VDS
VGS
12
D.U.T.
RG
+
ID , Drain Current (A)
-VDD
VGS
9
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
6
Fig 10a. Switching Time Test Circuit
VDS
3
90%
0
25
50
75
100
125
TC , Case Temperature
150
175
( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
(Z thJC)
10
D = 0.50
1
Thermal Response
0.20
0.10
0.05
0.1
0.02
0.01
P DM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
0.01
t1/ t
2
J = P DM x Z thJC
+T C
0.1
1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR3911/IRFU3911
120
1 5V
ID
TOP
D R IV E R
D .U .T
RG
+
V
- DD
IA S
20V
96
A
0 .0 1 Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V (B R )D SS
tp
E AS , Single Pulse Avalanche Energy (mJ)
L
VDS
3.4A
5.9A
8.4A
BOTTOM
72
48
24
0
25
50
75
100
125
150
175
( °C)
Starting T , Junction
Temperature
J
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
50KΩ
12V
.2µF
.3µF
QGS
QGD
D.U.T.
VG
+
V
- DS
VGS
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRFR3911/IRFU3911
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
•
•
•
•
RG
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFR3911/IRFU3911
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
2 .3 8 (.0 9 4 )
2 .1 9 (.0 8 6 )
6 .7 3 (.2 6 5 )
6 .3 5 (.2 5 0 )
1 .1 4 (.0 4 5 )
0 .8 9 (.0 3 5 )
-A 1 .2 7 (.0 5 0 )
0 .8 8 (.0 3 5 )
5 .4 6 (.2 1 5 )
5 .2 1 (.2 0 5 )
0 .5 8 (.0 2 3 )
0 .4 6 (.0 1 8 )
4
6 .4 5 (.2 4 5 )
5 .6 8 (.2 2 4 )
6 .2 2 (.2 4 5 )
5 .9 7 (.2 3 5 )
1.0 2 (.0 4 0 )
1.6 4 (.0 2 5 )
1 0 .4 2 (.4 1 0 )
9 .4 0 (.3 7 0 )
1
2
L E A D A S S IG N M E N T S
3
1 - GATE
-B -
1 .5 2 (.0 6 0 )
1 .1 5 (.0 4 5 )
3X
2X
1 .1 4 (.0 4 5 )
0 .7 6 (.0 3 0 )
0 .8 9 (.0 3 5 )
0 .6 4 (.0 2 5 )
0 .2 5 ( .0 1 0 )
2 - D R A IN
0 .5 1 (.0 2 0 )
M IN .
3 - S OU R CE
4 - D R A IN
0 .5 8 (.0 2 3 )
0 .4 6 (.0 1 8 )
M A M B
N O TE S :
2 .2 8 ( .0 9 0 )
1 D IM E N S IO N IN G & T O L E R A N C IN G P E R A N S I Y 1 4 .5 M , 1 9 8 2 .
4 .5 7 ( .1 8 0 )
2 C O N T R O L L IN G D IM E N S IO N : IN C H .
3 C O N F O R M S T O J E D E C O U T L IN E T O -2 5 2 A A .
4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP ,
S O L D E R D IP M A X. + 0 .1 6 (.0 0 6 ) .
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFR120
WITH ASSEMBLY
LOT CODE 1234
ASSEMBLED ON WW 16, 1999
IN T HE AS SEMBLY LINE "A"
PART NUMBER
INT ERNAT IONAL
RECT IFIER
LOGO
916A
12
ASSEMBLY
LOT CODE
8
IRFU120
34
DAT E CODE
YEAR 9 = 1999
WEEK 16
LINE A
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IRFR3911/IRFU3911
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6 .7 3 (.26 5 )
6 .3 5 (.25 0 )
2 .3 8 (.0 9 4 )
2 .1 9 (.0 8 6 )
-A -
0 .5 8 (.0 2 3 )
0 .4 6 (.0 1 8 )
1 .2 7 ( .0 5 0 )
0 .8 8 ( .0 3 5 )
5 .4 6 (.2 1 5 )
5 .2 1 (.2 0 5 )
L E A D A S S IG N M E N T S
1 - GATE
2 - D R A IN
3 - SOURCE
4 - D R A IN
4
6 .4 5 (.2 4 5 )
5 .6 8 (.2 2 4 )
6 .2 2 ( .2 4 5 )
5 .9 7 ( .2 3 5 )
1 .5 2 (.0 6 0 )
1 .1 5 (.0 4 5 )
1
2
3
-B -
N O TE S :
1 D IM E N S IO N IN G & TO L E R A N C IN G P E R A N S I Y 1 4 .5M , 19 8 2 .
2.2 8 (.0 9 0)
1.9 1 (.0 7 5)
2 C O N T R O L L IN G D IM E N S IO N : IN C H .
3 C O N F O R MS TO J E D E C O U T L IN E TO -2 5 2 A A .
9 .6 5 ( .3 8 0 )
8 .8 9 ( .3 5 0 )
4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP ,
S O L D E R D IP M A X. + 0.1 6 (.0 0 6 ).
3X
1 .1 4 (.0 45 )
0 .7 6 (.0 30 )
2 .28 (.0 9 0 )
3X
1 .1 4 ( .0 4 5 )
0 .8 9 ( .0 3 5 )
0 .8 9 (.0 35 )
0 .6 4 (.0 25 )
0 .2 5 (.0 1 0 )
M A M B
2X
0 .5 8 (.0 2 3 )
0 .4 6 (.0 1 8 )
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFR120
WIT H ASSEMBLY
LOT CODE 5678
ASSEMBLED ON WW 19, 1999
IN T HE ASSEMBLY LINE "A"
PART NUMBER
INT ERNAT IONAL
RECT IFIER
LOGO
IRFU120
919A
56
78
DAT E CODE
YEAR 9 = 1999
WEEK 19
LINE A
ASSEMBLY
LOT CODE
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9
IRFR3911/IRFU3911
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .47 6 )
11.9 ( .46 9 )
F E E D D IR E C T IO N
TRL
16 .3 ( .641 )
15 .7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FE E D D IR E C T IO N
N O T ES :
1 . C O N T R O LLIN G D IME N S IO N : M ILL IM ET E R .
2 . A LL D IM EN S IO N S A R E SH O W N IN M ILLIM ET E R S ( IN C H E S ).
3 . O U TL IN E C O N FO R MS T O E IA -481 & E IA -54 1.
1 3 IN C H
16 m m
N O TE S :
1. O U TL IN E C O N F O R M S T O E IA -481 .
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 1.9mH
RG = 25Ω, IAS = 8.4A.
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
ISD ≤ 8.4A, di/dt ≤ 320A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
* When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to application note #AN-994.
10
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