TI MSP430F2002TPWR Mixed signal microcontroller Datasheet

MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
D Low Supply Voltage Range 1.8 V to 3.6 V
D Ultralow Power Consumption
D Brownout Detector
D Serial Onboard Programming,
D
D
D
D
D
D
D
D
D
D
-- Active Mode: 220 μA at 1 MHz, 2.2 V
-- Standby Mode: 0.5 μA
-- Off Mode (RAM Retention): 0.1 μA
Five Power-Saving Modes
Ultrafast Wake-Up From Standby Mode in
Less Than 1 μs
16-Bit RISC Architecture, 62.5 ns
Instruction Cycle Time
Basic Clock Module Configurations:
-- Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies to ±1%
-- Internal Very Low Power LF Oscillator
-- 32-kHz Crystal
-- External Digital Clock Source
16-Bit Timer_A With Two Capture/Compare
Registers
On-Chip Comparator for Analog Signal
Compare Function or Slope A/D
(MSP430x20x1 only)
10-Bit 200-ksps A/D Converter With Internal
Reference, Sample-and-Hold, and Autoscan
(MSP430x20x2 only)
16-Bit Sigma-Delta A/D Converter With
Differential PGA Inputs and Internal
Reference (MSP430x20x3 only)
Universal Serial Interface (USI) Supporting
SPI and I2C
(MSP430x20x2 and MSP430x20x3 only)
D
D
D
No External Programming Voltage Needed
Programmable Code Protection by
Security Fuse
On-Chip Emulation Logic With Spy-Bi-Wire
Interface
Family Members Include:
MSP430F2001: 1KB + 256B Flash Memory
128B RAM
MSP430F2011: 2KB + 256B Flash Memory
128B RAM
MSP430F2002: 1KB + 256B Flash Memory
128B RAM
MSP430F2012: 2KB + 256B Flash Memory
128B RAM
MSP430F2003: 1KB + 256B Flash Memory
128B RAM
MSP430F2013: 2KB + 256B Flash Memory
128B RAM
Available in a 14-Pin Plastic Small-Outline
Thin Package (TSSOP), 14-Pin Plastic Dual
Inline Package (PDIP), and 16-Pin QFN
For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 1μs.
The MSP430x20xx series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer, and ten
I/O pins. In addition the MSP430x20x1 has a versatile analog comparator. The MSP430x20x2 and
MSP430x20x3 have built-in communication capability using synchronous protocols (SPI or I2C), and a 10-bit
A/D converter (MSP430x20x2) or a 16-bit sigma-delta A/D converter (MSP430x20x3).
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data for display or for transmission to a host system. Stand alone RF sensor front end is another
area of application.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2007 Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
AVAILABLE OPTIONS
PACKAGED DEVICES
PLASTIC
14-PIN TSSOP
(PW)
PLASTIC
14-PIN DIP
(N)
PLASTIC
16-PIN QFN
(RSA)
--40°C to 85°C
MSP430F2001IPW
MSP430F2011IPW
MSP430F2002IPW
MSP430F2012IPW
MSP430F2003IPW
MSP430F2013IPW
MSP430F2001IN
MSP430F2011IN
MSP430F2002IN
MSP430F2012IN
MSP430F2003IN
MSP430F2013IN
MSP430F2001IRSA
MSP430F2011IRSA
MSP430F2002IRSA
MSP430F2012IRSA
MSP430F2003IRSA
MSP430F2013IRSA
--40°C to 105°C
MSP430F2001TPW
MSP430F2011TPW
MSP430F2002TPW
MSP430F2012TPW
MSP430F2003TPW
MSP430F2013TPW
MSP430F2001TN
MSP430F2011TN
MSP430F2002TN
MSP430F2012TN
MSP430F2003TN
MSP430F2013TN
MSP430F2001TRSA
MSP430F2011TRSA
MSP430F2002TRSA
MSP430F2012TRSA
MSP430F2003TRSA
MSP430F2013TRSA
TA
device pinout, MSP430x20x1
PW or N PACKAGE
(TOP VIEW)
VCC
1
14
VSS
P1.0/TACLK/ACLK/CA0
2
13
XIN/P2.6/TA1
P1.1/TA0/CA1
3
12
XOUT/P2.7
P1.2/TA1/CA2
4
11
TEST/SBWTCK
P1.3/CAOUT/CA3
5
10
P1.4/SMCLK/CA4/TCK
P1.5/TA0/CA5/TMS
6
9
RST/NMI/SBWTDIO
P1.7/CAOUT/CA7/TDO/TDI
7
8
P1.6/TA1/CA6/TDI/TCLK
NC
VSS
15 14
11
XOUT/P2.7
P1.2/TA1/CA2
3
10
TEST/SBWTCK
P1.3/CAOUT/CA3
4
9
P1.4/SMCLK/CA4/TCK
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6
7
P1.7/CAOUT/CA7/TDO/TDI
2
P1.1/TA0/CA1
P1.6/TA1/CA6/TDI/TCLK
XIN/P2.6/TA1
1
P1.5/TA0/CA5/TMS
12
P1.0/TACLK/ACLK/CA0
NOTE: See port schematics section for detailed I/O information.
2
NC
VCC
RSA PACKAGE
(TOP VIEW)
RST/NMI/SBWTDIO
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
device pinout, MSP430x20x2
PW or N PACKAGE
(TOP VIEW)
VCC
1
14
VSS
P1.0/TACLK/ACLK/A0
2
13
XIN/P2.6/TA1
P1.1/TA0/A1
3
12
XOUT/P2.7
P1.2/TA1/A2
4
11
TEST/SBWTCK
P1.3/ADC10CLK/A3/VREF--/VeREF--
5
10
P1.4/SMCLK/A4/VREF+/VeREF+/TCK
P1.5/TA0/A5/SCLK/TMS
6
9
RST/NMI/SBWTDIO
P1.7/A7/SDI/SDA/TDO/TDI
7
8
P1.6/TA1/A6/SDO/SCL/TDI/TCLK
15 14
AVSS
DVSS
AVCC
DVCC
RSA PACKAGE
(TOP VIEW)
12
XIN/P2.6/TA1
2
11
XOUT/P2.7
P1.2/TA1/A2
3
10
TEST/SBWTCK
P1.3/ADC10CLK/A3/VREF--/VeREF--
4
9
7
RST/NMI/SBWTDIO
P1.7/A7/SDI/SDA/TDO/TDI
6
P1.6/TA1/A6/SDO/SCL/TDI/TCLK
P1.1/TA0/A1
P1.5/TA0/A5/SCLK/TMS
1
P1.4/SMCLK/A4/VREF+/VeREF+/TCK
P1.0/TACLK/ACLK/A0
NOTE: See port schematics section for detailed I/O information.
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MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
device pinout, MSP430x20x3
PW or N PACKAGE
(TOP VIEW)
VCC
1
14
VSS
P1.0/TACLK/ACLK/A0+
2
13
XIN/P2.6/TA1
P1.1/TA0/A0--/A4+
3
12
XOUT/P2.7
P1.2/TA1/A1+/A4--
4
11
TEST/SBWTCK
P1.3/VREF/A1--
5
10
P1.4/SMCLK/A2+/TCK
P1.5/TA0/A2--/SCLK/TMS
6
9
RST/NMI/SBWTDIO
P1.7/A3--/SDI/SDA/TDO/TDI
7
8
P1.6/TA1/A3+/SDO/SCL/TDI/TCLK
AVSS
DVSS
15 14
11
XOUT/P2.7
P1.2/TA1/A1+/A4--
3
10
TEST/SBWTCK
P1.3/VREF/A1--
4
9
P1.4/SMCLK/A2+/TCK
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6
7
P1.7/A3--/SDI/SDA/TDO/TDI
2
P1.1/TA0/A0--/A4+
P1.6/TA1/A3+/SDO/SCL/TDI/TCLK
XIN/P2.6/TA1
1
P1.5/TA0/A2--/SCLK/TMS
12
P1.0/TACLK/ACLK/A0+
NOTE: See port schematics section for detailed I/O information.
4
AVCC
DVCC
RSA PACKAGE
(TOP VIEW)
RST/NMI/SBWTDIO
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
functional block diagram, MSP430x20x1
VCC
VSS
P1.x & JTAG
8
P2.x &
XIN/XOUT
2
XOUT
XIN
Basic Clock
System+
ACLK
SMCLK
MCLK
Flash
RAM
2kB
1kB
128B
128B
Comparator
_A+
8 channel
input mux
Port P1
Port P2
8 I/O
Interrupt
capability,
pull--up/down
resistors
2 I/O
Interrupt
capability,
pull--up/down
resistors
MAB
16MHz
CPU
incl. 16
Registers
MDB
Emulation
(2BP)
JTAG
Interface
Watchdog
WDT+
Brownout
Protection
15/16--Bit
Timer_A2
2 CC
Registers
Spy--Bi Wire
RST/NMI
NOTE: See port schematics section for detailed I/O information.
functional block diagram, MSP430x20x2
VCC
VSS
P1.x & JTAG
8
XIN
P2.x &
XIN/XOUT
2
XOUT
Basic Clock
System+
ACLK
SMCLK
MCLK
16MHz
CPU
incl. 16
Registers
Flash
RAM
2kB
1kB
128B
128B
ADC10
10--bit
8 Channels
Autoscan
DTC
Port P1
Port P2
8 I/O
Interrupt
capability,
pull--up/down
resistors
2 I/O
Interrupt
capability,
pull--up/down
resistors
MAB
MDB
Emulation
(2BP)
JTAG
Interface
Watchdog
WDT+
Brownout
Protection
15/16--Bit
Timer_A2
2 CC
Registers
Spy--Bi Wire
USI
Universal
Serial
Interface
SPI, I2C
RST/NMI
NOTE: See port schematics section for detailed I/O information.
POST OFFICE BOX 655303
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MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
functional block diagram, MSP430x20x3
VCC
VSS
P1.x & JTAG
8
XOUT
XIN
Basic Clock
System+
ACLK
SMCLK
MCLK
16MHz
CPU
incl. 16
Registers
Flash
RAM
2kB
1kB
128B
128B
Port P1
Port P2
8 I/O
Interrupt
capability,
pull--up/down
resistors
2 I/O
Interrupt
capability,
pull--up/down
resistors
SD16_A
16--bit
Sigma-Delta A/D
Converter
MAB
MDB
Emulation
(2BP)
JTAG
Interface
Watchdog
WDT+
Brownout
Protection
15/16--Bit
Timer_A2
2 CC
Registers
Spy--Bi Wire
RST/NMI
NOTE: See port schematics section for detailed I/O information.
6
P2.x &
XIN/XOUT
2
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USI
Universal
Serial
Interface
SPI, I2C
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Terminal Functions, MSP430x20x1
TERMINAL
PW or N
RSA
NO.
NO.
P1.0/TACLK/ACLK/CA0
2
1
I/O
General-purpose digital I/O pin
Timer_A, clock signal TACLK input
ACLK signal ouput
Comparator_A+, CA0 input
P1.1/TA0/CA1
3
2
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output
Comparator_A+, CA1 input
P1.2/TA1/CA2
4
3
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: Out1 output
Comparator_A+, CA2 input
P1.3/CAOUT/CA3
5
4
I/O
General-purpose digital I/O pin
Comparator_A+, output / CA3 input
P1.4/SMCLK/C4/TCK
6
5
I/O
General-purpose digital I/O pin
SMCLK signal output
Comparator_A+, CA4 input
JTAG test clock, input terminal for device programming and test
P1.5/TA0/CA5/TMS
7
6
I/O
General-purpose digital I/O pin
Timer_A, compare: Out0 output
Comparator_A+, CA5 input
JTAG test mode select, input terminal for device programming and test
P1.6/TA1/CA6/TDI/TCLK
8
7
I/O
General-purpose digital I/O pin
Timer_A, compare: Out1 output
Comparator_A+, CA6 input
JTAG test data input or test clock input during programming and test
P1.7/CAOUT/CA7/TDO/TDI†
9
8
I/O
General-purpose digital I/O pin
Comparator_A+, output / CA7 input
JTAG test data output terminal or test data input during programming and
test
XIN/P2.6/TA1
13
12
I/O
Input terminal of crystal oscillator
General-purpose digital I/O pin
Timer_A, compare: Out1 output
XOUT/P2.7
12
11
I/O
Output terminal of crystal oscillator
General-purpose digital I/O pin
RST/NMI/SBWTDIO
10
9
I
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/SBWTCK
11
10
I
Selects test mode for JTAG pins on Port1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
VCC
1
16
Supply voltage
Ground reference
NAME
†
VSS
14
14
NC
NA
13, 15
QFN Pad
NA
Package
Pad
DESCRIPTION
I/O
Not connected
NA
QFN package pad connection to VSS recommended.
TDO or TDI is selected via JTAG instruction.
NOTE: If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
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• DALLAS, TEXAS 75265
7
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Terminal Functions, MSP430x20x2
TERMINAL
PW, or N
RSA
NO.
NO.
P1.0/TACLK/ACLK/A0
2
1
I/O
General-purpose digital I/O pin
Timer_A, clock signal TACLK input
ACLK signal ouput
ADC10 analog input A0
P1.1/TA0/A1
3
2
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output
ADC10 analog input A1
P1.2/TA1/A2
4
3
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: Out1 output
ADC10 analog input A2
P1.3/ADC10CLK/
A3/VREF--/VeREF--
5
4
I/O
General-purpose digital I/O pin
ADC10 conversion clock output
ADC10 analog input A3
Input for negative external reference voltage/negative internal reference
voltage output
P1.4/SMCLK/A4/VREF+/VeREF+/
TCK
6
5
I/O
General-purpose digital I/O pin
SMCLK signal output
ADC10 analog input A4
Input for positive external reference voltage/positive internal reference
voltage output
JTAG test clock, input terminal for device programming and test
P1.5/TA0/A5/SCLK/TMS
7
6
I/O
General-purpose digital I/O pin
Timer_A, compare: Out0 output
ADC10 analog input A5
USI: external clock input in SPI or I2C mode; clock output in SPI mode
JTAG test mode select, input terminal for device programming and test
P1.6/TA1/A6/SDO/SCL/TDI/TCLK
8
7
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1B input, compare: Out1 output
ADC10 analog input A6
USI: Data output in SPI mode; I2C clock in I2C mode
JTAG test data input or test clock input during programming and test
P1.7/A7/SDI/SDA/TDO/TDI†
9
8
I/O
General-purpose digital I/O pin
ADC10 analog input A7
USI: Data input in SPI mode; I2C data in I2C mode
JTAG test data output terminal or test data input during programming and
test
XIN/P2.6/TA1
13
12
I/O
Input terminal of crystal oscillator
General-purpose digital I/O pin
Timer_A, compare: Out1 output
XOUT/P2.7
12
11
I/O
Output terminal of crystal oscillator
General-purpose digital I/O pin
RST/NMI/SBWTDIO
10
9
I
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/SBWTCK
11
10
I
Selects test mode for JTAG pins on Port1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
VCC
1
NA
Supply voltage
VSS
14
NA
Ground reference
NAME
†
DESCRIPTION
I/O
TDO or TDI is selected via JTAG instruction.
NOTE: If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
8
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MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Terminal Functions, MSP430x20x2 (Continued)
TERMINAL
PW, or N
RSA
NO.
NO.
DVCC
NA
16
Digital supply voltage
AVCC
NA
15
Analog supply voltage
DVSS
NA
14
Digital ground reference
AVSS
NA
13
QFN Pad
NA
Package
Pad
NAME
DESCRIPTION
I/O
Analog ground reference
NA
QFN package pad connection to VSS recommended.
Terminal Functions, MSP430x20x3
TERMINAL
PW, or N
RSA
NO.
NO.
P1.0/TACLK/ACLK/A0+
2
1
I/O
General-purpose digital I/O pin
Timer_A, clock signal TACLK input
ACLK signal ouput
SD16_A positive analog input A0
P1.1/TA0/A0--/A4+
3
2
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output
SD16_A negative analog input A0
SD16_A positive analog input A4
P1.2/TA1/A1+/A4--
4
3
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: Out1 output
SD16_A positive analog input A1
SD16_A negative analog input A4
P1.3/VREF/A1--
5
4
I/O
General-purpose digital I/O pin
Input for an external reference voltage/internal reference voltage output
(can be used as mid-voltage)
SD16_A negative analog input A1
P1.4/SMCLK/A2+/TCK
6
5
I/O
General-purpose digital I/O pin
SMCLK signal output
SD16_A positive analog input A2
JTAG test clock, input terminal for device programming and test
P1.5/TA0/A2--/SCLK/TMS
7
6
I/O
General-purpose digital I/O pin
Timer_A, compare: Out0 output
SD16_A negative analog input A2
USI: external clock input in SPI or I2C mode; clock output in SPI mode
JTAG test mode select, input terminal for device programming and test
P1.6/TA1/A3+/SDO/SCL/TDI/TCLK
8
7
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1B input, compare: Out1 output
SD16_A positive analog input A3
USI: Data output in SPI mode; I2C clock in I2C mode
JTAG test data input or test clock input during programming and test
P1.7/A3--/SDI/SDA/TDO/TDI†
9
8
I/O
General-purpose digital I/O pin
SD16_A negative analog input A3
USI: Data input in SPI mode; I2C data in I2C mode
JTAG test data output terminal or test data input during programming and
test
NAME
†
DESCRIPTION
I/O
TDO or TDI is selected via JTAG instruction.
POST OFFICE BOX 655303
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9
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Terminal Functions, MSP430x20x3 (Continued)
TERMINAL
PW, or N
RSA
NO.
NO.
XIN/P2.6/TA1
13
12
I/O
Input terminal of crystal oscillator
General-purpose digital I/O pin
Timer_A, compare: Out1 output
XOUT/P2.7
12
11
I/O
Output terminal of crystal oscillator
General-purpose digital I/O pin
RST/NMI/SBWTDIO
10
9
I
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/SBWTCK
11
10
I
Selects test mode for JTAG pins on Port1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
VCC
1
NA
Supply voltage
VSS
14
NA
Ground reference
DVCC
NA
16
Digital supply voltage
AVCC
NA
15
Analog supply voltage
DVSS
NA
14
Digital ground reference
AVSS
NA
13
Analog ground reference
QFN Pad
NA
Package
Pad
NAME
DESCRIPTION
I/O
NA
QFN package pad connection to VSS recommended.
NOTE: If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
10
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• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g., ADD R4,R5
R4 + R5 ------> R5
Single operands, destination only
e.g., CALL
PC ---->(TOS), R8----> PC
Relative jump, un/conditional
e.g., JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
SYNTAX
EXAMPLE
Register
F F
MOV Rs,Rd
MOV R10,R11
Indexed
F F
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
Symbolic (PC relative)
F F
MOV EDE,TONI
Absolute
F F
MOV &MEM,&TCDAT
OPERATION
R10
----> R11
M(2+R5)----> M(6+R6)
M(EDE) ----> M(TONI)
M(MEM) ----> M(TCDAT)
Indirect
F
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) ----> M(Tab+R6)
Indirect
autoincrement
F
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) ----> R11
R10 + 2----> R10
F
MOV #X,TONI
MOV #45,TONI
Immediate
NOTE: S = source
#45
----> M(TONI)
D = destination
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MSP430x20x1, MSP430x20x2, MSP430x20x3
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operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode AM;
--
All clocks are active
D Low-power mode 0 (LPM0);
--
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 1 (LPM1);
--
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
D Low-power mode 2 (LPM2);
--
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3);
--
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4);
--
12
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh--0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU will
go into LPM4 immediately after power-up.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog Timer+
Flash key violation
PC out-of-range (see Note 1)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG
(see Notes 2 and 4)
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
30
0FFFAh
29
0FFF8h
28
Comparator_A+ (MSP430x20x1 only)
CAIFG (see Note 3)
maskable
0FFF6h
27
Watchdog Timer+
WDTIFG
maskable
0FFF4h
26
Timer_A2
TACCR0 CCIFG (see Note 3)
maskable
0FFF2h
25
Timer_A2
TACCR1 CCIFG.
TAIFG (see Notes 2 and 3)
maskable
0FFF0h
24
0FFEEh
23
0FFECh
22
0FFEAh
21
ADC10 (MSP430x20x2 only)
ADC10IFG (see Note 3)
maskable
SD16_A (MSP430x20x3 only)
SD16CCTL0 SD16OVIFG,
SD16CCTL0 SD16IFG
(see Notes 2 and 3)
maskable
USI
(MSP430x20x2, MSP430x20x3 only)
USIIFG, USISTTIFG
(see Notes 2 and 3)
maskable
0FFE8h
20
I/O Port P2
(two flags)
P2IFG.6 to P2IFG.7
(see Notes 2 and 3)
maskable
0FFE6h
19
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7
(see Notes 2 and 3)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
0FFDEh ... 0FFC0h
15 ... 0, lowest
(see Note 5)
NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h--01FFh) or from
within unused address ranges.
2. Multiple source flags
3. Interrupt flags are located in the module
4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
5. The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
interrupt enable 1 and 2
Address
7
6
0h
5
4
ACCVIE
NMIIE
rw-0
WDTIE:
OFIE:
NMIIE:
ACCVIE:
Address
3
2
1
OFIE
rw-0
0
WDTIE
rw-0
rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer
is configured in interval timer mode.
Oscillator fault enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
6
5
6
5
4
3
2
1
0
01h
interrupt flag register 1 and 2
Address
7
02h
4
3
2
1
NMIIFG
RSTIFG
PORIFG
OFIFG
rw-0
WDTIFG:
OFIFG:
RSTIFG:
PORIFG:
NMIIFG:
Address
rw-(0)
7
6
5
4
3
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
14
rw-(0)
Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC
power-up
Power-On Reset interrupt flag. Set on VCC power-up.
Set via RST/NMI-pin
03h
Legend
rw-1
rw-(1)
0
WDTIFG
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memory organization
MSP430F200x
MSP430F201x
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
1KB Flash
0FFFFh--0FFC0h
0FFFFh--0FC00h
2KB Flash
0FFFFh--0FFC0h
0FFFFh--0F800h
Information memory
Size
Flash
256 Byte
010FFh -- 01000h
256 Byte
010FFh -- 01000h
Size
128 Byte
027Fh -- 0200h
128 Byte
027Fh -- 0200h
16-bit
8-bit
8-bit SFR
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
RAM
Peripherals
flash memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port, or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of 64
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0--n.
Segments A to D are also called information memory.
D Segment A contains calibration data. After reset segment A is protected against programming and erasing.
It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data
is required.
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peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x2xx Family User’s Guide.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally-controlled oscillator
(DCO). The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 μs. The basic
clock module provides the following clock signals:
D Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
DCO Calibration Data (provided from factory in flash info memory segment A)
DCO Frequency
Calibration Register
Size
1 MHz
CALBC1_1MHZ
byte
010FFh
CALDCO_1MHZ
byte
010FEh
8 MHz
12 MHz
16 MHz
Address
CALBC1_8MHZ
byte
010FDh
CALDCO_8MHZ
byte
010FCh
CALBC1_12MHZ
byte
010FBh
CALDCO_12MHZ
byte
010FAh
CALBC1_16MHZ
byte
010F9h
CALDCO_16MHZ
byte
010F8h
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
digital I/O
There is one 8-bit I/O port implemented—port P1—and two bits of I/O port P2:
D
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt condition is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pull-up/pull-down resistor.
WDT+ watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
16
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timer_A2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A2 Signal Connections (MSP43020x1 only)
Input
Pin Number
PW, N
RSA
2 - P1.0
1 - P1.0
2 - P1.0
1 - P1.0
3 - P1.1
2 - P1.1
4 - P1.2
3 - P1.2
Device
Input Signal
Module
Input Name
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
TACLK
INCLK
Module
Block
Timer
Module
Output Signal
Output
Pin Number
PW, N
RSA
NA
TA0
CCI0A
3 - P1.1
2 - P1.1
ACLK (internal)
CCI0B
7 - P1.5
6 - P1.5
VSS
GND
4 - P1.2
3 - P1.2
VCC
VCC
TA1
CCI1A
CAOUT (internal)
CCI1B
VSS
GND
VCC
VCC
CCR0
CCR1
TA0
TA1
8 - P1.6
7 - P1.6
13 - P2.6
12 - P2.6
Timer_A2 Signal Connections (MSP430F20x2, MSP430F20x3)
Input
Pin Number
PW, N
RSA
2 - P1.0
1 - P1.0
Device
Input Signal
Module
Input Name
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
TACLK
INCLK
Module
Block
Timer
Module
Output Signal
Output
Pin Number
PW, N
RSA
NA
2 - P1.0
1 - P1.0
3 - P1.1
2 - P1.1
TA0
CCI0A
3 - P1.1
2 - P1.1
7 - P1.5
6 - P1.5
ACLK (internal)
CCI0B
7 - P1.5
6 - P1.5
VSS
GND
CCR0
TA0
VCC
VCC
4 - P1.2
3 - P1.2
TA1
CCI1A
4 - P1.2
3 - P1.2
8 - P1.6
7 - P1.6
TA1
CCI1B
8 - P1.6
7 - P1.6
VSS
GND
13 - P2.6
12 - P2.6
VCC
VCC
CCR1
TA1
comparator_A+ (MSP430x20x1 only)
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
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USI (MSP430x20x2 and MSP430x20x3 only)
The universal serial interface (USI) module is used for serial data communication and provides the basic
hardware for synchronous communication protocols like SPI and I2C.
ADC10 (MSP430x20x2 only)
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
SD16_A (MSP430x20x3 only)
The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit
sigma-delta core and reference generator. In addition to external analog inputs, internal VCC sense and
temperature sensors are also available.
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peripheral file map
PERIPHERALS WITH WORD ACCESS
ADC10 (MSP430x20x2 only)
ADC control 0
ADC control 1
ADC memory
ADC10CTL0
ADC10CTL1
ADC10MEM
01B0h
01B2h
01B4h
SD16_A (MSP430x20x3 only)
General Control
Channel 0 Control
Interrupt vector word register
Channel 0 conversion memory
SD16CTL
SD16CCTL0
SD16IV
SD16MEM0
0100h
0102h
0110h
0112h
Timer_A
Capture/compare register
Capture/compare register
Timer_A register
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
TACCR1
TACCR0
TAR
TACCTL1
TACCTL0
TACTL
TAIV
0174h
0172h
0170h
0164h
0162h
0160h
012Eh
Flash Memory
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
Watchdog Timer+
Watchdog/timer control
WDTCTL
0120h
PERIPHERALS WITH BYTE ACCESS
ADC10 (MSP430x20x2 only)
Analog enable
ADC10AE
04Ah
SD16_A (MSP430x20x3 only)
Channel 0 Input Control
Analog Enable
SD16INCTL0
SD16AE
0B0h
0B7h
USI
(MSP430x20x2 and
MSP430x20x3 only)
USI control 0
USI control 1
USI clock control
USI bit counter
USI shift register
USICTL0
USICTL1
USICKCTL
USICNT
USISR
078h
079h
07Ah
07Bh
07Ch
Comparator_A+
(MSP430x20x1 only)
Comparator_A+ port disable
Comparator_A+ control 2
Comparator_A+ control 1
CAPD
CACTL2
CACTL1
05Bh
05Ah
059h
Basic Clock System+
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
053h
058h
057h
056h
Port P2
Port P2 resistor enable
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
P2REN
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P1
Port P1 resistor enable
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
027h
026h
025h
024h
023h
022h
021h
020h
Special Function
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
IFG2
IFG1
IE2
IE1
003h
002h
001h
000h
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absolute maximum ratings†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.1 V
Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to VCC+0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, Tstg (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . --55°C to 150°C
Storage temperature, Tstg (programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . --40°C to 85°C
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
is applied to the TEST pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J--STD--020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
recommended operating conditions
MIN
NOM
MAX
UNITS
Supply voltage during program execution, VCC
1.8
3.6
V
Supply voltage during program/erase flash memory, VCC
2.2
3.6
V
Supply voltage, VSS
0
Operating free-air
free air temperature range,
range TA
Processor frequency fSYSTEM (Maximum MCLK frequency)
V
I Version
--40
85
°C
T Version
--40
105
°C
VCC = 1.8 V,
Duty Cycle = 50% ±10%
dc
6
VCC = 2.7 V,
Duty Cycle = 50% ±10%
dc
12
VCC ≥ 3.3 V,
Duty Cycle = 50% ±10%
dc
16
MHz
NOTES: 1. The MSP430 CPU is clocked directly with MCLK.
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
2. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this data
sheet.
Legend:
System Frequency -- MHz
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
6 MHz
1.8 V
2.2 V
2.7 V
3.3 V
3.6 V
Supply Voltage -- V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
Figure 1. Save Operating Area
20
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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
active mode supply current (into VCC) excluding external current (see Notes 1 and 2)
PARAMETER
IAM, 1MHz
IAM, 1MHz
IAM, 4kHz
IAM,100kHz
Active mode (AM)
current (1MHz)
Active mode (AM)
current (1MHz)
Active mode (AM)
current (4kHz)
Active mode (AM)
current (100kHz)
TEST CONDITIONS
TA
fDCO = fMCLK = fSMCLK = 1MHz,
fACLK = 32,768Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
CALBC1 1MHZ
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
VCC
2.2 V
MIN
TYP
MAX
220
270
UNIT
μA
fDCO = fMCLK = fSMCLK = 1MHz,
fACLK = 32,768Hz,
Program executes in RAM,
BCSCTL1 = CALBC1_1MHZ,
CALBC1 1MHZ
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
3V
300
2.2 V
190
370
μA
3V
260
1.2
fMCLK = fSMCLK =
fACLK = 32,768Hz/8 = 4,096Hz,
fDCO = 0Hz,
Program executes in flash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0
-40--85°C
2.2 V
105°C
2.2 V
-40--85°C
3V
105°C
3V
fMCLK = fSMCLK = fDCO(0, 0) ≈ 100kHz,
fACLK = 0Hz
0Hz,
Program executes in flash,
RSELx = 0, DCOx = 0,
CPUOFF = 0,
0 SCG0 = 0
0, SCG1 = 0,
0
OSCOFF = 1
-40--85°C
2.2 V
105°C
2.2 V
-40--85°C
3V
105°C
3V
3
6
μA
1.6
4
7
37
50
60
40
55
μA
65
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V--T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- active mode supply current (into VCC)
4.0
fDCO = 16 MHz
4.0
Active Mode Current -- mA
Active Mode Current -- mA
5.0
3.0
fDCO = 12 MHz
2.0
1.0
fDCO = 8 MHz
TA = 25 °C
2.0
2.0
2.5
3.0
3.5
TA = 25 °C
1.0
VCC = 2.2 V
4.0
0.0
0.0
VCC -- Supply Voltage -- V
Figure 2. Active mode current vs VCC, TA = 25°C
22
VCC = 3 V
TA = 85 °C
fDCO = 1 MHz
0.0
1.5
TA = 85 °C
3.0
POST OFFICE BOX 655303
4.0
8.0
12.0
16.0
fDCO -- DCO Frequency -- MHz
Figure 3. Active mode current vs DCO frequency
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
low power mode supply currents (into VCC) excluding external current (see Notes 1 and 2)
PARAMETER
ILPM0, 1MHz
ILPM0, 100kHz
ILPM2
ILPM3,LFXT1
TEST CONDITIONS
TA
Low-power mode
0 (LPM0) current,
current
see Note 3
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32,768 Hz,
CALBC1 1MHZ
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Low-power mode
0 (LPM0) current,
current
see Note 3
fMCLK = 0 MHz,
fSMCLK = fDCO(0, 0) ≈ 100 kHz,
fACLK = 0 Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 1
Low-power mode
2 (LPM2) current,
current
see Note 4
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
MHz
fACLK = 32,768 Hz,
CALBC1 1MHZ
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
_
CPUOFF = 1,
1 SCG0 = 0
0, SCG1 = 1,
1
OSCOFF = 0
Low-power mode
3 (LPM3) current,
see Note 4
fDCO = fMCLK = fSMCLK = 0 MHz,
MHz
fACLK = 32,768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
2.2 V
ILPM3,VLO
ILPM4
fDCO = fMCLK = fSMCLK = 0MHz,
0MHz
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
MAX
65
80
3V
85
100
2.2 V
37
48
3V
-40--85°C
105°C
-40--85°C
105°C
22V
2.2
3V
41
52
22
29
UNIT
31
25
32
0.7
1.2
25°C
0.7
1.0
1.4
2.3
85°C
22V
2.2
105°C
3
6
-40°C
0.9
1.2
0.9
1.2
1.6
2.8
25°C
3V
105°C
3
7
-40°C
0.4
0.7
0.5
0.7
1.0
1.6
85°C
22V
2.2
105°C
2
5
-40°C
0.5
0.9
0.6
0.9
1.3
1.8
105°C
2.5
6
-40°C
0.1
0.5
25°C
0.1
0.5
0.8
1.5
2
4
25°C
85°C
3V
2 2 V/3 V
2.2
μA
34
-40°C
85°C
Low-power mode
4 (LPM4) current,
current
see Note 5
TYP
μA
25°C
fDCO = fMCLK = fSMCLK = 0 MHz,
MHz
fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
MIN
μA
85°C
Low-power mode
3 current, (LPM3)
see Note 4
VCC
105°C
μA
μA
μA
μA
μA
A
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V--T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
3. Current for brownout and WDT clocked by SMCLK included.
4. Current for brownout and WDT clocked by ACLK included.
5. Current for brownout included.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs -- Ports P1 and P2
PARAMETER
VIT+
VIT--
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC
Positive-going
P
iti
i input
i
t threshold
th h ld
voltage
0.45
0.75
2.2 V
1.00
1.65
3V
1.35
2.25
Negative-going
N
ti
i input
i
t threshold
th h ld
voltage
0.25
0.55
2.2 V
0.55
1.20
3V
0.75
1.65
2.2 V
0.2
1.0
3V
0.3
1.0
Vhys
Input voltage hysteresis (VIT+ -VIT-- )
RPull
Pull-up/pull-down resistor
For pullup: VIN = VSS;
For pulldown: VIN = VCC
CI
Input Capacitance
VIN = VSS or VCC
20
35
50
5
V
VCC
V
V
kΩ
pF
inputs -- Ports P1 and P2
PARAMETER
t(int)
TEST CONDITIONS
Port P1, P2: P1.x to P2.x, External
trigger pulse width to set interrupt
flag, (see Note 1)
External interrupt timing
VCC
2.2 V/3 V
MIN
TYP
MAX
20
UNIT
ns
NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t(int) is met. It may be set even with trigger signals
shorter than t(int).
leakage current -- Ports P1 and P2
PARAMETER
Ilkg(Px.x)
TEST CONDITIONS
High-impedance leakage current
see Notes 1 and 2
VCC
2.2 V/3 V
MIN
TYP
MAX
UNIT
±50
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull-up/pull-down resistor is
disabled.
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs -- Ports P1 and P2
PARAMETER
VOH
VOL
High level output
High-level
voltage
Low level output
Low-level
voltage
TEST CONDITIONS
VCC
MIN
I(OHmax) = --1.5 mA (see Notes 1)
2.2 V
VCC --0.25
VCC
I(OHmax) = --6 mA (see Notes 2)
2.2 V
VCC --0.6
VCC
3V
VCC --0.25
VCC
I(OHmax) = --6 mA (see Notes 2)
3V
VCC --0.6
VCC
I(OLmax) = 1.5 mA (see Notes 1)
2.2 V
VSS
VSS+0.25
I(OLmax) = 6 mA (see Notes 2)
I(OHmax) = --1.5 mA (see Notes 1)
TYP
MAX
UNIT
2.2 V
VSS
VSS+0.6
I(OLmax) = 1.5 mA (see Notes 1)
3V
VSS
VSS+0.25
I(OLmax) = 6 mA (see Notes 2)
3V
VSS
VSS+0.6
V
V
NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum
voltage drop specified.
2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum
voltage drop specified.
output frequency -- Ports P1 and P2
PARAMETER
fPx.y
fPort_CLK
Port output frequency
(with load)
Clock output frequency
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
P1.4/SMCLK, CL = 20 pF, RL = 1 kOhm
(see Note 1 and 2)
2.2 V
10
MHz
3V
12
MHz
P2.0/ACLK, P1.4/SMCLK, CL = 20 pF
(see Note 2)
2.2 V
12
MHz
3V
16
MHz
NOTES: 1. A resistive divider with 2 times 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
VCC = 2.2 V
P1.7
25.0
TA = 25°C
TA = 85°C
20.0
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
I OL -- Typical Low-Level Output Current -- mA
I OL -- Typical Low-Level Output Current -- mA
30.0
VCC = 3 V
P1.7
40.0
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
0.5
VOL -- Low-Level Output Voltage -- V
2.0
2.5
3.0
3.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
0.0
VCC = 2.2 V
P1.7
I OH -- Typical High-Level Output Current -- mA
I OH -- Typical High-Level Output Current -- mA
1.5
Figure 5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
--5.0
--10.0
--15.0
TA = 85°C
--20.0
TA = 25°C
0.5
1.0
1.5
2.0
2.5
VCC = 3 V
P1.7
--10.0
--20.0
--30.0
TA = 85°C
--40.0
TA = 25°C
--50.0
0.0
0.5
1.0
1.5
Figure 6
Figure 7
NOTE: One output loaded at a time.
POST OFFICE BOX 655303
2.0
2.5
3.0
VOH -- High-Level Output Voltage -- V
VOH -- High-Level Output Voltage -- V
26
1.0
VOL -- Low-Level Output Voltage -- V
Figure 4
--25.0
0.0
TA = 25°C
• DALLAS, TEXAS 75265
3.5
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
VCC(start)
(see Figure 8)
dVCC/dt ≤ 3 V/s
V(B_IT--)
(see Figure 8 through Figure 10)
dVCC/dt ≤ 3 V/s
Vhys(B_IT--)
(see Figure 8)
dVCC/dt ≤ 3 V/s
td(BOR)
(see Figure 8)
t(reset)
Pulse length needed at RST/NMI pin
to accepted reset internally
VCC
MIN
TYP
MAX
0.7 × V(B_IT--)
70
2.2 V/3 V
2
130
UNIT
V
1.71
V
210
mV
2000
μs
μs
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT--)
+ Vhys(B_IT--) is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT--) + Vhys(B_IT--). The default
DCO settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency.
VCC
Vhys(B_IT--)
V(B_IT--)
VCC(start)
1
0
t d(BOR)
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- POR/brownout reset (BOR)
VCC
3V
VCC(drop) -- V
2
VCC = 3 V
Typical Conditions
1.5
t pw
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
tpw -- Pulse Width -- μs
1 ns
tpw -- Pulse Width -- μs
Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
3V
VCC(drop) -- V
VCC = 3 V
1.5
t pw
Typical Conditions
1
VCC(drop)
0.5
0
0.001
tf = tr
1
1000
tf
tr
tpw -- Pulse Width -- μs
tpw -- Pulse Width -- μs
Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
D DCO control bits DCOx have a step size as defined by parameter SDCO.
D Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal
to:
f average =
32 × f DCO(RSEL,DCO) × f DCO(RSEL,DCO+1)
MOD × f DCO(RSEL,DCO)+(32−MOD) × f DCO(RSEL,DCO+1)
DCO frequency
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
RSELx < 14
1.8
3.6
V
RSELx = 14
2.2
3.6
V
Vcc
Supply voltage range
3.0
3.6
V
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
2.2 V/3 V
0.06
0.14
MHz
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
2.2 V/3 V
0.07
0.17
MHz
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
2.2 V/3 V
0.10
0.20
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
2.2 V/3 V
0.14
0.28
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
2.2 V/3 V
0.20
0.40
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
0.28
0.54
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
2.2 V/3 V
0.39
0.77
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
2.2 V/3 V
0.54
1.06
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
2.2 V/3 V
0.80
1.50
MHz
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
2.2 V/3 V
1.10
2.10
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
2.2 V/3 V
1.60
3.00
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
2.2 V/3 V
2.50
4.30
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
2.2 V/3 V
3.00
5.50
MHz
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
2.2 V/3 V
4.30
7.30
MHz
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
2.2 V/3 V
6.00
9.60
MHz
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
2.2 V/3 V
8.60
13.9
MHz
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
12.0
18.5
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
16.0
26.0
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
2.2 V/3 V
SDCO
Frequency step between
tap DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
2.2 V/3 V
1.05
1.08
1.12
Measured at P1.4/SMCLK
2.2 V/3 V
40
50
60
RSELx = 15
Duty Cycle
1.55
ratio
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
%
29
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies -- tolerance at calibration
PARAMETER
TEST CONDITIONS
Frequency tolerance at calibration
TA
VCC
MIN
TYP
MAX
UNIT
25°C
3V
--1
±0.2
+1
%
25°C
3V
0.990
1
1.010
MHz
fCAL(1MHz)
1MHz calibration value
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
fCAL(8MHz)
8MHz calibration value
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
25°C
3V
7.920
8
8.080
MHz
fCAL(12MHz)
12MHz calibration value
BCSCTL1= CALBC1_12MHZ
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
25°C
3V
11.88
12
12.12
MHz
fCAL(16MHz)
16MHz calibration value
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
25°C
3V
15.84
16
16.16
MHz
MIN
MAX
UNIT
calibrated DCO frequencies -- tolerance over temperature 0°C -- +85°C
TA
VCC
1 MHz tolerance over temperature
PARAMETER
0--85°C
3.0 V
--2.5
±0.5
+2.5
%
8 MHz tolerance over temperature
0--85°C
3.0 V
--2.5
±1.0
+2.5
%
12 MHz tolerance over temperature
0--85°C
3.0 V
--2.5
±1.0
+2.5
%
16 MHz tolerance over temperature
0--85°C
3.0 V
--3.0
±2.0
+3.0
%
2.2 V
0.970
1
1.030
MHz
3.0 V
0.975
1
1.025
MHz
3.6 V
0.970
1
1.030
MHz
2.2 V
7.760
8
8.400
MHz
3.0 V
7.800
8
8.200
MHz
3.6 V
7.600
8
8.240
MHz
2.2 V
11.70
12
12.30
MHz
3.0 V
11.70
12
12.30
MHz
3.6 V
11.70
12
12.30
MHz
3.0 V
15.52
16
16.48
MHz
3.6 V
15.00
16
16.48
MHz
fCAL(1MHz)
fCAL(8MHz)
fCAL(12MHz)
fCAL(16MHz)
30
1MHz calibration value
8MHz calibration value
12MHz calibration value
16MHz calibration value
TEST CONDITIONS
BCSCTL1= CALBC1_1MHZ
CALBC1 1MHZ
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
BCSCTL1= CALBC1_8MHZ
CALBC1 8MHZ
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
0--85°C
0
85 C
0--85°C
0
85 C
BCSCTL1= CALBC1_12MHZ
CALBC1 12MHZ
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
0--85°C
0
85 C
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
CALDCO 16MHZ
Gating time: 2ms
0 85°C
0--85°C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYP
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies -- tolerance over supply voltage VCC
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
UNIT
1 MHz tolerance over VCC
25°C
1.8 V -- 3.6 V
--3
±2
+3
%
8 MHz tolerance over VCC
25°C
1.8 V -- 3.6 V
--3
±2
+3
%
12 MHz tolerance over VCC
25°C
2.2 V -- 3.6 V
--3
±2
+3
%
16 MHz tolerance over VCC
25°C
3.0 V -- 3.6 V
--3
±2
+3
%
25°C
1.8 V -- 3.6 V
0.970
1
1.030
MHz
fCAL(1MHz)
1MHz calibration value
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
fCAL(8MHz)
8MHz calibration value
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
25°C
1.8 V -- 3.6 V
7.760
8
8.240
MHz
fCAL(12MHz)
12MHz calibration value
BCSCTL1= CALBC1_12MHZ
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
25°C
2.2 V -- 3.6 V
11.64
12
12.36
MHz
fCAL(16MHz)
16MHz calibration value
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
25°C
3.0 V -- 3.6 V
15.00
16
16.48
MHz
TA
VCC
MIN
MAX
UNIT
1 MHz tolerance overall
I: -40--85°C
T: -40--105°C
1.8 V -- 3.6 V
--5
±2
+5
%
8 MHz tolerance overall
I: -40--85°C
T: -40--105°C
1.8 V -- 3.6 V
--5
±2
+5
%
12 MHz tolerance overall
I: -40--85°C
T: -40--105°C
2.2 V -- 3.6 V
--5
±2
+5
%
16 MHz tolerance overall
I: -40--85°C
T: -40--105°C
3.0 V -- 3.6 V
--6
±3
+6
%
calibrated DCO frequencies -- overall tolerance
PARAMETER
TEST CONDITIONS
TYP
fCAL(1MHz)
1MHz calibration value
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
I: -40--85°C
T: -40--105°C
1.8 V -- 3.6 V
0.950
1
1.050
MHz
fCAL(8MHz)
8MHz calibration value
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
I: -40--85°C
T: -40--105°C
1.8 V -- 3.6 V
7.600
8
8.400
MHz
fCAL(12MHz)
12MHz calibration value
BCSCTL1= CALBC1_12MHZ
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
I: -40--85°C
T: -40--105°C
2.2 V -- 3.6 V
11.40
12
12.60
MHz
fCAL(16MHz)
16MHz calibration value
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
I: -40--85°C
T: -40--105°C
3.0 V -- 3.6 V
15.00
16
17.00
MHz
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- calibrated 1MHz DCO frequency
1.03
1.02
VCC = 1.8 V
Frequency -- MHz
1.01
1.00
VCC = 2.2 V
VCC = 3.0 V
0.99
0.98
VCC = 3.6 V
0.97
--50.0
--25.0
0.0
25.0
50.0
75.0
100.0
TA -- Temperature -- °C
Figure 11. Calibrated 1 MHz Frequency vs. Temperature
1.03
Frequency -- MHz
1.02
1.01
TA = 105 °C
TA = 85 °C
1.00
TA = 25 °C
0.99
TA = --40 °C
0.98
0.97
1.5
2.0
2.5
3.0
VCC -- Supply Voltage -- V
3.5
4.0
Figure 12. Calibrated 1 MHz Frequency vs. VCC
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
wake-up from lower power modes (LPM3/4)
PARAMETER
tDCO,LPM3/4
tCPU,LPM3/4
TEST CONDITIONS
DCO clock wake-up time from
LPM3/4
(see Note 1)
VCC
MIN
TYP
MAX
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
2.2 V/3 V
2
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
2.2 V/3 V
1.5
BCSCTL1= CALBC1_12MHZ
DCOCTL = CALDCO_12MHZ
2.2 V/3 V
1
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
3V
1
UNIT
μs
s
CPU wake-up time from LPM3/4
(see Note 2)
1/fMCLK +
tClock,LPM3/4
NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g. port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
2. Parameter applicable only if DCOCLK is used for MCLK.
typical characteristics -- DCO clock wake-up time from LPM3/4
DCO Wake Time -- us
10.00
RSELx = 0...11
1.00
0.10
0.10
RSELx = 12...15
1.00
10.00
DCO Frequency -- MHz
Figure 13. DCO wake-up time from LPM3 vs DCO frequency
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, low frequency modes (see Note 4)
PARAMETER
TEST CONDITIONS
VCC
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
XTS = 0, LFXT1Sx = 0 or 1
1.8 V -- 3.6 V
fLFXT1,LF,logic
LFXT1 oscillator logic level
square wave input frequency,
LF mode
XTS = 0, LFXT1Sx = 3
1.8 V -- 3.6 V
Oscillation Allowance for LF
crystals
OALF
Integrated effective Load
Capacitance LF mode
Capacitance,
(see Note 1)
CL,eff
MIN
TYP
MAX
32,768
10,000
32,768
UNIT
Hz
50,000
Hz
XTS = 0, LFXT1Sx = 0;
fLFXT1,LF = 32,768 kHz,
CL,eff = 6 pF
500
kΩ
XTS = 0, LFXT1Sx = 0;
fLFXT1,LF = 32,768 kHz,
CL,eff = 12 pF
200
kΩ
XTS = 0, XCAPx = 0
1
pF
XTS = 0, XCAPx = 1
5.5
pF
XTS = 0, XCAPx = 2
8.5
pF
XTS = 0, XCAPx = 3
11
pF
Duty Cycle
LF mode
XTS = 0, Measured at
P1.4/ACLK,
fLFXT1,LF = 32,768 Hz
fFault,LF
Osc. fault frequency threshold,
LF mode (see Note 3)
XTS = 0, LFXT1Sx = 3
(see Note 2)
2.2 V/3 V
30
2.2 V/3 V
10
50
70
%
10,000
Hz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep as short of a trace as possible between the device and the crystal.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
----
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
internal very low power, low frequency oscillator (VLO)
PARAMETER
TEST CONDITIONS
TA
VCC
-40--85°C
2.2 V/3 V
105°C
2.2 V/3 V
fVLO
VLO frequency
dfVLO/dT
VLO frequency
temperature drift
(see Note 1)
I: -40--85°C
T: -40--105°C
2.2 V/3 V
dfVLO/dVCC
VLO frequency supply
voltage drift
(see Note 2)
25°C
1.8V -- 3.6V
MIN
TYP
MAX
4
12
20
NOTES: 1. Calculated using the box method:
I Version: (MAX(--40...85_C) -- MIN(--40...85_C))/MIN(--40...85_C)/(85_C -- (--40_C))
T Version: (MAX(--40...105_C) -- MIN(--40...105_C))/MIN(--40...105_C)/(105_C -- (--40_C))
2. Calculated using the box method: (MAX(1.8...3.6V) -- MIN(1.8...3.6V))/MIN(1.8...3.6V)/(3.6V -- 1.8V)
34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
22
UNIT
kHz
0.5
%/°C
4
%/V
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETER
TEST CONDITIONS
fTA
Timer A clock frequency
Timer_A
Internal: SMCLK, ACLK;
External: TACLK,
TACLK INCLK;
Duty Cycle = 50% ±10%
tTA,cap
Timer_A, capture timing
TA0, TA1
VCC
MIN
TYP
MAX
2.2 V
10
3V
16
2.2 V/3 V
UNIT
MHz
20
ns
USI, Universal Serial Interface (MSP430x20x2, MSP430x20x3 only)
PARAMETER
TEST CONDITIONS
fUSI
USI clock frequency
External: SCLK;
Duty Cycle = 50% ±10%;
SPI Slave Mode
VOL,I2C
Low-level output voltage on SDA
and SCL
USI module in I2C mode
I(OLmax) = 1.5 mA
VCC
MIN
TYP
MAX
2.2 V
10
3V
16
2.2 V/3 V
VSS
UNIT
MHz
VSS+0.4
V
typical characteristics -- USI low-level output voltage on SDA and SCL (MSP430x20x2, MSP430x20x3 only)
5.0
5.0
TA = 25°C
4.0
3.0
TA = 85°C
2.0
1.0
0.0
0.0
0.2
TA = 25°C
VCC = 3 V
0.4
0.6
0.8
1.0
I OL -- Low-Level Output Current -- mA
I OL -- Low-Level Output Current -- mA
VCC = 2.2 V
4.0
2.0
1.0
0.0
0.0
VOL -- Low-Level Output Voltage -- V
Figure 14. USI Low-Level Output Voltage vs.
Output Current
POST OFFICE BOX 655303
TA = 85°C
3.0
0.2
0.4
0.6
0.8
1.0
VOL -- Low-Level Output Voltage -- V
Figure 15. USI Low-Level Output Voltage vs.
Output Current
• DALLAS, TEXAS 75265
35
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x1 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted)
Comparator_A+ (see Note 1, MSP430x20x1 only)
PARAMETER
TEST CONDITIONS
I(DD)
CAON 1 CARSEL=0,
CAON=1,
CARSEL 0 CAREF=0
CAREF 0
I(Refladder/RefDiode)
CAON=1, CARSEL=0,
CAREF 1/2/3
CAREF=1/2/3,
no load at P1.0/CA0 and P1.1/CA1
V(IC)
V(Ref025)
V(Ref050)
Common-mode input
voltage
Voltage @ 0.25 V
V
Voltage @ 0.5V
V
CC
CC
CC
node
CC
node
VCC
MIN
TYP
MAX
2.2 V
25
40
3V
45
60
2.2 V
30
50
3V
45
71
CAON=1
2.2 V/3 V
0
VCC --1
PCA0=1, CARSEL=1, CAREF=1,
no load at P1.0/CA0 and P1.1/CA1
2.2 V/3 V
0.23
0.24
0.25
PCA0=1, CARSEL=1, CAREF=2,
no load at P1.0/CA0 and P1.1/CA1
2.2 V/3 V
0.47
0.48
0.5
2.2 V
390
480
540
3V
400
490
550
UNIT
μA
μA
V
V(RefVT)
(see Figure 19 and Figure 20)
PCA0=1, CARSEL=1, CAREF=3,
no load at P1.0/CA0
P1 0/CA0 and P1
P1.1/CA1,
1/CA1
TA = 85°C
V(offset)
Offset voltage
See Note 2
2.2 V/3 V
--30
30
mV
Vhys
Input hysteresis
CAON=1
2.2 V/3 V
0
0.7
1.4
mV
2.2 V
80
165
300
3V
70
120
240
t(response)
Response time
(low--high and high--low)
TA = 25°C, Overdrive 10 mV,
Without filter: CAF=0
(see Note 3, Figure 16 and
Figure 17)
mV
ns
TA = 25°C, Overdrive 10 mV,
2.2 V
1.4
1.9
2.8
With filter: CAF=1
μs
(see Note 3, Figure 16 and
3V
0.9
1.5
2.2
Figure 17)
NOTES: 1. The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.
The two successive measurements are then summed together.
3. Response time measured at P1.3/CAOUT.
36
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x1 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
0V
VCC
0
1
CAF
CAON
To Internal
Modules
Low Pass Filter
+
_
V+
V--
0
0
1
1
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 μs
Figure 16. Block Diagram of Comparator_A+ Module
VCAOUT
Overdrive
V-400 mV
t(response)
V+
Figure 17. Overdrive Definition
CASHORT
CA0
CA1
1
VIN
+
--
IOUT = 10μA
Comparator_A+
CASHORT = 1
Figure 18. Comparator_A+ Short Resistance Test Condition
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
37
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x1 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
typical characteristics -- Comparator_A+ (MSP430x20x1 only)
650
650
VCC = 2.2 V
600
V(REFVT) -- Reference Volts --mV
V(REFVT) -- Reference Volts --mV
VCC = 3 V
Typical
550
500
450
400
--45
--25
--5
15
35
55
75
95
600
Typical
550
500
450
400
--45
115
--25
--5
15
Short Resistance -- kOhms
100.00
VCC = 1.8V
VCC = 2.2V
VCC = 3.0V
VCC = 3.6V
1.00
0.0
0.2
0.4
0.6
0.8
VIN/VCC -- Normalized Input Voltage -- V/V
1.0
Figure 21. Short Resistance vs VIN/VCC
38
55
75
95
115
Figure 20. V(RefVT) vs Temperature, VCC = 2.2 V
Figure 19. V(RefVT) vs Temperature, VCC = 3 V
10.00
35
TA -- Free-Air Temperature -- °C
TA -- Free-Air Temperature -- °C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
10-bit ADC, power supply and input range conditions (see Note 1, MSP430x20x2 only)
PARAMETER
TEST CONDITIONS
TA
VCC
VCC
Analog supply voltage
range
VSS = 0 V
VAx
Analog input voltage range
(see Note 2)
All Ax terminals.
Analog inputs selected in
ADC10AE register.
ADC10 supply current
(see Note 3)
fADC10CLK = 5.0 MHz
ADC10ON = 1, REFON = 0
ADC10SHT0 = 1,
1
ADC10SHT1 = 0, ADC10DIV
=0
I: -40--85°C
40 85 C
T: -40--105°C
fADC10CLK = 5.0 MHz
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
I: -40--85°C
T: -40--105°C
fADC10CLK = 5.0 MHz
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
I: -40--85°C
T: -40--105°C
3V
-40--85°C
2.2 V/3 V
105°C
2.2 V/3 V
-40--85°C
2.2 V/3 V
105°C
2.2 V/3 V
IADC10
IREF+
Reference supply current,
reference buffer disabled
(see Note 4)
fADC10CLK = 5.0 MHz
ADC10ON = 0,
1, REF2
REF2_5V
REFON = 1
5V = 0
0,
REFOUT = 1,
ADC10SR=0
Reference buffer supply
current with ADC10SR=1
ADC10SR 1
(see Note 4)
fADC10CLK = 5.0 MHz
ADC10ON = 0,
REFON = 1,
REF2_5V = 0,
REFOUT = 1,
ADC10SR=1
CI
Input capacitance
Only one terminal Ax selected
at a time
I: -40--85°C
T: -40--105°C
RI
Input MUX ON resistance
0V ≤ VAx ≤ VCC
I: -40--85°C
T: -40--105°C
IREFB,1
NOTES: 1.
2.
3.
4.
TYP
MAX
UNIT
2.2
3.6
V
0
VCC
V
0.52
1.05
mA
3V
0.6
1.2
2.2 V/3 V
mA
0 25
0.25
Reference buffer supply
current with ADC10SR=0
ADC10SR 0
(see Note 4)
IREFB,0
2.2 V
MIN
2.2 V/3 V
0.4
04
mA
1.1
0.5
1.4
mA
1.8
mA
0.7
mA
0.8
mA
27
pF
2000
Ω
The leakage current is defined in the leakage current table with Px.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR-- for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
39
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
10-bit ADC, built-in voltage reference (MSP430x20x2 only)
PARAMETER
VCC,REF+
TEST CONDITIONS
Positive
P
iti built-in
b ilt i reference
f
analog
l
supply voltage range
VREF+
Positi e b
Positive
built-in
ilt in reference voltage
oltage
ILD,VREF+
Ma im m VREF+ load current
Maximum
c rrent
VCC
IVREF+ ≤ 1mA, REF2_5V=0
2.2
IVREF+ ≤ 0.5mA, REF2_5V=1
2.8
IVREF+ ≤ 1mA, REF2_5V=1
2.9
VREF+ load regulation
reg lation response time
UNIT
V
2.2 V/3 V
1.41
1.5
1.59
V
3V
2.35
2.5
2.65
V
±0.5
mA
3V
±1
IVREF+ = 500 μA +/-- 100 μA
Analog input voltage VAx ≈ 0.75 V;
REF2_5V = 0
2.2 V/3 V
±2
LSB
IVREF+ = 500 μA ± 100 μA
Analog input voltage VAx ≈ 1.25 V;
REF2_5V = 1
3V
±2
LSB
ADC10SR = 0
3V
400
ADC10SR = 1
3V
2000
100
IVREF+ =
100μA→900μA,
0 5 x VREF+
VAx ≈ 0.5
Error of conversion
result ≤ 1 LSB
ns
Max. capacitance at pin VREF+
(see Note 1)
IVREF+ ≤ ±1mA,
REFON = 1, REFOUT = 1
2.2 V/3 V
TCREF+
Temperature coefficient
IVREF+ = const. with
0 mA ≤ IVREF+ ≤ 1 mA
2.2 V/3 V
tREFON
Settling time of internal reference
voltage (see Note 2)
IVREF+ = 0.5 mA, REF2_5V=0
REFON = 0 → 1
Settling time of reference buffer
(see Note 2)
MAX
IVREF+ ≤ IVREF+max, REF2_5V = 0
CVREF+
tREFBURST
TYP
IVREF+ ≤ IVREF+max, REF2_5V = 1
2.2 V
VREF+ load regulation
reg lation
MIN
pF
±100 ppm/°C
3.6 V
30
IVREF+ = 0.5 mA,
REF2
5V=0,
REF2_5V=0,
REFON = 1,
REFBURST = 1
ADC10SR = 0
2.2 V
1
ADC10SR = 1
2.2 V
2.5
IVREF+ = 0.5 mA,
REF2
5V=1,
REF2_5V=1,
REFON = 1,
REFBURST = 1
ADC10SR = 0
3V
2
ADC10SR = 1
3V
4.5
μs
μs
s
NOTES: 1. The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/VREF+/VeREF+ (REFOUT=1),
must be limited; the reference buffer may become unstable otherwise.
2. The condition is that the error in a conversion started after tREFON or tRefBuf is less than ±0.5 LSB.
40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
10-bit ADC, external reference (see Note 1, MSP430x20x2 only)
PARAMETER
VeREF+
TEST CONDITIONS
Positive external reference input
voltage range (see Note 2)
UNIT
V
VeREF-- ≤ VeREF+ ≤ VCC -- 0.15V
SREF1 = 1, SREF0 = 1 (see Note 3)
1.4
3.0
V
0
1.2
V
1.4
VCC
V
∆VeREF
Differential external reference input
voltage range
∆VeREF = VeREF+ -- VeREF--
VeREF+ > VeREF-- (see Note 5)
Static input current into VeREF--
MAX
VCC
VeREF+ > VeREF--
IVeREF--
TYP
1.4
Negative external reference input
voltage range (see Note 4)
Static input current into VeREF+
MIN
VeREF+ > VeREF-SREF1 = 1, SREF0 = 0
VeREF--
IVeREF+
VCC
0V ≤ VeREF+ ≤ VCC,
SREF1 = 1, SREF0 = 0
2.2 V/3 V
±1
μA
0V ≤VeREF+ ≤ VCC -- 0.15V ≤ 3V
SREF1 = 1, SREF0 = 1 (see Note 3)
2.2 V/3 V
0
μA
0V ≤ VeREF-- ≤ VCC
2.2 V/3 V
±1
μA
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer
supply current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
4. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
5. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied
with reduced accuracy requirements.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
41
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
10-bit ADC, timing parameters (MSP430x20x2 only)
PARAMETER
TEST CONDITIONS
For specified
performance of
ADC10 linearity
parameters
fADC10CLK
ADC10 inp
inputt clock frequency
freq enc
fADC10OSC
ADC10 built-in oscillator frequency
tCONVERT
tADC10ON
Con ersion time
Conversion
VCC
MIN
MAX
UNIT
ADC10SR = 0
2.2 V/3 V
0.45
6.3
ADC10SR = 1
2.2 V/3 V
0.45
1.5
ADC10DIVx=0, ADC10SSELx = 0
fADC10CLK = fADC10OSC
2.2 V/3 V
3.7
6.3
MHz
ADC10 built-in oscillator,
ADC10SSELx = 0
fADC10CLK = fADC10OSC
2.2 V/3 V
2.06
3.51
μs
MH
MHz
13×
ADC10DIV×
1/fADC10CLK
fADC10CLK from ACLK, MCLK or
SMCLK: ADC10SSELx ≠ 0
Turn on settling time of the ADC
TYP
(see Note 1)
μs
100
ns
NOTES: 1. The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
10-bit ADC, linearity parameters (MSP430x20x2 only)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
EI
Integral linearity error
2.2 V/3 V
±1
LSB
ED
Differential linearity error
2.2 V/3 V
±1
LSB
EO
Offset error
±1
LSB
EG
Gain error
2.2 V/3 V
±1.1
±2
LSB
ET
Total unadjusted error
2.2 V/3 V
±2
±5
LSB
42
Source impedance RS < 100 Ω,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2.2 V/3 V
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
10-bit ADC, temperature sensor and built-in VMID (MSP430x20x2 only)
PARAMETER
ISENSOR
Temperature sensor supply
current (see Note 1)
VSensor
REFON = 0, INCHx = 0Ah,
TA = 25_C
ADC10ON = 1, INCHx = 0Ah
(see Note 2)
TCSENSOR
VOffset,Sensor
TEST CONDITIONS
Sensor offset voltage
Sensor output voltage
(see Note 3)
VCC
MIN
TYP
MAX
UNIT
2.2 V
40
120
3V
60
160
3.55
3.66
mV/°C
100
mV
mV
2.2 V/3 V
ADC10ON = 1, INCHx = 0Ah
(see Note 2)
3.44
--100
Temperature sensor voltage
at TA = 105°C (T Version only)
2.2 V/3 V
1265
1365
1465
Temperature sensor voltage
at TA = 85°C
2.2 V/3 V
1195
1295
1395
Temperature sensor voltage
at TA = 25°C
2.2 V/3 V
985
1085
1185
Temperature sensor voltage
at TA = 0°C
2.2 V/3 V
895
995
1095
2.2 V/3 V
30
tSensor(sample)
Sample time required if
channel 10 is selected (see
Note 4)
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
Current into divider at channel
11 (see Note 5)
ADC10ON = 1
1, INCHx = 0Bh
0Bh,
VMID
VCC divider at channel 11
ADC10ON = 1, INCHx = 0Bh,
VMID is ≈0.5 x VCC
2.2 V
1.06
1.1
1.14
3V
1.46
1.5
1.54
tVMID(sample)
Sample time required if
channel 11 is selected (see
Note 6)
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V
1400
3V
1220
μA
A
mV
μs
2.2 V
NA
3V
NA
μA
A
V
ns
NOTES: 1. The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON=1 and INCH=0Ah and sample signal
is high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature
sensor input (INCH = 0Ah).
2. The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
3. Values are not based on calculations using TCSensor or VOffset,sensor but on measurements.
4. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
5. No additional current is needed. The VMID is used during sampling.
6. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
43
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted)
SD16_A, power supply and recommended operating conditions (MSP430x20x3 only)
PARAMETER
AVCC
Analog supply voltage range
TEST CONDITIONS
TA
AVCC = DVCC = VCC
AVSS = DVSS = VSS = 0V
SD16LP = 0,
fSD16 = 1 MHz,
MHz
SD16OSR = 256
Analog supply current
including internal reference
TYP
GAIN 1
GAIN:
GAIN 32
GAIN:
fSD16
SD16 input clock frequency
SD16LP = 0
(Low power mode disabled)
fSD16
SD16 input clock frequency
SD16LP = 1
(Low power mode enabled)
730
105°C
-40--85°C
105°C
810
3V
V
1050
1150
1300
1160
105°C
μA
A
1700
1850
-40--85°C
-40--85°C
UNIT
1170
-40--85°C
105°C
MAX
3.6
-40--85°C
GAIN 4
GAIN:
4,8,16
8 16
GAIN 32
GAIN:
SD16LP = 1,
fSD16 = 0
0.5
5 MHz,
MHz
SD16OSR = 256
MIN
2.5
GAIN 1
GAIN:
1,2
2
ISD16
VCC
720
1030
1160
3V
810
105°C
1150
μA
A
1300
3V
0.03
1
3V
0.03
0.5
1.1
MHz
MHz
SD16_A, input range (MSP430x20x3 only)
PARAMETER
VID,FSR
VID
TEST CONDITIONS
Differential full scale input voltage
range (see Note 1)
Differential input voltage range
for specified performance
(see Note 1)
VCC
Bipolar Mode, SD16UNI = 0
TYP
0
Unipolar Mode, SD16UNI = 1
SD16REFON 1
SD16REFON=1
MIN
--(VREF/2)/
GAIN
UNIT
mV
+(VREF/2)/
GAIN
mV
SD16GAINx=1
±500
SD16GAINx=2
±250
SD16GAINx=4
±125
SD16GAINx=8
±62
SD16GAINx=16
±31
SD16GAINx=32
MAX
+(VREF/2)/
GAIN
mV
±15
SD16GAINx=1
3V
200
SD16GAINx=32
3V
75
SD16GAINx=1
3V
300
400
SD16GAINx=32
3V
100
150
ZI
Input impedance
(one input pin to AVSS)
fSD16 = 1MHz
ZID
Differential Input impedance
(IN+ to IN--)
fSD16 = 1MHz
VI
Absolute input voltage range
AVSS
-0.1V
AVCC
V
VIC
Common-mode input voltage
range
AVSS
-0.1V
AVCC
V
kΩ
kΩ
NOTES: 1. The analog input range depends on the reference voltage applied to VREF. If VREF is sourced externally, the full-scale range
is defined by VFSR+ = +(VREF/2)/GAIN and VFSR-- = --(VREF/2)/GAIN. The analog input range should not exceed 80% of
VFSR+ or VFSR-- .
44
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
SD16_A, SINAD performance (fSD16 = 1MHz, SD16OSRx = 1024, SD16REFON = 1, MSP430x20x3 only)
PARAMETER
SINAD1024
TEST CONDITIONS
Signal to Noise + Distortion Ratio
Signal-to-Noise
(OSR = 1024)
VCC
PW, or N
MIN
RSA
TYP
MIN
TYP
SD16GAINx = 1,
Signal Amplitude: VIN = 500mV,
Signal Frequency: fIN = 100Hz
3V
84
85
86
87
SD16GAINx = 2,
Signal Amplitude: VIN = 250mV,
Signal Frequency: fIN = 100Hz
3V
82
83
82
83
SD16GAINx = 4,
Signal Amplitude: VIN = 125mV,
Signal Frequency: fIN = 100Hz
3V
78
79
78
79
SD16GAINx = 8,
Signal Amplitude: VIN = 62mV,
Signal Frequency: fIN = 100Hz
3V
73
74
73
74
SD16GAINx = 16,
Signal Amplitude: VIN = 31mV,
Signal Frequency: fIN = 100Hz
3V
68
69
68
69
SD16GAINx = 32,
Signal Amplitude: VIN = 15mV,
Signal Frequency: fIN = 100Hz
3V
62
63
62
63
UNIT
dB
SD16_A, SINAD performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1, MSP430x20x3 only)
PARAMETER
SINAD256
TEST CONDITIONS
Signal to Noise + Distortion Ratio
Signal-to-Noise
(OSR = 256)
VCC
PW, or N
MIN
RSA
TYP
MIN
TYP
SD16GAINx = 1,
Signal Amplitude: VIN = 500mV,
Signal Frequency: fIN = 100Hz
3V
80
81
82
83
SD16GAINx = 2,
Signal Amplitude: VIN = 250mV,
Signal Frequency: fIN = 100Hz
3V
74
75
76
77
SD16GAINx = 4,
Signal Amplitude: VIN = 125mV,
Signal Frequency: fIN = 100Hz
3V
69
70
71
72
SD16GAINx = 8,
Signal Amplitude: VIN = 62mV,
Signal Frequency: fIN = 100Hz
3V
63
64
67
68
SD16GAINx = 16,
Signal Amplitude: VIN = 31mV,
Signal Frequency: fIN = 100Hz
3V
58
59
63
64
SD16GAINx = 32,
Signal Amplitude: VIN = 15mV,
Signal Frequency: fIN = 100Hz
3V
52
53
57
58
POST OFFICE BOX 655303
UNIT
dB
• DALLAS, TEXAS 75265
45
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
typical characteristics -- SD16_A SINAD performance over OSR (MSP430x20x3 only)
90.0
85.0
SINAD -- dB
80.0
75.0
70.0
65.0
60.0
RSA
PW, or N
55.0
10.00
100.00
1000.00
OSR
Figure 22. SINAD performance over OSR, fSD16 = 1MHz, SD16REFON = 1, SD16GAINx = 1
SD16_A, performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1, MSP430x20x3 only)
PARAMETER
G
dG/dT
Nominal Gain
Gain Temperature Drift
EOS
Offset Error
dEOS/dT
Offset Error Temperature
Coefficient
CMRR
TEST CONDITIONS
Common Mode Rejection Ratio
Common-Mode
VCC
MIN
TYP
MAX
SD16GAINx = 1
3V
0.97
1.00
1.02
SD16GAINx = 2
3V
1.90
1.96
2.02
SD16GAINx = 4
3V
3.76
3.86
3.96
SD16GAINx = 8
3V
7.36
7.62
7.84
SD16GAINx = 16
3V
14.56
15.04
15.52
SD16GAINx = 32
3V
27.20
28.35
29.76
SD16GAINx = 1 (see Note 1)
3V
SD16GAINx = 1
3V
±0.2
SD16GAINx = 32
3V
±1.5
15
UNIT
ppm/_C
SD16GAINx = 1
3V
±4
±20
SD16GAINx = 32
3V
±20
±100
SD16GAINx = 1,
Common-mode input signal:
VID = 500 mV, fIN = 50 Hz, 100 Hz
3V
>90
SD16GAINx = 32,
Common-mode input signal:
VID = 16 mV, fIN = 50 Hz, 100 Hz
3V
>75
%FSR
ppm
FSR/_C
dB
DC PSR
DC Power Supply Rejection
SD16GAINx = 1; VIN = 500mV
VCC = 2.5V - 3.6V (see Note 2)
2.5V--3.6V
0.35
%/V
AC PSRR
AC Power Supply Rejection Ratio
SD16GAINx = 1
VCC = 3.0V±100mV, fIN = 50 Hz
3V
>80
dB
NOTES: 1. Calculated using the box method: (MAX(--40...85_C) -- MIN(--40...85_C)) / MIN(--40...85_C) / (85_C -- (--40_C))
2. Calculated using the ADC output code and the box method:
(MAX-code(2.5...3.6V) -- MIN-code(2.5...3.6V)) / MIN-code(2.5...3.6V) / (3.6V -- 2.5V)
46
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
SD16_A, built-in voltage reference (MSP430x20x3 only)
PARAMETER
TEST CONDITIONS
TA
VCC
VREF
Internal reference voltage
SD16REFON = 1,
SD16VMIDON = 0
IREF
Reference supply
s ppl current
c rrent
SD16REFON = 1,
SD16VMIDON = 0
TC
Temperature coefficient
SD16REFON = 1,
SD16VMIDON = 0
CREF
VREF load capacitance
SD16REFON = 1,
SD16VMIDON = 0
(see Note 1)
ILOAD
VREF(I) maximum load current
SD16REFON = 1;
SD16VMIDON = 0
3V
tON
Turn on time
SD16REFON = 0 → 1;
SD16VMIDON = 0;
CREF = 100nF
3V
DC PSR
DC Power Supply Rejection
∆VREF/∆VCC
SD16REFON = 1;
SD16VMIDON = 0;
VCC = 2.5V - 3.6V
3V
-40--85°C
3V
105°C
3V
MIN
1.14
TYP
MAX
1.20
1.26
190
280
295
3V
18
50
100
V
μA
A
ppm/K
nF
±200
5
2.5V--3.6V
UNIT
nA
ms
100
uV/V
NOTES: 1. There is no capacitance required on VREF. However, a capacitance of at least 100nF is recommended to reduce any reference
voltage noise.
SD16_A, reference output buffer (MSP430x20x3 only)
PARAMETER
TEST CONDITIONS
TA
VCC
VREF,BUF
Reference buffer output voltage
SD16REFON = 1,
SD16VMIDON = 1
IREF,BUF
Reference Supply + Reference
output buffer quiescent current
SD16REFON = 1,
SD16VMIDON = 1
CREF(O)
Required load capacitance
on VREF
SD16REFON = 1,
SD16VMIDON = 1
ILOAD,Max
Maximum load current on VREF
SD16REFON = 1,
SD16VMIDON = 1
3V
Maximum voltage variation vs. load current
|ILOAD| = 0 to 1mA
3V
tON
SD16REFON = 0 → 1;
SD16VMIDON = 1;
CREF = 470nF
3V
Turn on time
MIN
TYP
3V
1.2
--40--85°C
3V
385
105°C
3V
MAX
UNIT
V
600
660
470
μA
A
nF
--15
±1
mA
+15
mV
100
μs
SD16_A, external reference input (MSP430x20x3 only)
PARAMETER
TEST CONDITIONS
VCC
VREF(I)
Input voltage range
SD16REFON = 0
3V
IREF(I)
Input current
SD16REFON = 0
3V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
1.0
TYP
1.25
MAX
UNIT
1.5
V
50
nA
47
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
SD16_A, temperature sensor (MSP430x20x3 only)
PARAMETER
TEST CONDITIONS
VCC
MIN
TCSensor
Sensor temperature coefficient
1.18
VOffset,Sensor
Sensor offset voltage
--100
VSensor
Sensor output voltage
(see Note 2)
1.32
MAX
mV/K
100
mV
3V
435
475
515
Temperature sensor voltage
at TA = 25°C
3V
355
395
435
Temperature sensor voltage
at TA = 0°C
3V
320
360
400
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
1.46
Temperature sensor voltage
at TA = 85°C
NOTES: 1. The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
2. Values are not based on calculations using TCSensor or VOffset,sensor but on measurements.
48
TYP
mV
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Flash Memory
PARAMETER
VCC(PGM/
ERASE)
TEST CONDITIONS
VCC
Program and Erase supply voltage
MIN
TYP
2.2
fFTG
Flash Timing Generator frequency
IPGM
Supply current from VCC during program
2.2 V/3.6 V
257
1
IERASE
Supply current from VCC during erase
2.2 V/3.6 V
1
tCPT
Cumulative program time (see Note 1)
2.2 V/3.6 V
tCMErase
Cumulative mass erase time
2.2 V/3.6 V
TJ = 25°C
V
476
kHz
5
mA
7
mA
10
ms
ms
105
tRetention
Data retention duration
tWord
Word or byte program time
30
tBlock, 0
Block program time for 1st byte or word
25
tBlock, 1-63
Block program time for each additional byte or word
tBlock, End
Block program end-sequence wait time
tMass Erase
Mass erase time
tSeg Erase
Segment erase time
cycles
100
years
18
see Note 2
UNIT
3.6
20
104
Program/Erase endurance
MAX
tFTG
6
10593
4819
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
RAM
PARAMETER
V(RAMh)
TEST CONDITIONS
RAM retention supply voltage (see Note 1)
CPU halted
MIN
1.6
TYP
MAX
UNIT
V
NOTE 1: This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
49
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
JTAG and Spy-Bi-Wire Interface
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V / 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V / 3 V
0.025
15
us
tSBW,En
Spy-Bi-Wire enable time
(TEST high to acceptance of first clock edge, see
Note 1)
2.2 V/ 3 V
1
us
tSBW,Ret
Spy-Bi-Wire return to normal operation time
2.2 V/ 3 V
15
100
2.2 V
0
5
MHz
3V
0
10
MHz
2.2 V/ 3 V
25
90
kΩ
fTCK
TCK input frequency -- 4-wire
4 wire JTAG (see Note 2)
RInternal
Internal pull-down resistance on TEST
60
us
NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWTCK pin high
before applying the first SBWTCK clock edge.
2. fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse-blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
TA = 25°C
VCC
MIN
TYP
MAX
2.5
6
UNIT
V
7
V
100
mA
1
ms
NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible and JTAG is switched
to bypass mode.
50
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
APPLICATION INFORMATION, MSP430x20x1
Port P1 (P1.0 to P1.3) pin functions, MSP430x20x1
PIN NAME (P1.X)
(P1 X)
P1.0/TACLK/ACLK/
/
/
/
CA0
P1.1/TA0/CA1
/
/
P1.2/TA1/CA2
/
/
X
CONTROL BITS / SIGNALS
FUNCTION
0 P1.0† Input/Output
Timer_A2.TACLK/INCLK
P1SEL.x
CAPD.x
0/1
0
0
0
1
0
ACLK
1
1
0
CA0 (see Note 3)
X
X
1
0/1
0
0
Timer_A2.CCI0A
0
1
0
Timer_A2.TA0
1
1
0
CA1 (see Note 3)
X
X
1
1 P1.1† Input/Output
2 P1.2† Input/Output
0/1
0
0
Timer_A2.CCI1A
0
1
0
Timer_A2.TA1
1
1
0
CA2 (see Note 3)
P1.3/CAOUT/CA3
/
/
P1DIR.x
X
X
1
0/1
0
0
N/A
0
1
0
CAOUT
1
1
0
CA3 (see Note 3)
X
X
1
3 P1.3† Input/Output
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the CAPD.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer
for that pin, regardless of the state of the associated CAPD.x bit.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
51
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.0 to P1.3) pin schematics, MSP430x20x1
Pad Logic
To Comparator_A+
From Comparator_A+
CAPD.x
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
P1.0/TACLK/ACLK/CA0
P1.1/TA0/CA1
P1.2/TA1/CA2
P1.3/CAOUT/CA3
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
Module X IN
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Control signal “From Comparator_A+”
PIN NAME
FUNCTION
SIGNAL “FROM COMPARATOR_A+” = 1
P2CA4
P2CA0
P2CA3
P2CA2
P2CA1
N/A
N/A
N/A
P1.0/TACLK/ACLK/CA0
CA0
0
1
P1.1/TA0/CA1
CA1
1
0
0
0
1
P1.2/TA1/CA2
CA2
1
1
0
1
0
P1.3/CAOUT/CA3
CA3
N/A
N/A
0
1
1
NOTES: 1. N/A: Not available or not applicable.
52
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
OR
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.4 to P1.7) pin functions, MSP430x20x1
PIN NAME (P1.X)
(P1 X)
P1.4/SMCLK/CA4/
/
/
/
TCK
X
FUNCTION
4 P1.4† Input/Output
N/A
P1.6/TA1/CA6/
/
/
/
TDI
P1.7/CAOUT/CA7/
/
/
/
TDO/TDI
P1DIR.x
P1SEL.x
CAPD.x
JTAG Mode
0/1
0
0
0
0
1
0
0
SMCLK
1
1
0
0
CA4 (see Note 3)
X
X
1
0
TCK (see Note 4)
P1.5/TA0/CA5/
/
/
/
TMS
CONTROL BITS / SIGNALS
5 P1.5† Input/Output
N/A
X
X
X
1
0/1
0
0
0
0
1
0
0
Timer_A2.TA0
1
1
0
0
CA5 (see Note 3)
X
X
1
0
TMS (see Note 4)
X
X
X
1
6 P1.6† Input/Output
0/1
0
0
0
N/A
0
1
0
0
Timer_A2.TA1
1
1
0
0
CA6 (see Note 3)
X
X
1
0
TDI (see Note 4)
X
X
X
1
7 P1.7† Input/Output
0/1
0
0
0
N/A
0
1
0
0
CAOUT
1
1
0
0
CA7 (see Note 3)
X
X
1
0
TDO/TDI (see Notes 4, 5)
X
X
X
1
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the CAPD.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer
for that pin, regardless of the state of the associated CAPD.x bit.
4. In JTAG mode the internal pull-up/down resistors are disabled.
5. Function controlled by JTAG
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
53
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.4 to P1.6) pin schematics, MSP430x20x1
Pad Logic
To Comparator_A+
From Comparator_A+
CAPD.x
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
DVCC
P1.4/SMCLK/CA4/TCK
P1.5/TA0/CA5/TMS
P1.6/TA1/CA6/TDI
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
To JTAG
From JTAG
Control signal “From Comparator_A+”
PIN NAME
FUNCTION
SIGNAL “FROM COMPARATOR_A+” = 1
P2CA3
P2CA2
P2CA1
P1.4/SMCLK/CA4/TCK
CA4
1
0
0
P1.5/TA0/CA5/TMS
CA5
1
0
1
P1.6/TA1/CA6/TDI
CA6
1
1
0
NOTES: 1. N/A: Not available or not applicable.
54
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.7) pin schematics, MSP430x20x1
Pad Logic
To Comparator_A+
From Comparator_A+
CAPD.7
P1REN.7
P1DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.7
DVSS
P1.7/CAOUT/CA7/TDO/TDI
Bus
Keeper
P1SEL.7
EN
P1IN.7
EN
Module X IN
D
P1IE.7
P1IRQ.7
EN
Q
P1IFG.7
P1SEL.7
P1IES.7
Set
Interrupt
Edge
Select
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
Control signal “From Comparator_A+”
PIN NAME
SIGNAL “FROM COMPARATOR_A+” = 1
FUNCTION
P1.7/CAOUT/CA7/TDO/TDI
CA7
P2CA3
P2CA2
P2CA1
1
1
1
NOTES: 1. N/A: Not available or not applicable.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
55
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P2 (P2.6) pin schematics, MSP430x20x1
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT
LFXT1 off
0
LFXT1CLK
1
P2SEL.7
Pad Logic
P2REN.6
P2DIR.6
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.6
DVSS
P2.6/XIN/TA1
Bus
Keeper
P2SEL.6
EN
P2IN.6
EN
Module X IN
D
P2IE.6
P2IRQ.6
EN
Q
P2IFG.6
P2SEL.6
P2IES.6
Set
Interrupt
Edge
Select
Port P2 (P2.6) pin functions, MSP430x20x1
PIN NAME (P2.X)
(P2 X)
P2.6/XIN/TA1
/
/
X
FUNCTION
P2DIR.x
P2SEL.x
0/1
0
XIN† (see Note 3)
0
1
Timer_A2.TA1
1
1
6 P2.6 Input/Output
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. XIN is used as digital clock input if the bits LFXT1Sx in register BCSCTL3 are set to 11.
56
CONTROL BITS / SIGNALS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P2 (P2.7) pin schematics, MSP430x20x1
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
LFXT1 off
0
LFXT1CLK
From P2.6/XIN
1
P2.6/XIN/TA1
Pad Logic
P2SEL.6
P2REN.7
P2DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.7
DVSS
P2.7/XOUT
Bus
Keeper
P2SEL.7
EN
P2IN.7
EN
Module X IN
D
P2IE.7
P2IRQ.7
EN
Q
P2IFG.7
Set
Interrupt
Edge
Select
P2SEL.7
P2IES.7
Port P2 (P2.7) pin functions, MSP430x20x1
PIN NAME (P2.X)
(P2 X)
P2.7/XOUT
/
X
FUNCTION
CONTROL BITS / SIGNALS
P2DIR.x
P2SEL.x
0/1
0
DVSS
0
1
XOUT† (see Note 3)
1
1
7 P2.7 Input/Output
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. If the pin P2.7/XOUT is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection
to this pin after reset.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
57
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
APPLICATION INFORMATION, MSP430x20x2
Port P1 (P1.0 to P1.2) pin functions, MSP430x20x2
PIN NAME (P1.X)
(P1 X)
P1.0/TACLK/ACLK/A0
/
/
/
X
FUNCTION
0 P1.0† Input/Output
Timer_A2.TACLK/INCLK
P1.1/TA0/A1
/
/
P1.2/TA1/A2
/
/
CONTROL BITS / SIGNALS
P1DIR.x
P1SEL.x
ADC10AE.x
INCHx
0/1
0
0
N/A
0
1
0
N/A
N/A
ACLK
1
1
0
A0 (see Note 3)
X
X
1
0
1 P1.1† Input/Output
0/1
0
0
N/A
Timer_A2.CCI0A
0
1
0
N/A
Timer_A2.TA0
1
1
0
N/A
A1 (see Note 3)
X
X
1
1
2 P1.2† Input/Output
0/1
0
0
N/A
Timer_A2.CCI1A
0
1
0
N/A
Timer_A2.TA1
1
1
0
N/A
A2 (see Note 3)
X
X
1
2
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the ADC10AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
58
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.0 to P1.2) pin schematics, MSP430x20x2
Pad Logic
To ADC 10
INCHx = x
ADC10AE.x
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
Bus
Keeper
P1SEL.x
P1.0/TACLK/ACLK/A0
P1.1/TA0/A1
P1.2/TA1/A2
EN
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
59
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.3) pin schematics, MSP430x20x2
SREF2
VSS
0
To ADC 10 VR--
Pad Logic
1
A3
INCHx = 3
ADC10AE.3
P1REN.3
P1DIR.3
0
P1OUT.3
0
1
0
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
DVCC
P1.3/ADC10CLK/
A3/VREF--/VeREF--
Bus
Keeper
P1SEL.3
EN
P1IN.3
EN
Module X IN
D
P1IE.3
P1IRQ.3
EN
Q
P1IFG.3
Set
Interrupt
Edge
Select
P1SEL.3
P1IES.3
Port P1 (P1.0 to P1.3) pin functions, MSP430x20x2
PIN NAME (P1.X)
(P1 X)
P1.3/ADC10CLK/
/
/
A3/VREF--/VeREF--
X
FUNCTION
3 P1.3† Input/Output
N/A
CONTROL BITS / SIGNALS
P1DIR.x
P1SEL.x
ADC10AE.x
INCHx
0/1
0
0
N/A
0
1
0
N/A
N/A
ADC10CLK
1
1
0
A3 (see Note 3)
X
X
1
3
VREF--/VeREF-- (see Notes 3, 4)
X
X
1
N/A
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the ADC10AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. An applied voltage is used as negative reference if bit SREF3 in register ADC10CTL0 is set.
60
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.4 to P1.7) pin functions, MSP430x20x2
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
P1.4/SMCLK/A4/
/
/ /
VREF+/VeREF+/
TCK
X
FUNCTION
4 P1.4† Input/Output
P1.7/SDI/SDA/A7/
/
/
/ /
TDO/TDI
USIP.x
ADC10AE.x
INCHx
JTAG
Mode
0/1
0
0
N/A
0
0
1
0
N/A
0
SMCLK
1
1
0
N/A
0
A4 (see Note 3)
X
X
1
4
0
VREF+/VeREF+
(see Notes 3, 4)
X
X
1
N/A
0
5 P1.5† Input/Output
N/A
N/A
/
X
X
X
X
1
0/1
0
X
0
N/A
0
0
1
X
0
N/A
0
Timer_A2.TA0
1
1
X
0
N/A
0
SCLK
X
X
1
0
N/A
0
A5 (see Note 3)
X
X
X
1
5
0
TMS (see Note 5)
P1.6/TA1/SDO/SCL/A6/
/
/
/
/ /
TDI
P1SEL.x
N/A
TCK (see Note 5)
P1.5/TA0/SCLK/A5/
/
/
/ /
TMS
P1DIR.x
X
X
X
X
X
1
0/1
0
X
0
N/A
0
Timer_A2.CCI1B
0
1
X
0
N/A
0
Timer_A2.TA1
1
1
X
0
N/A
0
SDO (SPI) / SCL (I2C)
X
X
1
0
N/A
0
A6 (see Note 3)
X
X
X
1
6
0
TDI (see Note 5)
X
X
X
X
X
1
7 P1.7† Input/Output
0/1
0
X
0
N/A
0
N/A
0
1
X
0
N/A
0
DVSS
1
1
X
0
N/A
0
SDI (SPI) / SDA (I2C)
X
X
1
0
N/A
0
A7 (see Note 3)
X
X
X
1
7
0
TDO/TDI (see Notes 5,
6)
X
X
X
X
X
1
6 P1.6† Input/Output
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the ADC10AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. The reference voltage is output if bit REFOUT in register ADC10CTL0 is set. An applied voltage is used as positive reference if
bits SREF0/1 in register ADC10CTL0 are set to 10 or 11.
5. In JTAG mode the internal pull-up/down resistors are disabled.
6. Function controlled by JTAG
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
61
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.4) pin schematics, MSP430x20x2
Pad Logic
To /from ADC10
positive reference
A4
INCHx = 4
ADC10AE.4
P1REN.4
P1DIR.4
0
0
Module X OUT
1
0
DVCC
1
P1.4/SMCLK/A4/VREF+/VeREF+/TCK
Bus
Keeper
P1SEL.4
EN
EN
Module X IN
D
P1IE.4
P1IRQ.4
EN
Q
P1IFG.4
P1SEL.4
P1IES.4
Set
Interrupt
Edge
Select
To JTAG
From JTAG
62
1
Direction
0: Input
1: Output
1
P1OUT.4
DVSS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.5) pin schematics, MSP430x20x2
Pad Logic
A5
INCHx = 5
ADC10AE.5
P1REN.5
P1SEL.5
USIPE5
P1DIR.5
0
USI Module Direction
1
P1OUT.5
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.5/TA0/SCLK/A5/TMS
Bus
Keeper
EN
P1IN.5
EN
Module X IN
D
P1IE.5
P1IRQ.5
EN
Q
P1IFG.5
P1SEL.5
P1IES.5
Set
Interrupt
Edge
Select
To JTAG
From JTAG
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
63
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.6) pin schematics, MSP430x20x2
Pad Logic
A6
INCHx = 6
ADC10AE.6
P1REN.6
P1SEL.6
USIPE6
P1DIR.6
0
USI Module Direction
1
P1OUT.6
0
Module X OUT
1
DVSS
0
DVCC
1
Direction
0: Input
1: Output
P1.6/TA1/SDO/SCL/A6/TDI
USI Module Output
(I2C Mode)
Bus
Keeper
EN
P1IN.6
EN
Module X IN
D
P1IE.6
P1IRQ.6
EN
Q
P1IFG.6
P1SEL.6
P1IES.6
Set
Interrupt
Edge
Select
To JTAG
From JTAG
64
1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.7) pin schematics, MSP430x20x2
Pad Logic
A7
INCHx = 7
ADC10AE.7
P1REN.7
P1SEL.7
USIPE7
P1DIR.7
0
USI Module Direction
1
P1OUT.7
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.7/SDI/SDA/A7/TDO/TDI
USI Module Output
(I2C Mode)
Bus
Keeper
EN
P1IN.7
EN
Module X IN
D
P1IE.7
P1IRQ.7
EN
Q
P1IFG.7
P1SEL.7
P1IES.7
Set
Interrupt
Edge
Select
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
65
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P2 (P2.6) pin schematics, MSP430x20x2
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT
LFXT1 off
0
LFXT1CLK
1
P2SEL.7
Pad Logic
P2REN.6
P2DIR.6
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.6
DVSS
P2.6/XIN/TA1
Bus
Keeper
P2SEL.6
EN
P2IN.6
EN
Module X IN
D
P2IE.6
P2IRQ.6
EN
Q
P2IFG.6
P2SEL.6
P2IES.6
Set
Interrupt
Edge
Select
Port P2 (P2.6) pin functions, MSP430x20x2
PIN NAME (P2.X)
(P2 X)
P2.6/XIN/TA1
/
/
X
FUNCTION
P2DIR.x
P2SEL.x
0/1
0
XIN† (see Note 3)
0
1
Timer_A2.TA1
1
1
6 P2.6 Input/Output
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. XIN is used as digital clock input if the bits LFXT1Sx in register BCSCTL3 are set to 11.
66
CONTROL BITS / SIGNALS
POST OFFICE BOX 655303
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MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P2 (P2.7) pin schematics, MSP430x20x2
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
LFXT1 off
0
LFXT1CLK
From P2.6/XIN
1
P2.6/XIN/TA1
Pad Logic
P2SEL.6
P2REN.7
P2DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.7
DVSS
P2.7/XOUT
Bus
Keeper
P2SEL.7
EN
P2IN.7
EN
Module X IN
D
P2IE.7
P2IRQ.7
EN
Q
P2IFG.7
Set
Interrupt
Edge
Select
P2SEL.7
P2IES.7
Port P2 (P2.7) pin functions, MSP430x20x2
PIN NAME (P2.X)
(P2 X)
P2.7/XOUT
/
X
FUNCTION
CONTROL BITS / SIGNALS
P2DIR.x
P2SEL.x
0/1
0
DVSS
0
1
XOUT† (see Note 3)
1
1
7 P2.7 Input/Output
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. If the pin P2.7/XOUT is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection
to this pin after reset.
POST OFFICE BOX 655303
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67
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
APPLICATION INFORMATION, MSP430x20x3
Port P1 (P1.0 to P1.3) pin functions, MSP430x20x3
PIN NAME (P1.X)
(P1 X)
P1.0/TACLK/ACLK/A0+
/
/
/
X
FUNCTION
0 P1.0† Input/Output
Timer_A2.TACLK/INCLK
P1.1/TA0/A0--/A4+
/
/
/
SD16AE.x
INCHx
0/1
0
0
N/A
0
1
0
N/A
N/A
1
1
0
A0+ (see Note 3)
X
X
1
0
0/1
0
0
N/A
Timer_A2.CCI0A
0
1
0
N/A
Timer_A2.TA0
1
1
0
N/A
A0-- (see Notes 3, 4)
X
X
1
0
1 P1.1† Input/Output
2 P1.2† Input/Output
Timer_A2.CCI1A
X
X
1
4
0/1
0
0
N/A
0
1
0
N/A
Timer_A2.TA1
1
1
0
N/A
A1+ (see Note 3)
X
X
1
1
A4-- (see Notes 3, 4)
P1.3/VREF/A1-/
/
P1SEL.x
ACLK
A4+ (see Note 3)
P1.2/TA1/A1+/A4-/
/
/
CONTROL BITS / SIGNALS
P1DIR.x
X
X
1
4
0/1
0
0
N/A
VREF
X
1
0
N/A
A1-- (see Notes 3, 4)
X
X
1
1
3 P1.3† Input/Output
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the SD16AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. With SD16AE.x = 0 the negative inputs are connected to VSS if the corresponding input is selected.
68
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.0) pin schematics, MSP430x20x3
INCH=0
Pad Logic
A0+
SD16AE.0
P1REN.0
P1DIR.0
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.0
DVSS
P1.0/TACLK/ACLK/A0+
Bus
Keeper
P1SEL.0
EN
P1IN.0
EN
Module X IN
P1IRQ.0
D
P1IE.0
EN
Q
P1IFG.0
P1SEL.0
P1IES.0
Set
Interrupt
Edge
Select
POST OFFICE BOX 655303
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69
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.1) pin schematics, MSP430x20x3
INCH=4
Pad Logic
A4+
INCH=0
0
A0--
AV SS
1
SD16AE.1
P1REN.1
P1DIR.1
0
0
Module X OUT
1
0
1
P1.1/TA0/A0--/A4+
Bus
Keeper
P1SEL.1
EN
P1IN.1
EN
Module X IN
P1IRQ.1
D
P1IE.1
EN
Q
P1IFG.1
P1SEL.1
P1IES.1
70
1
Direction
0: Input
1: Output
1
P1OUT.1
DVSS
DVCC
Set
Interrupt
Edge
Select
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MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.2) pin schematics, MSP430x20x3
INCH=1
Pad Logic
A1+
INCH=4
0
A4--
AV SS
1
SD16AE.2
P1REN.2
P1DIR.2
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P1OUT.2
DVSS
DVCC
P1.2/TA 1/A1+/A4-Bus
Keeper
P1SEL.2
EN
P1IN.2
EN
Module X IN
P1IRQ.2
D
P1IE.2
EN
Q
P1IFG.2
P1SEL.2
P1IES.2
Set
Interrupt
Edge
Select
POST OFFICE BOX 655303
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71
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.3) pin schematics, MSP430x20x3
Pad Logic
VREF
INCH=1
0
A1--
AV SS
1
SD16AE.3
P1REN.3
P1DIR.3
0
0
1
1
Direction
0: Input
1: Output
1
P1OUT.3
DVSS
DVCC
0
1
P1.3/VREF/A1-Bus
Keeper
P1SEL.3
EN
P1IN.3
P1IRQ.3
P1IE.3
P1IFG.3
P1SEL.3
P1IES.3
72
EN
Q
Set
Interrupt
Edge
Select
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MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.4 to P1.7) pin functions, MSP430x20x3
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
P1.4/SMCLK/A2+/
/
/
/
TCK
P1.5/TA0/SCLK/A2--/
/
/
/
/
TMS
P1.6/TA1/SDO/SCL/A3+/
/
/
/
/
/
TDI
P1.7/SDI/SDA/A3--/
/
/
/
/
TDO/TDI
X
FUNCTION
4 P1.4† Input/Output
P1DIR.x
P1SEL.x
USIP.x
SD16AE.x
INCHx
JTAG
Mode
0/1
0
N/A
0
N/A
0
N/A
0
1
N/A
0
N/A
0
SMCLK
1
1
N/A
0
N/A
0
A2+ (see Note 3)
X
X
N/A
1
2
0
TCK (see Note 5)
X
X
N/A
X
X
1
5 P1.5† Input/Output
0/1
0
X
0
N/A
0
N/A
0
1
X
0
N/A
0
Timer_A2.TA0
1
1
X
0
N/A
0
SCLK
X
X
1
0
N/A
0
A2-- (see Notes 3, 4)
X
X
X
1
2
0
TMS (see Note 5)
X
X
X
X
X
1
6 P1.6† Input/Output
0/1
0
X
0
N/A
0
Timer_A2.CCI1B
0
1
X
0
N/A
0
Timer_A2.TA1
1
1
X
0
N/A
0
SDO (SPI) / SCL (I2C)
X
X
1
0
N/A
0
A3+ (see Note 3)
X
X
X
1
3
0
TDI (see Note 5)
X
X
X
X
X
1
7 P1.7† Input/Output
0/1
0
X
0
N/A
0
0
1
X
0
N/A
0
N/A
DVSS
1
1
X
0
N/A
0
SDI (SPI) / SDA (I2C)
X
X
1
0
N/A
0
A3-- (see Notes 3, 4)
X
X
X
1
3
0
TDO/TDI (see Notes 5, 6)
X
X
X
X
X
1
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the SD16AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. With SD16AE.x = 0 the negative inputs are connected to VSS if the corresponding input is selected.
5. In JTAG mode the internal pull-up/down resistors are disabled.
6. Function controlled by JTAG
POST OFFICE BOX 655303
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73
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.4) pin schematics, MSP430x20x3
INCH=2
Pad Logic
A2+
SD16AE.4
P1REN.4
P1DIR.4
0
0
Module X OUT
1
0
DVCC
1
P1.4/SMCLK/A2+/TCK
Bus
Keeper
P1SEL.4
EN
P1IN.4
EN
Module X IN
P1IRQ.4
D
P1IE.4
EN
Q
P1IFG.4
P1SEL.4
P1IES.4
Set
Interrupt
Edge
Select
To JTAG
From JTAG
74
1
Direction
0: Input
1: Output
1
P1OUT.4
DVSS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.5) pin schematics, MSP430x20x3
Pad Logic
INCH=2
0
A2--
AV SS
1
SD16AE.5
P1REN.5
P1SEL.5
USIPE5
P1DIR.5
0
USI Module Direction
1
P1OUT.5
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.5/TA0/SCLK/A2--/TMS
Bus
Keeper
EN
P1IN.5
EN
Module X IN
P1IRQ.5
D
P1IE.5
EN
Q
P1IFG.5
P1SEL.5
P1IES.5
Set
Interrupt
Edge
Select
To JTAG
From JTAG
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
75
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.6) pin schematics, MSP430x20x3
Pad Logic
INCH=3
A3+
SD16AE.6
P1REN.6
P1SEL.6
USIPE6
P1DIR.6
0
USI Module Direction
1
P1OUT.6
0
Module X OUT
1
DVSS
0
DVCC
1
Direction
0: Input
1: Output
P1.6/TA1/SDO/SCL/A3+/TDI
USI Module Output
(I2C Mode)
Bus
Keeper
P1IN.6
EN
EN
Module X IN
P1IRQ.6
D
P1IE.6
EN
Q
P1IFG.6
P1SEL.6
P1IES.6
Set
Interrupt
Edge
Select
To JTAG
From JTAG
76
1
POST OFFICE BOX 655303
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MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.7) pin schematics, MSP430x20x3
Pad Logic
INCH=3
0
A3--
AV SS
1
SD16AE.x
P1REN.x
P1SEL.x
USIPE7
P1DIR.x
0
USI Module Direction
1
P1OUT.x
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.7/SDI/SDA/A3--/TDO/TDI
USI Module Output
(I2C Mode)
Bus
Keeper
EN
P1IN.x
EN
Module X IN
P1IRQ.x
D
P1IE.x
EN
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
POST OFFICE BOX 655303
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77
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P2 (P2.6) pin schematics, MSP430x20x3
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT
LFXT1 off
0
LFXT1CLK
1
P2SEL.7
Pad Logic
P2REN.6
P2DIR.6
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.6
DVSS
P2.6/XIN/TA1
Bus
Keeper
P2SEL.6
EN
P2IN.6
EN
Module X IN
D
P2IE.6
P2IRQ.6
EN
Q
P2IFG.6
P2SEL.6
P2IES.6
Set
Interrupt
Edge
Select
Port P2 (P2.6) pin functions, MSP430x20x3
PIN NAME (P2.X)
(P2 X)
P2.6/XIN/TA1
/
/
X
FUNCTION
P2DIR.x
P2SEL.x
0/1
0
XIN† (see Note 3)
0
1
Timer_A2.TA1
1
1
6 P2.6 Input/Output
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. XIN is used as digital clock input if the bits LFXT1Sx in register BCSCTL3 are set to 11.
78
CONTROL BITS / SIGNALS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P2 (P2.7) pin schematics, MSP430x20x3
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
LFXT1 off
0
LFXT1CLK
From P2.6/XIN
1
P2.6/XIN/TA1
Pad Logic
P2SEL.6
P2REN.7
P2DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.7
DVSS
P2.7/XOUT
Bus
Keeper
P2SEL.7
EN
P2IN.7
EN
Module X IN
D
P2IE.7
P2IRQ.7
EN
Q
P2IFG.7
Set
Interrupt
Edge
Select
P2SEL.7
P2IES.7
Port P2 (P2.7) pin functions, MSP430x20x3
PIN NAME (P2.X)
(P2 X)
P2.7/XOUT
/
X
FUNCTION
CONTROL BITS / SIGNALS
P2DIR.x
P2SEL.x
0/1
0
DVSS
0
1
XOUT† (see Note 3)
1
1
7 P2.7 Input/Output
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. If the pin P2.7/XOUT is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection
to this pin after reset.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
79
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Data Sheet Revision History
Literature
Number
SLAS491
80
Summary
Preliminary PRODUCT PREVIEW data sheet release
SLAS491A
Production data sheet release for MSP430x20x3I.
Updated specification and added characterization graphs.
SLAS491B
Production data sheet release for MSP430x20x3T, MSP430x20x1I and MSP430x20x1T.
105°C characterization results added.
SD16_A SINAD characterization results for MSP430x20x3RSA package added.
Updated SD16_A Power Supply Rejection specification.
DCO Calibration Register names: lower case “z” changed to upper case “Z”.
Vhys(B_IT--) MAX specification increased from 180mV to 210mV.
MIN and MAX percentages for “calibrated DCO frequencies -- tolerance over supply voltage VCC” corrected from 2.5% to
3.0% to match the specified frequency ranges.
SLAS491C
Production data sheet release for MSP430x20x2I and MSP430x20x2T.
SLAS491D
Changed fACLK to 0 Hz in ILPM4 test conditions on page 23.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F2001IN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2001IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2001IPWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2001IRSAR
ACTIVE
QFN
RSA
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2001IRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2001TN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2001TPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2001TPWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2001TRSAR
ACTIVE
QFN
RSA
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2001TRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2002IN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2002IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2002IPWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2002IRSAR
ACTIVE
QFN
RSA
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2002IRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2002TN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2002TPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2002TPWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2002TRSAR
ACTIVE
QFN
RSA
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2002TRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2003IN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2003IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2003IPWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2003IRSAR
ACTIVE
QFN
RSA
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2003IRSAT
ACTIVE
QFN
RSA
16
250
CU NIPDAU
Level-2-260C-1 YEAR
Addendum-Page 1
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F2003TN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2003TPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2003TPWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2003TRSAR
ACTIVE
QFN
RSA
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2003TRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2011IN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2011IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2011IPWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2011IRSAR
ACTIVE
QFN
RSA
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2011IRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2011TN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2011TPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2011TPWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2011TRSAR
ACTIVE
QFN
RSA
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2011TRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2012IN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2012IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2012IPWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2012IRSAR
ACTIVE
QFN
RSA
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2012IRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2012TN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2012TPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2012TPWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2012TRSAR
ACTIVE
QFN
RSA
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2012TRSAT
ACTIVE
QFN
RSA
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2013IN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 2
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F2013IPW
ACTIVE
TSSOP
PW
14
MSP430F2013IPWR
ACTIVE
TSSOP
PW
MSP430F2013IRSAR
ACTIVE
QFN
MSP430F2013IRSAT
ACTIVE
MSP430F2013TN
90
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
RSA
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
QFN
RSA
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2013TPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2013TPWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2013TRSAR
ACTIVE
QFN
RSA
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2013TRSAT
ACTIVE
QFN
RSA
16
250
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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