LT1160/LT1162 Half-/Full-Bridge N-Channel Power MOSFET Drivers U DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ The LT ®1160/LT1162 are cost effective half-/full-bridge N-channel power MOSFET drivers. The floating driver can drive the topside N-channel power MOSFETs operating off a high voltage (HV) rail of up to 60V. Floating Top Driver Switches Up to 60V Drives Gate of Top N-Channel MOSFET above Load HV Supply 180ns Transition Times Driving 10,000pF Adaptive Nonoverlapping Gate Drives Prevent Shoot-Through Top Drive Protection at High Duty Cycles TTL/CMOS Input Levels Undervoltage Lockout with Hysteresis Operates at Supply Voltages from 10V to 15V Separate Top and Bottom Drive Pins The internal logic prevents the inputs from turning on the power MOSFETs in a half-bridge at the same time. Its unique adaptive protection against shoot-through currents eliminates all matching requirements for the two MOSFETs. This greatly eases the design of high efficiency motor control and switching regulator systems. During low supply or start-up conditions, the undervoltage lockout actively pulls the driver outputs low to prevent the power MOSFETs from being partially turned on. The 0.5V hysteresis allows reliable operation even with slowly varying supplies. U APPLICATIONS ■ ■ ■ ■ ■ ■ PWM of High Current Inductive Loads Half-Bridge and Full-Bridge Motor Control Synchronous Step-Down Switching Regulators 3-Phase Brushless Motor Drive High Current Transducer Drivers Class D Power Amplifiers The LT1162 is a dual version of the LT1160 and is available in a 24-pin PDIP or in a 24-pin SO Wide package. , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATION 1N4148 HV = 60V MAX + 12V 1 + 10µF 25V 10 + BOOST PV + T GATE DR SV T GATE FB 4 UV OUT T SOURCE 14 13 12 11 1000µF 100V IRFZ44 + CBOOST 1µF LT1160 2 PWM 0Hz TO 100kHz 3 IN TOP B GATE DR IN BOTTOM B GATE FB SGND 5 PGND 6 9 8 IRFZ44 IN TOP IN BOTTOM T GATE DR B GATE DR L L L L L H L H H L H L H H L L 1160 TA01 1 LT1160/LT1162 U W W W ABSOLUTE MAXIMUM RATINGS Supply Voltage (Note 1).......................................... 20V Boost Voltage ......................................................... 75V Peak Output Currents (< 10µs) .............................. 1.5A Input Pin Voltages .......................... – 0.3V to V + + 0.3V Top Source Voltage ..................................... – 5V to 60V Boost to Source Voltage ........................... – 0.3V to 20V Operating Temperature Range Commercial .......................................... 0°C to 70°C Industrial ......................................... – 40°C to 85°C Junction Temperature (Note 2) ............................ 125°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C W U U PACKAGE/ORDER INFORMATION ORDER PART NUMBER TOP VIEW SV + 1 14 BOOST IN TOP 2 13 T GATE DR IN BOTTOM 3 12 T GATE FB UV OUT 4 11 T SOURCE LT1160CN LT1160CS LT1160IN LT1160IS 24 BOOST A A 1 IN TOP A 2 23 T GATE DR A IN BOTTOM A 3 22 T GATE FB A UV OUT A 4 21 T SOURCE A GND A 5 20 B GATE FB A 6 19 B GATE DR A 10 PV + PGND 6 9 B GATE DR IN TOP B 8 17 T GATE DR B NC 7 8 B GATE FB IN BOTTOM B 9 16 T GATE FB B UV OUT B 10 15 T SOURCE B SV + B 7 N PACKAGE 14-LEAD PDIP 18 BOOST B 14 PV + B GND B 11 B GATE FB B 12 N PACKAGE 24-LEAD PDIP TJMAX = 125°C, θJA = 70°C/ W (N) TJMAX = 125°C, θJA = 110°C/ W (S) LT1162CN LT1162CSW LT1162IN LT1162ISW PV + A SGND 5 S PACKAGE 14-LEAD PLASTIC SO ORDER PART NUMBER TOP VIEW SV + 13 B GATE DR B SW PACKAGE 24-LEAD PLASTIC SO WIDE TJMAX = 125°C, θJA = 58°C/ W (N) TJMAX = 125°C, θJA = 80°C/ W (SW) Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS Test Circuit, TA = 25°C, V + = VBOOST = 12V, VTSOURCE = 0V, CGATE = 3000pF. Gate Feedback pins connected to Gate Drive pins, unless otherwise specified. SYMBOL PARAMETER IS DC Supply Current (Note 3) CONDITIONS V + = 15V, VINTOP = 0.8V, VINBOTTOM = 2V V + = 15V, VINTOP = 2V, VINBOTTOM = 0.8V V + = 15V, VINTOP = 0.8V, VINBOTTOM = 0.8V MIN 7 7 7 TYP 11 10 11 MAX 15 15 15 IBOOST Boost Current (Note 3) V + = 15V, VTSOURCE = 60V, VBOOST = 75V, VINTOP = VINBOTTOM = 0.8V 3 4.5 6 VIL Input Logic Low ● 1.4 0.8 VIH Input Logic High ● IIN Input Current V +UVH UNITS mA mA mA mA V 2 1.7 7 25 µA V + Undervoltage Start-Up Threshold 8.4 8.9 9.4 V V +UVL V + Undervoltage Shutdown Threshold 7.8 8.3 8.8 V VBUVH VBOOST Undervoltage Start-Up Threshold VTSOURCE = 60V (VBOOST – VTSOURCE) 8.8 9.3 9.8 V VBUVL VBOOST Undervoltage Shutdown Threshold VTSOURCE = 60V (VBOOST – VTSOURCE) 8.2 8.7 9.2 V 2 VINTOP = VINBOTTOM = 4V ● V LT1160/LT1162 ELECTRICAL CHARACTERISTICS Test Circuit, TA = 25°C, V + = VBOOST = 12V, VTSOURCE = 0V, CGATE = 3000pF. Gate Feedback pins connected to Gate Drive pins, unless otherwise specified. SYMBOL PARAMETER CONDITIONS IUVOUT Undervoltage Output Leakage V + = 15V VUVOUT Undervoltage Output Saturation V + = 7.5V, I VOH Top Gate ON Voltage VINTOP = 2V, VINBOTTOM = 0.8V ● 11 Bottom Gate ON Voltage VINTOP = 0.8V, VINBOTTOM = 2V ● 11 Top Gate OFF Voltage VINTOP = 0.8V, VINBOTTOM = 2V Bottom Gate OFF Voltage VINTOP = 2V, VINBOTTOM = 0.8V Top Gate Rise Time VOL tr tf t D1 t D2 t D3 t D4 MIN TYP MAX 0.1 5 µA 0.2 0.4 V 11.3 12 V 11.3 12 V ● 0.4 0.7 V ● 0.4 0.7 V VINTOP (+) Transition, VINBOTTOM = 0.8V, Measured at VTGATE DR (Note 4) ● 130 200 ns Bottom Gate Rise Time VINBOTTOM (+) Transition, VINTOP = 0.8V, Measured at VBGATE DR (Note 4) ● 90 200 ns Top Gate Fall Time VINTOP (–) Transition, VINBOTTOM = 0.8V, Measured at VTGATE DR (Note 4) ● 60 140 ns Bottom Gate Fall Time VINBOTTOM (–) Transition, VINTOP = 0.8V, Measured at VBGATE DR (Note 4) ● 60 140 ns Top Gate Turn-On Delay VINTOP (+) Transition, VINBOTTOM = 0.8V, Measured at VTGATE DR (Note 4) ● 250 500 ns Bottom Gate Turn-On Delay VINBOTTOM (+) Transition, VINTOP = 0.8V, Measured at VBGATE DR (Note 4) ● 200 400 ns Top Gate Turn-Off Delay VINTOP (–) Transition, VINBOTTOM = 0.8V, Measured at VTGATE DR (Note 4) ● 300 600 ns Bottom Gate Turn-Off Delay VINBOTTOM (–) Transition, VINTOP = 0.8V, Measured at VBGATE DR (Note 4) ● 200 400 ns Top Gate Lockout Delay VINBOTTOM (+) Transition, VINTOP = 2V, Measured at VTGATE DR (Note 4) ● 300 600 ns Bottom Gate Lockout Delay VINTOP (+) Transition, VINBOTTOM = 2V, Measured at VBGATE DR (Note 4) ● 250 500 ns Top Gate Release Delay VINBOTTOM (–) Transition, VINTOP = 2V, Measured at VTGATE DR (Note 4) ● 250 500 ns Bottom Gate Release Delay VINTOP (–) Transition, VINBOTTOM = 2V, Measured at VBGATE DR (Note 4) ● 200 400 ns ● UVOUT = 2.5mA The ● denotes specifications which apply over the full operating temperature range. Note 1: For the LT1160, Pins 1, 10 should be connected together. For the LT1162, Pins 1, 7, 14, 20 should be connected together. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LT1160CN/LT1160IN: TJ = TA + (PD)(70°C/W) LT1160CS/LT1160IS: TJ = TA + (PD)(110°C/W) LT1162CN/LT1162IN: TJ = TA + (PD)(58°C/W) LT1162CS/LT1162IS: TJ = TA + (PD)(80°C/W) ● UNITS Note 3: IS is the sum of currents through SV +, PV + and Boost pins. IBOOST is the current through the Boost pin. Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Typical Performance Characteristics and Applications Information sections. The LT1160 = 1/2 LT1162. Note 4: See Timing Diagram. Gate rise times are measured from 2V to 10V and fall times are measured from 10V to 2V. Delay times are measured from the input transition to when the gate voltage has risen to 2V or decreased to 10V. 3 LT1160/LT1162 U W TYPICAL PERFORMANCE CHARACTERISTICS DC Supply Current vs Supply Voltage DC + Dynamic Supply Current vs Input Frequency DC Supply Current vs Temperature 14 60 V + = 12V 13 13 SUPPLY CURRENT (mA) BOTH INPUTS HIGH OR LOW 12 11 10 VINTOP = HIGH VINBOTTOM = LOW 9 VINTOP = LOW VINBOTTOM = HIGH 8 7 11 BOTH INPUTS HIGH OR LOW 10 9 8 VINTOP = HIGH VINBOTTOM = LOW 7 50% DUTY CYCLE CGATE = 3000pF 50 VINTOP = LOW VINBOTTOM = HIGH 12 SUPPLY CURRENT (mA) 14 SUPPLY CURRENT (mA) (LT1160 or 1/2 LT1162) 40 V + = 20V 30 V + = 15V 20 V + = 10V 10 6 6 5 –50 5 10 12 14 16 18 SUPPLY VOLTAGE (V) 20 22 0 –25 0 25 50 75 TEMPERATURE (°C) 100 DC + Dynamic Supply Current vs Input Frequency 60 50% DUTY CYCLE V+ = 12V SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA) 30 CGATE = 3000pF 20 13 12 12 10 START-UP THRESHOLD 9 8 SHUTDOWN THRESHOLD 7 6 10 0 CGATE = 1000pF 1 10 100 INPUT FREQUENCY (kHz) 5 –25 0 25 50 75 TEMPERATURE (°C) 1160/62 G04 1.2 1.0 0 25 50 75 TEMPERATURE (°C) 7 6 100 125 1160/62 G07 –25 0 25 50 75 TEMPERATURE (°C) 125 5.0 V + = 12V 4.5 4.0 11 10 9 8 7 3.5 3.0 2.5 2.0 1.5 6 1.0 5 0.5 4 –50 100 Top or Bottom Input Pin Current vs Input Voltage INPUT CURRENT (mA) 1.4 SHUTDOWN THRESHOLD 8 1160/62 G06 12 INPUT CURRENT (µA) INPUT THRESHOLD VOLTAGE (V) VHIGH VLOW START-UP THRESHOLD 9 4 –50 125 V + = 12V VIN = 4V 13 1.6 4 100 14 V + = 12V –25 10 Top or Bottom Input Pin Current vs Temperature 2.0 0.8 –50 11 1160/62 G05 Input Threshold Voltage vs Temperature 1.8 VTSOURCE = 60V 5 4 –50 1000 1000 Undervoltage Lockout (VBOOST) 13 11 CGATE = 10000pF 10 100 INPUT FREQUENCY (kHz) 1160/62 G03 Undervoltage Lockout (V +) 40 1 1160/62 G02 1160/62 G01 50 125 VBOOST – VTSOURCE VOLTAGE (V) 8 –25 50 25 0 75 TEMPERATURE (°C) 100 125 1160/62 G08 0 4 5 6 10 8 7 9 INPUT VOLTAGE (V) 11 12 1160/62 G09 LT1160/LT1162 U W TYPICAL PERFORMANCE CHARACTERISTICS Bottom Gate Rise Time vs Temperature Bottom Gate Fall Time vs Temperature 210 V + = 12V CLOAD = 10000pF 170 150 130 110 CLOAD = 3000pF 90 70 50 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 CLOAD = 10000pF 150 130 110 90 CLOAD = 3000pF 70 CLOAD = 1000pF 200 180 160 –25 0 25 50 75 TEMPERATURE (°C) 100 180 CLOAD = 10000pF TURN ON DELAY TIME (ns) 350 100 80 CLOAD = 3000pF –25 0 25 50 75 TEMPERATURE (°C) 125 Turn-Off Delay Time vs Temperature 400 V + = 12V CLOAD = 3000pF 350 300 TOP DRIVER 250 200 BOTTOM DRIVER 150 40 100 1160/62 G12 400 V + = 12V 120 CLOAD = 1000pF 80 –50 125 Turn-On Delay Time vs Temperature 140 CLOAD = 3000pF 140 1160/62 G11 Top Gate Fall Time vs Temperature V + = 12V CLOAD = 3000pF 300 TOP DRIVER 250 BOTTOM DRIVER 200 150 CLOAD = 1000pF 0 25 50 75 100 100 –50 125 –25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) 11160/62 G13 Lockout Delay Time vs Temperature –25 0 25 50 75 TEMPERATURE (°C) 100 125 1160/62 G15 400 V + = 12V CLOAD = 3000pF 350 TOP DRIVER 300 BOTTOM DRIVER 250 200 150 100 –50 100 –50 125 Release Delay Time vs Temperature 400 350 100 1160/62 G14 RELEASE DELAY TIME (ns) 20 –50 –25 LOCKOUT DELAY TIME (ns) TOP GATE FALL TIME (ns) 220 120 1160/62 G10 60 240 100 30 –50 125 CLOAD = 10000pF 260 170 50 CLOAD = 1000pF V + = 12V 280 TURN OFF DELAY TIME (ns) 190 300 V + = 12V 190 BOTTOM GATE FALL TIME (ns) 210 BOTTOM GATE RISE TIME (ns) Top Gate Rise Time vs Temperature TOP GATE RISE TIME (ns) 230 160 (LT1160 or 1/2 LT1162) V + = 12V CLOAD = 3000pF 300 TOP DRIVER 250 200 BOTTOM DRIVER 150 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1160/62 G16 100 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1160/62 G17 5 LT1160/LT1162 U U U PIN FUNCTIONS LT1160 LT1162 SV+ (Pin 1): Main Signal Supply. Must be closely decoupled to the signal ground Pin 5. SV + (Pins 1, 7): Main Signal Supply. Must be closely decoupled to ground Pins 5 and 11. IN TOP (Pin 2): Top Driver Input. Pin 2 is disabled when Pin 3 is high. A 3k input resistor followed by a 5V internal clamp prevents saturation of the input transistors. IN TOP (Pins 2, 8): Top Driver Input. The Input Top is disabled when the Input Bottom is high. A 3k input resistor followed by a 5V internal clamp prevents saturation of the input transistors. IN BOTTOM (Pin 3): Bottom Driver Input. Pin 3 is disabled when Pin 2 is high. A 3k input resistor followed by a 5V internal clamp prevents saturation of the input transistors. UV OUT (Pin 4): Undervoltage Output. Open collector NPN output which turns on when V + drops below the undervoltage threshold. SGND (Pin 5): Small Signal Ground. Must be routed separately from other grounds to the system ground. PGND (Pin 6): Bottom Driver Power Ground. Connects to source of bottom N-channel MOSFET. B GATE FB (Pin 8): Bottom Gate Feedback. Must connect directly to the bottom power MOSFET gate. The top MOSFET turn-on is inhibited until Pin 8 has discharged to below 2.5V. B GATE DR (Pin 9): Bottom Gate Drive. The high current drive point for the bottom MOSFET. When a gate resistor is used it is inserted between Pin 9 and the gate of the MOSFET. PV + (Pin 10): Bottom Driver Supply. Must be connected to the same supply as Pin 1. T SOURCE (Pin 11): Top Driver Return. Connects to the top MOSFET source and the low side of the bootstrap capacitor. T GATE FB (Pin 12): Top Gate Feedback. Must connect directly to the top power MOSFET gate. The bottom MOSFET turn-on is inhibited until V12 – V11 has discharged to below 2.9V. IN BOTTOM (Pins 3, 9): Bottom Driver Input. The Input Bottom is disabled when the Input Top is high. A 3k input resistor followed by a 5V internal clamp prevents saturation of the input transistors. UV OUT (Pins 4, 10): Undervoltage Output. Open collector NPN output which turns on when V + drops below the undervoltage threshold. GND (Pins 5, 11): Ground Connection. B GATE FB (Pins 6, 12): Bottom Gate Feedback. Must connect directly to the bottom power MOSFET gate. The top MOSFET turn-on is inhibited until Bottom Gate Feedback pins have discharged to below 2.5V. B GATE DR (Pins 13, 19): Bottom Gate Drive. The high current drive point for the bottom MOSFET. When a gate resistor is used it is inserted between the Bottom Gate Drive pin and the gate of the MOSFET. PV + (Pins 14, 20): Bottom Driver Supply. Must be connected to the same supply as Pins 1 and 7. T SOURCE (Pins 15, 21): Top Driver Return. Connects to the top MOSFET source and the low side of the bootstrap capacitor. T GATE FB (Pins 16, 22): Top Gate Feedback. Must connect directly to the top power MOSFET gate. The bottom MOSFET turn-on is inhibited until VTGF – VTSOURCE has discharged to below 2.9V. T GATE DR (Pin 13): Top Gate Drive. The high current drive point for the top MOSFET. When a gate resistor is used it is inserted between Pin 13 and the gate of the MOSFET. T GATE DR (Pins 17, 23): Top Gate Drive. The high current drive point for the top MOSFET. When a gate resistor is used it is inserted between the Top Gate Drive pin and the gate of the MOSFET. BOOST (Pin 14): Top Driver Supply. Connects to the high side of the bootstrap capacitor. BOOST (Pins 18, 24): Top Driver Supply. Connects to the high side of the bootstrap capacitor. 6 LT1160/LT1162 W FUNCTIONAL DIAGRA (LT1160 or 1/2 LT1162) U U BOOST TOP UV LOCK SV + BIAS T GATE DR – 3k IN TOP T GATE FB + 5V 2.9V T SOURCE PV + 3k IN BOTTOM 5V BOTTOM UV LOCK – UV OUT B GATE DR + 2.5V SGND LT1160 PGND 1/2 LT1162 GND B GATE FB 1160/62 BD TEST CIRCUIT (LT1160 or 1/2 LT1162) SV + + V/I 1µF BOOST + V/I T GATE DR 3k IN TOP IN BOTTOM T GATE FB UV OUT T SOURCE + 1µF 3000pF V + PV + V (LT1160) 50Ω 50Ω SGND B GATE DR PGND B GATE FB + V 3000pF 1160/62 TC01 7 LT1160/LT1162 WU W TI I G DIAGRA 2V IN TOP 0.8V 2V IN BOTTOM 0.8V tr 12V t D3 t D2 10V TOP GATE DRIVER 2V 0V t D1 tr 12V BOTTOM GATE DRIVER 0V t D3 tf t D4 t D2 10V 2V t D1 tf t D4 1160/62 TD U OPERATIO (Refer to Functional Diagram) The LT1160 (or 1/2 LT1162) incorporates two independent driver channels with separate inputs and outputs. The inputs are TTL/CMOS compatible; they can withstand input voltages as high as V+. The 1.4V input threshold is regulated and has 300mV of hysteresis. Both channels are noninverting drivers. The internal logic prevents both outputs from simultaneously turning on under any input conditions. When both inputs are high both outputs are actively held low. The floating supply for the top driver is provided by a bootstrap capacitor between the Boost pin and the Top Source pin. This capacitor is recharged each time the negative plate goes low in PWM operation. The undervoltage detection circuit disables both channels when V + is below the undervoltage trip point. A separate 8 UV detect block disables the high side channel when VBOOST – VTSOURCE is below its own undervoltage trip point. The top and bottom gate drivers in the LT1160 each utilize two gate connections: 1) a gate drive pin, which provides the turn on and turn off currents through an optional series gate resistor, and 2) a gate feedback pin which connects directly to the gate to monitor the gate-to-source voltage. Whenever there is an input transition to command the outputs to change states, the LT1160 follows a logical sequence to turn off one MOSFET and turn on the other. First, turn-off is initiated, then VGS is monitored until it has decreased below the turn-off threshold, and finally the other gate is turned on. LT1160/LT1162 U W U U APPLICATIONS INFORMATION Power MOSFET Selection Paralleling MOSFETs Since the LT1160 (or 1/2 LT1162) inherently protects the top and bottom MOSFETs from simultaneous conduction, there are no size or matching constraints. Therefore selection can be made based on the operating voltage and RDS(ON) requirements. The MOSFET BVDSS should be greater than the HV and should be increased to approximately (2)(HV) in harsh environments with frequent fault conditions. For the LT1160 maximum operating HV supply of 60V, the MOSFET BVDSS should be from 60V to 100V. When the above calculations result in a lower RDS(ON) than is economically feasible with a single MOSFET, two or more MOSFETs can be paralleled. The MOSFETs will inherently share the currents according to their RDS(ON) ratio as long as they are thermally connected (e.g., on a common heat sink). The LT1160 top and bottom drivers can each drive five power MOSFETs in parallel with only a small loss in switching speeds (see Typical Performance Characteristics). A low value resistor (10Ω to 47Ω) in series with each individual MOSFET gate may be required to “decouple” each MOSFET from its neighbors to prevent high frequency oscillations (consult manufacturer’s recommendations). If gate decoupling resistors are used the corresponding gate feedback pin can be connected to any one of the gates as shown in Figure 1. The MOSFET RDS(ON) is specified at TJ = 25°C and is generally chosen based on the operating efficiency required as long as the maximum MOSFET junction temperature is not exceeded. The dissipation while each MOSFET is on is given by: P = D(IDS)2(1+∂)RDS(ON) Where D is the duty cycle and ∂ is the increase in RDS(ON) at the anticipated MOSFET junction temperature. From this equation the required RDS(ON) can be derived: RDS(ON) = P ( )( ) 2 D IDS 1 + ∂ For example, if the MOSFET loss is to be limited to 2W when operating at 5A and a 90% duty cycle, the required RDS(ON) would be 0.089Ω/(1 + ∂). (1 + ∂) is given for each MOSFET in the form of a normalized RDS(ON) vs temperature curve, but ∂ = 0.007/°C can be used as an approximation for low voltage MOSFETs. Thus, if TA = 85°C and the available heat sinking has a thermal resistance of 20°C/W, the MOSFET junction temperature will be 125°C and ∂ = 0.007(125 – 25) = 0.7. This means that the required RDS(ON) of the MOSFET will be 0.089Ω/1.7 = 0.0523Ω, which can be satisfied by an IRFZ34 manufactured by International Rectifier. Transition losses result from the power dissipated in each MOSFET during the time it is transitioning from off to on, or from on to off. These losses are proportional to (f)(HV)2 and vary from insignificant to being a limiting factor on operating frequency in some high voltage applications. Driving multiple MOSFETs in parallel may restrict the operating frequency to prevent overdissipation in the LT1160 (see the following Gate Charge and Driver Dissipation). GATE DR LT1160 RG * RG* GATE FB *OPTIONAL 10Ω 1160 F01 Figure 1. Paralleling MOSFETs Gate Charge and Driver Dissipation A useful indicator of the load presented to the driver by a power MOSFET is the total gate charge QG, which includes the additional charge required by the gate-to-drain swing. QG is usually specified for VGS = 10V and VDS = 0.8VDS(MAX). When the supply current is measured in a switching application, it will be larger than given by the DC electrical characteristics because of the additional supply current associated with sourcing the MOSFET gate charge: dQ dQ ISUPPLY = IDC + G + G dt TOP dt BOTTOM 9 LT1160/LT1162 U W U U APPLICATIONS INFORMATION The actual increase in supply current is slightly higher due to LT1160 switching losses and the fact that the gates are being charged to more than 10V. Supply Current vs Input Frequency is given in the Typical Performance Characteristics. The LT1160 junction temperature can be estimated by using the equations given in Note 2 of the Electrical Characteristics. For example, the LT1160IS is limited to less than 31mA from a 12V supply: TJ = 85°C + (31mA)(12V)(110°C/W) = 126°C exceeds absolute maximum In order to prevent the maximum junction temperature from being exceeded, the LT1160 supply current must be verified while driving the full complement of the chosen MOSFET type at the maximum switching frequency. Ugly Transient Issues In PWM applications the drain current of the top MOSFET is a square wave at the input frequency and duty cycle. To prevent large voltage transients at the top drain, a low ESR electrolytic capacitor must be used and returned to the power ground. The capacitor is generally in the range of 25µF to 5000µF and must be physically sized for the RMS current flowing in the drain to prevent heating and premature failure. In addition, the LT1160 requires a separate 10µF capacitor connected closely between Pins 1 and 5 (the LT1162 requires two 10µF capacitors connected between Pins 1 and 5, and Pins 7 and 11). The LT1160 top source is internally protected against transients below ground and above supply. However, the gate drive pins cannot be forced below ground. In most applications, negative transients coupled from the source to the gate of the top MOSFET do not cause any problems. Switching Regulator Applications The LT1160 (or 1/2 LT1162) is ideal as a synchronous switch driver to improve the efficiency of step-down (buck) switching regulators. Most step-down regulators use a high current Schottky diode to conduct the inductor current when the switch is off. The fractions of the oscil- 10 lator period that the switch is on (switch conducting) and off (diode conducting) are given by: V Switch ON = OUT (Total Period) HV HV – VOUT Switch OFF = (Total Period) HV Note that for HV > 2VOUT the switch is off longer than it is on, making the diode losses more significant than the switch. The worst case for the diode is during a short circuit, when VOUT approaches zero and the diode conducts the short-circuit current almost continuously. Figure 2 shows the LT1160 used to synchronously drive a pair of power MOSFETs in a step-down regulator application, where the top MOSFET is the switch and the bottom MOSFET replaces the Schottky diode. Since both conduction paths have low losses, this approach can result in very high efficiency (90% to 95%) in most applications. For regulators under 10A, using low RDS(ON) N-channel MOSFETs eliminates the need for heat sinks. RGS holds the top MOSFET off when HV is applied before the 12V supply. One fundamental difference in the operation of a stepdown regulator with synchronous switching is that it never becomes discontinuous at light loads. The inductor current doesn’t stop ramping down when it reaches zero but actually reverses polarity resulting in a constant ripple current independent of load. This does not cause a significant efficiency loss (as might be expected) since the negative inductor current is returned to HV when the switch turns back on. However, I2R losses will occur under these conditions due to the recirculating currents. The LT1160 performs the synchronous MOSFET drive in a step-down switching regulator. A reference and PWM are required to complete the regulator. Any voltage mode or current mode PWM controller may be used but the LT3526 is particularly well-suited to high power, high efficiency applications such as the 10A circuit shown in Figure 4. In higher current regulators a small Schottky diode across the bottom MOSFET helps to reduce reverse-recovery switching losses. LT1160/LT1162 U U W U APPLICATIONS INFORMATION HV BOOST 12V SV + T GATE DR PV + T GATE FB LT1160 REF PWM + RGS RSENSE T SOURCE OUT A IN TOP OUT A IN BOTTOM B GATE FB + VOUT B GATE DR 1160 F02 Figure 2. Adding Synchronous Switching to a Step-Down Switching Regulator Motor Drive Applications In applications where rotation is always in the same direction, a single LT1160 controlling a half-bridge can be used to drive a DC motor. One end of the motor may be connected either to supply or to ground as seen on Figure 3. A motor in this configuration is controlled by its inputs which give three alternatives: run, free running stop (coasting) and fast stop (“plugging” braking, with the motor shorted by one of the MOSFETs). To drive a DC motor in both directions the LT1162 can be used to drive an H-bridge output stage. In this configuration the motor can be made to run clockwise, counterclockwise, stop rapidly (“plugging” braking) or free run (coast) to a stop. A very rapid stop may be achieved by reversing the current, though this requires more careful design to stop the motor dead. In practice a closed-loop control system with tachometric feedback is usually necessary. The motor speed in these examples can be controlled by switching the drivers with pulse width modulated square waves. This approach is particularly suitable for microcomputers/DSP control loops. + HV LT1160 12V SV + BOOST + T GATE DR PV T GATE FB T SOURCE IN TOP B GATE DR IN BOTTOM B GATE FB PGND 1160 F03 Figure 3. Driving a Supply Referenced Motor 11 LT1160/LT1162 U TYPICAL APPLICATIONS C1 0.1µF 4.7k 0.1µF + 60V MAX 10µF 2 17 3 16 4 15 5 0.1µF 510Ω 1 SV 2 14 LT3526 1k 1N4148 13 7 12 8 11 6 9 10 7 27k BOOST T GATE DR IN BOTTOM T GATE FB 4 T SOURCE UV OUT 5 1k + IN TOP 3 6 5k SHUTDOWN + LT1160 1N4148 + 1µF + 1N4148 0.33µF 2k 12V + 18 1 360Ω 0.022µF 1µF 4.7k 14 13 12 PGND B GATE DR NC B GATE FB IRFZ44 0.1µF 330k 11 10 PV + SGND 2N2222 2200µF EA LOW ESR L* 70µH RS** 0.007Ω 5V + IRFZ44 IRFZ44 9 MBR340 5400µF LOW ESR 8 2.2nF f = 25kHz * MAGNETICS CORE #55585-A2 30 TURNS 14GA MAGNET WIRE ** DALE TYPE LVR-3 ULTRONIX RCS01 1160/62 F04 Figure 4. 90% Efficiency, 40V to 5V 10A Low Dropout Voltage Mode Switching Regulator 12V 2200µF EA LOW ESR 1N4148 + 2k 2.2µF 10k 1 16 2 15 3 + 14 4 1µF 18k 0.1µF 6800pF 25k + + 10µF 2 1k 13 3 LT1846 5 12 4 6 11 5 7 10 1N4148 5k 6 100pF 8 9 500k 18k * HURRICANE LAB HL-KM147U 7 10k 4700pF 1k 2N2222 60V MAX LT1160 1 1N4148 + SV + IN TOP BOOST T GATE DR IN BOTTOM T GATE FB UV OUT T SOURCE SGND PV + PGND B GATE DR NC B GATE FB 14 13 12 IRFZ44 0.1µF 330k 11 L* 47µH 5V + 10 IRFZ44 IRFZ44 5400µF LOW ESR 9 MBR340 8 f = 40kHz ** DALE TYPE LVR-3 ULTRONIX RCS01 Figure 5. 90% Efficiency, 40V to 5V 10A Low Dropout Current Mode Switching Regulator 12 RS** 0.007Ω 1160/62 F05 LT1160/LT1162 U TYPICAL APPLICATIONS 100µF 10k + IN 150k 0.0033µF 1k 12V 60V MAX + 10µF 5V 0.1µF 1N4148 0.1µF 1000µF + LT1162 1k 1 8 1 8 1 2 7 2 7 2 6 3 6 3 5 4 5 4 3 100k 1k LT1015 4 TC4428 5 1k 8 1 7 2 6 3 1µF 10µF + LT1016 + 6 8 0.1µF 5 4 9 10k 10 11 1k 0.0033µF + 10k 1 14 2 13 10k 47µF 3 12 4 11 10k 95k 5 200k 6 LT1058 12 150k 47µF + 7 SV + A BOOST A IN TOP A T GATE DR A IN BOTTOM A T GATE FB A UV OUT A T SOURCE A PV + A GND A B GATE FB A B GATE DR A SV + B BOOST B IN TOP B T GATE DR B IN BOTTOM B T GATE FB B UV OUT B T SOURCE B PV + B GND B B GATE FB B B GATE DR B 22 0.1µF 330k 21 20 IRFZ44 1N4148 L* 158µH + 10µF 19 1000µF 18 IRFZ44 17 16 + 0.1µF 330k LOAD 15 L* 158µH 14 IRFZ44 13 + 10µF –12V 0.1µF 10 95k + 9 8 IRFZ44 23 10k 47µF 10k 47µF 7 24 + 10k * Kool Mµ® CORE #77548-A7 35 TURNS 14GA MAGNET WIRE fCARRIER = 100kHz 200k 1160/62 F06 Figure 6. 200W Class D, 10Hz to 1kHz Amplifier Kool Mµ is a registered trademark of Magnetics, Inc. 13 LT1160/LT1162 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N Package 14-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.770* (19.558) MAX 14 13 12 11 10 9 8 1 2 3 4 5 6 7 0.255 ± 0.015* (6.477 ± 0.381) 0.130 ± 0.005 (3.302 ± 0.127) 0.300 – 0.325 (7.620 – 8.255) 0.045 – 0.065 (1.143 – 1.651) 0.015 (0.380) MIN 0.065 (1.651) TYP 0.009 – 0.015 (0.229 – 0.381) +0.025 0.325 –0.015 0.005 (0.125) MIN 0.100 ± 0.010 (2.540 ± 0.254) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) ( +0.635 8.255 –0.381 ) 0.018 ± 0.003 (0.457 ± 0.076) 0.125 (3.175) MIN N14 0695 N Package 24-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 1.265* (32.131) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 0.255 ± 0.015* (6.477 ± 0.381) 0.300 – 0.325 (7.620 – 8.255) 0.130 ± 0.005 (3.302 ± 0.127) 0.045 – 0.065 (1.143 – 1.651) 0.015 (0.381) MIN 0.009 – 0.015 (0.229 – 0.381) 0.125 (3.175) MIN 0.005 (0.127) MIN +0.635 8.255 0.100 ± 0.010 –0.381 (2.540 ± 0.254) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) ( 14 +0.025 0.325 –0.015 ) 0.065 (1.651) TYP 0.018 ± 0.003 (0.457 ± 0.076) N24 0695 LT1160/LT1162 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. S Package 14-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.337 – 0.344* (8.560 – 8.738) 14 13 12 11 10 9 8 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 2 3 4 5 6 0.053 – 0.069 (1.346 – 1.752) 0.004 – 0.010 (0.101 – 0.254) 0° – 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) 7 0.050 (1.270) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. S14 0695 15 LT1160/LT1162 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. SW Package 24-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.598 – 0.614* (15.190 – 15.600) 24 23 22 21 20 19 18 17 16 15 14 13 0.394 – 0.419 (10.007 – 10.643) NOTE 1 0.291 – 0.299** (7.391 – 7.595) 1 2 3 4 5 6 7 8 10 11 12 0.037 – 0.045 (0.940 – 1.143) 0.093 – 0.104 (2.362 – 2.642) 0.010 – 0.029 × 45° (0.254 – 0.737) 9 0° – 8° TYP 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.050 (1.270) TYP 0.016 – 0.050 (0.406 – 1.270) 0.004 – 0.012 (0.102 – 0.305) 0.014 – 0.019 (0.356 – 0.482) NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS. S24 (WIDE) 0695 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1158 Half-Bridge N-Channel Power MOSFET Driver Single Input, Continuous Current Protection and Internal Charge Pump for DC Operation LT1336 Half-Bridge N-Channel Power MOSFET Driver with Boost Regulator Onboard Boost Regulator to Supply the High Side Driver 16 Linear Technology Corporation LT/GP 0196 10K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977 LINEAR TECHNOLOGY CORPORATION 1995