Intersil CDP1851DX Cmos programmable i/o interface Datasheet

CDP1851,
CDP1851C
CMOS Programmable I/O Interface
March 1997
Features
Description
• 20 Programmable I/O Lines
THE CDP1851 and CDP1851C are CMOS programmable twoport I/Os designed for use as general-purpose I/O devices.
They are directly compatible with CDP1800-series microprocessors functioning at maximum clock frequency. Each port
can be programmed in either byte-I/O or bit-programmable
modes for interfacing with peripheral devices such as printers
and keyboards.
• Programmable for Operation in Four Modes:
- Input
- Output
- Bidirectional
- Bit-programmable
Both ports A and B can be separately programmed to be 8-bit
input or output ports with handshaking control lines, RDY and
STROBE. Only port A can be programmed to be a bidirectional
port. This configuration provides a means for communicating
with a peripheral device or microprocessor system on a single
8-bit bus for both transmitting and receiving data. Handshaking
signals are provided to maintain proper bus access control.
Port A handshaking lines are used for input control and port B
handshaking lines are used for output; therefore port B must be
in the bit-programmable mode where handshaking is not used.
• Operates in Either I/O or Memory Space
Ordering Information
PACKAGE TEMP. RANGE
5V
10V
-40oC to +85oC CDP1851CE
PDIP
Burn-In
SBDIP
CDP1851E E40.6
CDP1851CEX
-40oC to +85oC CDP1851CD
Burn-In
PKG.
NO.
-
E40.6
-
D40.6
Ports A and B can be separately bit programmed so that each
individual line can be designated as an input or output line. The
handshaking lines may also be individually programmed as
input or output when port A is not in bidirectional mode.
CDP1851CDX CDP1851DX D40.6
The CDP1851 has a supply-voltage range of 4V to 10.5V, and
the CDP1851C has a range of 4V to 6.5V. Both types are supplied in 40-lead dual-in-line plastic (E suffix) or hermetic
ceramic (D suffix) packages. The CDP1851C is also available
in chip form (H suffix).
Pinout
CDP1851 Programming Modes
CDP1851, CDP1851C
(PDIP, SBDIP)
TOP VIEW
CLOCK 1
40 VDD
CS 2
39 RD/WE
RA0 3
38 WR/RE
RA1 4
37 TPB
BUS0 5
BUS2 7
36 A RDY
35 A
STROBE
34 A0
BUS3 8
33 A1
BUS4 9
32 A2
BUS5 10
31 A3
BUS6 11
30 A4
BUS7 12
29 A5
CLEAR 13
28 A6
A INT 14
27 A7
B INT 15
26 B7
B RDY 16
B 17
STROBE
B0 18
25 B6
B1 19
22 B3
VSS 20
21 B2
BUS1 6
MODE
(8)
PORT A
DATA PINS
(2)
PORT A
HANDSHAKING
PINS
(2)
PORT B
HANDSHAKING
PINS
(8)
PORT B
DATA PINS
Input
Accept Input
Data
READY, STROBE
Accept Input Data
READY, STROBE
Output
Output Data
READY, STROBE
Output Data
READY, STROBE
Bidirectional
(Port A Only)
Transfer Input/Output Data
Input Handshaking
for Port A
Must be Previously Set to Bit-Programmable Mode
Output Handshaking
for Port A
Bit-Programmable
Programmed Individually as Inputs or Outputs
Programmed Individually as Inputs or
Outputs
Programmed Individually as Inputs
or Outputs
Programmed Individually as Inputs or
Outputs
24 B5
23 B4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-5
File Number
1056.2
CDP1851, CDP1851C
Absolute Maximum Ratings
Thermal Information
DC Supply-Voltage Range, (VDD)
(Voltage Referenced to VSS Terminal)
CDP1851 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to+11V
CDP1851C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5 to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Device Dissipation Per Output Transistor
For TA = Full Package-Temperature Range
(All Package Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mW
Operating-Temperature Range (TA)
Package Type D, H . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
50
N/A
SBDIP Package . . . . . . . . . . . . . . . . . .
36
12
Maximum Storage Temperature Range (TSTG) . . . . -65oC to +150oC
Maximum Lead Temperature (During Soldering)
At Distance 1/16 ± 1/32 inch (1.59 ± 0.79mm)
from Case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Operating Conditions
At TA = Full Package-Temperature Range. For Maximum Reliability, Operating Conditions Should be
Selected so that Operation is Always within the Following Ranges:
LIMITS
CDP1851
PARAMETER
DC Operating Voltage Range
Input Voltage Range
CDP1851C
MIN
MAX
MIN
MAX
UNITS
4
10.5
4
6.5
V
VSS
VDD
VSS
VDD
V
Functional Diagram
DATA
BUS
DATA
BUS
BUFFER
SECTION
A
CLOCK
CS
RA0
RA1
WR/RD
RD/WR
TPB
CLEAR
A INT
B INT
ADDRESS
DECODE
AND
READ/
WRITE
LOGIC
A0
A1
A2
A3
A4
A5
A6
A7
READY
STROBE
MODE
CONTROL
AND
STATUS
REGISTERS
INTERRUPT
MASKING
AND
LOGIC
SECTION
B
B0
B1
B2
B3
B4
B5
B6
B7
READY
STROBE
FIGURE 1. FUNCTIONAL DIAGRAM FOR CDP1851 AND CDP1851C
4-6
CDP1851, CDP1851C
Static Electrical Specifications
At TA = -40oC to +85oC, VDD 5%, Unless Otherwise Specified
CONDITIONS
LIMITS
CDP1851
PARAMETER
Quiescent Device Current
IDD
Output Low Drive
(Sink) Current
IOL
Output High Drive
(Source) Current
IOH
Output Voltage Low-Level
(Note 2)
VOL
Output Voltage High Level
(Note 2)
VOH
Input Low Voltage
VIL
Input High Voltage
VlH
Input Leakage Current
IlN
Three-State Output Leakage
Current
IOUT
Operating Current (Note 3)
IDD1
VO
(V)
VIN
(V)
VDD
(V)
MIN
(NOTE1)
TYP
MAX
MIN
(NOTE1)
TYP
MAX
UNITS
-
0, 5
5
-
0.01
50
-
0.02
200
µA
-
0, 10
10
-
1
200
-
-
-
µA
0.4
0, 5
5
1.6
3.2
-
1.6
3.2
-
mA
0.5
0, 10
10
2.6
5.2
-
-
-
-
mA
4.6
0, 5
5
-1.15
-2.3
-
-1.15
-2.3
-
mA
9.5
0, 10
10
-2.6
-5.2
-
-
-
-
mA
-
0, 5
5
-
0
0.1
-
0
0.1
V
-
0, 10
10
-
0
0.1
-
-
-
V
-
0, 5
5
4.9
5
-
4.9
5
-
V
-
0, 10
10
9.9
10
-
-
-
-
V
0.5,
4.5
-
5
-
-
1.5
-
-
1.5
V
0.5,
9.5
-
10
-
-
3
-
-
-
V
0.5,
4.5
-
5
3.5
-
-
3.5
-
-
V
0.5,
9.5
-
10
7
-
-
-
-
-
V
0, 5
5
-
-
±1
-
-
±1
µA
0, 10
10
-
-
±2
-
-
-
µA
0, 5
0, 5
5
-
-
±1
-
-
±1
µA
0, 10
0, 10
10
-
-
±1
-
-
-
µA
Any
Input
-
0, 5
5
-
1.5
3
-
1.5
3
mA
-
0, 10
10
-
6
12
-
-
-
mA
CIN
-
-
-
-
5
7.5
-
5
7.5
pF
COUT
-
-
-
-
10
15
-
10
15
pF
Input Capacitance
Output Capacitance
CDP1851C
NOTES:
1. Typical values are for TA = 25oC and nominal VDD.
2. IOL = IOH = 1µA
3. Operating current is measured at 200kHz for VDD = 5V and 400kHz for VDD = 10V, with open output (worst-case frequencies for
CDP1802A system operating at maximum speed of 3.2MHz).
Functional Description
The CDP1851 has four modes of operation: input, output,
bidirectional, and bit-programmable. Port A is programmable
in all modes; port B is programmable in all but the
bidirectional mode. A control byte must be loaded into the
control register to program the ports. In the input and output
modes, each port has two handshaking signals, STROBE
and RDY. In the bidirectional mode, port A has four
handshaking signals: A RDY and A STROBE for input, B
RDY and B STROBE for output. If port A is programmed in
the bidirectional mode, port B must be programmed in the
bit-programmable mode. Each terminal of port A or B may
be individually programmed for input or output in the bit-
programmable mode. Since handshaking is not used in this
mode, the RDY and STROBE lines may also be used for bitprogramming if port A is not in the bidirectional mode.
Input Mode
When a peripheral device has data to input, it sends a
STROBE pulse to the PlO. The leading edge of this pulse
clears the RDY line, inhibiting further transmission from the
peripheral. The trailing edge of the STROBE pulse latches the
data into the PlO buffer register and also activates the INT line
to signal the CPU to read this data. The lNT pin can be wired
to the INT pin of the CPU or the EF lines for polling. The CPU
4-7
CDP1851, CDP1851C
then executes an input or a load instruction, depending on the
mapping technique used. In either case the proper code must
be asserted on the RAO, RA1, and CS lines to read the buffer
register (see Table 6).
The INT line is deactivated on the leading edge of TPB. The
trailing edge of TPB sets the RDY line to signal the peripheral that the port is ready to be loaded with new data. If RDY
is low when the input mode is entered (i.e. after a reset), a
“dummy” read must be done to set RDY high and signal the
peripheral device that the port is ready to be loaded.
Output Mode
A peripheral STROBE pulse sent to the PlO generates an
interrupt to signal the CPU that the peripheral device is
ready for data. The CPU executes the proper output or store
instruction. Data are then read from memory and placed on
the bus. The data are latched into the port buffer at the end
of the window when RE/WE = 0 and WR/RE = 1. The RDY
line is also set at this time, indicating to the peripheral that
there is data in the port buffer. The INT line is deactivated at
the beginning of the window. After the peripheral reads valid
port data, it can send another STROBE pulse, clearing the
RDY line and activating the INT line as in the input mode.
Bidirectional Mode
control port direction by using both sets of handshake signals.
The port A handshaking pins are used to control input data
from peripheral to PlO, while the port B handshaking pins are
used to control output data from PlO to peripheral. Data are
transferred in the same manner as the input and output
modes. Since A INT is used for both input and output, the status register must be read to determine what condition caused
A INT to be activated (see Table 5).
Bit-Programmable Mode
This mode allows individual bits of port A or port B to be
programmed as inputs or outputs. To output data to bits
programmed as outputs, the CPU loads a data byte into the
8-bit port as in the output mode (no handshaking). Only bits
programmed for outputs latch this data. Data must be stable
when reading from bits programmed as inputs, since the
input bits do not latch. When the CDP1851 inputs data to the
CPU the CPU also reads the output bits latched during the
last output cycle. The RDY and STROBE lines may be used
for I/O by using the STROBE/RDY I/O control byte in Table 2.
An additional feature available in the bit-programmable
mode is the ability to generate interrupts based on
input/output byte combinations. These interrupts can be
programmed to occur on logic conditions (AND, OR, NAND,
and NOR) generated by the eight I/O lines of each port (The
STROBE and RDY lines cannot generate interrupts).
This mode programs port A to function as both an input and
output port. The bidirectional feature allows the peripheral to
TPB
MRD
MWR
TPA
A0
A1
A2
CDP1800
A3
FAMILY
A4
µP
A5
A6
A7
TPB
WR/RE
RD/WE
CLOCK
RA0
RA1
PIO
NO. 1
CDP1851
A RDY
B RDY
A STROBE
B STROBE
PORT A0 - A7
PORT B0 - B7
CS
VDD
10kΩ
B INT
INT
A INT
BUS 0-7
BUS 0-7
ADDRESS REGISTER
ADDRESS
SELECTS
8001
No. 1 Control/Status Reg
8002
No. 1 Port A
8003
No. 1 Port B
8004
No. 2 Control/Status Reg
8008
No. 2 Port A
800C
No. 2 Port B
TPB
WR/RE
RD/WE
CLOCK
RA0
RA1
CS
A INT
B INT PIO
NO. 2
CDP1851
A RDY
B RDY
A STROBE
B STROBE
PORT A0 - A7
PORT B0 - B7
FIGURE 2. MEMORY SPACE I/O. THIS CONFIGURATION ALLOWS UP TO FOUR CDP1851s TO OCCUPY MEMORY SPACE 8XXX WITH
NO ADDITIONAL HARDWARE (A4-A5 AND A6-A7 ARE USED AS RA0 AND RA1 ON THE THIRD AND FOURTH PIO’s)
4-8
CDP1851, CDP1851C
Programming
The CDP1851 PlO must be cleared by a low on the CLEAR
input during power-on to set it for programming. Once
programmed, modes can be changed without clearing
except when exiting the bit-programmable mode. A low on
the CLEAR input sets both ports to the input modes,
disables interrupts, unmasks all bit-programmed interrupt
bits, and resets the status register, A RDY, and B RDY.
data on the STROBE and RDY lines is detected by reading
the status register. When using the STROBE or RDY lines for
output, the control byte must be loaded every time output data
is to be changed. To program logical conditions that will generate an interrupt, the interrupt control byte of Table 3 must be
loaded. An interrupt mask of the eight I/O lines may be loaded
next, if bit D4 (mask follows) of the interrupt control byte = 1.
The I/O lines are masked if the corresponding bit of the interrupt mask register is 1, otherwise it is monitored. Any combination of masked bits are permissible, except all bits masked
(mask = FF).
Mode Setting
INT Enable Disable
The control register must be sequentially loaded with the
appropriate mode set control bytes in order as shown in Table
1 (i.e. input mode then output mode, etc.). Port A is set with
the SET A bit = 1 and port B is set with the SET B bit = 1. If a
port is set to the bit-programmable mode, the bit-programming
control byte from Table 2 must be loaded. A bit is programmed
for output with the I/O bit = 1 and for input with the I/O bit = 0.
The STROBE and RDY lines may be programmed for input or
output with the STROBE/RDY control byte of Table 2. Input
To enable or disable the INT line in all modes, the interrupt
ENABLE/DISABLE byte must be loaded (see Table 4). Interrupts can also be detected by reading the status register
(see Table 5). All interrupts should be disabled when
programming or false interrupts may occur. The INT outputs
are open drain NMOS devices that allow wired O Ring (use
10K pull-up registers).
Initialization and Controls
GENERATE CLEAR PULSE
AT PIN 13
SET PORTS A AND B
TO INPUT, OUTPUT, OR
BIT-PROGRAMMABLE MODE
USING TABLE 1
YES
IS
EITHER PORT
SET TO THE
BIT-PROGRAMMABLE
MODE 3
NO
PERFORM FOLLOWING
SEQUENCE BEFORE
PROGRAMMING PORT A TO
BIDIRECTIONAL MODE
REPEAT FOR EACH
BIT-PROGRAMMABLE
PORT
NOW SET PORT A TO
BIDIRECTIONAL MODE,
IF DESIRED
SET BIT DIRECTION
USING TABLE 2
SET MASTER INTERRUPT
ENABLE/DISABLE
USING TABLE 4
WILL
INTERRUPTS
BE USED FOR
BIT-PROGRAMMED
PORT?
NO
MAIN PROGRAM
YES
REPEAT FOR EACH
BIT-PROGRAMMABLE
PORT
SET BIT LOGICAL
CONDITIONS AND
MASKING USING
TABLE 3
FIGURE 3. A FLOW CHART GUIDE TO CDP1851 MODE PROGRAMMING
NOTES:
1. STROBE/READY I/O Control Byte (Table 2) is also used to output data to STROBE and READY lines when bit-programmed.
2. Status register (Table 2) is used to input data from STROBE and READY lines when bit-programmed.
3. Interrupt status is also read from status register.
4-9
CDP1851, CDP1851C
TABLE 1. (RA1 = 0, RA0 = 1)
(NOTE 1)
MODE SET
7
6
5
4
3
2
1
0
Input
0
0
X
Set B
Set A
X
1
1
Output
0
1
X
Set B
Set A
X
1
1
Bit-Programmable
1
1
X
Set B
Set A
X
1
1
Bidirectional
1
0
X
X
Set A
X
1
1
NOTE:
1. Modes should be set in order as shown in Table 1.
If either port is set for bit-programmable mode, the two following control bytes should immediately follow:
TABLE 2. (RA1 = 0, RA0 = 1)
Bit-Programming (Note 1)
7
6
5
4
3
2
1
0
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
D7
D6
D5
D4
D3
D2
D1
D0
STROBE/RDY I/O Control (Notes 2 - 8)
NOTES:
1. Output = 1, Input = 0
2. (D1) 0 = Port A, 1 = Port B
3. (D2) 0 = No change to RDY line function, 1 = Change per bit (D6)
4. (D3) 0 = No change to STROBE line function, 1 = Change per bit (D7)
5. (D4) RDY line output data
6. (D5) STROBE line output data
7. (D6) RDY line used as:
Output = 1
Input = 0
8. (D7) STROBE line used as:
Output = 1
Input = 0
If interrupts will be used for either bit-programmed port, the following control bytes should be loaded.
TABLE 3. (RA1 = 0, RA0 = 1)
INTERRUPT CONTROL
Logical Conditions and Mask
7
6
5
4
3
2
1
0
0
D6
D5
D4
D3
1
0
1
NOTES:
1. (D3) 0 = Port A, 1 = Port B
2. (D4) 0 = No change in mask, 1 = Mask follows (See Table 3A)
3. (D5)(D6) 0, 0 = NAND; 1, 0 = OR; 0, 1 = NOR; 1, 1 = AND
TABLE 3A. (RA1 = 0, RA0 = 1)
INTERRUPT CONTROL
Mask Register (If D4 = 1)
7
6
5
4
3
2
1
0
B7 Mask
B6 Mask
B5 Mask
B4 Mask
B3 Mask
B2 Mask
B1 Mask
B0 Mask
NOTE:
1. If Bn Mask = 1 then mask Bit (for n = 0 to 7)
4-10
CDP1851, CDP1851C
TABLE 4. (RA1 = 0, RA0 = 1)
INTERRUPT CONTROL
Interrupt Enable/Disable
7
6
5
4
3
2
1
0
INT
Enable
X
X
X
A/B
0
0
1
NOTES:
1. INT Enable = 1, INT Enabled
= 0, INT Disabled
2. A/B = 0, Port A
= 1, Port B
TABLE 5. (RA1 = 0, RA0 = 1)
Status Register
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
NOTES:
1. All Modes
(D0) B INT status (1 means set)
(D1) A INT status (1 means set)
2. Bidirectional Mode Only
(D2) 1 = A INT was caused by A STROBE
(D3) 1 = A INT was caused by B STROBE
3. Bit-Programmable Mode
(D4) A RDY input data
(D5) A STROBE input data
(D6) B RDY input data
(D7) B STROBE input data
TABLE 6. CPU CONTROLS
(NOTE 1)
CS
RA1
RA0
RD/WE
WR/RE
0
X
X
X
X
No-op bus three-stated
X
0
0
X
X
No-op bus three-stated
X
X
X
0
0
No-op bus three-stated
X
X
X
1
1
No-op bus three-stated
X
X
X
1
1
No-op bus three-stated
1
0
1
1
0
Read status register (Note 1)
1
0
1
0
1
Load control register
1
1
0
1
0
Read port A (Note 1)
1
1
0
0
1
Load port A
1
1
1
1
0
Read port B (Note 1)
1
1
1
0
1
Load port B
ACTION
NOTE:
1. Read = RD/WE = 1 and WR/RE = 0 is latched on trailing edge of CLOCK.
TABLE 7. MEMORY I/O USE
RD/WE INPUT
WR/RE INPUT
TPB INPUT
I/O Space
MRD
TPB
TPB
Memory Space
MWR
MRD
TPB
4-11
}
PIO Terminal
}
CPU Terminals
CDP1851, CDP1851C
Function Pin Definition
CLOCK (Input):
B STROBE (Input):
Positive input pulse that latches READ and CS on its trailing
edge.
An input handshaking line for port B in the input and output
modes, and for port A when it is in the bidirectional mode. It
can be used as a data bit I/O line in the bit-programmable
mode except when port A is not programmed as bidirectional.
CS - CHIP SELECT (Input)
A high-level voltage at this input selects the CDP1851 PlO.
B0 - B7:
RA0 - REGISTER ADDRESS 0 (Input):
Data input or output lines for port B.
This input and RA1 are used to select either the ports or the
control/status registers.
VSS
Ground
RA1 - REGISTER ADDRESS 1(Input):
A0 - A7:
See RAO
Data input or output lines for port A.
BUS 0 - BUS 7:
A STROBE (Input):
Bidirectional CPU data bus.
CLEAR (Input)
A low-level voltage at this input resets both ports to the input
mode, and also resets the status register, A RDY, B RDY,
and interrupt enable (disabling interrupts).
An input handshaking line for port A in the input, output, and
bidirectional modes. It can also be used as a data bit I/O line
when port A is in the bit-programmable mode.
ARDY - AREADY (Output):
A output handshaking line or data bit I/O line.
A INT - A INTERRUPT (Output):
A low-level voltage at this output indicates the presence of
one of the interrupt conditions listed in Table 3. This output is
an open-drain NMOS device (to allow wired O Ring) and
must be tied to a pullup resistor, normally 10kΩ.
TPB (Input):
A positive input pulse used as a data load, set, or reset
strobe.
WR/RE - WRITE/READ ENABLE (Input):
B INT - B INTERRUPT (Output):
A low-level voltage at this output indicates the presence of
one of the interrupt conditions listed in Table 3. This output is
also an open-drain NMOS device and must be tied to a
pullup resistor.
B RDY - B READY (Output):
This output is a handshaking or data bit I/O line in the bitprogrammable mode.
A positive input used to write data from the CDP1851 to the
CPU bus.
RD/WE - READ/WRITE ENABLE (Input):
A positive input used to read data from the CPU bus to the
CDP1851 bus.
VDD:
Positive supply voltage.
4-12
CDP1851, CDP1851C
N0
N1
N2
TPA
MRD
TPB
CDP1802
RA0
RA1
CS
CLOCK
RD/WE
WR/RE
VDD
TPB
10kΩ
B INT
INT
A RDY
B RDY
A STROBE
B STROBE
PORT A0 - A7
CDP1851
PORT B0 - B7
A INT
BUS 0-7
BUS 0-7
RA0 BUS 0-7
RA1
CS
CLOCK
RD/WE
WR/RE
TPB
CDP1851
A RDY
B RDY
A STROBE
B STROBE
A INT
B INT
PORT B0 - B7
FIGURE 4. I/O SPACE I/O
4-13
PORT A0 - A7
CDP1851, CDP1851C
Dynamic Electrical Specifications
At TA = -40oC to +85oC, VDD ±5%, tr, tf = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF
LIMITS
CDP1851
PARAMETER
CDP1851C
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
UNITS
5
-
50
75
-
50
75
ns
10
-
25
40
-
-
-
ns
5
-
75
120
-
75
120
ns
10
-
40
60
-
-
-
ns
5
-
75
120
-
75
120
ns
VDD
(V)
INPUT MODE SEE FIGURES 4 AND 5
Minimum Setup Times:
Chip Select to CLOCK
RD/WE to CLOCK
tCSCL
tRWCL
WR/RE to CLOCK
tWRCL
Data in to STROBE
tDlST
Minimum Hold Times:
Chip Select After CLOCK
Address After TPB
Data In After STROBE
Data Bus Out After Address
Propagation Delay Times:
TPB to INT
STROBE to INT
TPB to RDY
STROBE to RDY
Minimum Pulse Widths:
CLOCK
TPB
STROBE
Access Time, Address to Data
Bus Out
tHCSCL
tHATPB
tHSTDl
tHADOH
tPINT
tSTlNT
tTPRDY
tSTRDY
tWCL
tWTPB
tWST
tADA
10
-
40
60
-
-
-
ns
5
-
75
120
-
75
120
ns
10
-
40
60
-
-
-
ns
5
-
75
120
-
75
120
ns
10
-
40
60
-
-
-
ns
5
-
-50
0
-
-50
0
ns
10
-
-25
0
-
-
-
ns
5
-
50
75
-
50
75
ns
10
-
25
40
-
-
-
ns
5
50
325
500
50
325
500
ns
10
25
165
250
-
-
-
ns
5
-
200
300
-
200
300
ns
10
-
100
150
-
-
-
ns
5
-
200
300
-
200
300
ns
10
-
100
150
-
-
-
ns
5
-
250
375
-
250
375
ns
10
-
125
200
-
-
-
ns
5
-
260
400
-
260
400
ns
10
-
130
200
-
-
-
ns
5
-
75
120
-
75
120
ns
10
-
40
60
-
-
-
ns
5
-
75
120
-
75
120
ns
10
-
40
60
-
-
-
ns
5
-
100
150
-
100
150
ns
10
-
50
75
-
-
-
ns
5
-
325
500
-
325
500
ns
10
-
165
250
-
-
-
ns
NOTES:
1. Typical values are for TA = 25oC and nominal voltages.
2. Maximum limits of minimum characteristics are the values above which all devices function.
4-14
CDP1851, CDP1851C
Test Circuit and Waveforms
VDD
1kΩ
A INT
A
INPUT
SIGNAL
B
A, B
50pF
50%
50%
1kΩ
B INT
50%
10%
tPINT
tWINT
50pF
CDP1851
tSTINT
FIGURE 5. INTERRUPT SIGNAL PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS
RDY
tSTRDY
tTPRDY
INT
tWST
tSTINT
tPINT
STROBE
tDIST
tHSTDI
DATA-IN
tWTPB
TPB
tWCL
CLOCK = (TPA)
tCSCL
tHCSCL
CS
tWRCL
WR/RE = (MRD)
MEMORY SPACE
tRWCL
RD/WE = (MWR)
RD/WE = (MRD)
I/O SPACE
WR/RE = (TPB)
tHATPB
RA1/RA0
VALID PORT ADDRESS
IO OR II
tADA
tHADOH
DATA BUS
FIGURE 6. INPUT MODE TIMING WAVEFORMS
4-15
CDP1851, CDP1851C
Dynamic Electrical Specifications
At TA = -40oC to +85oC, VDD ±5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF
LIMITS
CDP1851
PARAMETERS
CDP1851C
VDD
(V)
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
UNITS
5
-
50
75
-
50
75
ns
10
-
25
40
-
-
-
ns
5
-
75
120
-
75
120
ns
10
-
40
60
-
-
-
ns
5
-
75
120
-
75
120
ns
10
-
40
60
-
-
-
ns
5
-
50
75
-
50
75
ns
10
-
25
40
-
-
-
ns
5
-
80
120
-
80
120
ns
10
-
40
60
-
-
-
ns
5
-
75
120
-
75
120
ns
10
-
40
60
-
-
-
ns
5
-
50
75
-
50
75
ns
10
-
25
40
-
-
-
ns
5
-
50
75
-
50
75
ns
10
-
25
40
-
-
-
ns
5
-
225
350
-
225
350
ns
10
-
125
200
-
-
-
ns
5
-
300
450
-
300
450
ns
10
-
150
225
-
-
-
ns
5
-
350
525
-
350
525
ns
10
-
175
275
-
-
-
ns
5
-
200
300
-
200
300
ns
10
-
100
150
-
-
-
ns
5
-
260
400
-
260
400
ns
10
-
130
200
-
-
-
ns
OUTPUT MODE SEE FIGURES 4 AND 6
Minimum Setup Times:
Chip Select to CLOCK
RD/WE to CLOCK
WR/RE to CLOCK
Address to WRITE (Note 3)
Data Bus to WRITE (Note 3)
tCSCL
tRWCL
tWRCL
tAW
tDW
Minimum Hold Times:
Chip Select After CLOCK
Address After WRITE (Note 3)
Data Bus After WRITE (Note 3)
tHCSCL
tHAW
tHDW
Propagation Delay Times:
WRITE to Data Out (Note 3)
WRITE to INT (Note 3)
WRITE to RDY (Note 3)
STROBE to lNT
STROBE to RDY
tWDO
tWINT
tWRDY
tSTlNT
tSTRDY
4-16
CDP1851, CDP1851C
Dynamic Electrical Specifications
At TA = -40oC to +85oC, VDD ±5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF
LIMITS
CDP1851
PARAMETERS
CDP1851C
VDD
(V)
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
UNITS
5
-
75
120
-
75
120
ns
10
-
40
60
-
-
-
ns
5
-
100
150
-
100
150
ns
10
-
50
75
-
-
-
ns
5
-
175
275
-
175
275
ns
10
-
90
150
-
-
-
ns
Minimum Pulse Widths:
CLOCK
STROBE
WRITE (Note 3)
tWCL
tWST
tWW
NOTES:
1. Typical values are for TA = 25oC and nominal voltages.
2. Maximum limits of minimum characteristics are the values above which all devices function.
3. WRITE is the overlap of RD/WE = 0 and WR/RE = 1.
4-17
CDP1851, CDP1851C
INT
tWINT
tSTINT
RDY
tWRDY
tSTRDY
STROBE
tWTPB
tWCL
tWST
CLOCK = (TPA)
tHCSCL
CS
tCSCL
VALID DATA OUT
DATA-OUT
tWDO
tWRCL
WR/RE = (MRD)
MEMORY SPACE
RD/WE = (MWR)
tWW (NOTE 1)
WR/WE = (TPB)
I/O SPACE t
RWCL
RD/WE = (MRD)
tAW
tHAW
VALID PORT ADDRESS
IO OR II
RA1/RA0
tDW
tDW
VALID DATA
DATA BUS
NOTE:
1. Write is the overlap of WR/RE = 1 and RD/WE = 0
FIGURE 7. OUTPUT MODE TIMING WAVEFORMS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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4-18
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