MCP40D17/18/19 7-Bit Single I2C™ (with Command Code) Digital POT with Volatile Memory in SC70 Package Types Features • Potentiometer or Rheostat configuration options • 7-bit: Resistor Network Resolution - 127 Resistors (128 Steps) • Zero Scale to Full Scale Wiper operation • RAB Resistances: 5 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ • Low Wiper Resistance: 100Ω (typical) • Low Tempco: - Absolute (Rheostat): 50 ppm typical (0°C to 70°C) - Ratiometric (Potentiometer): 15 ppm typical • I2C Protocol - Supports SMBus 2.0 Write Byte/Word Protocol Formats - Supports SMBus 2.0 Read Byte/Word Protocol Formats • Standard I2C Device Addresses: - All devices offered with address “0101110” - MCP40D18 also offered with address “0111110” • Brown-out reset protection (1.5V typical) • Power-on Default Wiper Setting (Mid-scale) • Low-Power Operation: - 2.5 µA Static Current (typical) • Wide Operating Voltage Range: - 2.7V to 5.5V - Device Characteristics Specified - 1.8V to 5.5V - Device Operation • Wide Bandwidth (-3 dB) Operation: - 2 MHz (typical) for 5.0 kΩ device • Extended temperature range (-40°C to +125°C) • Very small package (SC70) • Lead free (Pb-free) package Rheostat Potentiometer MCP40D17 SC70-6 MCP40D18 SC70-6 VDD 1 VSS 2 B VDD 1 6 A A W SCL 3 5 W VSS 2 4 SDA SCL 3 W A B 6 W 5 B 4 SDA MCP40D19 SC70-5 VDD 1 VSS 2 5 W W B SCL 3 A 4 SDA Applications • PC Servers (I2C Protocol with Command Code) • Amplifier Gain Control and Offset Adjustment • Sensor Calibration (Pressure, Temperature, Position, Optical and Chemical) • Set point or offset trimming • Cost-sensitive mechanical trim pot replacement • RF Amplifier Biasing • LCD Brightnes and Contract Adjustment Resistance (typical) MCP40D17 I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 75 1.8V to 5.5V SC70-6 MCP40D18 I2C 128 Potentiometer RAM 5.0, 10.0, 50.0, 100.0 75 1.8V to 5.5V SC70-6 MCP40D19 I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 75 1.8V to 5.5V SC70-5 Note 1: Wiper Configuration Memory Type Device Control Interface # of Steps Device Features Options (kΩ) Wiper (Ω) VDD Operating Range ( 1) Package Analog characteristics only tested from 2.7V to 5.5V © 2009 Microchip Technology Inc. DS22152B-page 1 MCP40D17/18/19 Device Block Diagram VDD A (2) Power-up/ Brown-out Control VSS W I2C Serial Interface Module, Control Logic, & Memory SCL SDA Resistor Network 0 (Pot 0) B (1, 2) Note 1 Note 1: Some configurations will have this signal internally connected to ground. 2: In some configurations, this signal may not be connected externally (internally floating or grounded). I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6 MCP4017 ( 2, 4) I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6 MCP4012 ( 2) U/D 64 Rheostat RAM 2.1, 5.0, 10.0, 50.0 1.8V to 5.5V Yes No SOT-23-6 MCP4022 ( 2) U/D 64 Rheostat EE 2.1, 5.0, 10.0, 50.0 2.7V to 5.5V Yes Yes SOT-23-6 MCP4132 ( 3) SPI 129 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes No ( 3) SPI 129 Rheostat EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes Yes MCP4152 ( 3) SPI 257 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes No MCP4162 ( 3) PDIP-8, SOIC-8, MSOP-8, DFN-8 SPI 257 Rheostat EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes Yes MCP4532 ( 3) I2C 129 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes No MCP4542 ( 3) I2C 129 Rheostat EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes Yes MCP4552 ( 3) I2C 257 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes No ( 3) I2C 257 Rheostat EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes Yes MCP40D18 ( 2) I2C 128 Potentiometer RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6 MCP4018 ( 2, 4) I2C 128 Potentiometer RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6 MCP4013 ( 2) U/D 64 Potentiometer RAM 2.1, 5.0, 10.0, 50.0 1.8V to 5.5V Yes No SOT-23-6 MCP4023 ( 2) MCP40D17 MCP4142 MCP4562 Resistance (typical) Wiper Configuration Memory Type Device # of Steps Package ( 2) Control Interface HV Interface WiperLock Technology Comparison of Similar Microchip Devices ( 1) Options (kΩ) VDD Operating Range MSOP-8, DFN-8 U/D 64 Potentiometer EE 2.1, 5.0, 10.0, 50.0 2.7V to 5.5V Yes Yes SOT-23-6 MCP40D19 ( 2) I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-5 MCP4019 ( 2, 4) I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-5 ( 2) U/D 64 Rheostat RAM 2.1, 5.0, 10.0, 50.0 1.8V to 5.5V Yes No SOT-23-5 MCP4024 ( 2) U/D 64 Rheostat EE 2.1, 5.0, 10.0, 50.0 2.7V to 5.5V Yes Yes SOT-23-5 MCP4014 Note 1: 2: 3: 4: This table is broken into three groups by a thick line (and color coding). The unshaded devices in this table are the devices described in this data sheet, while the shaded devices offer a comparable resistor network configuration. Analog characteristics only tested from 2.7V to 5.5V. Analog characteristics only tested from 3.0V to 5.5V. These devices have a simplified I2C command format, which allows higher data throughput. DS22152B-page 2 © 2009 Microchip Technology Inc. MCP40D17/18/19 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Voltage on VDD with respect to VSS ..... -0.6V to +7.0V Voltage on SCL, and SDA with respect to VSS ............................................................................. -0.6V to 12.5V Voltage on all other pins (A, W, and B) with respect to VSS ............................ -0.3V to VDD + 0.3V Input clamp current, IIK (VI < 0, VI > VDD, VI > VPP ON HV pins) ........... ±20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ....................................... ±20 mA Maximum output current sunk by any Output pin ........................................................................... 25 mA Maximum output current sourced by any Output pin ........................................................................... 25 mA Maximum current out of VSS pin ...................... 100 mA Maximum current into VDD pin ......................... 100 mA Maximum current into A, W and B pins........... ±2.5 mA Package power dissipation (TA = +50°C, TJ = +150°C) † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. SC70-5 ............................................................ 302 mW SC70-6 ............................................................ 483 mW Storage temperature .......................... -65°C to +150°C Ambient temperature with power applied ........................................................... -40°C to +125°C ESD protection on all pins ........................≥ 4 kV (HBM) ........................................................................≥ 400V (MM) Maximum Junction Temperature (TJ) .............. +150°C © 2009 Microchip Technology Inc. DS22152B-page 3 MCP40D17/18/19 AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Parameters Sym Min Typ Max Units Conditions Supply Voltage VDD 2.7 — 5.5 V Analog Characteristics specified 1.8 — 5.5 V Digital Characteristics specified — — 1.65 V RAM retention voltage (VRAM) < VBOR VDD Start Voltage to ensure Wiper Reset VBOR VDD Rise Rate to ensure Power-on Reset VDDRR Delay after device exits the reset state (VDD > VBOR) TBORD — 10 20 µS IDD — 45 80 µA Serial Interface Active, Write all 0’s to Volatile Wiper VDD = 5.5V, FSCL = 400 kHz — 2.5 5 µA Serial Interface Inactive, (Stop condition, SCL = SDA = VIH), Wiper = 0, VDD = 5.5V Supply Current (Note 8) Note 1: 2: 3: 4: 5: 6: 7: 8: (Note 7) V/ms Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP40D18 device only, includes VWZSE and VWFSE. Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. POR/BOR is not rate dependent. Supply current is independent of current through the resistor network DS22152B-page 4 © 2009 Microchip Technology Inc. MCP40D17/18/19 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (extended) DC Characteristics Parameters Resistance (± 20%) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Sym RAB Resolution N Step Resistance RS Wiper Resistance RW Nominal Resistance Tempco ΔRAB/ΔT Ratiometeric Tempco ΔVWB/ΔT Resistor Terminal Input Voltage Range (Terminals A, B and W) Maximum current through Terminal (A, W or B) Note 5 Note 1: 2: 3: 4: 5: 6: 7: 8: Min Typ Max Units Conditions 4.0 5 6.0 kΩ -502 devices (Note 1) 8.0 10 12.0 kΩ -103 devices (Note 1) 40.0 50 60.0 kΩ -503 devices (Note 1) 80.0 100 120.0 kΩ -104 devices (Note 1) — RAB / (127) 128 Taps — Ω No Missing Codes Note 5 — 100 170 Ω VDD = 5.5 V, IW = 2.0 mA, code = 00h — 155 325 Ω VDD = 2.7 V, IW = 2.0 mA, code = 00h — 50 — ppm/°C TA = -20°C to +70°C — 100 — ppm/°C TA = -40°C to +85°C — 150 — ppm/°C TA = -40°C to +125°C — 15 — ppm/°C Code = Midscale (3Fh) VA,VW,VB Vss — VDD V IT — — 2.5 mA Terminal A IAW, W = Full Scale (FS) — — 2.5 mA Terminal B IBW, W = Zero Scale (ZS) — — 2.5 mA Terminal W IAW or IBW, W = FS or ZS — — 1.38 mA — — 0.688 mA — — 0.138 mA — — 0.069 mA Note 4, Note 5 IAB, VB = 0V, VA = 5.5V, RAB(MIN) = 4000 Terminal A and Terminal B IAB, VB = 0V, VA = 5.5V, RAB(MIN) = 8000 IAB, VB = 0V, VA = 5.5V, RAB(MIN) = 40000 IAB, VB = 0V, VA = 5.5V, RAB(MIN) = 80000 Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP40D18 device only, includes VWZSE and VWFSE. Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. POR/BOR is not rate dependent. Supply current is independent of current through the resistor network © 2009 Microchip Technology Inc. DS22152B-page 5 MCP40D17/18/19 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Parameters Sym Min Typ Max Units Full Scale Error (MCP40D18 only) (code = 7Fh) VWFSE -3.0 -0.1 — LSb 5 kΩ 2.7V ≤ VDD ≤ 5.5V -2.0 -0.1 — LSb 10 kΩ 2.7V ≤ VDD ≤ 5.5V -0.5 -0.1 — LSb 50 kΩ 2.7V ≤ VDD ≤ 5.5V -0.5 -0.1 — LSb 100 kΩ 2.7V ≤ VDD ≤ 5.5V — +0.1 +3.0 LSb 5 kΩ 2.7V ≤ VDD ≤ 5.5V — +0.1 +2.0 LSb 10 kΩ 2.7V ≤ VDD ≤ 5.5V — +0.1 +0.5 LSb 50 kΩ 2.7V ≤ VDD ≤ 5.5V — +0.1 +0.5 LSb 100 kΩ 2.7V ≤ VDD ≤ 5.5V Zero Scale Error (MCP40D18 only) (code = 00h) VWZSE Conditions Potentiometer Integral Non-linearity INL -0.5 ±0.25 +0.5 LSb 2.7V ≤ VDD ≤ 5.5V MCP40D18 device only (Note 2) Potentiometer Differential Nonlinearity DNL -0.25 ±0.125 +0.25 LSb 2.7V ≤ VDD ≤ 5.5V MCP40D18 device only (Note 2) Bandwidth -3 dB (See Figure 2-83, load = 30 pF) BW — 2 — MHz 5 kΩ Code = 3Fh Note 1: 2: 3: 4: 5: 6: 7: 8: — 1 — MHz 10 kΩ Code = 3Fh — 260 — kHz 50 kΩ Code = 3Fh — 100 — kHz 100 kΩ Code = 3Fh Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP40D18 device only, includes VWZSE and VWFSE. Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. POR/BOR is not rate dependent. Supply current is independent of current through the resistor network DS22152B-page 6 © 2009 Microchip Technology Inc. MCP40D17/18/19 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (extended) DC Characteristics Parameters Rheostat Integral Non-linearity MCP40D18 (Note 3) MCP40D17 and MCP40D19 devices only (Note 3) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Sym Min Typ Max R-INL -2.0 ±0.5 +2.0 LSb -5.0 +3.5 +5.0 LSb See Section 2.0 1.8V (Note 6) 10 kΩ 5.5V, IW = 450 µA LSb -4.0 +2.5 +4.0 LSb 2.7V, IW = 215 µA (Note 6) LSb 1.8V (Note 6) ±0.5 +1.125 LSb -1.5 +1 +1.5 LSb 2.7V, IW = 43 µA (Note 6) LSb 1.8V (Note 6) -0.8 ±0.5 +0.8 LSb -1.125 +0.25 +1.125 LSb 50 kΩ 5.5V, IW = 90 µA -1.125 100 kΩ 5.5V, IW = 45 µA 2.7V, IW = 21.5 µA (Note 6) LSb 1.8V (Note 6) ±0.25 +0.5 LSb -0.75 +0.5 +0.75 LSb 2.7V, IW = 430 µA (Note 6) LSb 1.8V (Note 6) See Section 2.0 5 kΩ 5.5V, IW = 900 mA -0.5 -0.5 ±0.25 +0.5 LSb -0.75 +0.5 +0.75 LSb 2.7V, IW = 215 µA (Note 6) LSb 1.8V (Note 6) See Section 2.0 -0.375 ±0.25 +0.375 LSb -0.375 ±0.25 +0.375 LSb LSb -0.375 ±0.25 +0.375 LSb -0.375 ±0.25 +0.375 LSb See Section 2.0 CAW — 75 Capacitance (Pw) CW — 120 Capacitance (PB) CBW — 75 7: 8: 2.7V, IW = 430 µA (Note 6) LSb See Section 2.0 Note 1: 2: 3: 4: 5: 6: 5.5V, IW = 900 µA +2.0 See Section 2.0 Capacitance (PA) 5 kΩ ±0.5 See Section 2.0 R-DNL Conditions -2.0 See Section 2.0 Rheostat Differential Non-linearity MCP40D18 (Note 3) MCP40D17 and MCP40D19 devices only (Note 3) Units LSb — 10 kΩ 50 kΩ 5.5V, IW = 450 µA 5.5V, IW = 90 µA 2.7V, IW = 43 µA (Note 6) 1.8V (Note 6) 100 kΩ 5.5V, IW = 45 µA 2.7V, IW = 21.5 µA (Note 6) 1.8V (Note 6) pF f =1 MHz, Code = Full Scale — pF f =1 MHz, Code = Full Scale — pF f =1 MHz, Code = Full Scale Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP40D18 device only, includes VWZSE and VWFSE. Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. POR/BOR is not rate dependent. Supply current is independent of current through the resistor network © 2009 Microchip Technology Inc. DS22152B-page 7 MCP40D17/18/19 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Parameters Sym Min Typ Max Units Conditions Digital Inputs/Outputs (SDA, SCK) Schmitt Trigger High Input Threshold VIH 0.7 VDD — — V Schmitt Trigger Low Input Threshold VIL -0.5 — 0.3VDD V Hysteresis of Schmitt Trigger Inputs (Note 5) VHYS — 0.1VDD — V N.A. — — V N.A. — — V 0.1 VDD — — V 0.05 VDD — — V VSS — 0.2VDD V 1.8V ≤ VDD ≤ 5.5V All inputs except SDA and SCL SDA and SCL 100 kHz 400 kHz VDD < 2.0V VDD ≥ 2.0V VDD < 2.0V VDD ≥ 2.0V Output Low Voltage (SDA) VOL VSS — 0.4 V VDD ≥ 2.0V, IOL = 3 mA Input Leakage Current IIL -1 — 1 µA VIN = VDD and VIN = VSS CIN, COUT — 10 — pF fC = 400 kHz N 0h — 7Fh hex Pin Capacitance VDD < 2.0V, IOL = 1 mA RAM (Wiper) Value Value Range Wiper POR/BOR Value 3Fh NPOR/BOR hex Power Requirements Power Supply Sensitivity (MCP40D18 only) Note 1: 2: 3: 4: 5: 6: 7: 8: PSS — 0.0005 0.0035 %/% VDD = 2.7V to 5.5V, VA = 2.7V, Code = 3Fh Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP40D18 device only, includes VWZSE and VWFSE. Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. POR/BOR is not rate dependent. Supply current is independent of current through the resistor network DS22152B-page 8 © 2009 Microchip Technology Inc. MCP40D17/18/19 I2C Mode Timing Waveforms and Requirements 1.1 SCL 93 91 90 92 SDA STOP Condition START Condition I2C Bus Start/Stop Bits Timing Waveforms. FIGURE 1-1: I2C BUS START/STOP BITS REQUIREMENTS TABLE 1-1: I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (Extended) Operating Voltage VDD range is described in Section 2.0 “Typical Performance Curves” Param. Symbol No. Characteristic FSCL D102 Cb 90 TSU:STA 91 92 93 Bus capacitive loading START condition Setup time THD:STA START condition Hold time TSU:STO STOP condition Setup time THD:STO STOP condition Hold time Standard Mode Fast Mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 103 Min Max Units 0 0 — — 4700 600 4000 600 4000 600 4000 600 100 400 400 400 — — — — — — — — kHz kHz pF pF ns ns ns ns ns ns ns ns Conditions Cb = 400 pF, 1.8V - 5.5V Cb = 400 pF, 2.7V - 5.5V Only relevant for repeated START condition After this period the first clock pulse is generated 102 100 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note 1: Refer to specification D102 (Cb) for load conditions. FIGURE 1-2: I2C Bus Data Timing. © 2009 Microchip Technology Inc. DS22152B-page 9 MCP40D17/18/19 I2C BUS DATA REQUIREMENTS (SLAVE MODE) TABLE 1-2: I2C AC Characteristics Parameter No. Sym Characteristic 100 THIGH Clock high time 101 TLOW Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Min Max Units 100 kHz mode 4000 — ns 1.8V-5.5V 600 4700 — — ns ns 2.7V-5.5V Clock low time 400 kHz mode 100 kHz mode 1300 — — 1000 ns ns 102A ( 5) TRSCL SCL rise time 400 kHz mode 100 kHz mode 102B ( 5) TRSDA SDA rise time 400 kHz mode 100 kHz mode 20 + 0.1Cb — 300 1000 ns ns 103A ( 5) TFSCL SCL fall time 400 kHz mode 100 kHz mode 20 + 0.1Cb — 300 300 ns ns 103B ( 5) TFSDA SDA fall time 400 kHz mode 100 kHz mode 20 + 0.1Cb — 40 300 ns ns 400 kHz mode 20 + 0.1Cb 300 ns Conditions 1.8V-5.5V 2.7V-5.5V Cb is specified to be from 10 to 400 pF Cb is specified to be from 10 to 400 pF Cb is specified to be from 10 to 400 pF Cb is specified to be from 10 to 400 pF ( 4) 106 THD:DAT Data input hold time 107 TSU:DAT 109 TAA Output valid from clock 110 TBUF Bus free time 2: 3: 4: 5: 6: 0 — ns 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 0 250 100 — — — — 3450 ns ns ns ns 400 kHz mode 100 kHz mode — 4700 900 — ns ns 400 kHz mode 1300 — ns 1.8V-5.5V, Note 6 2.7V-5.5V, Note 6 ( 2) ( 1) Time the bus must be free before a new transmission can start Philips Spec states N.A. Input filter spike 100 kHz mode — 50 ns suppression 400 kHz mode — 50 ns (SDA and SCL) As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tsu; DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. The MCP40D18/MCP40D19 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to guarantee that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not Tested. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. TSP Note 1: Data input setup time 100 kHz mode DS22152B-page 10 © 2009 Microchip Technology Inc. MCP40D17/18/19 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND. Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 5L-SC70 θJA — 331 — °C/W Note 1 Thermal Resistance, 6L-SC70 θJA — 207 — °C/W Conditions Temperature Ranges Thermal Package Resistances Note 1: Package Power Dissipation (PDIS) is calculated as follows: PDIS = (TJ - TA) / θJA, where: TJ = Junction Temperature, TA = Ambient Temperature. © 2009 Microchip Technology Inc. DS22152B-page 11 MCP40D17/18/19 NOTES: DS22152B-page 12 © 2009 Microchip Technology Inc. MCP40D17/18/19 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. IDD Interface Inactive (µA) 60 50 IDD (µA) 40 400 kHz, 5.5V 30 20 400 kHz, 2.7V 10 100 kHz, 5.5V 100 kHz, 2.7V 0 -40 0 40 80 Temperature (°C) 120 FIGURE 2-1: Interface Active Current (IDD) vs. SCL Frequency (fSCL) and Temperature (VDD = 1.8V, 2.7V and 5.5V). © 2009 Microchip Technology Inc. 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 5.5V 2.7V -40 0 40 80 120 Temperature (°C) FIGURE 2-2: Interface Inactive Current (ISHDN) vs. Temperature and VDD. (VDD = 1.8V, 2.7V and 5.5V). DS22152B-page 13 MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 0.2 0.1 0 60 -0.1 25°C RW -40°C 40 -0.2 20 125C Rw 125C INL 125C DNL 125°C 220 85° INL -40°C 0.1 140 100 RW 60 -40°C 25°C -0.1 -0.2 DNL DNL 125C Rw 125C INL 125C DNL 0.25 0.05 1000 -0.05 -0.15 RW -0.25 0 FIGURE 2-5: 5.0 kΩ : Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V). (A = VDD, B = VSS) DS22152B-page 14 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 125°C 3 2 RW 0 60 DNL -40°C 20 -1 32 64 96 Wiper Setting (decimal) FIGURE 2-7: 5.0 kΩ : Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 2.7V).(IW = 450 µA, B = VSS) -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 2000 RW INL 125C Rw 125C INL 125C DNL 44 39 34 29 1500 24 19 1000 14 DNL 500 9 4 0 32 64 96 Wiper Setting (decimal) Refer to AN1080 for additional information on the characteristics of the wiper resistance (RW) with respect to device voltage and wiper setting value. 25C Rw 25C INL 25C DNL 1 -0.35 0 85°C 25°C 2500 1500 500 -40C Rw -40C INL -40C DNL 100 0.35 0.15 -0.2 140 Wiper Resistance (RW) (ohms) INL 85C Rw 85C INL 85C DNL Error (LSb) 2000 25C Rw 25C INL 25C DNL -0.1 32 64 96 Wiper Setting (decimal) 0 FIGURE 2-4: 5.0 kΩ : Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 2.7V). (A = VDD, B = VSS) -40C Rw -40C INL -40C DNL DNL INL 32 64 96 Wiper Setting (decimal) 2500 RW -0.3 180 -0.3 0 25°C 40 220 0 20 Wiper Resistance (RW) (ohms) 0 60 260 0.2 180 Note: 0.1 300 0.3 0.2 125°C FIGURE 2-6: 5.0 kΩ : Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 5.5V).(IW = 1.4 mA, B = VSS) Wiper Resistance (RW) (ohms) 85C Rw 85C INL 85C DNL 0.3 80 0 Error (LSb) Wiper Resistance (RW) (ohms) 260 25C Rw 25C INL 25C DNL 125C Rw 125C INL 125C DNL 20 FIGURE 2-3: 5.0 kΩ : Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 5.5V). (A = VDD, B = VSS). -40C Rw -40C INL -40C DNL 85C Rw 85C INL 85C DNL 85°C 32 64 96 Wiper Setting (decimal) 300 25C Rw 25C INL 25C DNL INL -0.3 0 -40C Rw -40C INL -40C DNL 100 DNL INL 80 120 0.3 Error (LSb) 125°C 125C Rw 125C INL 125C DNL Error (LSb) 85°C 85C Rw 85C INL 85C DNL Error (LSb) 100 25C Rw 25C INL 25C DNL Wiper Resistance (RW) (ohms) -40C Rw -40C INL -40C DNL Error (LSb) Wiper Resistance (RW) (ohms) 120 -1 0 Note: 32 64 96 Wiper Setting (decimal) Refer to AN1080 for additional information on the characteristics of the wiper resistance (RW) with respect to device voltage and wiper setting value. FIGURE 2-8: 5.0 kΩ : Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V). (IW =260 µA, B = VSS) © 2009 Microchip Technology Inc. MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. -0.4 RBW Tempco (PPM) Full-Scale Error (FSE) (LSb) 0.0 -0.2 -0.6 -0.8 5.5V -1.0 -1.2 2.7 -1.4 1.8V -1.6 -1.8 -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-9: 5.0 kΩ : Full Scale Error (FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V). 200 180 160 140 120 100 80 60 40 20 0 2.7V 5.5V 0 32 64 96 Wiper Setting (decimal) FIGURE 2-12: 5.0 kΩ : RBW Tempco FIGURE 2-13: Response Time. 5.0 kΩ : Power-Up Wiper ΔRWB / ΔT vs. Code. Zero-Scale Error (ZSE) (LSb) 1.8 1.6 1.4 1.2 1.8V 1.0 2.7 0.8 0.6 0.4 5.5V 0.2 0.0 -40 0 40 80 Ambient Temperature (°C) 120 Nominal Resistance (RAB) (Ohms) FIGURE 2-10: 5.0 kΩ : Zero Scale Error (ZSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V). 5200 5180 5160 5140 5120 5100 5080 5060 5040 5020 5000 Wiper VDD 1.8V 2.7V 5.5V -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-11: 5.0 kΩ : Nominal Resistance (Ω) vs. Temperature and VDD. © 2009 Microchip Technology Inc. FIGURE 2-14: 5.0 kΩ : Digital Feedthrough (SCL signal coupling to Wiper pin). DS22152B-page 15 MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. FIGURE 2-15: 5.0 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=5.5V). FIGURE 2-18: 5.0 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=5.5V). FIGURE 2-16: 5.0 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=2.7V). FIGURE 2-19: 5.0 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=2.7V). FIGURE 2-17: 5.0 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=1.8V). FIGURE 2-20: 5.0 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=1.8V). DS22152B-page 16 © 2009 Microchip Technology Inc. MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 0.2 0.1 80 0 60 -0.1 -40°C DNL 25°C RW INL -0.2 20 -0.3 260 25C Rw 25C INL 25C DNL INL 220 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 180 0 140 -0.1 DNL 100 RW 25°C 60 -0.2 -40°C 20 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 2000 0.25 0.05 -0.05 1000 RW INL -0.15 -0.25 0 85°C FIGURE 2-23: 10 kΩ Pot Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V). (A = VDD, B = VSS). 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 125°C RW 3 2 25°C 100 0 60 -40°C DNL INL 20 -1 32 64 96 Wiper Setting (decimal) FIGURE 2-25: 10 kΩ Rheo Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 2.7V).(IW = 210 µA, B = VSS). -40C Rw -40C INL -40C DNL 3000 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 39 34 29 24 2000 19 INL 1000 DNL 4 -1 0 Note: 14 9 RW 0 32 64 96 Wiper Setting (decimal) Refer to AN1080 for additional information on the characteristics of the wiper resistance (RW) with respect to device voltage and wiper setting value. 25C Rw 25C INL 25C DNL 1 -0.35 © 2009 Microchip Technology Inc. -40C Rw -40C INL -40C DNL 0.35 0.15 DNL 0 -0.3 32 64 96 Wiper Setting (decimal) 140 Wiper Resistance (RW) (ohms) 3000 25C Rw 25C INL 25C DNL -0.1 -0.2 INL 0 Error (LSb) -40C Rw -40C INL -40C DNL RW 25°C 180 32 64 96 Wiper Setting (decimal) FIGURE 2-22: 10 kΩ Pot Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 2.7V). (A = VDD, B = VSS). Wiper Resistance (RW) (ohms) -40°C 40 FIGURE 2-24: 10 kΩ Rheo Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 5.5V).(IW = 450 µA, B = VSS). -0.3 0 Note: 0 220 0.1 0.2 125°C DNL 60 260 0.2 0.3 0.1 300 0.3 125°C 85° 125C Rw 125C INL 125C DNL 80 0 Error (LSb) Wiper Resistance (RW) (ohms) -40C Rw -40C INL -40C DNL 85C Rw 85C INL 85C DNL 20 FIGURE 2-21: 10 kΩ Pot Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 5.5V). (A = VDD, B = VSS). 300 25C Rw 25C INL 25C DNL 85°C 32 64 96 Wiper Setting (decimal) Wiper Resistance (RW) (ohms) 0 -40C Rw -40C INL -40C DNL 100 125°C 85°C 40 120 0.3 Error (LSb) 100 125C Rw 125C INL 125C DNL Error (LSb) 85C Rw 85C INL 85C DNL Error (LSb) 25C Rw 25C INL 25C DNL Wiper Resistance (RW) (ohms) -40C Rw -40C INL -40C DNL Error (LSb) Wiper Resistance (RW) (ohms) 120 32 64 96 Wiper Setting (decimal) Refer to AN1080 for additional information on the characteristics of the wiper resistance (RW) with respect to device voltage and wiper setting value. FIGURE 2-26: 10 kΩ Rheo Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V). (IW =260 µA, B = VSS). DS22152B-page 17 MCP40D17/18/19 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 100 RBW Tempco (PPM) Full-Scale Error (FSE) (LSb) Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 5.5V 2.7 1.8V 80 2.7V 60 40 5.5V 20 0 -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-27: 10 kΩ : Full Scale Error (FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V). 0 32 64 96 Wiper Setting (decimal) FIGURE 2-30: 10 kΩ : RBW Tempco FIGURE 2-31: Response Time. 10 kΩ : Power-Up Wiper ΔRWB / ΔT vs. Code. Zero-Scale Error (ZSE) (LSb) 0.9 0.8 0.7 0.6 1.8V 0.5 2.7 0.4 0.3 0.2 5.5V 0.1 0.0 -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-28: 10 kΩ : Zero Scale Error (ZSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V). Nominal Resistance (RAB) (Ohms) 10200 10150 10100 Wiper 1.8V 10050 VDD 10000 2.7 9950 5.5V 9900 -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-29: 10 kΩ : Nominal Resistance (Ω) vs. Temperature and VDD. DS22152B-page 18 FIGURE 2-32: 10 kΩ : Digital Feedthrough (SCL signal coupling to Wiper pin). © 2009 Microchip Technology Inc. MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. FIGURE 2-33: 10 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=5.5V). FIGURE 2-36: 10 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=5.5V). FIGURE 2-34: 10 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=2.7V). FIGURE 2-37: 10 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=2.7V). FIGURE 2-35: 10 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=1.8V). FIGURE 2-38: 10 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=1.8V). © 2009 Microchip Technology Inc. DS22152B-page 19 MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 0.2 0.1 0 60 DNL -0.1 INL -40°C RW 25°C -0.2 20 -0.3 260 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 220 125C Rw 125C INL 125C DNL 125°C 85° 0 DNL -0.1 INL RW 25°C 60 -0.2 20 -0.05 INL -0.15 2000 RW 0 -0.25 DS22152B-page 20 125C Rw 125C INL 125C DNL 125°C 0.3 0.2 INL 0.1 25°C -0.1 DNL 60 RW -0.2 -40°C 20 -0.3 32 64 96 Wiper Setting (decimal) FIGURE 2-43: 50 kΩ Rheo Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 2.7V).(IW = 45 µA, B = VSS). -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 8000 RW 6000 INL 4000 DNL 2000 -0.35 FIGURE 2-41: 50 kΩ Pot Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V). 85C Rw 85C INL 85C DNL 0 0 32 64 96 Wiper Setting (decimal) Refer to AN1080 for additional information on the characteristics of the wiper resistance (RW) with respect to device voltage and wiper setting value. 25C Rw 25C INL 25C DNL 85°C 10000 0.25 0.05 4000 -40C Rw -40C INL -40C DNL 100 Wiper Resistance (RW) (ohms) 6000 0 -0.3 140 0.35 0.15 DNL Note: 125C Rw 125C INL 125C DNL Error (LSb) Wiper Resistance (RW) (ohms) 8000 85C Rw 85C INL 85C DNL -0.2 32 64 96 Wiper Setting (decimal) 0 FIGURE 2-40: 50 kΩ Pot Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 2.7V). 25C Rw 25C INL 25C DNL RW 25°C 180 -0.3 -40C Rw -40C INL -40C DNL -0.1 -40°C 40 32 64 96 Wiper Setting (decimal) 10000 INL FIGURE 2-42: 50 kΩ Rheo Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 5.5V).(IW = 90 µA, B = VSS) -40°C 0 DNL 220 140 0.2 125°C 0 60 260 0.2 0.1 0.3 125C Rw 125C INL 125C DNL 0.1 300 0.3 180 100 85°C 0 Error (LSb) Wiper Resistance (RW) (ohms) -40C Rw -40C INL -40C DNL 85C Rw 85C INL 85C DNL 20 FIGURE 2-39: 50 kΩ Pot Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 5.5V). 300 25C Rw 25C INL 25C DNL 80 32 64 96 Wiper Setting (decimal) Wiper Resistance (RW) (ohms) 0 -40C Rw -40C INL -40C DNL 100 125°C 80 40 120 0.3 Error (LSb) 85°C 125C Rw 125C INL 125C DNL Error (LSb) 85C Rw 85C INL 85C DNL 0 Note: 23 21 19 17 15 13 11 9 7 5 3 1 -1 Error (LSb) 100 25C Rw 25C INL 25C DNL Wiper Resistance (RW) (ohms) -40C Rw -40C INL -40C DNL Error (LSb) Wiper Resistance (RW) (ohms) 120 32 64 96 Wiper Setting (decimal) Refer to AN1080 for additional information on the characteristics of the wiper resistance (RW) with respect to device voltage and wiper setting value. FIGURE 2-44: 50 kΩ Rheo Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V). (IW =260 µA, B = VSS). © 2009 Microchip Technology Inc. MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 100 RBW Tempco (PPM) Full-Scale Error (FSE) (LSb) 0.00 -0.04 -0.08 2.7 5.5V -0.12 1.8V -0.16 80 60 2.7V 40 5.5V 20 0 -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-45: 50 kΩ : Full Scale Error (FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V). 0 32 64 96 Wiper Setting (decimal) FIGURE 2-48: 50 kΩ : RBW Tempco FIGURE 2-49: Response Time. 50 kΩ : Power-Up Wiper ΔRWB / ΔT vs. Code. Zero-Scale Error (ZSE) (LSb) 0.20 0.16 1.8V 0.12 2.7 0.08 0.04 5.5V 0.00 -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-46: 50 kΩ : Zero Scale Error (ZSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V). Nominal Resistance (RAB) (Ohms) 49800 49600 Wiper 49400 49200 VDD 1.8V 2.7V 49000 5.5V 48800 -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-47: 50 kΩ : Nominal Resistance (Ω) vs. Temperature and VDD. © 2009 Microchip Technology Inc. FIGURE 2-50: 50 kΩ : Digital Feedthrough (SCL signal coupling to Wiper pin). DS22152B-page 21 MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. FIGURE 2-51: 50 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=5.5V). FIGURE 2-54: 50 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=5.5V). FIGURE 2-52: 50 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=2.7V). FIGURE 2-55: 50 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=2.7V). FIGURE 2-53: 50 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=1.8V). FIGURE 2-56: 50 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=1.8V). DS22152B-page 22 © 2009 Microchip Technology Inc. MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 0.2 0.1 0 INL 40 -0.1 RW -40°C 25°C -0.2 20 -0.3 260 25C Rw 25C INL 25C DNL DNL 220 85° 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 0 -0.1 100 INL 25°C 60 RW -0.2 2500 RW INL 0 -0.25 FIGURE 2-59: 100 kΩ Pot Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V). © 2009 Microchip Technology Inc. 0.3 0.2 -0.1 -40°C RW -0.2 25°C 20 -0.3 32 64 96 Wiper Setting (decimal) FIGURE 2-61: 100 kΩ Rheo Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 2.7V). (IW = 21 µA, B = VSS). -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL RW 10000 INL 7500 5000 DNL 2500 0 32 64 96 Wiper Setting (decimal) Refer to AN1080 for additional information on the characteristics of the wiper resistance (RW) with respect to device voltage and wiper setting value. 125°C DNL 60 -0.35 0 85°C 125C Rw 125C INL 125C DNL 0 12500 -0.15 85C Rw 85C INL 85C DNL 0.1 0.25 -0.05 5000 25C Rw 25C INL 25C DNL INL 15000 0.05 7500 -40C Rw -40C INL -40C DNL 0.35 0.15 DNL 10000 125C Rw 125C INL 125C DNL -0.2 -0.3 100 Wiper Resistance (RW) (ohms) 85C Rw 85C INL 85C DNL Error (LSb) 12500 25C Rw 25C INL 25C DNL INL 32 64 96 Wiper Setting (decimal) 0 FIGURE 2-58: 100 kΩ Pot Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 2.7V). -40C Rw -40C INL -40C DNL 25°C 140 32 64 96 Wiper Setting (decimal) 15000 RW 180 -0.3 0 Wiper Resistance (RW) (ohms) -0.1 -40°C 40 FIGURE 2-60: 100 kΩ Rheo Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 5.5V). (IW = 45 µA, B = VSS). -40°C 20 Note: 0 220 140 0.2 DNL 60 260 0.2 125°C 0.1 0.3 125C Rw 125C INL 125C DNL 0.1 300 0.3 180 125°C 85°C 0 Error (LSb) Wiper Resistance (RW) (ohms) -40C Rw -40C INL -40C DNL 85C Rw 85C INL 85C DNL 20 FIGURE 2-57: 100 kΩ Pot Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 5.5V). 300 25C Rw 25C INL 25C DNL 80 32 64 96 Wiper Setting (decimal) Wiper Resistance (RW) (ohms) 0 -40C Rw -40C INL -40C DNL 100 DNL 80 60 120 0.3 Error (LSb) 125°C 85°C 125C Rw 125C INL 125C DNL Error (LSb) 85C Rw 85C INL 85C DNL 0 Note: 19 17 15 13 11 9 7 5 3 1 -1 Error (LSb) 100 25C Rw 25C INL 25C DNL Wiper Resistance (RW) (ohms) -40C Rw -40C INL -40C DNL Error (LSb) Wiper Resistance (RW) (ohms) 120 32 64 96 Wiper Setting (decimal) Refer to AN1080 for additional information on the characteristics of the wiper resistance (RW) with respect to device voltage and wiper setting value. FIGURE 2-62: 100 kΩ Rheo Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V). (IW =260 µA, B = VSS). DS22152B-page 23 MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 100 RBW Tempco (PPM) Full-Scale Error (FSE) (LSb) 0.00 -0.02 5.5V -0.04 2.7 -0.06 80 60 2.7V 40 20 5.5V 1.8V -0.08 0 -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-63: 100 kΩ : Full Scale Error (FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V). 0 32 64 96 Wiper Setting (decimal) FIGURE 2-66: 100 kΩ : RBW Tempco ΔRWB / ΔT vs. Code. Zero-Scale Error (ZSE) (LSb) 0.12 0.08 1.8V 2.7 0.04 5.5V 0.00 -40 0 40 80 Ambient Temperature (°C) 120 Nominal Resistance (RAB) (Ohms) FIGURE 2-64: 100 kΩ : Zero Scale Error (ZSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V). 99800 99600 99400 99200 99000 98800 98600 98400 98200 98000 97800 FIGURE 2-67: Response Time. 100 kΩ : Power-Up Wiper Wiper VDD 1.8V 2.7V 5.5V -40 0 40 80 Ambient Temperature (°C) FIGURE 2-65: 100 kΩ : Nominal Resistance (Ω) vs. Temperature and VDD. DS22152B-page 24 120 FIGURE 2-68: 100 kΩ : Digital Feedthrough (SCL signal coupling to Wiper pin). © 2009 Microchip Technology Inc. MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. FIGURE 2-69: 100 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD = 5.5V). FIGURE 2-72: 100 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD = 5.5V). FIGURE 2-70: 100 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD = 2.7V). FIGURE 2-73: 100 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD = 2.7V). FIGURE 2-71: 100 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD = 1.8V). FIGURE 2-74: 100 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD = 1.8V). © 2009 Microchip Technology Inc. DS22152B-page 25 MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 4 0.3 3.5 2.5 VOL (mV) VIH (V) 0.25 5.5V 3 2.7V 2 1.5 2.7V (@ 3mA) 0.2 0.15 5.5V (@ 3mA) 0.1 1 1.8V (@ 1mA) 0.05 0.5 1.8V 0 0 -40 0 40 80 120 -40 0 Temperature (°C) FIGURE 2-75: Temperature. VIH (SCL, SDA) vs. VDD and FIGURE 2-77: Temperature. 80 120 VOL (SDA) vs. VDD and 1.2 2 5.5 V 1 5.5V 1.5 2.7V 0.8 VDD (V) VIL (V) 40 Temperature (°C) 1 2.7V 0.6 0.4 0.5 1.8V 0.2 0 0 -40 0 40 80 120 -40 0 Temperature (°C) FIGURE 2-76: Temperature. DS22152B-page 26 VIL (SCL, SDA) vs. VDD and 40 80 120 Temperature (°C) FIGURE 2-78: and Temperature. POR/BOR Trip point vs. VDD © 2009 Microchip Technology Inc. MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 10 10 Code = 7Fh Code = 7Fh 0 0 Code = 3Fh dB dB -20 Code = 0Fh -30 Code = 3Fh -10 -10 Code = 1Fh Code = 1Fh -20 Code = 0Fh -30 Code = 01h -40 Code = 01h -40 -50 -50 100 1,000 -60 100 10,000 1,000 5 kΩ – Gain vs. Frequency FIGURE 2-79: (-3 dB). FIGURE 2-82: 100 kΩ – Gain vs. Frequency (-3 dB). 2.1 10 10,000 Frequency (kHz) Frequency (kHz) Test Circuits Code = 7Fh 0 Code = 3Fh +5V dB -10 -20 -30 +5V Code = 0Fh Code = 1Fh VIN Code = 01h A W -40 B -50 -60 100 1,000 + VOUT - 10,000 Frequency (kHz) FIGURE 2-80: (-3 dB). 10 kΩ – Gain vs. Frequency FIGURE 2-83: (-3 dB). Gain vs. Frequency Test 10 Code = 7Fh 0 Code = 3Fh dB -10 Code = 1Fh -20 Code = 0Fh -30 Code = 01h -40 -50 -60 100 1,000 10,000 Frequency (kHz) FIGURE 2-81: (-3 dB). 50 kΩ – Gain vs. Frequency © 2009 Microchip Technology Inc. DS22152B-page 27 MCP40D17/18/19 NOTES: DS22152B-page 28 © 2009 Microchip Technology Inc. MCP40D17/18/19 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. Additional descriptions of the device pins follow. TABLE 3-1: PINOUT DESCRIPTION FOR THE MCP40D17/18/19 Pin Number Pin Name MCP40D17 MCP40D18 MCP40D19 (SC70-6) (SC70-6) (SC70-5) Pin Type Buffer Type Function VDD 1 1 1 P — Positive Power Supply Input VSS 2 2 2 P — Ground SCL 3 3 3 I/O ST (OD) I2C Serial Clock pin SDA 4 4 4 I/O ST (OD) I2C Serial Data pin B 5 — — I/O A Potentiometer Terminal B W 6 5 5 I/O A Potentiometer Wiper Terminal A — 6 — I/O A Potentiometer Terminal A Legend: A = Analog input I = Input © 2009 Microchip Technology Inc. ST (OD) = Schmitt Trigger with Open Drain O = Output I/O = Input/Output P = Power DS22152B-page 29 MCP40D17/18/19 3.1 Positive Power Supply Input (VDD) The VDD pin is the device’s positive power supply input. The input power supply is relative to VSS and can range from 1.8V to 5.5V. A de-coupling capacitor on VDD (to VSS) is recommended to achieve maximum performance. While the device’s voltage is in the range of 1.8V ≤ VDD < 2.7V, the Resistor Network’s electrical performance of the device may not meet the data sheet specifications. 3.2 Ground (VSS) The VSS pin is the device ground reference. 3.3 I2C Serial Clock (SCL) The SCL pin is the serial clock pin of the I2C interface. The MCP40D17/18/19 acts only as a slave and the SCL pin accepts only external serial clocks. The SCL pin is an open-drain output. Refer to Section 5.0 “Serial Interface - I2C Module” for more details of I2C Serial Interface communication. 3.4 I2C Serial Data (SDA) The SDA pin is the serial data pin of the I2C interface. The SDA pin has a Schmitt trigger input and an open-drain output. Refer to Section 5.0 “Serial Interface - I2C Module” for more details of I2C Serial Interface communication. 3.5 3.6 Potentiometer Wiper (W) Terminal The terminal W pin is connected to the internal potentiometer’s terminal W (the wiper). The wiper terminal is the adjustable terminal of the digital potentiometer. The terminal W pin does not have a polarity relative to terminals A or B pins. The terminal W pin can support both positive and negative current. The voltage on terminal W must be between VSS and VDD. 3.7 Potentiometer Terminal A The terminal A pin (available on some devices) is connected to the internal potentiometer’s terminal A. The potentiometer’s terminal A is the fixed connection to the Full Scale (0x7F tap) wiper value of the digital potentiometer. The terminal A pin is available on the MCP40D18 devices. The terminal A pin does not have a polarity relative to the terminal W pin. The terminal A pin can support both positive and negative current. The voltage on terminal A must be between VSS and VDD. The terminal A pin is not available on the MCP40D17 and MCP40D19 devices. For these devices, the potentiometer’s terminal A is internally floating. Potentiometer Terminal B The terminal B pin (available on some devices) is connected to the internal potentiometer’s terminal B. The potentiometer’s terminal B is the fixed connection to the Zero Scale (0x00 tap) wiper value of the digital potentiometer. The terminal B pin is available on the MCP40D17 device. The terminal B pin does not have a polarity relative to the terminal W pin. The terminal B pin can support both positive and negative current. The voltage on terminal B must be between VSS and VDD. The terminal B pin is not available on the MCP40D18 and MCP40D19 devices. For these devices, the potentiometer’s terminal B is internally connected to VSS. DS22152B-page 30 © 2009 Microchip Technology Inc. MCP40D17/18/19 4.0 GENERAL OVERVIEW The MCP40D17/18/19 devices are general purpose digital potentiometers intended to be used in applications where a programmable resistance with moderate bandwidth is desired. This Data Sheet covers a family of three Digital Potentiometer and Rheostat devices. The MCP40D18 device is the Potentiometer configuration, while the MCP40D17 and MCP40D19 devices are the Rheostat configuration. Applications generally suited for the MCP40D17/18/19 devices include: • • • • • Computer Servers Set point or offset trimming Sensor calibration Selectable gain and offset amplifier designs Cost-sensitive mechanical trim pot replacement 4.1.1 POWER-ON RESET When the device powers up, the device VDD will cross the VPOR/VBOR voltage. Once the VDD voltage crosses the VPOR/VBOR voltage, the following happens: • Volatile wiper register is loaded with the default wiper value (3Fh) • The device is capable of digital operation 4.1.2 BROWN-OUT RESET When the device powers down, the device VDD will cross the VPOR/VBOR voltage. Once the VDD voltage decreases below the VPOR/VBOR voltage the following happens: • Serial Interface is disabled If the VDD voltage decreases below the VRAM voltage the following happens: • Volatile wiper registers may become corrupted As the Device Block Diagram shows, there are four main functional blocks. These are: As the voltage recovers above the VPOR/VBOR voltage see Section 4.1.1 “Power-on Reset”. • POR/BOR Operation • Serial Interface - I2C Module • Resistor Network Serial commands not completed due to a Brown-out condition may cause the memory location to become corrupted. The POR/BOR operation and the Memory Map are discussed in this section and the I2C and Resistor Network operation are described in their own sections. The Serial Commands commands are discussed in Section 5.4. 4.1.3 4.1 POR/BOR Operation The Power-on Reset is the case where the device is having power applied to it from VSS. The Brown-out Reset occurs when a device had power applied to it, and that power (voltage) drops below the specified range. The devices RAM retention voltage (VRAM) is lower than the POR/BOR voltage trip point (VPOR/VBOR). The maximum VPOR/VBOR voltage is less than 1.8V. WIPER REGISTER (RAM) The Wiper Register is volatile memory that starts functioning at the RAM retention voltage (VRAM). The Wiper Register will be loaded with the default wiper value when VDD will rise above the VPOR/VBOR voltage. 4.1.4 DEVICE CURRENTS The current of the device can be classified into two modes of the device operation. These are: • Serial Interface Inactive (Static Operation) • Serial Interface Active Static Operation occurs when a Stop condition is received. Static Operation is exited when a Start condition is received. When VPOR/VBOR < VDD < 2.7V, the Resistor Network’s electrical performance may not meet the data sheet specifications. In this region, the device is capable of reading and writing to its volatile memory if the proper serial command is executed. Table 4-1 shows the digital pot’s level of functionality across the entire VDD range, while Figure 4-1 illustrates the Power-up and Brown-out functionality. © 2009 Microchip Technology Inc. DS22152B-page 31 MCP40D17/18/19 TABLE 4-1: VDD Level DEVICE FUNCTIONALITY AT EACH VDD REGION (NOTE 1) Serial Interface Potentiometer Terminals “unknown” VDD < VBOR < 1.8V Ignored VBOR ≤ VDD < 1.8V “Unknown” Operational with reduced electrical specs 1.8V ≤ VDD < 2.7V Accepted Operational with reduced electrical specs 2.7V ≤ VDD ≤ 5.5V Accepted Operational Note 1: Wiper Setting Comment Unknown Wiper Register loaded with POR/BOR value Wiper Register Electrical performance may not determines Wiper meet the data sheet specifications. Setting Wiper Register Meets the data sheet specifications determines Wiper Setting For system voltages below the minimum operating voltage, the customer will be recommended to use a voltage supervisor to hold the system in reset. This will ensure that MCP4017/18/19 commands are not attempted out of the operating range of the device. Normal Operation Range VDD Outside Specified AC/DC Range Normal Operation Range 2.7V 1.8V VPOR/BOR VRAM VSS FIGURE 4-1: DS22152B-page 32 Analog Characteristics not specified Analog Characteristics not specified Device’s Serial VBOR Delay Interface is “Not Operational” Wiper Forced to Default POR/BOR setting Power-up and Brown-out. © 2009 Microchip Technology Inc. MCP40D17/18/19 5.0 SERIAL INTERFACE I2C MODULE 5.1 A 2-wire I2C serial protocol is used to write or read the digital potentiometer’s wiper register. The I2C protocol utilizes the SCL input pin and SDA input/output pin. The I2C serial interface supports the following features: • Slave mode of operation • 7-bit addressing • The following clock rate modes are supported: - Standard mode, bit rates up to 100 kb/s - Fast mode, bit rates up to 400 kb/s • Support Multi-Master Applications The serial clock is generated by the Master. The I2C Module is compatible with the Phillips I2C specification. Philips only defines the field types, field lengths, timings, etc. of a frame. The frame content defines the behavior of the device. The frame content for the MCP40D17, MCP40D18, and MCP40D19 devices are defined in this section of the data sheet. Figure 5-1 shows a typical I2C bus configurations. Single I2C Bus Configuration Device 1 Device n Host Controller Device 2 FIGURE 5-1: Configurations. I2C specifications require active low, passive high functionality on devices interfacing to the bus. Since devices may be operating on separate power supply sources, ESD clamping diodes are not permitted. The specification recommends using open drain transistors tied to VSS (common) with a pull-up resistor. The specification makes some general recommendations on the size of this pull-up, but does not specify the exact value since bus speeds and bus capacitance impacts the pull-up value for optimum system performance. Common pull-up values range from 1 kΩ to a maximum of ~10 kΩ. Power sensitive applications tend to choose higher values to minimize current losses during communication but these applications also typically utilize lower VDD. The SDA and SCL float (are not driving) when the device is powered down. A "glitch" filter is on the SCL and SDA pins when the pin is an input. When these pins are an output, there is a slew rate control of the pin that is independent of device frequency. 5.1.1 Device 3 Device 4 I2C I/O Considerations SLOPE CONTROL The device implements slope control on the SDA output. The slope control is defined by the fast mode specifications. For Fast (FS) mode, the device has spike suppression and Schmidt trigger inputs on the SDA and SCL pins. Typical Application I2C Bus Refer to Section 2.0 “Typical Performance Curves”, AC/DC Electrical Characteristics table for detailed input threshold and timing specifications. © 2009 Microchip Technology Inc. DS22152B-page 33 MCP40D17/18/19 5.2 I2C Bit Definitions If the Slave Address is not valid, the Slave Device will issue a Not A (A). The A bit will have the SDA signal high. I2C bit definitions include: • • • • • • Start Bit Data Bit Acknowledge (A) Bit Repeated Start Bit Stop Bit Clock Stretching If an error condition occurs (such as an A instead of A) then a START bit must be issued to reset the command state machine. TABLE 5-1: Figure 5-8 shows the waveform for these states. 5.2.1 START BIT The Start bit (see Figure 5-2) indicates the beginning of a data transfer sequence. The Start bit is defined as the SDA signal falling when the SCL signal is “High”. 2nd Bit 1st Bit SDA Acknowledge Bit Response Event General Call A Slave Address valid A Slave Address not valid A Bus Collision N.A. SCL S FIGURE 5-2: 5.2.2 Start Bit. 5.2.4 DATA BIT The SDA signal may change state while the SCL signal is Low. While the SCL signal is High, the SDA signal MUST be stable (see Figure 5-3). 2nd Bit 1st Bit SDA S FIGURE 5-3: Data Bit. REPEATED START BIT Note 1: A bus collision during the Repeated Start condition occurs if: ACKNOWLEDGE (A) BIT SCL I2C Module Resets, or a “Don’t Care” if the collision occurs on the Masters “Start bit”. The Repeated Start bit (see Figure 5-5) indicates the current Master Device wishes to continue communicating with the current Slave Device without releasing the I2C bus. The Repeated Start condition is the same as the Start condition, except that the Repeated Start bit follows a Start bit (with the Data bits + A bit) and not a Stop bit. • SDA is sampled low when SCL goes from low to high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". The A bit (see Figure 5-4) is a response from the Slave device to the Master device. Depending on the context of the transfer sequence, the A bit may indicate different things. Typically the Slave device will supply an A response after the Start bit and 8 “data” bits have been received. The A bit will have the SDA signal low. SDA Comment The Start bit is the beginning of a data transfer sequence and is defined as the SDA signal falling when the SCL signal is “High”. SCL 5.2.3 MCP40D17/18/19 A / A RESPONSES D0 8 FIGURE 5-4: A SDA 1st Bit 9 Acknowledge Waveform. SCL Sr = Repeated Start FIGURE 5-5: Waveform. DS22152B-page 34 Repeat Start Condition © 2009 Microchip Technology Inc. MCP40D17/18/19 5.2.5 STOP BIT 5.2.7 If any part of the I2C transmission does not meet the command format, it is aborted. This can be intentionally accomplished with a START or STOP condition. This is done so that noisy transmissions (usually an extra START or STOP condition) are aborted before they corrupt the device. The Stop bit (see Figure 5-6) Indicates the end of the I2C Data Transfer Sequence. The Stop bit is defined as the SDA signal rising when the SCL signal is “High”. A Stop bit resets the I2C interface of the other devices. SDA A / A 5.2.8 SCL 5.2.6 IGNORING AN I2C TRANSMISSION AND “FALLING OFF” THE BUS The MCP40D17/18/19 expects to receive entire, valid I2C commands and will assume any command not defined as a valid command is due to a bus corruption and will enter a passive high condition on the SDA signal. All signals will be ignored until the next valid START condition and CONTROL BYTE are received. P FIGURE 5-6: Transmit Mode. ABORTING A TRANSMISSION Stop Condition Receive or CLOCK STRETCHING “Clock Stretching” is something that the Secondary Device can do, to allow additional time to “respond” to the “data” that has been received. The MCP40D17/18/19 will not strech the clock signal (SCL) since memory read accesses occur fast enough. SDA SCL S FIGURE 5-7: 1st 2nd 3rd 4th 5th 6th 7th 8th A/A 1st 2nd 3rd 4th 5th 6th 7th 8th A/A Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit P Typical 16-bit I2C Waveform Format. SDA SCL START Condition FIGURE 5-8: Data allowed to change Data or A valid STOP Condition I2C Data States and Bit Sequence. © 2009 Microchip Technology Inc. DS22152B-page 35 MCP40D17/18/19 I2C COMMAND PROTOCOL 5.2.9 TABLE 5-2: The MCP40D17/18/19 is a slave I2C device which supports 7-bit slave addressing. The slave address contains seven fixed bits. Figure 5-9 shows the control byte format. MCP40D17 5.2.9.1 MCP40D19 Device MCP40D18 Control Byte (Slave Address) The Control Byte is always preceded by a START condition. The Control Byte contains the slave address consisting of seven fixed bits and the R/W bit. Figure 59 shows the control byte format and Table 5-2 shows the I2C address for the devices. 5.2.9.2 5.2.10 Comment ‘0101110’ ‘0101110’ ‘0111110’ ‘0101110’ MCP40D18-xxxE/LT MCP40D18-xxxAE/LT Hardware Address Pins GENERAL CALL The General Call is a method that the Master device can communicate with all other Slave devices. The MCP40D17/18/19 devices do not respond to General Call address and commands, and therefore the communications are Not Acknowledged. Slave Address Start bit I2C Address The MCP40D17/MCP40D18/MCP40D19 does not support hardware address bits. All devices are offered with the I2C slave address of “0101110”, while the MCP40D18 also offers a second standard I2C slave address of “0111110”. S A6 A5 A4 A3 A2 A1 A0 R/W “0” “1” “0” “1” “1” “1” “0” DEVICE I2C ADDRESS A/A R/W bit R/W = 0 = write R/W = 1 = read A bit (controlled by slave device) A = 0 = Slave Device Acknowledges byte A = 1 = Slave Device does not Acknowledge byte FIGURE 5-9: Slave Address Bits in the I2C Control Byte (Slave Address = “0101110”). Second Byte S 0 0 0 0 0 0 0 0 A General Call Address X X X X X X X 0 A P “7-bit Command” Reserved 7-bit Commands (By I2C Specification - Philips # 9398 393 40011, Ver. 2.1 January 2000) “0000 011”b - Reset and write programmable part of slave address by hardware “0000 010”b - Write programmable part of slave address by hardware “0000 000”b - NOT Allowed The Following is a “Hardware General Call” Format Second Byte S 0 0 0 0 0 0 0 0 A General Call Address FIGURE 5-10: DS22152B-page 36 X X X X X “7-bit Command” n occurrences of (Data + A / A) X X 1 A X X X X X X X X A P This indicates a “Hardware General Call” MCP40D17/18/19 will ignore this byte and all following bytes (and A), until a Stop bit (P) is encountered. General Call Formats. © 2009 Microchip Technology Inc. MCP40D17/18/19 5.3 Software Reset Sequence Note: This technique should be supported by any I2C compliant device. The 24XXXX I2C Serial EEPROM devices support this technique, which is documented in AN1028. The Stop bit terminates the current I2C bus activity. The MCP40D17/18/19 wait to detect the next Start condition. This sequence does not effect any other I2C devices which may be on the bus, as they should disregard this as an invalid command. At times it may become necessary to perform a Software Reset Sequence to ensure the MCP40D17/ 18/19 device is in a correct and known I2C Interface state. This only resets the I2C state machine. 5.4 This is useful if the MCP40D17/18/19 device powers up in an incorrect state (due to excessive bus noise, etc), or if the Master Device is reset during communication. Figure 5-11 shows the communication sequence to software reset the device. • Write Operation • Read Operations S ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ S P Nine bits of ‘1’ Start bit Start bit Stop bit FIGURE 5-11: Format. Software Reset Sequence Serial Commands The MCP40D17/18/19 devices support 2 serial commands. These commands are: The I2C command formats have been defined so to support the SMBus version 2.0 Write Byte/Word Protocol formats and Read Byte/Word Protocol formats. The SMBus specification defines this operation is Section 5 of the Version 2.0 document (August 3, 2000). This protocol format may be convienient for customers using library routines for the I2C bus, where all they need to do is specify the command (read, write, ...) with the Device Address, the Register Address, and the Data. If higher data throughput is desired, please look at the MCP4017/18/19 devices which have a simplier I2C command format. The 1st Start bit will cause the device to reset from a state in which it is expecting to receive data from the Master Device. In this mode, the device is monitoring the data bus in Receive mode and can detect the Start bit forces an internal Reset. The nine bits of ‘1’ are used to force a Reset of those devices that could not be reset by the previous Start bit. This occurs only if the MCP40D17/18/19 is driving an A on the I2C bus, or is in output mode (from a Read command) and is driving a data bit of ‘0’ onto the I2C bus. In both of these cases, the previous Start bit could not be generated due to the MCP40D17/18/19 holding the bus low. By sending out nine ‘1’ bits, it is ensured that the device will see a A (the Master Device does not drive the I2C bus low to acknowledge the data sent by the MCP40D17/18/19), which also forces the MCP40D17/18/19 to reset. The 2nd Start bit is sent to address the rare possibility of an erroneous write. This could occur if the Master Device was reset while sending a Write command to the MCP40D17/18/19, AND then as the Master Device returns to normal operation and issues a Start condition while the MCP40D17/18/19 is issuing an A. In this case if the 2nd Start bit is not sent (and the Stop bit was sent) the MCP40D17/18/19 could initiate a write cycle. Note: The potential for this erroneous write ONLY occurs if the Master Device is reset while sending a Write command to the MCP40D17/18/19. © 2009 Microchip Technology Inc. DS22152B-page 37 MCP40D17/18/19 5.4.1 WRITE OPERATION 5.4.2 The read operation requires the START condition, Control Byte, Acknowledge, Command Code, Acknowledge, Restart Condition, Control Byte, Acknowledge, Data Byte, the master generating the A and STOP (or RESTART) condition. The first Control Byte requires the R/W bit equal to a logic zero (R/W = “0”) to write the Command Code, while the second Control Byte requires the R/W bit equal to a logic one (R/W = “1”) to generate a read sequence. The MCP40D17/18/19 will A the Slave Address Byte and A all the Data Bytes. The I2C Master will A the Slave Address Byte and the last Data Byte. If there are multiple Data Bytes, the I2C Master will A all Data Bytes except the last Data Byte (which it will A). The write operation requires the START condition, Control Byte, Acknowledge, Command Code, Acknowledge, Data Byte, Acknowledge and STOP (or RESTART) condition. The Control (Slave Address) Byte requires the R/W bit equal to a logic zero (R/W = “0”) to generate a write sequence. The MCP40D17/ 18/19 is responsible for generating the Acknowledge (A) bits. Data is written to the MCP40D17/18/19 after every byte transfer (during the A bit). If a STOP or RESTART condition is generated during a data transfer (before the A bit), the data will not be written to MCP40D17/18/ 19. Data bytes may be written after each Acknowledge. The command is terminated once a Stop (P) condition occurs. Refer to Figure 5-12 for the single byte write sequence and Figure 5-13 for the generic (multi-byte) write sequence. For a single byte write, the master sends a STOP or RESTART condition after the 1st data byte is sent. The MCP40D17/18/19 maintains control of the SDA signal until all data bits have been clocked out. The command is terminated once a Stop (P) or Restart (S) condition occurs. Refer to Figure 5-15 for the read command sequence. For a single read, the master sends a STOP or RESTART condition after the 1st data byte (and A bit) is sent from the slave. The MSb of each Data Byte is a don’t care, since the wiper register is only 7-bits wide. Figure 5-16 shows the I2C read communication behavior of the Master Device and the MCP40D17/18/ 19 device and the resultant I2C bus values. The command is terminated once a Stop (P) or Restart (S) condition occurs. Figure 5-14 shows the I2C write communication behavior of the Master Device and the MCP40D17/18/ 19 device and the resultant I2C bus values. Note: READ OPERATIONS Note: A command code with a non-zero value will cause the data not to be read from the wiper register A command code with a non-zero value will cause the data not to be written to the wiper register Fixed Address S 0 1 0 1 1 Read/Write bit (“0” = Write) 1 0 Slave Address Byte 0 A 0 0 0 0 0 0 Command Code 0 0 STOP bit A X D6 D5 D4 D3 D2 D1 D0 A P Data Byte Legend S = Start Condition P = Stop Condition A = Acknowledge X = Don’t Care R/W = Read/Write bit D6:D0 = Data bits FIGURE 5-12: DS22152B-page 38 I2C Single Byte Write Command Format (Slave Address = “0101110”). © 2009 Microchip Technology Inc. MCP40D17/18/19 Fixed Address S 0 1 0 1 1 Read/Write bit (“0” = Write) 1 1 0 A 0 0 0 0 0 0 0 0 A X D6 D5 D4 D3 D2 D1 D0 A Command Code Slave Address Byte Data Byte STOP bit X D6 D5 D4 D3 D2 D1 D0 A X D6 D5 D4 D3 D2 D1 D0 A P Data Byte Data Byte Legend S = Start Condition P = Stop Condition A = Acknowledge X = Don’t Care R/W = Read/Write bit D6:D0 = Data bits FIGURE 5-13: I2C Write Command Format (Slave Address = “0101110”). Write 1 Byte with Command Code = 00h S Slave Address Master R A / C W K Command Code A C K Data Byte A C K P S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 d d d d d d d 1 P MCP40D17/18/19 I2C Bus 0 0 0 S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 d d d d d d d 0 P Write 2 Byte with Command Code = 00h S Slave Address Master R A / C W K Command Code A C K Data Byte S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 d d d d d d d 1 MCP40D17/18/19 I2C Bus 0 0 0 S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 d d d d d d d 0 Data Byte Master A C K P 0 d d d d d d d 1 P MCP40D17/18/19 I2C Bus FIGURE 5-14: A C K 0 0 d d d d d d d 0 P I2C Write Communication Behavior (Slave Address = “0101110”). © 2009 Microchip Technology Inc. DS22152B-page 39 MCP40D17/18/19 Read/Write bit (“0” = Write) S 0 1 0 1 1 1 0 0 A 0 0 0 0 0 0 0 0 A Command Code Slave Address Byte STOP bit Read/Write bit (“1” = Read) S 0 1 0 1 1 1 0 1 A 0 D6 D5 D4 D3 D2 D1 D0 A(2) P Slave Address Byte Legend S = Start Condition P = Stop Condition A = Acknowledge X = Don’t Care R/W = Read/Write bit D6:D0 = Data bits Data Byte Note 1: Master Device is responsible for ACK / NACK signal. If a NACK signal occurs, the MCP40D17/18/19 will abort this transfer and release the bus. 2: The Master Device will Not ACK, and the MCP40D17/18/19 will release the bus so the Master Device can generate a Stop or Repeated Start condition. FIGURE 5-15: I2C Read Command Format (Slave Address = “0101110”). Read 1 Byte with Command Code = 00h S Slave Address Master R A / C W K Command Code A C R K S Slave Address R A / C WK S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 S 0 1 0 1 1 1 0 1 1 MCP40D17/18/19 I2C Bus 0 0 0 S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 S 0 1 0 1 1 1 0 1 0 Data Byte Master A C K P 1 P MCP40D17/18/19 0 d d d d d d d 1 I2C Bus 0 d d d d d d d 1 P Read 2 Byte with Command Code = 00h S Slave Address Master R A / C W K Command Code A C R K S Slave Address R A / C WK S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 S 0 1 0 1 1 1 0 1 1 MCP40D17/18/19 I2C Bus 0 0 0 S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 S 0 1 0 1 1 1 0 1 0 Data Byte Master A C K Data Byte A C K P 0 1 P MCP40D17/18/19 0 d d d d d d d 1 0 d d d d d d d 1 I2C Bus 0 d d d d d d d 0 0 d d d d d d d 1 P FIGURE 5-16: DS22152B-page 40 I2C Read Communication Behavior (Slave Address = “0101110”). © 2009 Microchip Technology Inc. MCP40D17/18/19 6.0 RESISTOR NETWORK A The Resistor Network is made up of two parts. These are: • Resistor Ladder • Wiper Figure 6-1 shows a block diagram for the resistive network. RS RW (1) RW (1) RW (1) N = 126 RS 7Eh N = 125 Digital potentiometer applications can be divided into two resistor network categories: • Rheostat configuration • Potentiometer (or voltage divider) configuration 7Fh N = 127 RS 7Dh W The MCP40D17 is a true rheostat, with terminal B and the wiper (W) of the variable resistor available on pins. The MCP40D18 device offers a voltage divider (potentiometer) with terminal B internally connected to ground. The MCP40D19 device is a Rheostat device with terminal A of the resistor floating, terminal B internally connected to ground, and the wiper (W) available on pin. 6.1 Resistor Ladder Module The resistor ladder is a series of equal value resistors (RS) with a connection point (tap) between the two resistors. The total number of resistors in the series (ladder) determines the RAB resistance (see Figure 6-1). The end points of the resistor ladder are connected to the device Terminal A and Terminal B pins. The RAB (and RS) resistance has small variations over voltage and temperature. The Resistor Network has 127 resistors in a string between terminal A and terminal B. This gives 7-bits of resolution. The wiper can be set to tap onto any of these 127 resistors thus providing 128 possible settings (including terminal A and terminal B). This allows zero scale to full scale connections. N=1 RS 01h RW (1) RW (1) N=0 B 00h Analog Mux Note 1: The wiper resistance is tap dependent. That is, each tap selection resistance has a small variation. This variation has more effect on devices with smaller RAB resistance (5.0 kΩ). FIGURE 6-1: Diagram. TABLE 6-1: Wiper Setting 07Fh 07Eh - 040h 03Fh 03Eh - 001h 000h Resistor Network Block WIPER SETTING MAP Properties Full Scale (W = A) W=N W = N (Mid Scale) W=N Zero Scale (W = B) A wiper setting of 00h connects the Terminal W (wiper) to Terminal B (Zero Scale). A wiper setting of 3Fh is the Mid scale setting. A wiper setting of 7Fh connects the Terminal W (wiper) to Terminal A (Full Scale). Table 6-1 illustrates the full wiper setting map. Terminal A and B as well as the wiper W do not have a polarity. These terminals can support both positive and negative current. © 2009 Microchip Technology Inc. DS22152B-page 41 MCP40D17/18/19 Step resistance (RS) is the resistance from one tap setting to the next. This value will be dependent on the RAB value that has been selected. Equation 6-1 shows the calculation for the step resistance while Table 6-2 shows the typical step resistances for each device. EQUATION 6-1: RS CALCULATION A POR/BOR event will load the Volatile Wiper register value with the default value. Table 6-3 shows the default values offered. TABLE 6-3: DEFAULT FACTORY SETTINGS SELECTION Resistance Typical Code RAB Value R AB R S = --------127 Default POR Wiper Setting Code (1) -502 5.0 kΩ Mid-scale 3Fh Equation 6-2 illustrates the calculation used to determine the resistance between the wiper and terminal B. -103 10.0 kΩ Mid-scale 3Fh -503 50.0 kΩ Mid-scale 3Fh -104 100.0 kΩ Mid-scale 3Fh EQUATION 6-2: Note 1: RWB CALCULATION R AB N - + RW R WB = ------------127 N = 0 to 127 (decimal) Custom POR/BOR Wiper Setting options are available, contact the local Microchip Sales Office for additional information. Custom options have minimum volume requirements. The digital potentiometer is available in four nominal resistances (RAB) where the nominal resistance is defined as the resistance between terminal A and terminal B. The four nominal resistances are 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The total resistance of the device has minimal variation due to operating voltage (see Figure 2-11, Figure 2-29, Figure 2-47, or Figure 2-65). TABLE 6-2: STEP RESISTANCES Resistance (Ω) Part Number Case Minimum MCP40D17/18/19Typical 502 Maximum Minimum MCP40D17/18/19Typical 103 Maximum Total (RAB) Step (RS) 4000 31.496 5000 39.370 6000 47.244 8000 62.992 10000 78.740 12000 94.488 40000 314.961 Minimum MCP40D17/18/19Typical 503 Maximum 50000 393.701 60000 472.441 Minimum 80000 629.921 MCP40D17/18/19Typical 104 Maximum DS22152B-page 42 100000 787.402 120000 944.882 © 2009 Microchip Technology Inc. MCP40D17/18/19 6.2 Resistor Configurations 6.2.1 6.2.2 RHEOSTAT CONFIGURATION When used as a rheostat, two of the three digital potentiometer’s terminals are used as a resistive element in the circuit. With terminal W (wiper) and either terminal A or terminal B, a variable resistor is created. The resistance will depend on the tap setting of the wiper (and the wiper’s resistance). The resistance is controlled by changing the wiper setting The unused terminal (B or A) should be left floating. Figure 6-2 shows the two possible resistors that can be used. Reversing the polarity of the A and B terminals will not affect operation. POTENTIOMETER CONFIGURATION When used as a potentiometer, all three terminals of the device are tied to different nodes in the circuit. This allows the potentiometer to output a voltage proportional to the input voltage. This configuration is sometimes called voltage divider mode. The potentiometer is used to provide a variable voltage by adjusting the wiper position between the two endpoints as shown in Figure 6-3. Reversing the polarity of the A and B terminals will not affect operation. V1 A V3 W A B RAW or W RBW B Resistor FIGURE 6-2: Rheostat Configuration. This allows the control of the total resistance between the two nodes. The total resistance depends on the “starting” terminal to the Wiper terminal. So at the code 00h, the RBW resistance is minimal (RW), but the RAW resistance in maximized (RAB + RW). Conversely, at the code 3Fh, the RAW resistance is minimal (RW), but the RBW resistance in maximized (RAB + RW). The resistance Step size (RS) equates to one LSb of the resistor. Note: To avoid damage to the internal wiper circuitry in this configuration, care should be taken to insure the current flow never exceeds 2.5 mA. V2 FIGURE 6-3: Configuration. Potentiometer The temperature coefficient of the RAB resistors is minimal by design. In this configuration, the resistors all change uniformly, so minimal variation should be seen. The Wiper resistor temperature coefficient is different to the RAB temperature coefficient. The voltage at node V3 (Figure 6-3) is not dependent on this Wiper resistance, just the ratio of the RAB resistors, so this temperature coefficient in most cases can be ignored. Note: To avoid damage to the internal wiper circuitry in this configuration, care should be taken to insure the current flow never exceeds 2.5 mA. The pinout for the rheostat devices is such that as the wiper register is incremented, the resistance of the resistor will increase (as measured from Terminal B to the W Terminal). © 2009 Microchip Technology Inc. DS22152B-page 43 MCP40D17/18/19 6.3 Wiper Resistance In a potentiometer configuration, the wiper resistance variation does not effect the output voltage seen on the W pin. Wiper resistance is the series resistance of the analog switch that connects the selected resistor ladder node to the Wiper Terminal common signal (see Figure 6-1). The slope of the resistance has a linear area (at the higher voltages) and a non-linear area (at the lower voltages). In where resistance increases faster than the voltage drop (at low voltages). A value in the volatile wiper register selects which analog switch to close, connecting the W terminal to the selected node of the resistor ladder. The resistance is dependent on the voltages on the analog switch source, gate, and drain nodes, as well as the device’s wiper code, temperature, and the current through the switch. As the device voltage decreases, the wiper resistance increases (see Figure 6-4 and Table 6-4). RW The wiper can connect directly to Terminal B or to Terminal A. A zero scale connections, connects the Terminal W (wiper) to Terminal B (wiper setting of 000h). A full scale connections, connects the Terminal W (wiper) to Terminal A (wiper setting of 7Fh). In these configurations the only resistance between the Terminal W and the other Terminal (A or B) is thaΩt of the analog switches. VDD Note: The wiper resistance is typically measured when the wiper is positioned at either zero scale (00h) or full scale (3Fh). The slope of the resistance has a linear area (at the higher voltages) and a nonlinear area (at the lower voltages). FIGURE 6-4: Relationship of Wiper Resistance (RW) to Voltage. Since there is minimal variation of the total device resistance over voltage, at a constant temperature (see Figure 2-11, Figure 2-29, Figure 2-47, or Figure 2-65), the change in wiper resistance over voltage can have a significant impact on the INL and DNL error. The wiper resistance in potentiometer-generated voltage divider applications is not a significant source of error. The wiper resistance in rheostat applications can create significant nonlinearity as the wiper is moved toward zero scale (00h). The lower the nominal resistance, the greater the possible error. In a rheostat configuration, this change in voltage needs to be taken into account. Particularly for the lower resistance devices. For the 5.0 kΩ device the maximum wiper resistance at 5.5V is approximately 3.2% of the total resistance, while at 2.7V it is approximately 6.5% of the total resistance. TABLE 6-4: TYPICAL STEP RESISTANCES AND RELATIONSHIP TO WIPER RESISTANCE RW / RS (%) ( 1) Resistance (?) Typical Total (RAB) Step (RS) Wiper (RW) Typical Max @ Max @ 5.5V 2.7V RW = Typical RW / RAB (%) ( 2) RW = Max RW = Max @ 5.5V @ 2.7V RW = Typical RW = Max RW = Max @ 5.5V @ 2.7V 5000 39.37 100 170 325 254.00% 431.80% 825.5% 2.00% 3.40% 6.50% 10000 78.74 100 170 325 127.00% 215.90% 412.75% 1.00% 1.70% 3.25% 50000 393.70 100 170 325 25.40% 43.18% 82.55% 0.20% 0.34% 0.65% 100000 787.40 100 170 325 12.70% 21.59% 41.28% 0.10% 0.17% 0.325% Note 1: 2: RS is the typical value. The variation of this resistance is minimal over voltage. RAB is the typical value. The variation of this resistance is minimal over voltage. DS22152B-page 44 © 2009 Microchip Technology Inc. MCP40D17/18/19 6.4 Operational Characteristics Understanding the operational characteristics of the device’s resistor components is important to the system design. 6.4.1 6.4.1.1 6.4.1.2 Differential Non-linearity (DNL) DNL error is the measure of variations in code widths from the ideal code width. A DNL error of zero would imply that every code is exactly 1 LSb wide. ACCURACY 111 Integral Non-linearity (INL) INL error for these devices is the maximum deviation between an actual code transition point and its corresponding ideal transition point after offset and gain errors have been removed. These endpoints are from 0x00 to 0x7F. Refer to Figure 6-5. Positive INL means higher resistance than ideal. Negative INL means lower resistance than ideal. 110 Actual transfer function 101 Digital 100 Input Code 011 Ideal transfer function 010 Wide code, > 1 LSb 001 INL < 0 000 111 110 Narrow code < 1 LSb Actual transfer function Digital Pot Output 101 Digital Input Code FIGURE 6-6: 100 6.4.1.3 011 Ideal transfer function 010 001 000 INL < 0 Digital Pot Output FIGURE 6-5: INL Accuracy. © 2009 Microchip Technology Inc. DNL Accuracy. Ratiometric temperature coefficient The ratiometric temperature coefficient quantifies the error in the ratio RAW/RWB due to temperature drift. This is typically the critical error when using a potentiometer device (MCP40D18) in a voltage divider configuration. 6.4.1.4 Absolute temperature coefficient The absolute temperature coefficient quantifies the error in the end-to-end resistance (Nominal resistance RAB) due to temperature drift. This is typically the critical error when using a rheostat device (MCP40D17 and MCP40D19) in an adjustable resistor configuration. DS22152B-page 45 MCP40D17/18/19 6.4.2 MONOTONIC OPERATION Monotonic operation means that the device’s resistance increases with every step change (from terminal A to terminal B or terminal B to terminal A). The wiper resistances difference at each tap location. When changing from one tap position to the next (either increasing or decreasing), the ΔRW is less than the ΔRS. When this change occurs, the device voltage and temperature are “the same” for the two tap positions. RS63 0x3F RS62 Digital Input Code 0x3E 0x3D RS3 0x03 RS1 0x02 RS0 0x01 0x00 RW (@ tap) n=? RBW = RSn + RW(@ Tap n) n=0 Resistance (RBW) FIGURE 6-7: DS22152B-page 46 RBW. © 2009 Microchip Technology Inc. MCP40D17/18/19 7.0 DESIGN CONSIDERATIONS In the design of a system with the MCP40D17/18/19 devices, the following considerations should be taken into account. These are: • The Power Supply • The Layout In the design of a system with the MCP40D17/18/19 devices, the following considerations should be taken into account: • Power Supply Considerations • Layout Considerations 7.1 Power Supply Considerations The typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 7-1 illustrates an appropriate bypass strategy. In this example, the recommended bypass capacitor value is 0.1 µF. This capacitor should be placed as close to the device power pin (VDD) as possible (within 4 mm). 7.2 Layout Considerations Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP40D17/18/19’s performance. Careful board layout will minimize these effects and increase the Signal-to-Noise Ratio (SNR). Bench testing has shown that a multi-layer board utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals. If low noise is desired, breadboards and wire-wrapped boards are not recommended. 7.2.1 RESISTOR TEMPCO Characterization curves of the resistor temperature coefficient (Tempco) are shown in Figure 2-11, Figure 2-29, Figure 2-47, and Figure 2-65. These curves show that the resistor network is designed to correct for the change in resistance as temperature increases. This technique reduces the end to end change is RAB resistance. The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, VDD and VSS should reside on the analog plane. VDD 0.1 µF VDD W B VSS FIGURE 7-1: Connections. SCL SDA PICmicro® Microcontroller A MCP40D17/18/19 0.1 µF VSS Typical Microcontroller © 2009 Microchip Technology Inc. DS22152B-page 47 MCP40D17/18/19 NOTES: DS22152B-page 48 © 2009 Microchip Technology Inc. MCP40D17/18/19 8.0 APPLICATIONS EXAMPLES VDD Digital potentiometers have a multitude of practical uses in modern electronic circuits. The most popular uses include precision calibration of set point thresholds, sensor trimming, LCD bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. The MCP40D17/18/19 devices can be used to replace the common mechanical trim pot in applications where the operating and terminal voltages are within CMOS process limitations (VDD = 2.7V to 5.5V). 8.1 Set Point Threshold Trimming Applications that need accurate detection of an input threshold event often need several sources of error eliminated. Use of comparators and operational amplifiers (op amps) with low offset and gain error can help achieve the desired accuracy, but in many applications, the input source variation is beyond the designer’s control. If the entire system can be calibrated after assembly in a controlled environment (like factory test), these sources of error are minimized if not entirely eliminated. Figure 8-1 illustrates a common digital potentiometer configuration. This configuration is often referred to as a “windowed voltage divider”. Note that R1 is not necessary to create the voltage divider, but its presence is useful when the desired threshold has limited range. It is “windowed” because R1 can narrow the adjustable range of VTRIP to a value much less than VDD – VSS. If the output range is reduced, the magnitude of each output step is reduced. This effectively increases the trimming resolution for a fixed digital potentiometer resolution. This technique may allow a lower-cost digital potentiometer to be utilized (64 steps instead of 256 steps). The MCP40D18’s low DNL performance is critical to meeting calibration accuracy in production without having to use a higher precision digital potentiometer. EQUATION 8-1: CALCULATING THE WIPER SETTING FROM THE DESIRED VTRIP R1 MCP40D18 A SDA SCL W VOUT B FIGURE 8-1: Using the Digital Potentiometer to Set a Precise Output Voltage. 8.1.1 TRIMMING A THRESHOLD FOR AN OPTICAL SENSOR If the application has to calibrate the threshold of a diode, transistor or resistor, a variation range of 0.1V is common. Often, the desired resolution of 2 mV or better is adequate to accurately detect the presence of a precise signal. A “windowed” voltage divider, utilizing the MCP40D18, would be a potential solution. Figure 8-2 illustrates this example application. VDD VDD Rsense VCC+ R1 Comparator MCP40D18 A VTRIP SDA W MCP6021 SCL B V CC0.1 µF FIGURE 8-2: Calibration. Set Point or Threshold R WB V TRIP = V DD ⎛⎝ -------------------⎞⎠ R1 + R2 RAB = RNominal RWB = RAB • D= VTRIP VDD D 127 • (R1 + RAB ) • 127 D = Digital Potentiometer Wiper Setting (0-127) © 2009 Microchip Technology Inc. DS22152B-page 49 MCP40D17/18/19 8.2 Operational Amplifier Applications MCP40D18 B Figure 8-3 and Figure 8-4 illustrate typical amplifier circuits that could replace fixed resistors with the MCP40D17/18/19 to achieve digitally-adjustable analog solutions. VIN + VOUT ‚ VDD ‚ Op Amp VIN A Op Amp VDD W R1 MCP6291 R1 W B MCP40D18 A W MCP40D17 FIGURE 8-3: Trimming Offset and Gain in a Non-Inverting Amplifier. DS22152B-page 50 VOUT + MCP6021 1 fc = ----------------------------- 2 π ⋅ R Eq ⋅ C R3 B MCP40D18 R4 A Thevenin R = ( R 1 + R AB – R WB ) || ( R 2 + R WB ) + R w Equivalent Eq FIGURE 8-4: Programmable Filter. © 2009 Microchip Technology Inc. MCP40D17/18/19 8.3 Temperature Sensor Applications Thermistors are resistors with very predictable variation with temperature. Thermistors are a popular sensor choice when a low-cost temperature-sensing solution is desired. Unfortunately, thermistors have non-linear characteristics that are undesirable, typically requiring trimming in an application to achieve greater accuracy. There are several common solutions to trim and linearize thermistors. Figure 8-5 and Figure 8-6 are simple methods for linearizing a 3-terminal NTC thermistor. Both are simple voltage dividers using a Positive Temperature Coefficient (PTC) resistor (R1) with a transfer function capable of compensating for the linearity error in the Negative Temperature Coefficient (NTC) thermistor. The circuit, illustrated by Figure 8-5, utilizes a digital rheostat for trimming the offset error caused by the thermistor’s part-to-part variation. This solution puts the digital potentiometer’s RW into the voltage divider calculation. The MCP40D17/18/19’s RAB temperature coefficient is a low 50 ppm (-20°C to +70°C). RW’s error is substantially greater than RAB’s error because RW varies with VDD, wiper setting and temperature. For the 50 kΩ devices, the error introduced by RW is, in most cases, insignificant as long as the wiper setting is > 6. For the 2 kΩ devices, the error introduced by RW is significant because it is a higher percentage of RWB. For these reasons, the circuit illustrated in Figure 8-5 is not the most optimum method for “exciting” and linearizing a thermistor. The circuit illustrated by Figure 8-6 utilizes a digital potentiometer for trimming the offset error. This solution removes RW from the trimming equation along with the error associated with RW. R2 is not required, but can be utilized to reduce the trimming “window” and reduce variation due to the digital pot’s RAB part-to-part variability. VDD R1 NTC Thermistor VOUT MCP40D18 FIGURE 8-6: Thermistor Calibration using a Digital Potentiometer in a Potentiometer Configuration. VDD R1 NTC Thermistor VOUT R2 MCP40D17 FIGURE 8-5: Thermistor Calibration using a Digital Potentiometer in a Rheostat Configuration. © 2009 Microchip Technology Inc. DS22152B-page 51 MCP40D17/18/19 8.4 Wheatstone Bridge Trimming Another common configuration to “excite” a sensor (such as a strain gauge, pressure sensor or thermistor) is the wheatstone bridge configuration. The wheatstone bridge provides a differential output instead of a single-ended output. Figure 8-7 illustrates a wheatstone bridge utilizing one to three digital potentiometers. The digital potentiometers in this example are used to trim the offset and gain of the wheatstone bridge. VDD 5 kΩ MCP40D17 VOUT MCP40D17 50 kΩ FIGURE 8-7: Trimming. DS22152B-page 52 MCP40D17 50 kΩ Wheatstone Bridge © 2009 Microchip Technology Inc. MCP40D17/18/19 9.0 DEVELOPMENT SUPPORT 9.1 Development Tools 9.2 Several additional technical documents are available to assist you in your design and development. These technical documents include Application Notes, Technical Briefs, and Design Guides. Table 9-1 shows some of these documents. The MCP40D17/18/19 devices can be evaluated with the MCP4XXXDM-PGA board, but it will require the removal of the MCP4017 device and the installation of the MCP40D17 device. Please check the Microchip web site for the release of this board. The board part number is tentatively MCP4XXXDM-PGA, and is expected to be available in the fall of 2009. Note: Technical Documentation The MCP40D17 device is identical to the MCP4017 device with the exception of the I2C interface protocol format. TABLE 9-1: TECHNICAL DOCUMENTATION Application Note Number Title Literature # AN1080 Understanding Digital Potentiometers Resistor Variations DS01080 AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737 AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692 AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691 AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219 — Digital Potentiometer Design Guide DS22017 — Signal Chain Design Guide DS21825 © 2009 Microchip Technology Inc. DS22152B-page 53 MCP40D17/18/19 NOTES: DS22152B-page 54 © 2009 Microchip Technology Inc. MCP40D17/18/19 10.0 PACKAGING INFORMATION 10.1 Package Marking Information Example: 5-Lead SC70 XXNN 1 Part Number Code MCP40D19T-502E/LT BTNN MCP40D19T-103E/LT BUNN MCP40D19T-503E/LT BVNN MCP40D19T-104E/LT BWNN ATNN 1 6-Lead SC70 XXNN 1 Example: Part Number Code MCP40D17T-502E/LT AJNN MCP40D18T-502E/LT APNN MCP40D17T-103E/LT AKNN MCP40D18T-502AE/LT ATNN MCP40D17T-503E/LT ALNN MCP40D18T-103E/LT AQNN MCP40D17T-104E/LT AMNN MCP40D18T-103AE/LT AUNN MCP40D18T-503E/LT ARNN Legend: XX...X Y YY WW NNN e3 * Note: Part Number Code MCP40D18T-503AE/LT AVNN MCP40D18T-104E/LT ASNN MCP40D18T-104AE/LT AWNN AJNN 1 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS22152B-page 55 MCP40D17/18/19 . # #$ # /! - 0 # 1/ %# #!# ## +22--- 2 / D b 3 1 2 E1 E 4 5 e A e A2 c A1 L 3# 4# 5$8 %1 44" " 5 5 56 7 ( 1# 6, : # ; < ; < < !!1/ / #! %% 9()* 6, =!# " ; !!1/=!# " ( ( ( 6, 4# ; ( . 4 9 #4# 4! / 4!=!# ; < 9 8 ( < !"! #$! !% # $ !% # $ !# "'( )*+ ) #&#,$ --# $## #&! ! DS22152B-page 56 - *9) © 2009 Microchip Technology Inc. MCP40D17/18/19 . # #$ # /! - 0 # 1/ %# #!# ## +22--- 2 / © 2009 Microchip Technology Inc. DS22152B-page 57 MCP40D17/18/19 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22152B-page 58 © 2009 Microchip Technology Inc. MCP40D17/18/19 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009 Microchip Technology Inc. DS22152B-page 59 MCP40D17/18/19 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22152B-page 60 © 2009 Microchip Technology Inc. MCP40D17/18/19 APPENDIX A: REVISION HISTORY Revision B (August 2009) the following is the List of Modifications: 1. 2. Document updated to include the new standard I2C slave address (“0111110“) for the MCP40D18 device. Section 10.0 “Packaging Information”: Corrected the Marking codes for 5-lead SC70 Codes shown were for the 6-lead SC70. Updated Package Outline Drawings. Revision A (May 2009) • Original Release of this Document. © 2009 Microchip Technology Inc. DS22152B-page 61 MCP40D17/18/19 NOTES: DS22152B-page 62 © 2009 Microchip Technology Inc. MCP40D17/18/19 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device XXX X I2C MCP40D17: Single Rheostat with interface MCP40D17T:Single Rheostat with I2C interface (Tape and Reel) MCP40D18: Single Potentiometer to GND with I2C Interface MCP40D18T:Single Potentiometer to GND with I2C Interface (Tape and Reel) MCP40D19: Single Rheostat to GND with I2C Interface MCP40D19T:Single Rheostat to GND with I2C Interface (Tape and Reel) Resistance Version: 502 103 503 104 = = = = 5 kΩ 10 kΩ 50 kΩ 100 kΩ I2C Device Address Version: blank = ‘0101110’ A = ‘0111110’ (1) Temperature Range: E Note 1: /XX I2C Device Temperature Package Address Range Resistance Version Device: Package: X Examples: a) MCP40D17T-502E/LT: b) MCP40D17T-103E/LT: c) MCP40D17T-503E/LT: d) MCP40D17T-104E/LT: a) MCP40D18T-502E/LT: b) MCP40D18T-103E/LT: c) MCP40D18T-503E/LT: d) MCP40D18T-104E/LT: a) MCP40D18T-502AE/LT: 5 kΩ, 6-LD SC70 MCP40D18T-103AE/LT: 10 kΩ, 6-LD SC70 MCP40D18T-503AE/LT: 50 kΩ, 6-LD SC70 MCP40D18T-104AE/LT: 100 kΩ, 6-LD SC70 b) c) d) = -40°C to +125°C LT = Plastic Small Outline Transistor (SC70), 5-lead, 6-lead This address is a standard option on the MCP40D18 device only. It is a custom device on the MCP40D17 and MCP40D19 devices. © 2009 Microchip Technology Inc. a) MCP40D19T-502E/LT: b) MCP40D19T-103E/LT: c) MCP40D19T-503E/LT: d) MCP40D19T-104E/LT: 5 kΩ, 6-LD SC70 10 kΩ, 6-LD SC70 50 kΩ, 6-LD SC70 100 kΩ, 6-LD SC70 5 kΩ, 6-LD SC70 10 kΩ, 6-LD SC70 50 kΩ, 6-LD SC70 100 kΩ, 6-LD SC70 5 kΩ, 5-LD SC70 10 kΩ, 5-LD SC70 50 kΩ, 5-LD SC70 100 kΩ, 5-LD SC70 DS22152B-page 63 MCP40D17/18/19 NOTES: DS22152B-page 64 © 2009 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2009 Microchip Technology Inc. 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