Hanbit HMD1M32M2GL-6 4mbyte(1mx32) fast page mode, 1k refresh, 72pin simm, 5v design Datasheet

HANBit
HMD1M32M2GL
4Mbyte(1Mx32) Fast Page Mode, 1K Refresh, 72Pin SIMM, 5V
Design
Part No. HMD1M32M2GL
DESCRIPTION
The HMD1M32M2GL is an 1M x 32 bits Dynamic RAM MODULE which is assembled 2 pieces of 1M x 16bit DRAMs in 42 pin
SOJ package on single sides the printed circuit board with decoupling capacitors. The HMD1M32M2GL is optimized for
application to the systems, which are required high density and large capacity such as main memory of the computers and an
image memory systems, and to the others, which are, requested compact size.
The HMD1M32M2GL provides common data and outputs.
Features
PIN ASSIGNMENT
w 72 pins Single In-Line Package
w Fast Page Mode Capability
w Single +5V± 0.5V power supply
w Fast Access Time & Cycle Time
tRAC
tCAC
tRC
PIN
SYMBOL
PIN
SYMBO
L
PIN
SYMBOL
1
Vss
25
DQ22
49
DQ8
tPC
2
DQ0
26
DQ7
50
DQ24
DQ16
27
DQ23
51
DQ9
HMD1M32M2G-5
50
15
90
35
3
HMD1M32M2G-6
60
15
110
40
4
DQ1
28
A8
52
DQ25
w Low Power
5
DQ17
29
NC(A10)
53
DQ10
w /RAS Only Refresh, /CAS before /RAS Refresh,
6
DQ2
30
Vcc
54
DQ26
7
DQ18
31
/WE2
55
DQ11
8
DQ3
32
NC
56
DQ27
Hidden Refresh Capability
w All inputs and outputs TTL Compatible
9
DQ19
33
Vcc
57
DQ12
10
Vcc
34
/RAS
58
DQ28
11
/WEO
35
Vcc
59
/WE3
12
A0
36
NC
60
DQ29
13
A1
37
NC
61
DQ13
14
A2
38
/OE
62
DQ30
FUNCTION
Read/Write
Enable
15
A3
39
Vss
63
DQ14
16
A4
40
/CAS
64
DQ31
17
A5
41
Vcc
65
DQ15
Power (+5V)
18
A6
42
NC
66
Vcc
w 1,024 Refresh Cycles/16ms
PIN DESCRIPTION
PIN
FUNCTION
A0 – A9
Address Inputs
DQ0 –
Data
Input/Output
DQ31
/RAS
/CAS
/OE
Row Address
Strobe
Column
Address Strobe
Data Output
Enable
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PIN
/WE
Vcc
19
A7
43
NC
67
NC
DQ4
44
NC
68
NC
DQ20
45
A9
69
Vss
22
DQ5
46
NC(A11)
70
NC
23
DQ21
47
/WE1
71
Vss
24
DQ6
48
Vcc
72
Vss
Vss
Ground
20
NC
No
Connection
21
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HMD1M32M2GL
FUNCTIONAL BLOCK DIAGRAM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U1
/RAS
/RAS
/CAS0
/LCAS
/CAS1
/UCAS
/OE
/OE
/WE
A0-A9
U2
/RAS
/RAS
/LCAS
/CAS2
DQ0-DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ8-DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16-DQ23
/UCAS
DQ8
DQ9D
Q10
DQ11
DQ12
DQ13
DQ14
DQ15
/CAS3
/OE
/WE
DQ24-DQ31
A0-A9
/WE
A0-A9
Vcc
0.1uF Capacitor
Vss
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HMD1M32M2GL
ABSOLUTE MAXIMUM RATINGS*
SYMBOL
PARAMETER
RATING
UNIT
0 ~ 70
C
Storage Temperature (Plastic)
-55 ~ 150
C
Voltage on any Pin Relative to Vss
-1.0 ~ 7.0
V
VCC
Power Supply Voltage
-1.0 ~ 7.0
V
IOUT
Short Circuit Output Current
100
mA
2
W
Ambient Temperature under Bias
TA
TSTG
VIN/VOUT
Power Dissipation
PD
*NOTE: 1. Stress greater than above absolute Maximum Ratings?
May cause permanent damage to the device.
RECOMMENDED DC OPERATING CONDITIONS (TA = 0 ~ 70C)
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
Supply Voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input High Voltage
VIH
2.4
-
Vcc+1
V
Input Low Voltage
VIL
-1.0
-
0.8
V
*NOTE: All voltages referenced to Vcc
DC AND OPERATING CHARACTERISTICS
SYMBOL
VOH
VOL
PARAMETER
MIN
Output High Level Voltage (IOUT = -5mA)
2.4
Output Low Level Voltage (IOUT = 4.2mA)
0
MAX
V
0.4
Operating Current
-5
280
(/RAS,/CAS,Address Cycling : tRC = tRC min)
-6
260
ICC1
ICC2
UNIT
V
mA
Standby Current (/RAS,/CAS = VIH)
-
4
mA
/RAS Only Refresh Current
-5
280
(/RAS Cycling, /CAS = VIH,: tRC = tRC min)
-6
260
Fast Page Mode Current
-5
180
mA
(/RAS =VIL, /CAS, Address Cycling : tPC = tPC min)
-6
160
mA
2
mA
ICC3
mA
ICC4
ICC5
Standby Current (/RAS,/CAS >= Vcc – 0.2V)
ICC6
/CAS before /RAS Refresh Current (tRC = tRC min)
-5
280
-6
260
mA
-
400
uA
-10
10
uA
-10
10
uA
Self Refresh Current
ICCS
(/RAS=/UCAS=/LCAS=VIL, /WE=/OE=A0~A9= Vcc – 0.2V or 0.2V,
DQ0~DQ31= Vcc – 0.2V, 0.2V or Open)
Input Leakage Current
II(L)
IO(L)
(Any Input (0V<=VIN<= VIN + 0.5V, All Other Pins Not Under Test = 0V)
Output Leakage Current(DOUT is Disabled, 0V<=V OUT<= Vcc)
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Note: 1. Icc depends on output load condition when the device is selected.
Icc (max) is specified at the output open condition.
2. Address can be changed once or less while /RAS = V IL.
3. Address can be changed once or less while /CAS = V IH
CAPACITANCE
o
( TA=25 C, Vcc = 5V+/- 10%, f = 1Mhz )
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
NOTE
Input Capacitance (A0-A9)
CI1
-
5
pF
1
Input Capacitance (/WE,/RAS, /CAS0-
C I2
-
7
pF
1,2
CDQ1
-
7
pF
1,2
/CAS3,/OE)
Input/Output Capacitance (DQ0-31)
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. /CAS = VIH to disable DOUT.
AC CHARACTERISTICS ( 0
o
C ≤ TA ≤ 70oC , Vcc = 5V±10%, VIH /VIL = 2.4/0.8V, VOH /VOL =2.4/0.4V, See notes 1,2)
-5
SYMBOL
-6
PARAMETER
UNIT
MIN
MAX
MIN
NOTE
MAX
Random Read or Write Cycle Time
90
110
ns
tRWC
Read-modify-writer cycle time
133
155
ns
tRAC
Access Time from /RAS
50
60
ns
3,4,10
tCAC
Access Time from /CAS
15
15
ns
3,4,5
Access Time from Column Address
25
30
ns
3,10
tRC
Taa
Output Buffer Turn-off Time
0
13
0
15
ns
6
tT
Transition Time (Rise and Fall)
3
50
3
50
ns
2
TRP
/RAS Precharge Time
30
tRAS
/RAS Pulse Width
50
tRSH
/RAS Hold Time
13
15
ns
tCSH
/CAS Hold Time
50
60
ns
tCAS
/CAS Pulse Width
13
10K
15
10K
ns
tRCD
/RAS to /CAS Delay Time
20
37
20
45
ns
4
tRAD
/RAS to Column Address Delay Time
15
25
15
30
ns
10
tCRP
/CAS to /RAS Precharge Time
5
5
ns
tASR
Row Address Setup Time
0
0
ns
tRAH
Row Address Hold Time
10
10
ns
tASC
Column Address Setup Time
0
0
ns
11
tCAH
Column Address Hold Time
10
10
ns
11
tRAL
Column Address to /RAS Lead Time
25
30
ns
tRCS
Read Command Setup Time
0
0
ns
tRCH
Read Command Hold Time to /CAS
0
0
ns
tOFF
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40
10K
60
ns
10K
ns
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HMD1M32M2GL
tRRH
Read Command Hold Time to /RAS
0
0
ns
tWCH
Write Command Hold Time
10
10
ns
Write Command Pulse Width
10
10
ns
tRWL
Write Command to /RAS Lead Time
13
15
ns
tCWL
Write Command to /CAS Lead Time
13
15
ns
tDS
Data-in Setup Time
0
0
ns
9
tDH
Data-in Hold Time
10
10
ns
9
tREF
Refresh Period (1024 Cycle)
twcs
Write Command Setup Time
0
0
ms
7
tCWD
/CAS to /WE delay time
36
40
ms
7,13
tRWD
/RAS to /WE delay time
73
85
ns
7
tAWD
Column Address to /WE delay time
48
55
ns
7
tCPWD
/CAS precharge to /WE delay time
53
60
ns
7
5
5
ns
10
10
ns
5
5
ns
tWP
16
16
8
ms
/CAS Setup Time
15
tCSR
(/CAS-before-/RAS Refresh Cycle)
/CAS Hold Time
tCHR
16
(/CAS-before-/RAS Refresh Cycle)
tRPC
tCPA
/RAS Precharge to /CAS Hold Time
Access Time from /CAS Precharge
30
35
ns
tPC
Fast Page Mode Cycle Time
35
40
ns
tCP
Fast Page Mode /RAS Precharge Time
10
10
ns
tRASP
Fast Page Mode /CAS Pulse Time
50
/RAS
Hold
Time
time
from
200K
60
200K
3
12
ns
/CAS
30
tRHCP
35
ns
Precharge
tOEA
/OE Access Time
tOED
/OE to data delay
13
tOEZ
Output buffer turn off delay time from /OE
0
tOEH
/OE command hold time
13
15
ns
/RAS Pulse Width(CBR self refresh)
100
100
us
/RAS Precharge Time(CBR self refresh)
90
110
ns
tRASS
tPRS
13
15
15
13
0
ns
3
ns
15
ns
/CAS Hold Time(CBR self refresh)
-50
-50
ns
tCHS
Note: 1. An initial pause of 200us is required after power-up followed by any 8 /RAS-only refresh or /CAS-before-/RAS
refresh cycles before proper device operation is achieved.
2. Input voltage levels are VIH / VIL. VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Also, transition times are measured between . VIH and VIL are assumed to be 5ns for all inputs.
3. Measured with a load circuit equivalent to 2TTL loads and 100pF.
4. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only,
if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC .
5. Assumes that tRCD <= tRCD (max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH /
VOL .
7. TWCS, TRWD, TCWD, TCPWD are non restrictive operating parameter. They are included in the data sheet as electrical
characteristics
only. If twcs >= twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance)
throughout
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HMD1M32M2GL
the entire cycle. If tCWD >= tCWD (min), tRWD >= tRWD (min), TCPWD>= TCPWD(min), then the cycle is a read-modify-write
cycle and the data output will contain the data read from the selected address. If neither of the above conditions is
satisfied, the condition of the data out is indeterminate.
8. Either tRCH or tRRH must be satisfied for a read cycles.
9. These parameters are referenced to /CAS falling edge in early write cycles and to /WE falling edge in /OE controlled
write cycle and read-modify-write cycles.
10. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only,
if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA.
11. tASC, tCAH are are referenced to the earlier /CAS falling edge.
12. tCP is specified from the later /CAS rising edge in the previous cycle to the earlier /CAS falling edge in the next cycle.
13. tCWD is referenced to the later /CAS falling edge at word read-modify-write cycle.
14. tCWL is specified from /WE falling edge to the earlier /CAS rising edge .
15. tCSR is referenced to the earlier /CAS falling edge before /RAS transition low.
16. tCHR is referenced to the later /CAS rising edge after /RAS transition low.
PACKAGING INFORMATION
2.54 mm
0.25 mm MAX
MIN
1.27±0.08 mm
1.27 mm
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HMD1M32M2GL
ORDERING INFORMATION
Part Number
Density
Org.
Package
HMD1M32M2GL-5
4MByte
X32
72 Pin-SIMM
HMD1M32M2GL-6
4MByte
x 32
72 Pin-SIMM
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Component
Vcc
MODE
SPEED
2EA
5V
FP
50ns
2EA
5V
FP
60ns
Number
HANBit Electronics Co., Ltd.
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