Vishay IRFD9020 Power mosfet Datasheet

IRFD9020
www.vishay.com
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Dynamic dV/dt rating
-60
RDS(on) ()
VGS = -10 V
• Repetitive avalanche rated
0.28
Qg max. (nC)
19
• For automatic insertion
Qgs (nC)
5.4
• End stackable
11
• P-channel
Qgd (nC)
Configuration
• 175 °C operating temperature
Single
• Fast switching
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
S
HVMDIP
DESCRIPTION
G
S
Third generation power MOSFETs from Vishay provides the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and cost
effectiveness.
The 4 pin DIP package is a low cost machine-insertable
case style which can be stacked in multiple combinations on
standard 0.1" pin centers. The dual drain serves as a thermal
link to the mounting surface for power dissipation levels up
to 1 W.
G
D
D
P-Channel MOSFET
ORDERING INFORMATION
Package
HVMDIP
Lead (Pb)-Free
IRFD9020PbF
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
-60
Gate-Source Voltage
VGS
± 20
VGS at -10 V
Continuous Drain Current
Pulsed Drain Current
TA = 25 °C
TA = 100 °C
a
ID
IDM
Linear Derating Factor
Single Pulse Avalanche Energy
b
EAS
UNIT
V
-1.6
-1.1
A
-13
0.0083
W/°C
140
mJ
Current a
IAR
-1.6
A
Repetitive Avalanche Energy a
EAR
0.13
mJ
Repetitive Avalanche
Maximum Power Dissipation
TA = 25 °C
Peak Diode Recovery dV/dt c
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak temperature) d
For 10 s
PD
1.3
W
dV/dt
-4.5
V/ns
TJ, Tstg
-55 to +175
300
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = -25 V, starting TJ = 25 °C, L = 15 mH, Rg = 25 , IAS = -3.2 A (see fig. 12).
c. ISD  -11 A, dI/dt  -140 A/ms, VDD  VDS, TJ  175 °C.
d. 1.6 mm from case.
S16-1506-Rev. D, 01-Aug-16
Document Number: 90170
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFD9020
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient
SYMBOL
TYP.
MAX.
UNIT
RthJA
-
120
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
VDS
VGS = 0 V, ID = - 250 μA
-60
-
-
V
VDS/TJ
Reference to 25 °C, ID = -1 mA
-
- 0.056
-
V/°C
VGS(th)
VDS = VGS, ID = -1 μA
-2.0
-
-4.0
V
nA
VGS = 20
-
-
100
VDS = -60 V, VGS = 0 V
-
-
- 100
VDS = -48 V, VGS = 0 V, TJ = 150 °C
-
-
- 500
-
-
0.28

1.3
-
-
S
IGSS
IDSS
RDS(on)
gfs
ID = - 0.96 A b
VGS = -10 V
VDS = -25 V, ID = - 0.96
Ab
μA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
VGS = 0 V,
VDS = -25 V,
f = 1.0 MHz, see fig. 5
-
570
-
-
360
-
-
65
-
-
-
19
-
-
5.4
pF
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
-
-
11
Turn-On Delay Time
td(on)
-
13
-
-
68
-
-
15
-
-
29
-
-
4.0
-
-
6.0
-
-
-
- 1.6
-
-
- 13
-
-
- 6.3
V
-
100
200
ns
-
0.32
0.64
μC
Rise Time
Turn-Off Delay Time
tr
td(off)
Fall Time
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
VGS = -10 V
ID = - 11 A, VDS = -48 V,
see fig. 6 and 13 b
VDD = - 30 V, ID = -11 A,
Rg = 18 , RD = 2.5, see fig. 10b
Between lead,
6 mm (0.25") from
package and center of
die contact
D
nC
ns
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current a
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the 
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = -1.6 A, VGS = 0 V b
TJ = 25 °C, IF = - 11A, di/dt = 100 A/μs b
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
S16-1506-Rev. D, 01-Aug-16
Document Number: 90170
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFD9020
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
TA = 25 °C
Fig. 1 - Typical Output Characteristics, TA = 25 °C
Fig. 3 - Typical Transfer Characteristics
TA = 175 °C
Fig. 2 - Typical Output Characteristics, TA = 175 °C
S16-1506-Rev. D, 01-Aug-16
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 90170
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFD9020
www.vishay.com
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Vishay Siliconix
Fig. 7 - Typical Source-Drain Diode Forward Voltage
TA = 25 °C
TJ = 150 °C
SINGLE PULSE
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
S16-1506-Rev. D, 01-Aug-16
Fig. 8 - Maximum Safe Operating Area
Document Number: 90170
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFD9020
www.vishay.com
Vishay Siliconix
RD
VDS
VGS
D.U.T.
-ID, Drain Current (A)
Rg
+VDD
- 10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
td(on)
td(off) tf
tr
VGS
10 %
90 %
VDS
TA, Ambient Temperature (°C)
Fig. 10b - Switching Time Waveforms
Thermal Response (ZthJA)
Fig. 9 - Maximum Drain Current vs. Ambient Temperature
t1, Rectangular Pulse Duration (s)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
IAS
L
Vary tp to obtain
required IAS
VDS
D.U.T.
Rg
VDS
+ V DD
VDD
IAS
- 10 V
tp
0.01 Ω
tp
VDS
Fig. 12a - Unclamped Inductive Test Circuit
S16-1506-Rev. D, 01-Aug-16
Fig. 12b - Unclamped Inductive Waveforms
Document Number: 90170
5
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFD9020
www.vishay.com
Vishay Siliconix
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
- 10 V
12 V
0.2 µF
0.3 µF
QGS
-
QGD
D.U.T.
VG
+ VDS
VGS
- 3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S16-1506-Rev. D, 01-Aug-16
Fig. 13b - Gate Charge Test Circuit
Document Number: 90170
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFD9020
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
+
• dV/dt controlled by Rg
• ISD controlled by duty factor “D”
• D.U.T. - device under test
+
-
VDD
Note
• Compliment N-Channel of D.U.T. for driver
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = - 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = - 5 V for logic level and - 3 V drive devices
Fig. 14 - For P-Channel









Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?90170.
S16-1506-Rev. D, 01-Aug-16
Document Number: 90170
7
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
HVM DIP (High voltage)
0.248 [6.29]
0.240 [6.10]
0.043 [1.09]
0.035 [0.89]
0.197 [5.00]
0.189 [4.80]
0.133 [3.37]
0.125 [3.18]
0.180 [4.57]
0.160 [4.06]
0.094 [2.38]
0.086 [2.18]
A
L
0.160 [4.06]
0.140 [3.56]
0° to 15°
2x
0.017 [0.43]
0.013 [0.33]
0.045 [1.14]
2 x 0.035 [0.89]
E min.
0.024 [0.60]
4x
0.020 [0.51]
0.100 [2.54] typ.
E max.
INCHES
MILLIMETERS
DIM.
MIN.
MAX.
MIN.
A
0.310
0.330
7.87
MAX.
8.38
E
0.300
0.425
7.62
10.79
L
0.270
0.290
6.86
7.36
ECN: X10-0386-Rev. B, 06-Sep-10
DWG: 5974
Note
1. Package length does not include mold flash, protrusions or gate burrs. Package width does not include interlead flash or protrusions.
Document Number: 91361
Revision: 06-Sep-10
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1
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
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Revision: 08-Feb-17
1
Document Number: 91000
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