IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI 1M x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES • High-speed access times: 8, 10, 20 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • CE power-down • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single power supply VDD 1.65V to 2.2V (IS61WV102416ALL) speed = 20ns for VDD 1.65V to 2.2V VDD 2.4V to 3.6V (IS61/64WV102416BLL) speed = 10ns for VDD 2.4V to 3.6V speed = 8ns for VDD 3.3V + 5% • Packages available: – 48-ball miniBGA (9mm x 11mm) – 48-pin TSOP (Type I) • Industrial and Automotive Temperature Support • Lead-free available • Data control for upper and lower bytes ® OCTOBER 2006 DESCRIPTION The ISSI IS61WV102416ALL/BLL and IS64WV102416BLL are high-speed, 16M-bit static RAMs organized as 1024K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The device is packaged in the JEDEC standard 48-pin TSOP Type I and 48-pin Mini BGA (9mm x 11mm). FUNCTIONAL BLOCK DIAGRAM A0-A19 DECODER 1024K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CE OE WE CONTROL CIRCUIT UB LB Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 1 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® 48-pin mini BGA (9mmx11mm) 1 2 3 4 5 6 A LB OE A0 A1 A2 NC B I/O8 UB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 VDD GND E VDD I/O12 NC A16 I/O4 F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 A19 A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NC PIN DESCRIPTIONS 2 A0-A19 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection VDD Power GND Ground Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® 48-pin TSOP-I (12mm x 20mm) A4 A3 A2 A1 A0 NC CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE NC A19 A18 A17 A16 A15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A5 A6 A7 A8 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A9 A10 A11 A12 A13 A14 PIN DESCRIPTIONS A0-A19 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection VDD Power GND Ground Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 3 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® TRUTH TABLE I/O PIN I/O0-I/O7 I/O8-I/O15 WE CE OE LB UB Not Selected X H X X X High-Z High-Z ISB1, ISB2 Output Disabled H X L L H X X H X H High-Z High-Z High-Z High-Z ICC Read H H H L L L L L L L H L H L L DOUT High-Z DOUT High-Z DOUT DOUT ICC Write L L L L L L X X X L H L H L L DIN High-Z DIN High-Z DIN DIN ICC Mode VDD Current ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND VDD Relates to GND Storage Temperature Power Dissipation Value –0.5 to VDD + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance CI/O Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® OPERATING RANGE (VDD) (IS61WV102416ALL) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C VDD (20 nS) 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V OPERATING RANGE (VDD) (IS61WV102416BLL)(1) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C VDD (8 nS) 3.3V + 5% 3.3V + 5% VDD (10 nS) 2.4V-3.6V 2.4V-3.6V Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns. OPERATING RANGE (VDD) (IS64WV102416BLL) Range Automotive Ambient Temperature –40°C to +125°C VDD (10 nS) 2.4V-3.6V Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 5 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 3.3V + 5% Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage VIL Input LOW Voltage(1) 2 VDD + 0.3 V –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Min. Max. Unit Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 2.4V-3.6V Symbol Parameter Test Conditions VOH Output HIGH Voltage VDD = Min., IOH = –1.0 mA 1.8 — V VOL Output LOW Voltage VDD = Min., IOL = 1.0 mA — 0.4 V VIH Input HIGH Voltage 2.0 VDD + 0.3 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 1.65V-2.2V Symbol Parameter Test Conditions VDD Min. Max. Unit VOH Output HIGH Voltage IOH = -0.1 mA 1.65-2.2V 1.4 — V VOL Output LOW Voltage IOL = 0.1 mA 1.65-2.2V — 0.2 V VIH Input HIGH Voltage 1.65-2.2V 1.4 VDD + 0.2 V VIL(1) Input LOW Voltage 1.65-2.2V –0.2 0.4 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Notes: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width -2.0ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width -2.0ns). Not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® AC TEST CONDITIONS (HIGH SPEED) Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load Unit (2.4V-3.6V) 0.4V to VDD-0.3V 1.5ns VDD/2 Unit (3.3V + 5%) 0.4V to VDD-0.3V 1.5ns VDD/2 + 0.05 Unit (1.65V-2.2V) 0.4V to VDD-0.2V 1.5ns VDD/2 See Figures 1 and 2 See Figures 1 and 2 See Figures 1 and 2 AC TEST LOADS 319 Ω ZO = 50Ω 3.3V 50Ω 1.5V OUTPUT OUTPUT 30 pF Including jig and scope Figure 1. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 5 pF Including jig and scope 353 Ω Figure 2. 7 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 Symbol Parameter ICC VDD Dynamic Operating Supply Current Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX VIN = 0.4V or VDD –0.3V Min. Max. Com. Ind. Auto. typ.(2) — — — 110 115 — -10 Min. Max. — — — -20 Min. Max. Unit 90 95 140 — — — 50 60 100 mA 60 ICC1 Operating Supply Current VDD = Max., IOUT = 0 mA, f = 0 VIN = 0.4V or VDD –0.3V Com. Ind. Auto. — — — 85 90 — — — — 85 90 110 — — — 45 55 90 mA ISB1 TTL Standby Current (TTL Inputs) VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 Com. Ind. Auto. — — — 30 35 — — — — 30 35 70 — — — 30 35 70 mA ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Auto. typ.(2) — — — 20 25 — — — — 20 25 60 — — — 20 25 60 mA 4 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -8 Symbol tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2 tLZCE(2) tBA tHZB(2) tLZB(2) tPU tPD Parameter -10 Min. Max. Min. Max. Unit Read Cycle Time 8 — 10 — ns Address Access Time — 8 — 10 ns Output Hold Time 2.5 — 2.5 — ns CE Access Time — 8 — 10 ns OE Access Time — 5.5 — 6.5 ns OE to High-Z Output — 3 — 4 ns OE to Low-Z Output 0 — 0 — ns CE to High-Z Output 0 3 0 4 ns CE to Low-Z Output 3 — 3 — ns LB, UB Access Time — 5.5 — 6.5 ns LB, UB to High-Z Output 0 3 0 3 ns LB, UB to Low-Z Output 0 — 0 — ns Power Up Time 0 — 0 — ns Power Down Time — 8 — 10 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 9 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter -20 ns Min. Max. Unit tRC Read Cycle Time 20 — ns tAA Address Access Time — 20 ns tOHA Output Hold Time 2.5 — ns tACE CE Access Time — 20 ns tDOE OE Access Time — 8 ns tHZOE(2) OE to High-Z Output 0 8 ns tLZOE OE to Low-Z Output 0 — ns (2 tHZCE CE to High-Z Output 0 8 ns (2) tLZCE CE to Low-Z Output 3 — ns tBA LB, UB Access Time — 8 ns tHZB LB, UB to High-Z Output 0 8 ns tLZB LB, UB to Low-Z Output 0 — ns (2) Notes: 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) (CE and OE Controlled) t RC ADDRESS t AA t OHA OE t HZOE t DOE CE t LZOE t ACE t HZCE t LZCE DOUT HIGH-Z DATA VALID CE_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 11 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 Symbol Parameter -10 Min. Max. Min. Max. Unit tWC Write Cycle Time 8 — 10 — ns tSCE CE to Write End 6.5 — 8 — ns tAW Address Setup Time to Write End 6.5 — 8 — ns tHA Address Hold from Write End 0 — 0 — ns tSA Address Setup Time 0 — 0 — ns tPWB LB, UB Valid to End of Write 6.5 — 8 — ns tPWE1 WE Pulse Width 6.5 — 8 — ns tPWE2 WE Pulse Width (OE = LOW) 8.0 — 10 — ns tSD Data Setup to Write End 5 — 6 — ns tHD Data Hold from Write End 0 — 0 — ns (2) tHZWE WE LOW to High-Z Output — 3.5 — 5 ns tLZWE(2) WE HIGH to Low-Z Output 2 — 2 — ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter -20 ns Min. Max. Unit tWC Write Cycle Time 20 — ns tSCE CE to Write End 12 — ns tAW Address Setup Time to Write End 12 — ns tHA Address Hold from Write End 0 — ns tSA Address Setup Time 0 — ns tPWB LB, UB Valid to End of Write 12 — ns tPWE1 WE Pulse Width (OE = HIGH) 12 — ns tPWE2 WE Pulse Width (OE = LOW) 17 — ns tSD Data Setup to Write End 9 — ns tHD Data Hold from Write End 0 — ns tHZWE(3) WE LOW to High-Z Output — 9 ns tLZWE(3) WE HIGH to Low-Z Output 3 — ns Notes: 1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 13 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR1.eps 14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA t PBW UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR2.eps WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CEWR3.eps Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 15 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® AC WAVEFORMS WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CE LOW t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, t HA, tSD, and tHD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. 16 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit VDR VDD for Data Retention See Data Retention Waveform 1.2 3.6 V IDR Data Retention Current VDD = 1.2V, CE ≥ VDD – 0.2V — — 20 50 mA tSDR tRDR Data Retention Setup Time See Data Retention Waveform 0 — ns Recovery Time See Data Retention Waveform tRC — ns Ind. Auto. DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD 1.65V 1.4V VDR CE GND CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 17 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ISSI ® ORDERING INFORMATION Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V Speed (ns) 1 10 (8 ) Order Part No. Package IS61WV102416BLL-10MI IS61WV102416BLL-10MLI IS61WV102416BLL-10TI IS61WV102416BLL-10TLI 48 mini BGA (9mm x 11mm) 48 mini BGA (9mm x 11mm), Lead-free TSOP (Type I) TSOP (Type I), Lead-free Note: 1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V - 3.6V Industrial Range: -40°C to +85°C Voltage Range: 1.65V to 2.2V Speed (ns) 20 Order Part No. Package IS61WV102416ALL-20MI IS61WV102416ALL-20TI 48 mini BGA (9mm x 11mm) TSOP (Type I) Automotive Range: -40°C to +125°C Voltage Range: 2.4V to 3.6V Speed (ns) 10 18 Order Part No. Package IS64WV102416BLL-10MA3 48 mini BGA (9mm x 11mm) IS64WV102416BLL-10TA3 TSOP (Type I) Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 09/22/06 ISSI PACKAGING INFORMATION ® Mini Ball Grid Array Package Code: M (48-pin) Top View Bottom View φ b (48x) 1 2 3 4 5 6 6 A D 5 4 3 2 1 A e B B C C D D D1 E E F F G G H H e E E1 A2 A SEATING PLANE Notes: 1. Controlling dimensions are in millimeters. A1 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 01/15/03 ISSI PACKAGING INFORMATION ® Mini Ball Grid Array Package Code: M (48-pin) mBGA - 6mm x 8mm MILLIMETERS INCHES Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 48 A — — 1.20 .— — 0.047 A1 0.25 — 0.40 0.010 — 0.016 A2 0.60 — — 0.024 — D 7.90 8.00 8.10 0.311 0.314 0.319 5.60BSC 0.220BSC E 5.90 6.00 6.10 0.232 0.236 0.240 E1 4.00BSC 0.157BSC e 0.80BSC 0.031BSC D1 b 0.40 0.45 0.50 — 0.016 0.018 0.020 mBGA - 7.2mm x 8.7mm mBGA - 9mm x 11mm MILLIMETERS INCHES Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 48 MILLIMETERS INCHES Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 48 A — — 1.20 — — 0.047 A A1 0 .24 — 0.30 0.009 — 0.012 A1 A2 0.60 — — 0.024 — — A2 D 8.60 8.70 8.80 D 10.90 11.00 11.10 0.429 0.433 0.437 5.25BSC 0.207BSC D1 0.339 0.343 0.346 — — 1.20 — — 0.047 0.24 — 0.30 0.60 — — 0.009 — 0.012 0.024 — — 5.25BSC 0.207BSC E 7.10 7.20 7.30 0.280 0.283 0.287 E E1 3.75BSC 0.148BSC E1 3.75BSC 0.148BSC e 0.75BSC 0.030BSC e 0.75BSC 0.030BSC 0.012 0.014 0.016 b b 2 0.30 0.35 0.40 D1 8.90 0.30 9.00 0.35 9.10 0.40 0.350 0.354 0.358 0.012 0.014 0.016 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 01/15/03 ISSI PACKAGING INFORMATION Plastic TSOP - 48 pins Package Code: T (Type I) A A1 1 N E b e D1 SEATING PLANE D Lα Plastic TSOP (T - Type I) Millimeters Inches Symbol Min Max Min Max Ref. Std. N 48 A — 1.20 — 0.047 A1 0.05 0.15 0.002 0.006 b 0.17 0.27 0.007 0.011 C 0.10 0.21 0.004 0.008 D 19.8 20.2 0.780 0.795 D1 18.2 18.6 0.716 0.732 E 11.8 12.2 0.464 0.480 e 0.50 BSC 0.020 BSC L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° Integrated Silicon Solution, Inc. PK13197T48 Rev. B 07/17/97 C Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. ®