AMIS-30421 Micro-Stepping Stepper Motor Bridge Controller Introduction The AMIS−30421 is a micro-stepping stepper motor bridge controller for large current range bipolar applications. The chip interfaces via a SPI interface with an external controller in order to control 2 external power NMOS H−bridges. It has an on-chip voltage regulator, current sensing, self adapting PWM controller and pre-driver with smart slope control switching allowing the part to be EMC compliant with industrial and automotive applications. It uses a proprietary PWM algorithm for reliable current control. The AMIS−30421 contains a current translation table and takes the next micro-step depending on the clock signal on the “NXT” input pin and the status of the “DIR” (direction) register or input pin. The chip provides a so-called “Speed and Load Angle” output. This allows the creation of stall detection algorithms and control loops based on load angle to adjust torque and speed. The AMIS−30421 is implemented in a mature technology, enabling fast high voltage analog circuitry and multiple digital functionalities on the same chip. The chip is fully compatible with automotive voltage requirements. The AMIS−30421 is easy to use and ideally suited for large current stepper motor applications in the automotive, industrial, medical and marine environment. With the on−chip voltage regulator it further reduces the BOM for mechatronic stepper applications. Key Features • • • • • • • • • • • • • • • Dual H−Bridge Pre−Drivers for 2−Phase Stepper Motors Programmable Current via SPI On−chip Current Translator SPI Interface Speed and Load Angle Output 8 Step Modes from Full Step up to 64 Micro−Steps Current−Sense via Two External Sense Resistors PWM Current Control with Automatic Selection of Fast and Slow Decay Low EMC PWM with Selectable Voltage Slopes Full Output Protection and Diagnosis Thermal Warning and Shutdown Compatible with 3.3 V Microcontrollers Integrated 3.3 V Regulator to Supply External Microcontroller Integrated Reset Function to Reset External Microcontroller These Devices are Pb−Free and are RoHS Compliant* http://onsemi.com 1 44 QFN44 CASE 485BY MARKING DIAGRAM 1 AMIS30421 0C421−001 AWLYYWWG A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 40 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2011 October, 2011 − Rev. 0 1 Publication Order Number: AMIS−30421/D AMIS−30421 OSC Voltage Regulator CLK CS DI DO Temp . Sense VBB GXBL GXBR + − I−sense RSENSXP COMP RSENSXN GYTL GYTR EMC P W M Band − gap GYBL GYBR I−sense + − WD ERR VCP P W M T R A N S L A T O R Load Angle CLR SLA GXTL GXTR EMC OTP Logic & Registers MOTXP MOTXN Chargepump POR NXT DIR CPP CPN VDD VREGH BLOCK DIAGRAM COMP RSENSYP RSENSYN MOTYP MOTYN AMIS −30421 TEST GND Figure 1. Block Diagram AMIS−30421 NC NC GND VCP CPP CPN VBB GND NC NC NC 44 43 42 41 40 39 38 37 36 35 34 PIN OUT NC 1 33 NC GXBL 2 32 GYBL MOTXP 3 31 MOTYP GXTL 4 30 GYTL GXBR 5 29 GYBR MOTXN 6 28 MOTYN GXTR 7 27 GYTR RSENSXP 8 26 RSENSYP RSENSXN AMIS−30421 15 16 17 18 19 20 21 22 WD CLK CS DI DO TEST NC CLR NXT ERR 23 14 11 SLA DIR GND 13 RSENSYN 24 12 25 10 VREGH 9 VDD Figure 2. Pin Out AMIS−30421 http://onsemi.com 2 AMIS−30421 Table 1. PIN LIST AND DESCRIPTION Name Pin Description Type GXBL 2 Gate of external NMOS FET of the X bridge bottom left side MOTXP 3 Positive end of phase X−coil GXTL 4 Gate of external NMOS FET of the X bridge top left side Analog Output Analog Output Equivalent Schematic Analog Output Analog I/O GXBR 5 Gate of external NMOS FET of the X bridge bottom right side MOTXN 6 Negative end of phase X−coil GXTR 7 Gate of external NMOS FET of the X bridge top right side RSENSXP 8 Resistor sense of the X bridge positive pin Analog Input RSENSXN 9 Resistor sense of the X bridge negative pin Analog Input VDD 10 Low voltage supply output (needs external decoupling capacitor) Analog I/O Analog Output Supply Type 7 GND 11 Ground, heat sink VREGH 13 High voltage supply output Analog output Supply SLA 14 Speed and Load Angle output Analog output Type 6 ERRb 15 Error output Digital Output Type 2 or 4 CLR 16 Clear input Digital Input Type 1 WDb 17 Watchdog and Power On Reset output Digital Output Type 2 or 4 CLK 18 SPI Clock input Digital Input Type 1 CSb 19 SPI Chip Select input Digital Input Type 3 DI 20 SPI Data input Digital Input Type 1 DO 21 SPI Data output Digital Output Type 2 or 4 TEST 22 Test input. To be tied to ground. Digital Input Type 1 NXT 23 Next Microstep input Digital Input Type 1 Type 1 DIR 24 Direction input Digital Input RSENSYN 25 Resistor sense of the Y bridge negative pin Analog Input RSENSYP 26 Resistor sense of the Y bridge positive pin Analog Input GYTR 27 Gate of external NMOS FET of the Y bridge top right side MOTYN 28 Negative end of phase Y−coil GYBR 29 Gate of external NMOS FET of the Y bridge bottom right side Analog Output Analog Output Analog Output Analog I/O GYTL 30 Gate of external NMOS FET of the Y bridge top left side MOTYP 31 Positive end of phase Y−coil GYBL 32 Gate of external NMOS FET of the Y bridge bottom left side GND 37 Ground, heat sink Supply VBB 38 High voltage supply input Supply CPN 39 Negative connection of charge pump capacitor Analog I/O CPP 40 Positive connection of charge pump capacitor Analog I/O VCP 41 Charge Pump filter capacitor Analog I/O GND 42 Ground, heat sink NC 1, 12, 33, 34, 35, 36, 43, 44 NOTE: Analog I/O Analog Output Supply Not connected or connect with ground Output type of WDb−, ERRb− and DO−pin is selectable through SPI http://onsemi.com 3 Type 8 AMIS−30421 EQUIVALENT SCHEMATICS Following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified representations of the circuits used. VDD VDD IN OUT Rpd TYPE 1: CLK, DI, NXT, DIR, CLR, TEST Input TYPE 2: DO, WDb, ERRb Open Drain Output VDD VDD Rpu IN OUT TYPE 3: CSb Input TYPE 4: DO, WDb, ERRb Push Pull Output VDD Rout SLA TYPE 6: SLA Analog Output VBB1 VDD VDD VBB TYPE 7: VDD Power Supply NOTE: TYPE 8: VBB Power Supply Output type of WDb−, ERRb− and DO−pin is selectable through SPI Figure 3. In− and Output Equivalent Diagrams http://onsemi.com 4 AMIS−30421 ELECTRICAL SPECIFICATION Table 2. ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2) Symbol Parameter Min Max Unit VBB Analog DC supply voltage (Note 3) −0.3 +40 V Iload Logic supply external load current, Normal Mode 0 −10 mA Logic supply external load current, Sleep Mode 0 −1 mA Voltage on pins RSENSXP, RSENSXN, RSENSYP and RSENYN −2.0 +2.0 V Voltage on digital I/O pins and SLA−pin −0.3 3.6 V VRSENS VLVIO VDD + 0.3 ISLA Load current on SLA−pin 0 −40 mA TST Storage temperature −55 +160 °C Junction Temperature under bias (Note 4) −50 +175 °C VHBM Human Body Model electrostatic discharge immunity (Note 5) −1.5 +1.5 kV VHBM Human Body Model electrostatic discharge immunity, high voltage pins (Note 6) −4 +4 kV VMM Machine Model electrostatic discharge immunity (Note 7) −150 +150 V VCDM Charge Device Model electrostatic discharge immunity (Note 8) −500 +500 V TJ Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. If more than one value is mentioned, the most stringent applies. 2. Convention: currents flowing in the circuit are defined as positive. 3. +36 V < VBB < +40 V limited to 1 day over lifetime 4. Circuit functionality not guaranteed. 5. According to JEDEC JESD22−A114C 6. High Voltage Pins MOTxx, VBB, GND; According to JEDEC JESD22−A114C 7. According to JEDEC EIA−JESD22−A115−A 8. According to STM5.3.1−1999 RECOMMEND OPERATION CONDITIONS Operating ranges define the limits for functional operation and parametric characteristics of the device. Note that the functionality of the chip outside these operating ranges is not guaranteed. Operating outside the recommended operating ranges for extended periods of time may affect device reliability. Table 3. OPERATING RANGES Symbol Parameter Min Max Unit +6 +30 V VBB Analog DC supply VDD Logic Supply Output Voltage (Normal Mode) +3.0 +3.6 V Junction temperature (Note 9) −40 +125 °C TJ 9. High junction temperature can result in reduced lifetime. http://onsemi.com 5 AMIS−30421 Table 4. DC PARAMETERS The DC parameters are given for VBB and temperature in their operating ranges unless otherwise specified. Convention: currents flowing in the circuit are defined as positive. Pin(s) Symbol Parameter Remark/Test Conditions Min Typ Max Unit 30 V SUPPLY & VOLTAGE REGULATOR VBB VBB Nominal operating supply range 6 IBB Total internal current consumption Unloaded outputs, IINT included, H−bridge disabled 20 mA ISLEEP Sleep mode current consumption Unloaded outputs, CSb = VDD 150 mA VDD VDD VDD_SLEEP Regulated Output Voltage Regulated Output Voltage in Sleep IINT Internal load current ILOAD External load current IDDLIM Current limitation ILOAD_PD −10 mA ≤ Iload ≤ 0 mA 3.0 3.3 3.6 V −1 mA ≤ Iload ≤ 0 mA 2.1 2.95 3.63 V 8 mA −10 mA −80 mA −1 mA 11.5 V VBB V Unloaded outputs Pin shorted to ground −20 Output current in sleep VREGH VREGH High voltage regulator VBBLV v VBB v 30 V Based on Figure 9 H−bridge disabled 13.25 V v VBBLV v 15.75 V 8.0 9.5 6 V v VBB < VBBLV Based on Figure 9 H−bridge disabled 13.25 V v VBBLV v 15.75 V POWER ON RESET (POR) VDDH VDDL VDD Internal POR comparator threshold VDD rising, see Figure 4 1.44 1.8 2.53 Internal POR comparator threshold VDD falling, see Figure 4 1.16 1.5 1.93 Internal POR comparator hysteresis VDDhys V 0.3 UNDERVOLTAGE VBBUH VBBUL VBB VBBUhys VBB undervoltage release level VBB rising, see Figure 5 5.5 6.5 VBB undervoltage trigger level VBB falling, see Figure 5 5.3 6.3 VBB undervoltage hysteresis V 0.25 OVERVOLTAGE VBBOH VBBOL VBB VBBOhys VBB overvoltage trigger level VBB rising, see Figure 5 30.0 VBB overvoltage release level VBB falling, see Figure 5 29.0 32.0 31 V −1.25 −33.00 mA −45 +45 % −10.5 −115.5 mA −45 +45 % 25 W VBB overvoltage hysteresis 1 PRE−DRIVER Gate charge current ION_tol IOFF IOFF_tol RSW GXTR, GXTL, GXBR, GXBL, GYTR, GYTL, GYBR, GYBL ION Selectable through SPI Gate charge current tolerance Gate discharge current Selectable through SPI Gate discharge current tolerance Switch On−resistance See also Figure 10 http://onsemi.com 6 5 10 AMIS−30421 Table 4. DC PARAMETERS The DC parameters are given for VBB and temperature in their operating ranges unless otherwise specified. Convention: currents flowing in the circuit are defined as positive. Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit PRE−DRIVER VSENS0 PWM comparator toggle level 0 78 100 122 mV VSENS1 PWM comparator toggle level 1 105.3 135 164.7 mV VSENS2 PWM comparator toggle level 2 156 200 244 mV PWM comparator toggle level 3 210.6 270 391.4 mV PWM comparator toggle level 4 261.3 335 408.7 mV VSENS5 PWM comparator toggle level 5 312 400 488 mV VSENS6 PWM comparator toggle level 6 390 500 610 mV VSENS7 PWM comparator toggle level 7 468 600 732 mV 0 0.3 x VDD V 0.7 x VDD VDD V VSENS3 VSENS4 RSENSxx DIGITAL INPUTS VIL VIH Rpd Rpu Logic Low Threshold CLK, DI, Logic High Threshold CSb, NXT, DIR, CLR Internal Pull Down Resistor CSb Internal Pull Up Resistor CSb excluded, See also Figure 3 25 50 75 kW See also Figure 3 25 50 75 kW DIGITAL OUTPUTS Logic low output level VOL VOH VOL_OPEN DO, ERRb, WDb Output set to type 4 (see Figure 3) Logic high output level 0.5 VDD − 0.5 V IOL = 8 mA, Output set to type 2 (see Figure 3) Logic Low level open drain 0.5 SPEED AND LOAD ANGLE OUTPUT Vout Output Voltage Range Voff Output Offset SLA−pin Voff_tol GSLA 0.5 Selectable through SPI Tolerance on SLA output offset SLA GSLA_tol Gain of SLA−pin = VBEMF / VSLA Selectable through SPI Tolerance on SLA gain Rout Output Resistance SLA−pin ISLA_load VDD − 0.5 0.6 1.2 V −17 +17 % 0.0625 1 −10 +10 % 1 kW −40 mA See also Figure 3 Load current SLA−pin V 0 THERMAL WARNING & SHUTDOWN T1 Trigger level thermal range 1 See Figure 22 −5 15 35 °C T2 Trigger level thermal range 2 See Figure 22 55 70 85 °C T3 Trigger level thermal range 3 See Figure 22 138 150 162 °C TTW Thermal Warning See Figure 22 138 150 162 °C TTSD Thermal shutdown See Figure 22 TTW + 20 °C CHARGE PUMP VCP − VBB VCPP – VCPN Chargepump overdrive voltage VCP Based on Figure 9 Chargepump pumping voltage 3.5 VBB – 2.5 15.75 V 3.5 VBB – 2.5 15.75 V Cpump External pump capacitor See also C2 Figure 9 220 nF Cbuffer CPP CPN External buffer capacitor See also C3 Figure 9 220 nF http://onsemi.com 7 AMIS−30421 Table 4. DC PARAMETERS The DC parameters are given for VBB and temperature in their operating ranges unless otherwise specified. Convention: currents flowing in the circuit are defined as positive. Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit PACKAGE THERMAL RESISTANCE VALUE Thermal Resistance Junction−to−Ambient Rthja Simulated Conform JEDEC JESD−51, (2S2P) 30 K/W Simulated Conform JEDEC JESD−51, (1S0P) 60 K/W 0.95 K/W Thermal Resistance Junction−to−Exposed Pad Rthjp Table 5. AC PARAMETER The AC parameters are given for VBB and temperature in their operating ranges unless otherwise specified. Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit 6.4 8 9.6 MHz 60 ms 120 ms INTERNAL OSCILLATOR Frequency of internal oscillator fosc POWER−UP tPU tPOR tRF tDSPI POR Power−up time CVDD = 200 nF, See Figure 4 Reset duration See Figure 4 80 Reset filter time See Figure 4 1 SPI Delay See Figure 4 100 15 ms 500 ms 30 kHz PREDRIVER fPWM PWM frequency Frequency depends only on internal oscillator 20 25 t1 Bridge MOSFET switch on time t1 Selectable through SPI. See Figure 11. 375 1250 ns t2 Bridge MOSFET switch on time t2 Selectable through SPI. See Figure 11. 1250 4750 ns toff Bridge MOSFET switch off time Selectable through SPI. See Figure 11. 1250 4750 ns −20 +20 % 0.32 163.84 ms −20 +20 % 0 1 ms −20 +20 % tswitch_tol topen topen_acc tnocross tnocross_acc Bridge MOSFET switch on/off tolerance Open circuit time out Selectable through SPI Open circuit time out accuracy Non overlap time Selectable through SPI Non overlap accuracy http://onsemi.com 8 AMIS−30421 Table 5. AC PARAMETER The AC parameters are given for VBB and temperature in their operating ranges unless otherwise specified. Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit DIGITAL INPUTS tNXT_HI NXT Minimum, high pulse width 625 ns tNXT_LO NXT Minimum, low pulse width 625 ns tDIR_SET NXT set up time, following change of DIR or <DIRCTRL> 1 ms tDIR_HOLD NXT hold time, before change of DIR or <DIRCTRL> 1 ms tSLP_SET <SLP> set up time 300 ms <SLP> hold time 1 ms tMOTEN_SET <MOTEN> set up time 1 ms tMOTEN_HO <MOTEN> hold time 1 ms tSLP_HOLD LD tMSP See Figure 6 <MSP[7:0]> update delay 1 ms CLEAR FUNCTION tCLR_SET tCLR CLR Clear set up time See Figure 7 40 Clear duration time See Figure 7 20 ms 90 ms 50 ns 2.5 ms ms DIGITAL OUTPUTS tH2L DO, WDb, Output fall−time from VOH to VOL ERRb Output type 2, capacitive load 400 pF and pull−up resistor of 1.5 kW WATCHDOG tWDPR Prohibited watchdog acknowledge time tWDTO Watchdog time out interval 32 512 Watchdog time out accuracy −20 +20 % 500 ns tWDTO_acc tWDRD Watchdog Reset Delay SERIAL PERIPHERAL INTERFACE (SPI) SPI Clock period tCLK tCLK_HIGH CLK tCLK_LOW tDI_SET DI tDI_HOLD tCS_HIGH tCS_SET CSb tCS_HOLD 1 ms SPI Clock high time 100 ns SPI Clock low time 100 ns 50 ns 50 ns SPI Chip Select high time 2.5 ms SPI Chip Select set up time 100 ns SPI Chip Select hold time 100 ns SPI Data Input set up time See Figure 8 SPI Data Input hold time SPEED AND LOAD ANGLE OUTPUT tSLA_DELAY SLA tMinSLA tMinSLA_Acc SLA output update delay Not−transparent Mode See Figure 20 Minimum zero crossing time Selectable through SPI Minimum zero crossing accuracy 60 ms 40 360 ms −20 +20 % 250 kHz CHARGE PUMP fCP tCPU CPN CPP Charge pump frequency MOTxx Start−up time of charge pump 160 Spec external components in Table 4 http://onsemi.com 9 200 250 ms AMIS−30421 VBB t tPU VDD VDDH VDDL ≤tRF t POR Internal signal t tPOR VWDb <WDEN> tDSPI Enable Watchdog WD Timer > tWDPR and tWDTO t WDTO Internal signal t WDPR Remarks: −WDb−pin pulled up to VDD −tWDTO = <WDT[3:0]> −<WDEN> and <WDT[3:0]> are SPI bits É Ï Ï É Ï É Ï É Ï É tPOR t Write ‘1’ to <WDEN> ≤ tWDPR or ≥ tWDTO t tWDRD t Figure 4. Power−On−Reset Timing Diagram VBB V BBOH VBBOL V BBUH V BBUL Figure 5. Under− and Overvoltage http://onsemi.com 10 t AMIS−30421 NXT (<NXTP> = 1) NXT (<NXTP> = 0) DIR or <DRCTRL> <SM[2:0]> <MSP[7:0]> ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ <SLP> <MOTEN> tMOTEN_SET tMOTEN_HOLD t DIR_HOLD tDIR_SET t SLP_SET tSLP_HOLD t MSP tNXT_HI tNXT_LOW Remarks: −<CIRCTRL>, <SM[2:0]>, <MSP[7:0]>, <SLP>, <MOTEN> and <NXTP> are SPI bits −Timing for SPI bits starts after CS is high −TSLP_SET only relates to the digital inputs pins DIR and NXT Figure 6. Digital Input Timing Diagram <SPI> CLR tCLR_SET tCLR Remarks: <SPI> is any SPI data Figure 7. CLR−pin Timing Diagram CS CLK ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ DI t DI_SET tCS_SET tDI_HOLD ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ t CS_HIGH tCLK_HIGH t CLK_LOW t CLK tCS_HOLD Figure 8. SPI Bus Timing Diagram http://onsemi.com 11 AMIS−30421 TYPICAL APPLICATION SCHEMATIC VBAT C3 C2 C1 D1 VDD 38 VDD 41 CPP CPN VCP VBB C4 39 40 10 7 C5 4 6 VREGH C8 3 13 C7 2 5 CS Microcontroller SPI Interface DI DO NXT Motor Positioner DIR CLR Diagnostics SLA C6 AMIS−30421 18 27 19 30 20 28 21 31 23 32 24 29 16 26 15 14 R6 25 11 GND Position Feedback ERR 9 37 GXTL T1 T2 T3 T4 MOTXN MOTXP GXBL GXBR RSENSXP M R1 RSENSXN GYTR GYTL T5 T6 T7 T8 MOTYN MOTYP GYBL GYBR RSENSYP R2 RSENSYN 42 GND CLK 8 17 GND WD Reset GXTR Figure 9. Typical Application Schematic AMIS−30421 Table 6. EXTERNAL COMPONENTS LIST AND DESCRIPTION Component Function Typ Value Tolerance Unit C1 VBB buffer capacitor (Note 1) 100 ±20% mF C2 Charge−pump pumping capacitor 220 ± 20% nF C3 Charge−pump buffer capacitor 220 ±20% nF C4 VBB decoupling capacitor (Note 2) 100 ±20% nF C5, C8 VDD buffer capacitor 100 ±20 % nF C6 Low pass filter SLA 1 ±20% nF C7 VREGH buffer capacitor 4.7 ±20% uF R1, R2 Sense Resistors >25 ±1% mW R6 Low pass filter SLA 5.6 ±1% kW D1 Optional reverse protection diode T1 … T8 MBRD1045 H−Bridge N−MOSFET NTD4815N or NTD4813N or NTD40N03R or NTD5807N 10. ESR < 1 W. 11. ESR < 50 mW. http://onsemi.com 12 AMIS−30421 FUNCTIONAL DESCRIPTION H−Bridge Pre−Drivers The H−bridge pre−drivers for external N−type MOSFETs are controlled by means of current sources for slope regulation (Figure 10). The current source value can be set through SPI (see p35 and further). During the MOSFET switch−on and switch−off phase this current source will be applied for a certain time (respectively ton and toff where ton is divided in t1 and t2). After this time (ton or toff) the gate of the MOSFET is pulled high or low by means of a switch (SWon or SWoff). The timings can also be set through SPI (see p37 and further). To prevent short circuits, an additional time tnocross can be added between switching off one MOSFET and switching on the other MOSFET of a half H−bridge (SPI bits <NO_CROSS[1:0]>). More information on the current sources and timings can be found in Table 5. A detailed description of the SPI settings for the H−bridge pre−drivers can be found at p31 and further. Figure 11 gives a detailed view on the different stages during switching of the MOSFET. Ion SWon External MOSFET Ioff SWoff AMIS−30421 Figure 10. Pre−driver Topology Vgate 5 1 2 ION1 ION2 t1 3 4 5 IOFF t2 ton toff Figure 11. Detailed View on MOSFET Switching http://onsemi.com 13 tnocross t AMIS−30421 PWM Current Control pins DIR and NXT. It is translating consecutive steps in corresponding currents in both motor coils for a given step mode. One out of 8 possible stepping modes can be selected through SPI bits <SM[2:0]>. After power−up or clear (CLR−pin) the coil current translator is set to position 0. For all stepping modes except full step this means that the coil current is maximum in the Y−coil and zero in the X−coil (see Table 7). If NXT pulses are applied when the DIR−pin is pulled low, SPI bit <DIRCTRL> is zero and SPI bit <MOTEN> is one, the coil current translator will step through Table 7 from top till bottom. If DIR−pin is pulled high or SPI bit <DIRCTRL> is set to ‘1’, the coil current translator will step in opposite direction through the table. Figures 12 up to 15 gives another view on the different stepping modes. The Y−coil current is plotted on the Y−axes, the X−coil current on the X−axes. Notice that all stepping modes from Table 7 can be plotted on a circle with the exception of half step uncompensated and full step. These are plotted on a square. A PWM comparator compares continuously the actual winding current (measured over the external sense resistor) with the requested current and feeds back the information to a digital regulation loop. This loop then generates a PWM signal, which turns on/off the current sources (Ion, Ioff) and switches (SWon, SWoff). The switching points of the PWM duty−cycle are synchronized to the on−chip PWM clock. The frequency of the PWM controller is fixed and will not vary with changes in the supply voltage. Also variations in motor−speed or load−conditions of the motor have no effect. There are no external components required to adjust the PWM frequency. For EMC reasons it’s possible to add jitter to the PWM by means of the <PWMJ> bit. Step Translator and Step Mode The step translator provides the control of the motor by means of the stepmode SPI bits <SM[2:0]>, the enable SPI bit <MOTEN>, the direction SPI bit <DIRCTRL> and input IY DIR−pin = high IY Start = 0 DIR−pin = high DIR−pin = low DIR−pin = low Start = 0 Step 1 Step 15 Step 1 Step 7 Step 2 Step 14 Step13 Step2 Step 6 Step 3 Step 4 Step12 IX IX Step 11 Step 3 Step5 Step5 Step 6 Step 10 Step 9 Step7 Step 4 Step 8 Figure 12. Circular representation Half−step Compensated Figure 13. Circular representation 1/4 Microstepping IY DIR−pin = high IY DIR−pin = low Step7 Start= 0 DIR−pin = high Step 1 DIR−pin = low Start= 0 Step 1 Step2 Step 6 Step5 IX Step4 IX Step 3 Step3 Figure 14. Square Representation Half−step Uncompensated Figure 15. Square Representation Full−step Remark: ♦ ♦ Step2 Positive coil current flows from MOTXP to MOTXN and MOTYP to MOTYN. In above figures SPI bit <DIRCTRL> is set to ‘0’. When set to ‘1’, rotation will be reversed. http://onsemi.com 14 AMIS−30421 Table 7. CIRCULAR TRANSLATOR TABLE Stepmode ( <SM[2:0]> ) % of Imax 000 001 010 011 100 101 110 111 1/64 1/32 1/16 1/8 1/4 1/2 comp 1/2 uncomp Full Coil x Coil y 0 0 0 0 0 0 0 − 0 100 1 − − − − − − − 3 100 2 1 − − − − − − 5 100 3 − − − − − − − 8 100 4 2 1 − − − − − 10 100 5 − − − − − − − 13 100 6 3 − − − − − − 14 100 7 − − − − − − − 17 98 8 4 2 1 − − − − 19 98 9 − − − − − − − 22 98 10 5 − − − − − − 25 97 11 − − − − − − − 27 97 12 6 3 − − − − − 30 97 13 − − − − − − − 32 95 14 7 − − − − − − 35 95 15 − − − − − − − 37 94 16 8 4 2 1 − − − 38 94 17 − − − − − − − 41 92 18 9 − − − − − − 43 90 19 − − − − − − − 46 90 20 10 5 − − − − − 48 89 21 − − − − − − − 51 87 22 11 − − − − − − 52 87 23 − − − − − − − 54 86 24 12 6 3 − − − − 56 84 25 − − − − − − − 59 83 26 13 − − − − − − 60 81 27 − − − − − − − 62 79 28 14 7 − − − − − 63 78 29 − − − − − − − 67 76 30 15 − − − − − − 68 75 31 − − − − − − − 70 73 32 16 8 4 2 1 1 1 71 / 100 71 / 100 33 − − − − − − − 73 70 34 17 − − − − − − 75 68 35 − − − − − − − 76 67 36 18 9 − − − − − 78 63 37 − − − − − − − 79 62 38 19 − − − − − − 81 60 39 − − − − − − − 83 59 40 20 10 5 − − − − 84 56 41 − − − − − − − 86 54 42 21 − − − − − − 87 52 43 − − − − − − − 87 51 44 22 11 − − − − − 89 48 45 − − − − − − − 90 46 46 23 − − − − − − 90 43 47 − − − − − − − 92 41 48 24 12 6 3 − − − 94 38 49 − − − − − − − 94 37 50 25 − − − − − − 95 35 51 − − − − − − − 95 32 52 26 13 − − − − − 97 30 53 − − − − − − − 97 27 54 27 − − − − − − 97 25 55 − − − − − − − 98 22 56 28 14 7 − − − − 98 19 57 − − − − − − − 98 17 58 29 − − − − − − 100 14 59 − − − − − − − 100 13 60 30 15 − − − − − 100 10 61 − − − − − − − 100 8 62 31 − − − − − − 100 5 63 − − − − − − − 100 3 http://onsemi.com 15 AMIS−30421 Table 7. CIRCULAR TRANSLATOR TABLE Stepmode ( <SM[2:0]> ) % of Imax 000 001 010 011 100 101 110 111 1/64 1/32 1/16 1/8 1/4 1/2 comp 1/2 uncomp Full Coil x 64 32 16 8 4 2 2 − 100 0 65 − − − − − − − 100 −3 66 33 − − − − − − 100 −5 67 − − − − − − − 100 −8 68 34 17 − − − − − 100 −10 69 − − − − − − − 100 −13 70 35 − − − − − − 100 −14 71 − − − − − − − 98 −17 72 36 18 9 − − − − 98 −19 73 − − − − − − − 98 −22 74 37 − − − − − − 97 −25 75 − − − − − − − 97 −27 76 38 19 − − − − − 97 −30 77 − − − − − − − 95 −32 78 39 − − − − − − 95 −35 79 − − − − − − − 94 −37 80 40 20 10 5 − − − 94 −38 81 − − − − − − − 92 −41 82 41 − − − − − − 90 −43 83 − − − − − − − 90 −46 84 42 21 − − − − − 89 −48 85 − − − − − − − 87 −51 86 43 − − − − − − 87 −52 87 − − − − − − − 86 −54 88 44 22 11 − − − − 84 −56 89 − − − − − − − 83 −59 90 45 − − − − − − 81 −60 91 − − − − − − − 79 −62 92 46 23 − − − − − 78 −63 93 − − − − − − − 76 −67 94 47 − − − − − − 75 −68 95 − − − − − − − 73 −70 96 48 24 12 6 3 3 2 71 / 100 −71 / −100 97 − − − − − − − 70 −73 98 49 − − − − − − 68 −75 99 − − − − − − − 67 −76 100 50 25 − − − − − 63 −78 101 − − − − − − − 62 −79 102 51 − − − − − − 60 −81 103 − − − − − − − 59 −83 104 52 26 13 − − − − 56 −84 105 − − − − − − − 54 −86 106 53 − − − − − − 52 −87 107 − − − − − − − 51 −87 108 54 27 − − − − − 48 −89 109 − − − − − − − 46 −90 110 55 − − − − − − 43 −90 111 − − − − − − − 41 −92 112 56 28 14 7 − − − 38 −94 113 − − − − − − − 37 −94 114 57 − − − − − − 35 −95 115 − − − − − − − 32 −95 116 58 29 − − − − − 30 −97 117 − − − − − − − 27 −97 118 59 − − − − − − 25 −97 119 − − − − − − − 22 −98 120 60 30 15 − − − − 19 −98 121 − − − − − − − 17 −98 122 61 − − − − − − 14 −100 Coil y 123 − − − − − − − 13 −100 124 62 31 − − − − − 10 −100 125 − − − − − − − 8 −100 126 63 − − − − − − 5 −100 127 − − − − − − − 3 −100 http://onsemi.com 16 AMIS−30421 Table 7. CIRCULAR TRANSLATOR TABLE Stepmode ( <SM[2:0]> ) % of Imax 000 001 010 011 100 101 110 111 1/64 1/32 1/16 1/8 1/4 1/2 comp 1/2 uncomp Full Coil x Coil y 128 64 32 16 8 4 4 − 0 −100 129 − − − − − − − −3 −100 130 65 − − − − − − −5 −100 131 − − − − − − − −8 −100 132 66 33 − − − − − −10 −100 133 − − − − − − − −13 −100 134 67 − − − − − − −14 −100 135 − − − − − − − −17 −98 136 68 34 17 − − − − −19 −98 137 − − − − − − − −22 −98 138 69 − − − − − − −25 −97 139 − − − − − − − −27 −97 140 70 35 − − − − − −30 −97 141 − − − − − − − −32 −95 142 71 − − − − − − −35 −95 143 − − − − − − − −37 −94 144 72 36 18 9 − − − −38 −94 145 − − − − − − − −41 −92 146 73 − − − − − − −43 −90 147 − − − − − − − −46 −90 148 74 37 − − − − − −48 −89 149 − − − − − − − −51 −87 150 75 − − − − − − −52 −87 151 − − − − − − − −54 −86 152 76 38 19 − − − − −56 −84 153 − − − − − − − −59 −83 154 77 − − − − − − −60 −81 155 − − − − − − − −62 −79 156 78 39 − − − − − −63 −78 157 − − − − − − − −67 −76 158 79 − − − − − − −68 −75 159 − − − − − − − −70 −73 160 80 40 20 10 5 5 3 −71 / −100 −71 / −100 161 − − − − − − − −73 −70 162 81 − − − − − − −75 −68 163 − − − − − − − −76 −67 164 82 41 − − − − − −78 −63 165 − − − − − − − −79 −62 166 83 − − − − − − −81 −60 167 − − − − − − − −83 −59 168 84 42 21 − − − − −84 −56 169 − − − − − − − −86 −54 170 85 − − − − − − −87 −52 171 − − − − − − − −87 −51 172 86 43 − − − − − −89 −48 173 − − − − − − − −90 −46 174 87 − − − − − − −90 −43 175 − − − − − − − −92 −41 176 88 44 22 11 − − − −94 −38 177 − − − − − − − −94 −37 178 89 − − − − − − −95 −35 179 − − − − − − − −95 −32 180 90 45 − − − − − −97 −30 181 − − − − − − − −97 −27 182 91 − − − − − − −97 −25 183 − − − − − − − −98 −22 184 92 46 23 − − − − −98 −19 185 − − − − − − − −98 −17 186 93 − − − − − − −100 −14 187 − − − − − − − −100 −13 188 94 47 − − − − − −100 −10 189 − − − − − − − −100 −8 190 95 − − − − − − −100 −5 191 − − − − − − − −100 −3 http://onsemi.com 17 AMIS−30421 Table 7. CIRCULAR TRANSLATOR TABLE Stepmode ( <SM[2:0]> ) % of Imax 000 001 010 011 100 101 110 111 1/64 1/32 1/16 1/8 1/4 1/2 comp 1/2 uncomp Full Coil x Coil y 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 96 − 97 − 98 − 99 − 100 − 101 − 102 − 103 − 104 − 105 − 106 − 107 − 108 − 109 − 110 − 111 − 112 − 113 − 114 − 115 − 116 − 117 − 118 − 119 − 120 − 121 − 122 − 123 − 124 − 125 − 126 − 127 − 48 − − − 49 − − − 50 − − − 51 − − − 52 − − − 53 − − − 54 − − − 55 − − − 56 − − − 57 − − − 58 − − − 59 − − − 60 − − − 61 − − − 62 − − − 63 − − − 24 − − − − − − − 25 − − − − − − − 26 − − − − − − − 27 − − − − − − − 28 − − − − − − − 29 − − − − − − − 30 − − − − − − − 31 − − − − − − − 12 − − − − − − − − − − − − − − − 13 − − − − − − − − − − − − − − − 14 − − − − − − − − − − − − − − − 15 − − − − − − − − − − − − − − − 6 − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − 7 − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − 6 − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − 7 − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − 0 − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −100 −100 −100 −100 −100 −100 −100 −98 −98 −98 −97 −97 −97 −95 −95 −94 −94 −92 −90 −90 −89 −87 −87 −86 −84 −83 −81 −79 −78 −76 −75 −73 −71 / −100 −70 −68 −67 −63 −62 −60 −59 −56 −54 −52 −51 −48 −46 −43 −41 −38 −37 −35 −32 −30 −27 −25 −22 −19 −17 −14 −13 −10 −8 −5 −3 0 3 5 8 10 13 14 17 19 22 25 27 30 32 35 37 38 41 43 46 48 51 52 54 56 59 60 62 63 67 68 70 71 / 100 73 75 76 78 79 81 83 84 86 87 87 89 90 90 92 94 94 95 95 97 97 97 98 98 98 100 100 100 100 100 100 Remarks: ♦ ♦ Positive coil current conducts from MOTXP to MOTXN or MOTYP to MOTYN. For some microstep positions 2 values are given for Coil X and Coil Y. The second value is only valid for <SM[2:0]> = “11x” http://onsemi.com 18 AMIS−30421 Direction The direction of rotation can be changed by means of the DIR−pin and the SPI bit <DIRCTRL>. See also Figure 12 up to Figure 15. Setup and hold times need to be respected when changing direction (see Figure 6). Certain errors (see Error Output p24) will automatically disable the motor driver (<MOTEN> = 0). The errors first need to be cleared before one is able to enable the motor driver again. Setup and hold times need to be respected (see Figure 6). NXT Input Microstep Position Every rising or falling edge on the NXT−pin (selectable through SPI bit <NXTP>) will move the coil current one step up or down (dependant on the DIR−pin and <DIRCTRL> bit) in the translator table (see Table 7). The motor current will be updated at the next PWM cycle. To be able to track the position in the current translator table (Table 7), the microstep position SPI byte can be used (<MSP[7:0]>). This byte gives the position within the current translator table in units of 1/64 microsteps. This means that when working in 1/4th microstepping the read out microstep positions will be 0, 16, 32, ... The microstep position can be used to track/verify the real position of the stepper motor and as a reference point for changing the stepping mode (to avoid phase shift (see further)). See also Application Note AND8399 for more information on this (this application note is based on AMIS−305xx but is similar for AMIS−30421). Keep in mind that <MSP[7:0]> will only be update 1 ms after the NXT pulse was applied. Enable The enable SPI bit <MOTEN> is used to enable the PWM regulator and drive coil current through the stepper motor coils. When ‘1’ the motor driver is enabled and coil current will be conducted. If ‘0’ (zero), the H−bridge drivers are disabled. When the motor driver is enabled, the NXT− and DIR−pin as also the <DIRCTRL> SPI bit can be used to control the movement of the stepper motor. It’s not allowed to apply pulses on the NXT−pin when the motor driver is disabled. VDIR t VNXT Step up in translator table Step up in translator table Step down in translator table Step down in translator table t Figure 16. Translator table update Microstep full step mode at the moment the coil current is 100% in one of the coils will result in a movement of the rotor. Reversed, changing from full step to any other stepping mode will also result in a movement of the rotor (see Figure 18, top left). If the stepping mode is changed to full step when the coil current in both coils is 71%, the coil current in both coils will only be 71% in full step stepping mode instead of 100% (see Figure 18, top right). Changing to full step stepping mode when the coil current in one of the coils is not 100% nor 71% will result in an offset (see Figure 18, bottom). Notice that stepping is now done on a rectangle instead of a square. There will always be coil current present in both coils when working in full step stepping mode (see Table 7). When zero current is requested in one of the coils, half step stepping mode can be used to mimic full step (see section Full Step Stepping Mode in application note AND8399/D for more info). <SM[2:0]> is used to set the microstep stepping mode. Changing to another microstep stepping mode can be done but the setup and hold timings need to be respected (see Figure 6). Additionally, one needs to be careful to not introduce an offset (or phase shift) in the translator table. Increasing to a higher stepping mode (e.g. from 1/2 to 1/4) can be done at any moment without introducing an offset or phase shift. Decreasing to a lower stepping mode (e.g. from 1/4 to 1/2) can introduce an offset or phase shift if the change to the lower stepping mode is not done at the right moment. One needs to make sure that the translator table position is shared both by the old and new stepping mode setting. Figure 17 gives a good and bad example of reducing the stepping mode. To avoid the creation of an offset it’s advised to only change the stepping mode at a full−step position (<MSP[7:0]> equal to 0, 64, 128 or 192). Changing the stepping mode to (or from) full step stepping mode also needs to be done with care. Changing to http://onsemi.com 19 AMIS−30421 IY IY IY IY DIR−pin = low DIR pin = low Step 1 Step 2 Step 1 Step 2 IX IX IX IX Step 3 1/4th Stepping Mode 1/4th Stepping Mode Half Step Correct change to a lower stepping mode. Step 2 of 1/4th stepping mode is equal to Step 1 of half step stepping mode (see Table 7). No offset or phase shift is created. Half Step Incorrect change to a lower stepping mode. Step 1 of 1/4th stepping mode is not shared with a step in half step stepping mode (see Table 7). An offset or phase shift will be created! Figure 17. NXT−Step Mode Synchronization IY IY IY IY Step Step Step IX Half Step IX Step IX Full Step Half Step IY IX Full Step IY Step Step IX IX Half Step Full Step Figure 18. Changing to/from Full step Stepping Mode Programmable Peak−Current active. The voltage regulator remains functional during and after the clear action and the WDb−pin is not activated. After a clear, NXT pulses can be applied after tCLR_SET (see Figure 7). The amplitude of the current waveform in the motor coils (Imax) can be programmed through SPI bits <CUR[2:0]>. The coil current can be calculated as next: I max + <CUR[2:0}> ń R SENSE Speed and Load Angle Output The SLA−pin provides an output voltage that indicates the level of the BEMF (Back Electro Magnetic Force) voltage of the motor. This BEMF voltage is sampled during every so−called ”coil current zero crossing”. Per coil, two zero−current positions exist per electrical period, yielding in a total of four zero−current observation points per electrical period. Because of the relatively high recirculation currents in the coil during current decay, the coil voltage VCOIL shows a RSENSE is resistor R1 and R2 as given in Figure 9. A change in the coil current (<CUR[2:0]>) will be updated at the next PWM cycle. Clear Logic 0 on the CLR−pin allows normal operation of the chip. To clear the complete digital inside AMIS−30421, the CLR−pin needs to be pulled to logic 1 for a minimum time of tCLR (Table 5). Clearing the motor driver can not be done during Sleep Mode. During a clear the charge pump remains http://onsemi.com 20 AMIS−30421 When working in not−transparent mode (<SLAT> = ‘0’) keep in mind that there is a delay between applying the NXT pulse (to leave the “coil current zero crossing”) and the updated voltage on the SLA−pin (see tSLA_DELAY in Figure 20 and Table 5). transient behavior. This transient behavior (which is not the BEMF) can be made visible or invisible on the SLA−pin by means of SPI bit <SLAT>. When set to transparent (<SLAT> = ‘1’), the coil voltage is sampled every PWM cycle and updated on the SLA−pin (see Figure 19). When set to not−transparent (<SLAT> = ‘0’), only the last sample (taken right before leaving the “coil current zero crossing”) will be copied to the SLA−pin (see Figure 20). I coil I coil t Coil Current Zero Crossing V NXT Next Microstep Next step Previous Microstep Next step V NXT Next Microstep Next step Coil Current Zero Crossing Next step Previous Microstep t t t I coil I coil Current Decay Current Decay t V coil t V coil VBB + 0.6V V BB + 0.6V VBEMF V BEMF t t V SLA Transparent V SLA Not−transparent Bemf of previous zero crossing Last sample before leaving zero crossing is retained. Bemf of previous zero crossing t tSLA _DELAY Remark: Vcoil is only drawn during the coil current zero crossing t Remark: Vcoil is only drawn during the coil current zero crossing Figure 19. Principle of BEMF Measurement in Transparent Mode Figure 20. Principle of BEMF Measurement in Not−Transparent Mode Figure 21). By using SPI bits <MIN_SLA_TIME[1:0]> one can stretch the “coil current zero crossing” without changing the speed of the motor (see Figure 21). AMIS−30421 will ignore but keep track of the NXT pulses applied during the “stretched coil current zero crossing” and compensate the ignored pulses when leaving the “coil current zero crossing”. More information on using the SLA−pin can be found in application note AND8399. Although this application note refers to AMIS−305xx, it is also valid for AMIS−30421. The relationship between the voltage measured on the SLA−pin and the coil voltage is: VSLA = 0.6 + (0.6 x <SLA_OFFS>) + (Vcoil x <SLAG>) SPI bit <SLA_OFFS> can be used to add an additional offset of 0.6 V. Five different SLA gain values can be set by means of SPI bits <SLAG[2:0]>. AMIS−30421 has the ability to stretch the “coil current zero crossing”. If NXT pulses are applied too fast it’s possible that the “coil current zero crossing” is too short making it impossible to measure the real BEMF (see http://onsemi.com 21 AMIS−30421 Figure 21. BEMF sampling without (left) and with (right) zero crossing stretching Sleep Mode The voltage regulator remains active but with reduced current−output capability (ILOAD_PD). When Sleep Mode is left a start−up time is needed for the charge pump to stabilize. After this time (tSLP_SET) NXT commands can be issued (see also Figure 6). Enabling the motor when the charge pump is not stable can result in overcurrent errors (see section Over−Current Detection). Because of this it’s advised to keep the motor disabled during the stabilization time (tSLP_SET). The IO−pins of AMIS−30421 have internal pull−down or pull−up resistors (see Figure 3). Keep this in mind when entering Sleep Mode. In Sleep Mode VDD can drop to 2.1 V minimum (see VDD_SLEEP in Table 4). Keep in mind that in this case it’s not allowed to pull the input pins above 2.1 V! AMIS−30421 can be placed in Sleep Mode by means of SPI bit <SLP>. This mode allows reduction of current−consumption when the motor is not in operation. The effect of sleep mode is as follows: • The drivers are put in HiZ • All analog circuits are disabled and in low−power mode • All SPI registers maintain their logic content • SPI communication is still possible (slightly current increase during SPI communication). • Status Registers can not be cleared by reading out • NXT and DIR inputs are forbidden • Oscillator and digital clocks are silent • Motor driver can not be cleared by means of the CLR−pin http://onsemi.com 22 AMIS−30421 WARNING, ERROR DETECTION AND DIAGNOSTICS FEEDBACK Thermal Warning and Shutdown Note: Successive resetting the motor driver in case of a short circuit condition may damage the drivers. AMIS−30421 has 4 thermal ranges which can be read out through SPI bits <TR[1:0]> and <TSD>. Thermal Range 1 goes from −40°C up to T1. Thermal Range 2 goes from T1 to T2 and Thermal Range 3 goes from T2 up to T3 (T1, T2 and T3 can be found in Table 4). Once above T3 the 4th thermal level is reached which is the thermal warning range. When junction temperature rises above TTW (= T3), the ERRb−pin will be activated. If junction temperature increases above thermal shutdown level (TTSD), then the circuit goes in Thermal Shutdown Mode and all driver transistors are disabled (high impedance). The condition to get out of the Thermal Shutdown Mode is to be at a temperature lower than TTW and by clearing the <TSD> SPI bit. ÂÂ ÏÏ ÏÏ ÂÂ ÈÈ ÈÈ ÈÈ ÇÇ ÇÇ ÇÇ ÀÀ ÀÀ ÀÀ TTSD T 3= TTW Open Coil/Current Not Reached Detection Open coil detection is based on the observation of 100% duty cycle of the PWM regulator. If in a coil 100% duty cycle is detected for a certain time, an open coil will be latched (see Status Register 1 and 2) and the ERRb−pin will be activated (drivers are disabled). The time this 100% duty cycle needs to be present is adjustable with SPI bits <OPEN_COIL[1:0]>. A short time will result in fast detection of an open−coil but could also trigger unwanted open−coil errors. Increase the timing if this is the case. When the resistance of a motor coil is very large and the supply voltage is low, it can happen that the motor driver is not able to deliver the requested current to the motor. Under these conditions the PWM controller duty cycle will be 100% and the ERRb−pin will flag this situation. This feature can be used to test if the operating conditions (supply voltage, motor coil resistance) still allow reaching the requested coil−current or else the coil current should be reduced. Note: A short circuit could trigger an open coil. Thermal Range 4 = Thermal Warning (ERRb−pin active) Thermal Range 3 T2 Thermal Range 2 T1 Thermal Range 1 Charge Pump Failure −40°C The charge pump is an important circuit that guarantees low RDS(on) for all external MOSFET’s, especially for low supply voltages. If supply voltage is too low or external components are not properly connected to guarantee a low RDS(on) of the drivers, a charge pump failure is latched (<CPFAIL>), the ERRb−pin is activated and the driver is disabled (<MOTEN> = ‘0’). One needs to read Status Register 1 to clear the charge pump failure. After power on reset (POR) the charge pump voltage will need some time to exceed the required threshold. During that time the ERRb−pin will be active but not latched for 250us. If the slope of the power supply VBB is slow during power up (charge pump not started after 250 ms), a charge pump failure will be latched and the ERRb−pin is activated (see also Figure 23). Figure 22. Thermal Ranges Over−Current Detection The over−current detection circuit monitors the load current in each activated output stage. If the load current exceeds the over−current detection threshold, the ERRb−pin will be activated and the drivers are switched off (motor driver disabled) to reduce the power dissipation and to protect the H−bridge. Each driver has an individual detection bit (see Status Register 1 and 2). The error condition is latched and the microcontroller needs to read out the error to reset the error and to be able to re−enable the motor driver again. http://onsemi.com 23 AMIS−30421 VBB t VERRb t Charge Pump Failure during start up Charge Pump Failure longer than 250 us due to slow voltage slope Error is latched. Figure 23. Charge Pump Failure Watchdog During and after power up the WDb−pin is an open drain output. One can change this to a push−pull output by using SPI bit <IO_OT>. When VBB is applied, the WDb−pin is kept low for tpor (Table 5). This can for instance be used to reset an external microcontroller at power up. The WDb−pin also has a second function, a Watchdog function. When the watchdog is enabled (<WDEN> = ‘1’), a timer will start counting up. When the counter reaches a certain value (<WDT[3:0]>), the <WD> SPI bit will be set and the WDb−pin will be pulled low for a time equal to tPOR to reset the external microcontroller. To avoid that the microcontroller gets reset, the microcontroller needs to re−enable the watchdog before the count value is reached (= write ‘1’ to <WDEN> before <WDT[3:0]> is reached). This functionality can be used to reset a “stuck” microcontroller. The SPI bit <WD> can be used to detect a cold or warm boot. When powering the application (cold boot), <WD> will be zero. If the microcontroller has been reset by the WDb−pin (warm boot), <WD> bit will be ‘1’. The microcontroller can use this information to detect a cold or warm boot. It’s forbidden to re−enable the watchdog too fast (minimum time between re−enabling must be above tWDPR (see Figure 4)). One may also not enable the watchdog too fast after power up (see tDSPI, Figure 4). A small analogue filter avoids resetting due to spikes or noise on the VDD supply (trf). Error Output The error output (ERRb−pin) will be activated if an error is reported. Next errors will be reported: • Thermal Warning • Thermal Shutdown • Overcurrent • Open Coil • Charge Pump Failure • All errors except a Thermal Warning will disable the H−bridge drivers to protect the motor driver (<MOTEN> = ‘0’). To reset the error one needs to read out the error. Only when all errors are reset it will be possible to re−enable the motor driver (<MOTEN> = ‘1’). Keep in mind that during power up a charge pump failure will be reported during the first 250us but will not be latched (see also Charge Pump Failure). During and after power up the ERRb−pin is an open drain output. One can change this to a push−pull output with SPI bit <IO_OT>. http://onsemi.com 24 AMIS−30421 POWER SUPPLY AND THERMAL CALCULATION • In Sleep Mode (<SLP> = ‘1’) the VBAT consumption is Logic Supply Regulator AMIS−30421 has an on−chip 3.3V low−drop regulator to supply the digital part of the chip itself, some low−voltage analog blocks and external circuitry. See Table 4 for the limitations. maximum 150 mA making Tj = Tamb. • In Normal Mode when the driver is disabled (<MOTEN> = ‘0’), the VBAT consumption is maximum 20 mA (no external load on VDD−pin). The junction temperature can be calculated as next: Over− and Undervoltage T J + T A ) ǒV BAT AMIS−30421 has undervoltage detection. If VBB drops below VBBUL, the drivers are disabled. To be able to enable the drivers again the VBB voltage needs to rise above VBBUH. Overvoltage detection is also present. If the voltage rises above VBBOH the drivers are disabled. The voltage needs to drop below VBBOL to be able to enable the driver again. See also Figure 5. I BAT Rth JAǓ For an 18 V application operating at an ambient temperature of 125°C this would give: T J + 125° C ) ǒ18 V 20 mA 30° CńWǓ T J + 135.8° C • In Normal Mode with the driver enabled (<MOTEN> = ‘1’) the gate charge current needs to be included in the calculations. Start−Up Behavior Figure 4 gives the start−up of AMIS−30421. After VBB is applied and after a certain power up time (tPU), the internal voltage regulator VDD will start−up. When VDD gets above VDDH, the internal POR will be released and the digital will start−up. The WDb−pin will be kept low for an additional 100ms (tPOR). After the WDb−pin is deactivated and after a time tDSPI, SPI communication can be initiated. I BAT + 20 mA ) ǒ6 V REGH C ISS f PWMǓ For an 18 V application driving external MOSFET’s with an input capacitance of 1 nF this would result in: I BAT + 20 mA ) ǒ6 12.8 V 1 nF 30 kHzǓ I BAT + 22.3 mA Operating at 125°C ambient temperature this result in a junction temperature of: T J + 125° C ) ǒ18 V 22.3 mA 30° CńWǓ Junction Temperature Calculation To calculate the junction temperature of AMIS−30421 the thermal resistance junction−to−ambient must be known. When only a PCB heat sink is used, a typical value is 30°C/W (see Table 4). There are three modes the junction temperature can be calculated for. T J + 137° C http://onsemi.com 25 AMIS−30421 SPI INTERFACE The serial peripheral interface (SPI) allows an external microcontroller (Master) to communicate with AMIS−30421. The implemented SPI block is designed to interface directly with numerous microcontrollers from several manufacturers. AMIS−30421 acts always as a Slave and can’t initiate any transmission. The operation of the device is configured and controlled by means of SPI registers which are observable for read and/or write from the Master. DO signal is the output from the Slave (AMIS−30421), and DI signal is the output from the Master. A chip select line (CSb) allows individual selection of a Slave SPI device in a multiple−slave system. The CSb line is active low. If AMIS−30421 is not selected, DO is in HiZ and does not interfere with SPI bus activity. The output type of DO can be set in SPI (<IO_OT>). Since AMIS−30421 operates as a Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks data out on the falling edge and samples data in on rising edge of clock. The Master SPI port must be configured in MODE 0 too, to match this operation. The diagram below is both a Master and a Slave timing diagram since CLK, DO and DI pins are directly connected between the Master and the Slave. SPI Transfer Format and Pin Signals During a SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (CLK) synchronizes shifting and sampling of the information on the two serial data lines (DO and DI). 8 7 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB CS ÏÏÏÏ ÏÏÏÏ CLK DI DO MSB Figure 24. Timing Diagram of a SPI Transfer Transfer Packet Two command types can be distinguished in the communication between master and AMIS−30421: • CMD2 = ‘0’: READ from SPI Register with address ADDR[4:0] • CMD2 = ‘1’: WRITE to SPI Register with address ADDR[4:0] Serial data transfer is assumed to follow MSB first rule. The transfer packet contains one or more bytes. Byte 1 contains the Command and the SPI Register Address and indicates to AMIS−30421 the chosen type of operation and addressed register. Byte 2 contains data, or sent from the Master in a WRITE operation, or received from AMIS−30421 in a READ operation. BYTE1 BYTE2 Command and SPI Register Address Data MSB CMD2 LSB CMD1 Command CMD0 ADDR4 ÏÏÏ ÏÏÏ ÏÏ ÏÏ ADDR3 ADDR2 ADDR1 MSB ADDR0 D7 LSB D6 D5 D4 D3 D2 D1 D0 SPI Register Address Figure 25. SPI Transfer Packet READ Operation the same time the data shifted in from DI (Master) should be interpreted as the following successive command or dummy data. Status Register 0, 1 and 2 (see SPI Registers) contain 7 data bits and a parity check bit. The most significant bit (D7) represents a parity of D[6:0]. If the number of logical ones in D[6:0] is odd, the parity bit D7 equals ‘1’. If the number of logical ones in D[6:0] is even then the parity bit D7 equals If the Master wants to read data from a Status or Control Register, it initiates the communication by sending a READ command. This READ command contains the address of the SPI register to be read out. At the falling edge of the eight clock pulse the data−out shift register is updated with the content of the corresponding internal SPI register. In the next 8−bit clock pulse train this data is shifted out via DO pin. At http://onsemi.com 26 AMIS−30421 root cause of the problem can be determined by reading out the Status Registers. However, if the error occurs at the moment CSb is low, one first needs to pull CSb high to update the Status Registers properly. Only then the Status Registers can be read out to determine the error. For this reason it is also recommended to keep CSb high when the SPI bus is idle. ‘0’. This simple mechanism protects against noise and increases the consistency of the transmitted data. If a parity check error occurs it is recommended to initiate an additional READ command to obtain the status again. The CSb−pin is active low and may remain low between successive READ commands as illustrated in Figure 28. There is one exception. In case an error condition occurs the CS ÏÏÏ ÏÏ ÏÏ ÏÏ CLK DI DO 0 Old Data or Not Valid 0 0 Addr[4] Addr[3] Addr[2] Addr[1] Addr[0] Command or Dummy Command or Dummy Command or Dummy Command or Dummy Command or Dummy Command or Dummy Command or Dummy Command or Dummy D[4 ] from Addr D[3] from Addr D[2 ] from Addr D[1] from Addr D[0 ] from Addr Next command or dummy data Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid D[7] from Addr D[6 ] from Addr D[5] from Addr Data from previous command or not valid after POR . Figure 26. Single READ Operation Where Data from SPI Register is Read by the Master WRITE Operation less bits are transmitted the complete transfer packet is ignored. A WRITE command executed for a read−only register (e.g. Status Registers) will not affect the addressed register and the device operation. AMIS−30421 responds on every incoming byte by shifting out via DO the data stored in the last received address. Because after a power−on−reset the initial address is unknown the data shifted out via DO is not valid. If the Master wants to write data to a Control Register it initiates the communication by sending a WRITE command. This contains the address of the SPI register to write to. The command is followed with a data byte. This incoming data will be stored in the corresponding Control Register after CSb goes from low to high. It is important that the writing action to the Control Register is exactly 16 bits long and that CSb goes high after these 16 bits. If more or The new data is written into the corresponding internal register at the rising edge of CS. CS ÏÏÏ ÏÏÏ CLK DI DO 1 Old Data or Not Valid ÏÏ ÏÏ ÏÏ 0 0 Addr[4] Addr[3] Addr[2] Addr[1] Addr[0] D[7] from Addr D[6 ] from Addr D[5] from Addr D[4 ] from Addr D[3] from Addr D[2 ] from Addr D[1] from Addr D[0 ] from Addr Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data or Not Valid Old Data From Addr Old Data From Addr Old Data From Addr Old Data From Addr Old Data From Addr Old Data From Addr Old Data From Addr Old Data From Addr Data from previous command or not valid after POR . Old data from Addr Figure 27. Single WRITE Operation Where Data from the Master is Written in SPI Register Examples of READ and WRITE Operations followed by writing a control byte in Control Register at Addr3. Note that during the WRITE command the old data of the pointed register is returned at the moment the new data is shifted in. In the following examples successive READ and/or WRITE operations are combined. In Figure 28 the Master first reads the status from Register at Addr1 and at Addr2 New data is written into Register with Addr3 at rising edge of CSb CS DI Read Data from Addr1 Read Data from Addr2 Write Data to Addr3 New Data to Addr 3 DO Old Data or Not Valid Data from Addr1 Data from Addr2 Old Data from Addr3 Data from previous command or not valid after POR Figure 28. 2 Successive READ Commands Followed by a WRITE Command After a WRITE operation the Master could initiate a READ command in order to verify the data correctly written as illustrated in Figure 29. During reception of the READ command the old data is returned for a second time. Only after receiving the READ command the new data is transmitted. This rule also applies when the master device http://onsemi.com 27 AMIS−30421 wants to initiate an SPI transfer to read the Status Registers. Because the internal system clock updates the Status Registers only when CSb line is high, the first read out byte might represent old status information (Figure 30). New data is written into Register with Addr4 at rising edge of CSb CS DI Write Data to Addr4 New Data for Addr4 Read Data from Addr4 Command or Dummy DO Old Data or Not Valid Old Data from Addr4 Old Data From Addr4 New Data From Addr4 Data from previous command or not valid after POR Figure 29. WRITE Operation Followed by a READ operation to verify CS DI Read from 0x04 Read from 0x05 Read from 0x06 Command or Dummy DO Old Data or Not Valid Data from 0x04 Data from 0x05 Data from 0x06 Data from previous command or not valid after POR Figure 30. 3 READ Operations in a Row Bad Examples of READ and WRITE Operations be determined. A second problem with Figure 33 is that the data written to Addr9 will not be stored because CSb was not toggled after the write operation. Figure 34 gives the correct way of reading out errors. When the error is detected (toggling of ERRb−pin), CSb is made high to make sure the Status Registers are updated. Then the Status Registers are read out. Notice that ERRb toggles after Status Register 1 is read out (Addr 0x05). This indicates that the error was an overcurrent in the X−coil, a charge pump failure or an open X−coil. Also notice that because CSb is made high after the write operation, the write operation will now be done correctly. The following example demonstrates a bad WRITE operation. After a WRITE operation a read operation is done before CSb is made high. The data will not be written in the Register. Figure 32 demonstrates how it should be done (see also Figure 29). The second example (Figure 33) demonstrates an incorrect way of reading errors. After a WRITE operation the ERRb−pin toggles indication an error. Without toggling CSb the 3 Status Registers are read out to determine the error. Because CSb was not high after the error was detected, the Status Registers will not be updated and the error can not New data is NOT written into Register because WRITE operation did not ended with CSb going high! CS DI Write Data to Addr8 New Data for Addr8 Read Data from Addr8 Command or Dummy Read Data from Addr8 Command or Dummy DO Old Data or Not Valid Old Data from Addr8 Old Data From Addr8 Old Data from Addr8 Old Data From Addr8 Old Data from Addr8 Data was not written in Addr8 because WRITE operation did not ended with CSb going high! Data from previous command or not valid after POR Figure 31. Bad Example of Write Operation http://onsemi.com 28 AMIS−30421 CS DI Write Data to Addr8 New Data for Addr8 Read Data from Addr8 Command or Dummy DO Old Data or Not Valid Old Data from Addr8 Old Data From Addr8 New Data from Addr8 Data from previous command or not valid after POR Figure 32. Good Write Operation ERR CS DI Write Data to Addr9 New Data for Addr9 Read Data from 0x04 Read Data from 0x05 Read Data from 0x06 New Command or Dummy DO Old Data or Not Valid Old Data from Addr9 Old Data From Addr9 Old Data from 0x04 Old Data from 0x05 Old Data from 0x06 Data from previous command or not valid after POR Figure 33. Bad Example of Error Read Out ERR CS Making CSb high will update the Status Registers DI Write Data to Addr9 New Data for Addr9 Read Data from 0x04 Read Data from 0x05 Read Data from 0x06 New Command or Dummy DO Old Data or Not Valid Old Data from Addr9 Old Data From Addr9 New Data from 0x04 New Data from 0x05 New Data from 0x06 Data from previous command or not valid after POR Figure 34. Correct Read Out of Error SPI Register Description Below table gives an overview of all SPI Registers that can be used. Table 8. SPI REGISTER OVERVIEW Address Access Abbreviation Watchdog Register SPI Register 0x00 R/W WR Control Register 0 0x01 R/W CR0 Control Register 1 0x02 R/W CR1 Control Register 2 0x03 R/W CR2 Status Register 0 0x04 R SR0 Status Register 1 0x05 R SR1 Status Register 2 0x06 R SR2 Status Register 3 0x07 R SR3 Predriver Register 0 0x09 R/W PDRV0 http://onsemi.com 29 AMIS−30421 Table 8. SPI REGISTER OVERVIEW Address Access Abbreviation Predriver Register 1 SPI Register 0x0A R/W PDRV1 Predriver Register 2 0x0B R/W PDRV2 Predriver Register 3 0x0C R/W PDRV3 Predriver Register 4 0x0D R/W PDRV4 Predriver Register 5 0x0E R/W PDRV5 Predriver Register 6 0x0F R/W PDRV6 Predriver Register 7 0x10 R/W PDRV7 Where: R/W = read and write access, R = read access only Watchdog Register (WR) The Watchdog Register is located at address 0x00 and can be used to enable the watchdog and set the watchdog time−out. It can also be used to set the short circuit and open coil detection time−out. Table 9. WATCHDOG REGISTER Watchdog Register (WR) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 1 0 0 Data WDEN Access 0x00 WDT[3:0] OPEN_COIL[1:0] − Table 10. WATCHDOG REGISTER PARAMETERS Parameter WDEN WDT[3:0] OPEN_COIL[1:0] Value Value 0 Disable 1 Enable 0000 32 ms 0001 64 ms 0010 96 ms 0011 128 ms 0100 160 ms 0101 192 ms 0110 224 ms 0111 256 ms 1000 288 ms 1001 320 ms 1010 352 ms 1011 384 ms 1100 416 ms 1101 448 ms 1110 480 ms 1111 512 ms 00 2.56 ms 01 0.32 ms 10 20.48 ms 11 163.84 ms Description Info Enables the watchdog p24 Defines the watchdog time−out period. The watchdog needs to be re−enabled (WDEN) within this time or WDb−pin is activated for tPOR. p24 Defines the open coil detection time−out. If an open coil is detected for a time longer than OpenTimeOut[1:0], an open coil (OPEN_X and/or OPEN_Y) will be reported. Note: Short circuit could trigger open coil detection. p23 Remark: Bit 0 of Watchdog Register should always be ‘0’ (zero)! http://onsemi.com 30 AMIS−30421 Control Register 0 (CR0) Control Register 0 is located at address 0x01 and is used to set the maximum coil current and stepping mode. It’s also used to set the “coil current zero crossing” duration. Table 11. CONTROL REGISTER 0 Control Register 0 (CR0) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0x01 SM[2:0] Data MIN_SLA_TIME[1:0] CUR[2:0] Table 12. CONTROL REGISTER 0 PARAMETERS Parameter SM[2:0] MIN_SLA_TIME[1:0] CUR[2:0] Value Value 000 64th Description 001 32nd 010 16th 011 8th 100 4th 101 Half step compensated 110 Half step uncompensated 111 Full Step 00 40 ms 01 120 ms 10 200 ms 11 360 ms 000 100 mV 001 135 mV 010 200 mV 011 270 mV 100 335 mV 101 400 mV 110 500 mV 111 600 mV Info Defines the 8 stepping modes for the PWM regulator. p19 Defines the minimum “coil current zero crossing” duration. Remark: when NXT frequency gets above PWM frequency (fPWM), MIN_SLA_TIME could be 40us longer. p20 Defines the maximum voltage over the coil current sense resistor which defines the maximum coil current. The maximum coil current is calculated as next: Icoil = CUR[2:0] / Rsense p20 Control Register 1 (CR1) Control Register 1 is located at address 0x02 and can used to set the direction, NXT−pin polarity, output configuration of WDb−, ERRb− and DO−pin and to enable PWM jitter. It can also be used to set an additional delay between switching off and on MOSFET’s of one half H−bridge (to prevent a short circuit). Table 13. CONTROL REGISTER 1 Control Register 1 (CR1) Address 0x02 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 1 0 0 0 1 Data DIRCTRL NXTP − IO_OT − PWMJ http://onsemi.com 31 NO_CROSS[1:0] AMIS−30421 Table 14. CONTROL REGISTER 1 PARAMETERS Parameter Value Value 0 CW 1 CCW 0 Positive Edge 1 Negative Edge Description DIRCTRL NXTP IO_OT PWMJ NO_CROSS[1:0] 0 Push Pull 1 Open Drain 0 Disabled 1 Enabled 00 0 ns 01 250 ns 10 500 ns 11 1000 ns Info Defines the direction of rotation. Remark: CW and CCW is relative. Direction of rotation will be defined by the status of the DIR−pin and connection of the stepper motor! p19 Defines the active edge on the NXT−pin. p19 Defines the output type of WDb−, ERRb− and DO−pin p24 Enables or disables PWM jitter p15 Defines the time between switching off one MOSFET and switching on the other MOSFET of the same half H−bridge (= tnocross). p13 Remark: Bit 3 and bit 5 of Control Register 1 should always be ‘0’ (zero)! Control Register 2 (CR2) Control Register 2 is located at address 0x03 and can be used to enable the motor driver and to put the motor driver in sleep mode. It also has some parameters that can be used to set the SLA. Table 15. CONTROL REGISTER 2 Control Register 2 (CR2) Address Access 0x03 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 Reset 0 0 0 0 Data MOTEN SLP − SLAT SLAG[2:0] 0 SLA_OFFS Table 16. CONTROL REGISTER 2 PARAMETERS Parameter MOTEN SLP SLAT SLAG[2:0] Value Value Description Info 0 Disabled 1 Enabled Enables the PWM regulator. Remark: the regulator is automatically disabled if one of the bits in Status Register 1 or 2 is set. p19 0 Normal Mode 1 Sleep Mode Enables the sleep mode (power down mode) p22 0 Not Transparent 1 Transparent Defines the type of SLA sampling. p20 000 1 001 0.5 010 0.25 011 0.125 100 0.0625 Defines the motor terminal voltage division factor for the SLA−pin. p20 101 0.0625 110 0.0625 111 0.0625 http://onsemi.com 32 AMIS−30421 Table 16. CONTROL REGISTER 2 PARAMETERS Parameter Value Value 0 No additional offset 1 Additional offset of 0.6 V SLA_OFFS Description Info To enable an additional offset on the SLA−pin of 0.6V. p20 Remark: Bit 5 of Control Register 2 should always be ‘0’ (zero)! Status Register 0 (SR0) Status Register 0 is located at address 0x04 and can only be read. Status Register 0 is a non−latched register meaning that the value of the register can change without the need of reading out the register. The register can be used to retrieve the temperature range or to verify a watchdog event. Notice that bit 7 is the parity bit (see READ operation p26). Table 17. STATUS REGISTER 0 Status Register 0 (SR0) Address 0x04 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R R R R R R R R Reset 0 0 0 0 0 1 0 0 Data PAR WD − − − − TR[1:0] Table 18. STATUS REGISTER 0 PARAMETERS Parameter TR[1:0] Value Value Description 00 −40°C to 15°C 01 15°C to 72°C 10 73°C to 150°C 11 TSD = 0: 150°C to 170°C TSD = 1: >170°C 0 No watchdog event Motor driver thermal range. Remark: TR[1:0] = 11 and TSD = 0 => Thermal Warning TR[1:0] = 11 and TSD = 1 => Thermal Shutdown TSD is located in Status Register 2 p23 If WDEN = 1 and watchdog not acknowledged before the Watchdog Time−out (WDT[3:0]), WDb−pin will be pulled low for 100ms to reset an external microcontroller and WD bit will be set to ‘1’ to indicate this event. The external microcontroller can use this bit to verify a cold (WD = 0) or warm boot (WD = 1). WD 1 Info Watchdog event occurred p24 Status Register 1 (SR1) Status Register 1 is located at address 0x05 and can only be read. Status Register 1 is a latched register. If an error occurs the bit will be set and can only be cleared by reading out this bit1. The register is used to report an overcurrent or open coil in the X−coil, or to report a charge pump failure. Notice that bit 7 is the parity bit (see READ operation p26). Table 19. STATUS REGISTER 1 Status Register 1 (SR1) Address 0x05 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Data PAR OVCXPT OVCXPB OVCXNT OVCXNB CPFAIL OPEN_X − 1. In Sleep mode the register can be read out but will not be cleared! http://onsemi.com 33 AMIS−30421 Table 20. STATUS REGISTER 1 PARAMETERS Parameter Value Value 0 No overcurrent 1 Overcurrent 0 No overcurrent 1 Overcurrent 0 No overcurrent 1 Overcurrent 0 No overcurrent 1 Overcurrent 0 No charge pump failure 1 Charge pump failure 0 No open coil detected 1 Open coil detected OVCXPT OVCXPB OVCXNT OVCXNB CPFAIL OPEN_X Description Info Overcurrent detection in top transistor XP−terminal p23 Overcurrent detection in bottom transistor XP−terminal p23 Overcurrent detection in top transistor XN−terminal p23 Overcurrent detection in bottom transistor XN−terminal p23 Charge pump failure detection p23 Open coil detection for X−coil Note: a short circuit could trigger an open coil p23 Status Register 2 (SR2) Status Register 2 is located at address 0x06 and can only be read. Status Register 2 is a latched register. If an error occurs the bit will be set and can only be cleared by reading out this bit2. The register is used to report an overcurrent or open coil in the Y−coil, or to report a thermal shutdown. Notice that bit 7 is the parity bit (see READ operation p26). Table 21. STATUS REGISTER 2 Status Register 2 (SR2) Address 0x06 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Data PAR OVCYPT OVCYPB OVCYNT OVCYNB TSD OPEN_Y − Table 22. STATUS REGISTER 2 PARAMETERS Parameter OVCYPT OVCYPB OVCYNT OVCYNB TSD OPEN_Y Value Value Description 0 No overcurrent 1 Overcurrent 0 No overcurrent 1 Overcurrent 0 No overcurrent 1 Overcurrent 0 No overcurrent 1 Overcurrent 0 No thermal shutdown 1 Thermal shutdown 0 No open coil detected 1 Open coil detected Info Overcurrent detection in top transistor YP−terminal p23 Overcurrent detection in bottom transistor YP−terminal p23 Overcurrent detection in top transistor YN−terminal p23 Overcurrent detection in bottom transistor YN−terminal p23 Thermal Shutdown detection p23 Open coil detection for X−coil Note: a short circuit could trigger an open coil p23 2. In Sleep mode the register can be read out but will not be cleared! http://onsemi.com 34 AMIS−30421 Status Register 3 (SR3) Status Register 3 is located at address 0x07 and can only be read. Status Register 3 contains the microstepping position and can be used to retrieve the position in the translator table (see Table 7). It is a non−latched register meaning that the microstepping position can be updated by the motor driver at any moment. Status Register 3 does not contain a parity bit. Table 23. STATUS REGISTER 3 Status Register 3 (SR3) Address 0x07 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 MSP[7:0] Data Table 24. STATUS REGISTER 3 PARAMETERS Parameter Value Value Description MSP[7:0] xxxx xxxx Microstepping position Info Indicates the position within the translator table p19 Predriver Register 0 (PDRV0) Predriver Register 0 is located at address 0x09 and can be used to set the current source for the gate charge of the external top MOSFET’s during t1 (see Figure 11). Table 25. PREDRIVER REGISTER 0 Predriver Register 0 (PDRV0) Address 0x09 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 0 1 0 0 1 1 TOP_ION1[6:3] Data − TOP_ION1[2:0] Table 26. PREDRIVER REGISTER 0 PARAMETERS Parameter Value TOP_ION1[6:3] xxxx TOP_ION1[2:0] xxx Value Description Info Current source value Defines the current source for the external top MOSFET’s during t1. Current source can be calculated as next: 1 mA + (PDRV0[7:4] x 2 mA) + 0.25 mA + (PDRV0[2:0] x 0.25 mA) p13 Predriver Register 1 (PDRV1) Predriver Register 1 is located at address 0x0A and can be used to set the current source for the gate charge of the external top MOSFET’s during t2 (see Figure 11). Table 27. PREDRIVER REGISTER 1 Predriver Register 1 (PDRV1) Address 0x0A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 1 1 Data TOP_ION2[6:3] − http://onsemi.com 35 TOP_ION2[2:0] AMIS−30421 Table 28. PREDRIVER REGISTER 1 PARAMETERS Parameter Value TOP_ION2[6:3] xxxx TOP_ION2[2:0] xxx Value Description Current source value Info Defines the current source for the external top MOSFET’s during t2. Current source can be calculated as next: 1 mA + (PDRV1[7:4] x 2 mA) + 0.25 mA + (PDRV1[2:0] x 0.25 mA) p13 Predriver Register 2 (PDRV2) Predriver Register 2 is located at address 0x0B and can be used to set the current source for the gate charge of the external bottom MOSFET’s during t1 (see Figure 11). Table 29. PREDRIVER REGISTER 2 Predriver Register 2 (PDRV2) Address 0x0B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 0 1 0 0 1 1 BOT_ION1[6:3] Data − BOT_ION1[2:0] Table 30. PREDRIVER REGISTER 2 PARAMETERS Parameter Value BOT_ION1[6:3] xxxx BOT_ION1[2:0] xxx Value Description Current source value Info Defines the current source for the external bottom MOSFET’s during t1. Current source can be calculated as next: 1 mA + (PDRV2[7:4] x 2 mA) + 0.25 mA + (PDRV2[2:0] x 0.25 mA) p13 Predriver Register 3 (PDRV3) Predriver Register 3 is located at address 0x0C and can be used to set the current source for the gate charge of the external bottom MOSFET’s during t2 (see Figure 11). Table 31. PREDRIVER REGISTER 3 Predriver Register 3 (PDRV3) Address 0x0C Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 1 1 BOT_ION2[6:3] Data − BOT_ION2[2:0] Table 32. PREDRIVER REGISTER 3 PARAMETERS Parameter Value BOT_ION2[6:3] xxxx BOT_ION2[2:0] xxx Value Description Info Current source value Defines the current source for the external bottom MOSFET’s during t2. Current source can be calculated as next: 1 mA + (PDRV3[7:4] x 2 mA) + 0.25 mA + (PDRV3[2:0] x 0.25 mA) p13 http://onsemi.com 36 AMIS−30421 Predriver Register 4 (PDRV4) Predriver Register 4 is located at address 0x0D and can be used to set the current source for the gate discharge of the external MOSFET’s (see Figure 11). Table 33. PREDRIVER REGISTER 4 Predriver Register 4 (PDRV4) Address 0x0D Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 0 0 0 1 0 0 TOP_IOFF[3:0] Data BOT_IOFF[3:0] Table 34. PREDRIVER REGISTER 4 PARAMETERS Parameter Value Value Description Info TOP_IOFF[3:0] xxxx Current source value Defines the current source for the external top MOSFET’s during toff. Current source can be calculated as next: 10.5 mA + (PDRV4[7:4] x 7 mA) p13 BOT_IOFF[3 :0] xxxx Current source value Defines the current source for the external bottom MOSFET’s during toff. Current source can be calculated as next: 10.5 mA + (PDRV4[3:0] x 7 mA) p13 Predriver Register 5 (PDRV5) Predriver Register 5 is located at address 0x0E and can be used to set t2 (see Figure 11). Table 35. PREDRIVER REGISTER 5 Predriver Register 5 (PDRV5) Address 0x0E Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 0 0 0 1 0 0 Data − TOP_t2[2:0] − BOT_t2[2:0] Table 36. PREDRIVER REGISTER 5 PARAMETERS Parameter TOP_t2[2:0] Value Value 000 1.25 ms 001 1.75 ms 010 2.25 ms 011 2.75 ms 100 3.25 ms 101 3.75 ms 110 4.25 ms 111 4.75 ms Description Defines the switch on duration t2 for the external top MOSFET’s. http://onsemi.com 37 Info p13 AMIS−30421 Table 36. PREDRIVER REGISTER 5 PARAMETERS Parameter BOT_t2[2 :0] Value Value 000 1.25 ms 001 1.75 ms 010 2.25 ms 011 2.75 ms 100 3.25 ms 101 3.75 ms 110 4.25 ms 111 4.75 ms Description Info Defines the switch on duration t2 for the external bottom MOSFET’s. p13 Predriver Register 6 (PDRV6) Predriver Register 6 is located at address 0x0F and can be used to set toff (see Figure 11). Table 37. PREDRIVER REGISTER 6 Predriver Register 6 (PDRV6) Address 0x0F Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 0 0 0 1 0 0 Data − TOP_toff[2:0] − BOT_toff[2:0] Table 38. PREDRIVER REGISTER 6 PARAMETERS Parameter TOP_toff[2:0] BOT_toff[2 :0] Value Value 000 1.25 ms 001 1.75 ms 010 2.25 ms 011 2.75 ms 100 3.25 ms 101 3.75 ms 110 4.25 ms 111 4.75 ms 000 1.25 ms 001 1.75 ms 010 2.25 ms 011 2.75 ms 100 3.25 ms 101 3.75 ms 110 4.25 ms 111 4.75 ms Description Info Defines the switch off duration (toff) for the external top MOSFET’s. p13 Defines the switch off duration (toff) for the external bottom MOSFET’s. p13 http://onsemi.com 38 AMIS−30421 Predriver Register 7 (PDRV7) Predriver Register 7 is located at address 0x10 and can be used to set t1 (see Figure 11). Table 39. PREDRIVER REGISTER 7 Predriver Register 7 (PDRV7) Address 0x10 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 1 0 0 0 1 0 Data − TOP_t1[2:0] − BOT_t1[2:0] Table 40. PREDRIVER REGISTER 7 PARAMETERS Parameter TOP_t1[2:0] BOT_t1[2 :0] Value Value 000 375 ns 001 500 ns 010 625 ns 011 750 ns 100 875 ns 101 1000 ns 110 1125 ns 111 1250 ns 000 375 ns 001 500 ns 010 625 ns 011 750 ns 100 875 ns 101 1000 ns 110 1125 ns 111 1250 ns Description Info Defines the switch on duration t1 for the external top MOSFET’s. p13 Defines the switch on duration t1 for the external bottom MOSFET’s. p13 http://onsemi.com 39 AMIS−30421 PACKAGE THERMAL CHARACTERISTICS 34 35 36 37 38 39 40 41 42 43 44 The major thermal resistances of the device are the Rth from the junction to the ambient (Rthja) and the overall Rth from the junction to exposed pad (Rthjp). In Table 4 one can find the values for the Rthja and Rthjp, simulated according to JESD−51. The Rthja for 2S2P is simulated conform JEDEC JESD−51 as follows: • A 4−layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used • Board thickness is 1,46mm (FR4 PCB material) • The 2 signal layers: 70 um thick copper with an area of 5500 mm2 copper and 20% conductivity • The 2 power internal planes: 36 mm thick copper with an area of 5500 mm2 copper and 90% conductivity The Rthja for 1S0P is simulated conform to JEDEC JESD−51 as follows: • A 1−layer printed circuit board with only 1 layer • Board thickness is 1.46 mm (FR4 PCB material) • The layer has a thickness of 70 mm copper with an area of 5500 mm2 copper and 20% conductivity 34 35 36 37 38 39 40 41 42 43 44 The AMIS−30421 is available in a NQFP44 package. For cooling optimizations, the NQFP has an exposed thermal pad which has to be soldered to the PCB ground plane. The ground plane needs thermal vias to conduct the heat to the bottom layer. Figure 35 gives an example of good heat transfer. The exposed thermal pad is soldered directly on the top ground layer (left picture of Figure 35). It’s advised to make the top ground layer as large as possible (see arrows Figure 35). To improve the heat transfer even more, the exposed thermal pad is connected to a bottom ground layer by using thermal vias (see right picture of Figure 35). It’s advised to make this bottom ground layer as large as possible and with as less as possible interruptions. For precise thermal cooling calculations the major thermal resistances of the device are given (Table 4). The thermal media to which the power of the devices has to be given are: • Static environmental air (via the case) • PCB board copper area (via the exposed pad) 26 9 25 9 25 10 24 10 24 11 23 11 23 22 8 21 26 20 27 8 19 7 18 27 17 28 7 16 6 15 28 14 29 6 13 5 12 29 22 30 5 21 4 20 30 19 31 4 18 3 17 31 16 32 3 15 33 2 14 1 32 13 33 2 12 1 Figure 35. PCB Ground Plane Layout Condition (left picture displays the top ground layer, right picture displays the bottom ground layer) ORDERING INFORMATION Part No. AMIS30421C4211G Peak Current Temperature Range Package Shipping† NA −40°C to +170°C NQFP−44 (7 x 7 mm) (Pb−Free) Units / Tube AMIS30421C4211RG Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 40 AMIS−30421 PACKAGE DIMENSIONS QFN44 7x7, 0.5P CASE 485BY ISSUE O ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ D PIN 1 REFERENCE L A B L1 DETAIL A DIM A A1 A3 b D D2 E E2 e K L L1 ÉÉÉ ÉÉÉ EXPOSED Cu TOP VIEW MOLD CMPD DETAIL B ALTERNATE CONSTRUCTION (A3) DETAIL B 0.05 C NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO THE PLATED TERMINAL AND IS MEASURED ABETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. ALTERNATE CONSTRUCTIONS E 0.15 C 0.15 C L A 0.08 C A1 NOTE 4 C SIDE VIEW SEATING PLANE MILLIMETERS MIN MAX 0.80 0.90 −−− 0.05 0.20 REF 0.20 0.30 7.00 BSC 4.60 4.80 7.00 BSC 4.60 4.80 0.50 BSC 0.20 −−− 0.45 0.65 −−− 0.15 SOLDERING FOOTPRINT* 2X 0.10 M D2 DETAIL A 1 K 12 0.10 23 11 44X 0.82 4.90 C A B M C A B 2X 7.30 E2 1 44X L 0.50 PITCH 33 44 e 34 44X BOTTOM VIEW 44X 0.30 DIMENSIONS: MILLIMETERS b 0.10 M C A B 0.05 M C NOTE 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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