ICS840002I-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER www.IDT.com GENERAL DESCRIPTION FEATURES The ICS840002I-01 is a 2 output LVCMOS/LVTTL Synthesizer optimized to generate Ethernet HiPerClockS™ reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from IDT. Using a 25MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL1:0): 156.25MHz, 125MHz, and 62.5MHz. The ICS840002I-01 uses IDT’s 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical random rms phase jitter, easily meeting Ethernet jitter requirements. The ICS840002I01 is packaged in a small 16-pin TSSOP package. • Two LVCMOS/LVTTL outputs @ 3.3V, 17Ω typical output impedance • Selectable crystal oscillator interface or LVCMOS single-ended input • Supports the following output frequencies: 156.25MHz, 125MHz and 62.5MHz • Output frequency range: 56MHz - 175MHz • VCO range: 560MHz - 700MHz • Output skew: 12ps (maximum) • RMS phase jitter at 156.25MHz (1.875MHz - 20MHz): 0.47ps (typical) Offset Noise Power 100Hz ............... -97.4 dBc/Hz 1kHz ............. -120.2 dBc/Hz 10kHz ............. -127.6 dBc/Hz 100kHz ............. -126.1 dBc/Hz ICS • Power supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free RoHS (6) packages FREQUENCY SELECT FUNCTION TABLE Inputs F_SEL1 F_SEL0 0 M Divider Value N Divider Value Output Frequency (25MHz Ref.) 25 4 156.25 0 0 1 25 5 125 1 0 25 10 62.5 1 1 25 5 125 BLOCK DIAGRAM OE PIN ASSIGNMENT Pullup F_SEL0 nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA VDD 2 F_SEL1:0 Pullup:Pullup nPLL_SEL Pulldown nXTAL_SEL XTAL_IN Pulldown 25MHz OSC F_SEL1:0 0 1 00 01 10 11 XTAL_OUT TEST_CLK Pulldown 1 Phase Detector VCO 0 N ÷4 ÷5 ÷10 ÷5 Q0 Q1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 F_SEL1 GND GND Q0 Q1 VDDO XTAL_IN XTAL_OUT ICS840002I-01 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View M = ÷25 (fixed) MR 840002AGI-01 Pulldown 1 REV. A OCTOBER 22, 2007 ICS840002I-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER www.IDT.com TABLE 1. PIN DESCRIPTIONS Number 1, 16 Name F_SEL0, F_SEL1 Type Input Description Pullup Frequency select pin. LVCMOS/LVTTL interface levels. Selects between the cr ystal or TEST_CLK inputs as the PLL reference Pulldown source. When HIGH, selects TEST_CLK. When LOW, selects XTAL inpus. LVCMOS/LVTTL interface levels. Pulldown Single-ended LVCMOS/LVTTL clock input. Output enable pin. When HIGH, the outputs are active. When LOW, the Pullup outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are Pulldown reset causing active outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, the PLL is bypassed and the output frequency = Pulldown reference clock frequency/N output divider. LVCMOS/LVTTL interface levels. Analog supply pin. 2 nXTAL_SEL Input 3 TEST_CLK Input 4 OE Input 5 MR Input 6 nPLL_SEL Input 7 VDDA Power 8 9, 10 11 VDD XTAL_OUT, XTAL_IN VDDO Power Core supply pin. Input Cr ystal oscillator interface. Power Output supply pin. 12, 13 Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 14, 15 GND Power Power supply ground. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF CPD Power Dissipation Capacitance 8 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ROUT Output Impedance 840002AGI-01 3.3V±5% 14 17 21 Ω 2.5V±5% 16 21 25 Ω www.icst.com/products/hiperclocks.html 2 REV. A OCTOBER 18, 2007 ICS840002I-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER www.IDT.com ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 89°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol VDD Parameter Core Supply Voltage VDDA Analog Supply Voltage Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 Units V 3.135 3.3 3.465 V 3.135 3.3 3.465 V 2.375 2.5 2.625 V VDDO Output Supply Voltage IDD Power Supply Current 100 mA IDDA IDDO Analog Supply Current Output Supply Current 12 5 mA mA Maximum 2.625 Units V TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol VDD Parameter Core Supply Voltage Test Conditions Minimum 2.375 Typical 2.5 VDDA Analog Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 95 mA IDDA IDDO Analog Supply Current Output Supply Current 12 5 mA mA 840002AGI-01 www.icst.com/products/hiperclocks.html 3 REV. A OCTOBER 18, 2007 ICS840002I-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER www.IDT.com TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5% OR 2.5V±5%, OR VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions V IH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current OE, F_SEL0, F_SEL1 nPLL_SEL, MR, nXTAL_SEL, TEST_CLK OE, F_SEL0, F_SEL1 nPLL_SEL, MR, nXTAL_SEL, TEST_CLK VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 Minimum Typical Maximum Units VDD = 3.3V 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V VDD = VIN = 3.465V or 2.625V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V -0.3 0.7 V 5 µA 150 µA -150 µA VDD = 3.465V or 2.625V, VIN = 0V -5 µA VDDO = 3.3V ± 5% 2.6 V VDDO = 2.5V ± 5% 1.8 V VDDO = 3.3V or 2.5V ± 5% 0.5 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Maximum Units NOTE: Characterized using an 18pF parallel resonant crystal. TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency tsk(o) Output Skew; NOTE 1, 3 tjit(Ø) RMS Phase Jitter (Random); NOTE 2 tR / tF Output Rise/Fall Time Test Conditions Minimum Typical F_SEL[1:0] = 00 140 175 MHz F_SEL[1:0] = 01 112 140 MHz F_SEL[1:0] = 10 or 11 56 70 MHz 12 ps 156.25MHz (1.875MHz - 20MHz) 0.47 ps 125MHz (1.875MHz - 20MHz) 0.57 ps 62.5MHz (1.875MHz - 20MHz) 20% to 80% 0.51 200 odc Output Duty Cycle 46 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 840002AGI-01 www.icst.com/products/hiperclocks.html 4 ps 700 ps 54 % REV. A OCTOBER 18, 2007 ICS840002I-01 www.IDT.com FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency tsk(o) Test Conditions Minimum F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] = 10 or 11 Typical Maximum Units 140 175 MHz 112 140 MHz 56 68 MHz Output Skew; NOTE 1, 3 tjit(Ø) RMS Phase Jitter (Random); NOTE 2 tR / tF Output Rise/Fall Time 12 ps 156.25MHz (1.875MHz - 20MHz) 0.47 ps 125MHz (1.875MHz - 20MHz) 0.55 ps 62.5MHz (1.875MHz - 20MHz) 0.49 20% to 80% 200 odc Output Duty Cycle 46 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. ps 700 ps 54 % TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol fOUT Parameter Output Frequency tsk(o) Output Skew; NOTE 1, 3 tjit(Ø) RMS Phase Jitter (Random); NOTE 2 tR / tF Output Rise/Fall Time Test Conditions Minimum Maximum Units F_SEL[1:0] = 00 140 Typical 175 MHz F_SEL[1:0] = 01 112 140 MHz F_SEL[1:0] = 10 or 11 56 68 MHz 12 ps 156.25MHz (1.875MHz - 20MHz) 0.49 ps 125MHz (1.875MHz - 20MHz) 0.56 ps 62.5MHz (1.875MHz - 20MHz) 0.52 ps 20% to 80% 200 odc Output Duty Cycle 46 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 840002AGI-01 www.icst.com/products/hiperclocks.html 5 700 ps 54 % REV. A OCTOBER 18, 2007 ICS840002I-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER www.IDT.com TYPICAL PHASE NOISE AT 62.5MHZ @3.3V 0 ä -10 -20 1Gb Ethernet Filter -40 62.5MHz -50 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.51ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 ä NOISE POWER dBc Hz -30 -110 -120 -130 -140 -150 -160 ä -170 -180 Phase Noise Result by adding 1Gb Ethernet Filter to raw data -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 156.25MHZ @3.3V 0 ä -10 -20 10Gb Ethernet Filter -40 156.25MHz -50 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.47ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 -110 ä NOISE POWER dBc Hz -30 -120 -130 -140 -150 ä -160 -170 Phase Noise Result by adding 10Gb Ethernet Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 840002AGI-01 www.icst.com/products/hiperclocks.html 6 REV. A OCTOBER 18, 2007 ICS840002I-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER www.IDT.com PARAMETER MEASUREMENT INFORMATION 2.05V±5% 1.25V±5% 1.65V±5% SCOPE VDD, VDDA, VDDO Qx LVCMOS SCOPE VDD, VDDA VDDO Qx LVCMOS GND GND -1.25V±5% -1.65V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 1.25V±5% Noise Power Phase Noise Plot SCOPE VDD, VDDA, VDDO Qx LVCMOS Phase Noise Mask GND Offset Frequency f1 RMS Jitter = Area Under the Masked Phase Noise Plot -1.25V±5% 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER V 80% DDO Qx 80% 2 Clock Outputs V DDO Qy f2 20% 20% tR tF 2 t sk(o) OUTPUT SKEW OUTPUT RISE/FALL TIME V DDO 2 Q0, Q1 Pulse Width t odc = PERIOD t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 840002AGI-01 www.icst.com/products/hiperclocks.html 7 REV. A OCTOBER 18, 2007 ICS840002I-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER www.IDT.com APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840002I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each VDDA. 3.3V or 2.5V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS840002I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332 ICS840002I-01 Figure 2. CRYSTAL INPUt INTERFACE 840002AGI-01 www.icst.com/products/hiperclocks.html 8 REV. A OCTOBER 18, 2007 ICS840002I-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER www.IDT.com LAYOUT GUIDELINE C2=22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. 1KΩ pullup or pulldown resistors can be used for the logic control input pins. Figure 3 shows a schematic example of the ICS840002I-01. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18 pF parallel resonant 25MHz crystal is used. The C1=22pF and Logic Control Input Examples Set Logic Input to '1' VDD RU1 1K Set Logic Input to '0' VDD R2 33 RU2 Not Install To Logic Input pins RD1 Not Install To Logic Input pins U1 RD2 1K VDD 1 2 3 4 5 6 7 8 VDDA R1 10 C3 10uF Zo = 50 Ohm VDD C4 0.01u LVCMOS FSEL0 XTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA VDD FSEL1 GND GND Q0 Q1 VDDO XTAL_IN XTAL_OUT 16 15 14 13 12 11 10 9 VDD R3 100 C6 0.1u Zo = 50 Ohm C5 0.1u ICS840002I-01 R4 100 XTAL2 If not using the crystal input, it can be left floating. For additional protection the XTAL_IN pin can be tied to ground. LVCMOS C2 22pF X1 XTAL1 Optional Termination C1 22pF Unused output can be left floating. There should no trace attached to unused output. Device characterized with all outputs terminated. FIGURE 3. ICS840002I-01 SCHEMATIC EXAMPLE 840002AGI-01 www.icst.com/products/hiperclocks.html 9 REV. A OCTOBER 18, 2007 ICS840002I-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER www.IDT.com RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 137.1°C/W 89.0°C/W 118.2°C/W 81.8°C/W 106.8°C/W 78.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS840002I-01 is: 3356 840002AGI-01 www.icst.com/products/hiperclocks.html 10 REV. A OCTOBER 18, 2007 ICS840002I-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER www.IDT.com PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 16 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 840002AGI-01 www.icst.com/products/hiperclocks.html 11 REV. A OCTOBER 18, 2007 ICS840002I-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER www.IDT.com TABLE 8. ORDERING INFORMATION Part/Order Number ICS840002AGI-01 ICS840002AGI-01T ICS840002AGI-01LF ICS840002AGI-01LFT Marking ICS840002AI01 ICS840002AI01 002AI01L 002AI01L Package 16 Lead TSSOP 16 Lead TSSOP 16 Lead "Lead-Free" TSSOP 16 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an ""LF"" suffix to the part number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS™ and FEMTOCLOCKS™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840002AGI-01 www.icst.com/products/hiperclocks.html 12 REV. A OCTOBER 18, 2007 ICS840002I-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER www.IDT.com REVISION HISTORY SHEET Rev Table Page Description of Change Date A T8 12 Ordering Information Table - Added Lead-Free par t number, marking and note. 10/18/07 840002AGI-01 www.icst.com/products/hiperclocks.html 13 REV. A OCTOBER 18, 2007