LSI LS7212 Programmable digital delay timer Datasheet

LSI/CSI
UL
®
LS7211-7212
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
(631) 271-0400 FAX (631) 271-0405
A3800
PROGRAMMABLE DIGITAL DELAY TIMER
1
18
TRIG
B
2
17
WB0
V DD (+V)
3
16
WB1
15
WB2
14
WB3
6
13
WB4
7
12
WB5
V SS (-V)
8
11
WB6
OUT
9
10
WB7
A
1
18
TRIG
B
2
17
WB0
V DD (+V)
3
16
WB1
XTLI/CLOCK
4
15
WB2
14
WB3
13
WB4
7
12
WB5
V SS (-V)
8
11
WB6
OUT
9
10
WB7
RC/CLOCK
4
RCS/CLKS
5
PSCLS
RESET
TABLE 1. MODE SELECTION
A
0
0
1
1
B
0
1
0
1
MODE
One-Shot (OS)
Delayed Operate (DO)
Delayed Release (DR)
Dual Delay (DD)
PSCLS
RESET
5
6
LS7212
XTLO
LSI
I/O DESCRIPTION:
MODE SELECT Inputs (A &B, Pins 1 & 2)
The 4 operating modes are selected by Inputs A and B
according to Table 1
A
LS7211
DESCRIPTION:
The LS7211/LS7212 are monolithic CMOS integrated circuits for generating digitally programmable delays. The delay is controlled by 8 binary weighted inputs, WB0-WB7, in
conjunction with an applied clock or oscillator frequency.
The programmed time delay manifests itself in the Delay
Output (OUT) as a function of the Operating Mode selected
by the Mode Select inputs A and B: One-Shot, Delayed
Operate, Delayed Release or Dual Delay. The time delay is
initiated by a transition of the Trigger Input (TRIG).
June 1997
PIN ASSIGNMENT - TOP VIEW
LSI
FEATURES:
• 8-bit programmable delay from nanoseconds to days
• On chip oscillator (RC or Crystal) or external clock time base
• Selectable prescaler for real time delay generation based
on 50Hz/60Hz time base or 32.768KHz watch crystal
• Four operating modes
• Reset input for delay abort
• Low quiescent and operating current
• Direct relay drive
• +4V to +18V operation (VDD-VSS)
• LS7211/LS7212 (DIP), LS7211-S/LS7212-S (SOIC)-See Figure 1
FIGURE 1
Each input has an internal pull-up resistor of about 500KΩ.
One-Shot Mode (OS)
A positive transition at the TRIG input causes OUT to
switch low without delay and starts the delay timer. At the
end of the programmed delay timeout, OUT switches high.
If a delay timeout is in progress when a positive transition
occurs at the TRIG input, the delay timer will be restarted.
A negative transition at the TRIG input has no effect.
Delayed Operate Mode (DO)
A positive transition at the TRIG input starts the delay timer. At the end of the delay timeout, OUT switches low. A
negative transition at the TRIG input causes OUT to switch
high without delay. OUT is high when TRIG is low.
7211-041700-1
Delayed Release Mode (DR)
A negative transition at the TRIG input starts the delay timer. At the end of the delay timeout, OUT switches high. A
postive transition at the TRIG input causes OUT to switch
low without delay. OUT is low when TRIG is high.
Dual Delay Mode (DD)
A positive or negative transition at the TRIG input starts
the delay timer. At the end of the delay timeout, OUT
switches to the logic state which is the inverse of the TRIG
input. If a delay timeout is in progress when a transition
occurs at the TRIG input, the delay timer is restarted.
TRIGGER Input (TRIG, Pin 18)
A transition at the TRIG input causes OUT to switch with or
without delay, depending on the selected mode. The TRIG
input to OUT transition relation is always opposite in polarity, with the exception of One-Shot mode. (See Mode
definitions above.) TRIG input has an internal pull-down resistor of about 500KΩ and is buffered by a Schmitt trigger
to provide input hysterisis.
LS7211 TIME BASE Input (RC/CLOCK, Pin 4)
For LS7211, the basic timing signal is applied at the RC/
CLOCK input. The clock can be provided from either an external source or generated by an internal oscillator by connecting an R-C network to this input.
The frequency of oscillation is given by ƒ 1/RC. Chip-tochip oscillation tolerance is ± 5% for a fixed value of RC.
The minimum resistance, R MIN = 4000Ω, VDD = + 4V
= 1200Ω, VDD = +10V
= 600Ω, VDD = +18V
The external clock mode is selected by applying a logic low
to the RCS/CLKS input (Pin 5); the internal oscillator mode
is selected by applying a high level to the RCS/CLKS input.
LS7212 TIME BASE Input (XTLI/CLOCK, Pin 4)
For LS7212, the basic timing clock is applied to the XLTI/
CLOCK input from either an external clock source or generated by an internal crystal oscillator by connecting a crystal
between XTLI/CLOCK input and the XTLO output (Pin 5).
LS7211 TIME BASE SELECT Input (RCS/CLKS, Pin 5)
For LS7211, the external clock operation at Pin 4 is selected by applying a logic low to the RCS/CLKS input. The
internal oscillator option with RC timer at Pin 4 is selected
by applying a logic high at the RCS/CLKS input. RCS/CLKS
input has an internal pull-down resistor of about 500KΩ.
LS7212 TIME BASE Output (XTLO, Pin 5)
For LS7212, when a crystal is used for generating the time
base oscillation, the crystal is connected between XTLI/
CLOCK and XTLO pins.
TIMER RESET Input (RESET, Pin 7)
When RESET input switches high, any timeout in progress
is aborted and OUT switches high without delay. With RESET high, OUT remains high. When RESET switches low
with TRIG low in any mode, OUT remains high. When RESET switches low with TRIG high in Delayed Operate and
Dual Delay modes, the delay timer is started and OUT
switches low at the end of the delay timeout. When RESET switches low with TRIG high in Delayed Release
mode, OUT switches low without delay. When RESET
switches low with TRIG high in One-Shot mode, OUT remains high. RESET input has an internal pull-down resistor
of about 500KΩ.
VSS (-V, Pin 8)
Supply voltage negative terminal or GND.
DELAY Output (OUT, Pin 9)
Except in One-Shot mode, OUT switches with or without
delay (depending on mode) in inverse relation to the logic
level of the TRIG input. In One-Shot mode, a timed low
level is produced at OUT, in response to a positive transition of the TRIG input.
WEIGHTING BIT Inputs (WB7 To WB0, Pins 10 - 17)
Inputs WB0 through WB7 are binary weighted delay bits
used to program the delay according to the following
relations:
One-Shot Mode: Pulse width = SW
ƒ
All other Modes: Delay = SW + .5
ƒ
Where:
S = Prescale factor (See Table 2)
ƒ = Time base frequency at Pin 4
W = WB0 + WB1 + ....... WB7
PRESCALER SELECT Input (PSCLS, Pin 6)
The PSCLS input is a 3-state input, which selects one of
three prescale factors according to Table 2.
The weighting factor W is calculated by substituting in the
equation above for W, the weighted values for all the WB
inputs that are at logic high. The weighted values for the
WB inputs are shown in Table 3. Each WB input has an internal pull-down resistor of about 500KΩ.
TABLE 2. PRESCALE FACTOR SELECTION
TABLE 3. BIT WEIGHTS
PSCLS Input
Logic Level
Float
Low
High
S (Prescale Factor )
LS7211
LS7212
1
1
3000
32768
3600
32768x60
Using prescale factors of 3000 and 3600, delays in units of
minutes can be produced from 50Hz and 60Hz line sources. Prescale factors of 32,768 and 32,768 x 60 can be used
to generate accurate delays in units of seconds and minutes, respectively, from a 32KHz watch crystal.
7211-102097-2
BITS
WB0
WB1
WB2
WB3
WB4
WB5
WB6
WB7
VDD (+V, Pin 3)
Supply voltage positive terminal.
VALUE
1
2
4
8
16
32
64
128
ABSOLUTE MAXIMUM RATINGS: (All voltages referenced to VSS)
SYMBOL
VALUE
DC Supply Voltage
VDD
+19
Voltage (Any Pin)
VIN
VSS-.3 to VDD+.3
Operating Temperature
TA
-20 to +85
Storage Temperature
TSTG
-65 to +150
UNIT
V
V
°C
°C
ELECTRICAL CHARACTERISTICS (Voltages referenced to Vss)
Characteristic
SYMBOL
Supply Voltage
VDD
Supply Current
IDD
4.0
10.0
18.0
Min
4.0
32
190
560
-20°C
Max
18.0
-
Min
4.0
27
160
437
+25°C
Max
18.0
-
Min
4.0
20
110
330
+85°C
Max
18.0
-
4.0
10.0
18.0
4.0
10.0
18.0
4.0
10.0
18.0
4.0
10.0
18.0
4.0
10.0
18.0
3.0
6.6
11.0
1.5
3.0
4.8
2.1
5.3
9.3
1.0
3.0
5.8
1.2
4.1
7.2
-
3.0
6.6
11.0
1.5
3.0
4.8
2.1
5.3
9.3
1.0
3.0
5.8
1.2
4.1
7.2
-
3.0
6.6
11.0
1.5
3.0
4.8
2.1
5.3
9.3
1.0
3.0
5.8
1.2
4.1
7.2
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
4.0
10.0
18.0
4.0
10.0
18.0
4.0
10.0
18.0
4.0
10.0
18.0
-
2.6
22.0
70.0
5.8
26.0
82.0
2.0
37.0
132.0
100
100
4.6
33.0
121.0
-
2.0
17.0
54.0
4.4
20.0
63.0
1.6
28.0
101.0
100
100
3.5
25.0
93.0
-
1.5
13.0
41.0
3.4
15.2
48.0
1.3
22.0
77.0
200
200
2.7
19.0
71.0
µA
µA
µA
µA
µA
µA
µA
µA
µA
nA
nA
µA
µA
µA
4.0
10.0
18.0
4.0
10.0
18.0
23.0
43.0
56.0
2.6
7.8
11.5
-
18.0
33.0
43.0
2.0
6.0
8.8
-
13.0
25.0
32.0
1.5
4.5
6.5
-
mA
mA
mA
mA
mA
mA
VDD
Unit
V
µA
µA
µA
Condition
with the clock off
Input Voltages:
Trigger Low
VTL
Trigger High
VTH
Trigger Hysteresis
All other inputs, Low
VIL
All other inputs, High
VIH
-
-
-
-
-
Input Currents:
PSCLS Low
IPL
PSCLS High
IPH
A, B Low
IML
A, B High
All other inputs, Low
IMH
IIL
All other inputs, High
IIH
Input at VSS
Input at VDD
Input at VSS
Input at VDD
Input at VSS
Input at VDD
Output Current:
OUT Sink
IOSNK
OUT Source
IOSRC
7211-070397-3
Vo = +0.5V
Vo = VDD-.5V
ELECTRICAL CHARACTERISTICS (Voltages referenced to Vss) (Con’t)
Characteristic
SYMBOL
VDD
Unit
Min
Max
Min
Max
Min
Max
4.0
10.0
18.0
4.0
10.0
18.0
4.0
10.0
18.0
-
1.3
4.0
6.0
2.3
7.0
11.0
1.2
4.0
7.0
-
1.0
3.0
4.5
1.8
5.5
8.5
0.93
3.0
5.5
-
0.76
2.3
3.4
1.3
4.0
6.5
0.7
2.3
4.2
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
4.0
10.0
18.0
23
0
0
215
80
50
-
30
0
0
280
105
65
-
40
0
0
370
140
85
-
ns
ns
ns
ns
ns
ns
Condition
Switching Characteristics (See Fig. 3)
RC Oscillator Frequency
fosc
External Clock or
Crystal Oscillator
Frequency
fext
fext
TRIG Set-Up Time
A, B Set-Up Time
WB0 - WB7 Set-Up Time
t1
t2
t3
Clock to Out Delay
t4
For prescale
factor S = 1 or 3000
or 3600
S = 32768
or
32768 X 60
CL = 50pF
+V
500K
A
1
MODE
REG
+
V
500K
B 2
EDGE
DETECT
TRIG 18
CONTROL
LOGIC
LATCH
9 OUT
BUF
500K
RESET 7
500K
CLOCK
8
LATCH/TIMER
CLOCK/RC/XTLI 4
10-17 WB7-WB0
500K (8)
MUX
OSC
PRESCALER
XTLO(LS7212)
5
5
RCS/CLKS(LS7211)
500K
+V
+V
1M
PSCLS
-V (Gnd)
3-STATE
DECODER
6
1M
FIGURE 2. LS7211/LS7212 BLOCK DIAGRAM
3 VDD
8 VSS
t0
Clock
t1
t1
TRIG
t4
t2
A = 0, B = 1, Delayed Operate
A,B
t3
Programmed Delay
t4
WB0-WB7
OUT
Immediate Release
Note 1. TRIG input is clocked in by the negative edge of external clock.
Note 2. Inputs A, B and WB0 - WB7 are sampled only at a TRIG input transition and ignored at all other times.
Note 3. OUT is switched by the positive edge of the external clock.
FIGURE 3. INPUT/OUTPUT TIMING
TRIG
F
RESET
OUT(OS)
C
OUT(DO)
OUT(DR)
D
OUT(DD)
G
A
B
H
E
A. Turn-on delay in DO and DD modes; Pulse-width in OS mode.
B. Turn-off delay in DR and DD modes.
C. Pulse-width extended by re-trigger in OS mode. No effect in DO and DD modes because TRIG switches back low
before turn-on delay has timed out.
D. Turn-off delay in DR mode.
E. Turn-on delay in DO and DD modes; pulse-width in OS mode.
F. No effect in DO, DR and DD modes because of TRIG’s switching back to opposite levels.
G. Time-outs aborted and OUT force high by RESET.
H. After the removal of RESET, OUT switches to the inverse polarity of TRIG immediately (DR) or after the timeout
(DO,DD). No effect in OS.
FIGURE 4. MODE ILLUSTRATION WITH TRIG, OUT AND RESET
470K
+V
25pF
5
LS7211
CRYSTAL
3
5
LS7212
10M
V DD
+V
4
RCS/CLKS
XTLO
4
CLOCK
XTLI
25pF
4
10K
ƒ
CLOCK
4
RC
.1µF
LS7212
LS7211
FIGURE 6.
MULTI-TIMER WITH SINGLE CRYSTAL TIME-BASE
V SS
+V
8
3
ƒ = 10 X 10
1
-6
X .1 X 10
3
V DD
= 1KHz
LS7211
FIGURE 5. RC- Oscillator Connection
1M
4
120VAC
CLOCK
200pF
V SS
8
FIGURE 7. DRIVING CLOCK INPUT FROM THE AC LINE
+V
3
V DD
*
*
8
10-17
2
1,2
3
V DD
*
*
WB0-WB7
A,B
8
10-17
2
1,2
WB0-WB7
A,B
LS7211
LS7211
18
TRIGGER
TRIG
4
ƒ
OUT
9
CLOCK
18
4
TRIG
OUT
CLOCK
Vss
8
*
Vss
8
Connect for desired delay and mode
FIGURE 8. DELAY EXTENSION BY CASCADING
7211-102297-6
9
OUT
+V
1
2
TRIGGER IN
18
4
A
V DD
B
WB0
TRIG
WB1
XTLI
WB2
3
17
1s/1m
16
2s/2m
15
4s/4m
14
25pF
ƒ
25pF
8s/8m
WB3
10M
13
470K
5
16s/16m
WB4
XTLO
12
32s/32m
WB5
+V
S1
6
WB6
PSCLS
WB7
LS7212
7
11
64s/64m
10
128s/128m
s = seconds
m = minutes
RESET
+V
8
OUTPUT
9
Vss
OUT
NOTE : Crystal Frequency, ƒ = 32,768Hz
Switch: S1 low: Delay increment = 1s; Maximum Delay = 255s
S1 high: Delay increment = 1m; Maximum Delay = 255m
FIGURE 9. PROGRAMMABLE ACCURATE REAL-TIME DELAY GENERATION
+V
3
1
V DD
A
2
17
B
WB0
WB1
WB2
4
ƒi
16
15
14
CLOCK
+V
WB3
LS7212
7
12
RESET
18
13
WB4
WB5
WB6
TRIG
11
10
9
ƒo
WB7
OUT
Vss
8
CASE 1. MODE = DO or DR; PRESCALE FACTOR, S = 1
In this setup a frequency division of the input clock, ƒi by a factor of 2 to 257, in increments of 1 can be
obtained according to the equation:
ƒo =
ƒi
W+2
where W (weighting factor) = 0 to 255
The ƒo pulse width is non-symmetrical (non-50% duty -cycle)
CASE 2. MODE = DD; PRESCALE FACTOR, S = 1
In this setup a frequency division of the input clock, ƒi by a factor of 2 to 512, in increments of 2 can be
obtained according to the equation:
ƒo =
ƒi
2(W + 1)
where W (weighting factor) = 0 to 255
The ƒo pulse widths are symmetrical with 50% duty -cycle
EXAMPLES OF CASE 1 and CASE 2 FREQUENCY DIVISIONS WITH W = 2
ƒi
ƒo
Case 1, Mode = DO;
÷4
ƒo
Case 2, Mode = DD;
÷6
FIGURE 10.
PROGRAMMABLE FREQUENCY DIVIDER
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