Cypress CY7B9945V-2AXC High speed multi-phase pll clock buffer Datasheet

RoboClock®
CY7B9945V
PRELIMINARY
High Speed Multi-phase PLL Clock Buffer
Features
Functional Description
■
500 ps max Total Timing Budget™ (TTB™) window
■
24–200 MHz input and output operation
■
Low output-output skew < 200 ps
■
10 + 1 LVTTL outputs driving 50W terminated lines
The CY7B9945V high speed multi-phase PLL clock buffer offers
user selectable control over system clock functions. This multiple
output clock driver provides the system integrator with functions
necessary to optimize the timing of high performance computer
and communication systems.
■
Dedicated feedback output
■
Phase adjustments in 625/1300 ps steps up to +10.4 ns
■
3.3V LVTTL/LVPECL, fault tolerant, and hot insertable
reference inputs
■
Multiply or divide ratios of 1–6, 8, 10, and 12
■
Individual output bank disable
■
Output high impedance option for testing purposes
■
Integrated phase locked loop (PLL) with lock indicator
■
Low cycle-cycle jitter (<100 ps peak-peak)
■
3.3V operation
■
Industrial temperature range: –40°C to +85°C
■
52-pin 1.4 mm TQFP package
The device features a guaranteed maximum TTB window specifying all occurrences of output clocks. This includes the input
reference clock across variations in output frequency, supply
voltage, operating temperature, input edge rate, and process.
Ten configurable outputs each drive terminated transmission
lines with impedances as low as 50W while delivering minimal
and specified output skews at LVTTL levels. The outputs are
arranged in two banks of four and six outputs. These banks
enable a divide function of 1 to 12, with phase adjustments in 625
ps–1300 ps increments up to ±10.4 ns. The dedicated feedback
output enables divide-by functionality from 1 to 12 and limited
phase adjustments. However, if needed, any one of the ten
outputs can be connected to the feedback input as well as driving
other inputs.
Selectable reference input is a fault tolerant feature that enables
smooth change over to a secondary clock source when the
primary clock source is not in operation. The reference inputs
and feedback inputs are configurable to accommodate both
LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
Logic Block Diagram
FS
3
REFA+
REFALO C K
REFB+
PLL
REFBREFSEL
FBK
MODE
FBF0
3
FBDS0
3
FBDS1
3
1F0
3
1F1
3
1D S0
3
1D S1
3
1F2
3
1F3
3
D iv id e
and
Phase
S e le c t
QF
1Q 0
1Q 1
D iv id e
and
Phase
S e le c t
1Q 2
1Q 3
D IS 1
2Q 0
2F0
3
2F1
3
2D S 0
3
2D S1
3
2Q 1
D iv id e
and
Phase
S e le c t
2Q 2
2Q 3
2Q 4
2Q 5
D IS 2
Cypress Semiconductor Corporation
Document Number: 38-07336 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 21, 2007
[+] Feedback
CY7B9945V
PRELIMINARY
REFA+
VCCQ
FBK
GND
QF
VCCN
1Q1
VCCN
1Q0
GND
FBDS0
FBDS1
LOCK
Pin Configuration
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
3
37
4
36
5
35
6
34
7
33
8
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
Document Number: 38-07336 Rev. *F
REFAREFSEL
REFBREFB+
1F2
FS
G ND
1Q 2
VCCN
1Q 3
FBF0
1F0
VCCQ
DIS2
MODE
GND
GND
2Q5
VCCN
2Q4
DIS1
1F1
1F3
VCCQ
GND
CY7B9945V
1DS0
2F1
2F0
2DS1
G ND
2Q 0
VCCN
2Q 1
2Q 2
VCCN
2Q 3
G ND
1DS1
2DS0
Page 2 of 11
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CY7B9945V
PRELIMINARY
Pin Definitions
Pin
Name
IO
Type
Description
34
FS
Input
Three level Frequency Select. This input must be set according to the nominal frequency
Input
(fNOM). See Table 1.
40,39,
36,37
REFA+, REFAREFB+, REFB-
Input
LVTTL/
LVDIFF
Reference Inputs. These inputs can operate as differential PECL or
single-ended TTL reference inputs to the PLL. When operating as a
single-ended LVTTL input, the complementary input is left open.
38
REFSEL
Input
LVTTL
Reference Select Input. The REFSEL input controls the configuration of
reference input When LOW, it uses the REFA pair as the reference input. When
HIGH, it uses the REFB pair as the reference input. This input has an internal
pull down.
42
FBK
Input
LVTTL
Feedback Input Clock. The PLL operates such that the rising edges of the
reference and feedback signals are aligned in phase and frequency. This pin
provides the clock output QF feedback to the phase detector.
28,18, 1F[0:3], 2F[0:1]
35,17, 2,
1
Input
19,26
DIS[1:2]
Input
14,12,
13,3
[1:2]DS[0:1]
Input
Three level Output Divider Function Select. Each pair determines the divider ratio of the
Input
respective bank of outputs. See Table 4.
29
FBF0
Input
Three level Feedback Output Phase Function Select. This input determines the phase of
Input
the QF output. See Table 3.
50,51
FBDS[0:1]
Input
Three level Feedback Output Divider Function Select. This input determines the divider
Input
ratio of the QF output. See Table 4.
Three level Output Phase Function Select. Each pair determines the phase of the
Input
respective bank of outputs. See Table 3.
LVTTL
Output Disable. Each input controls the state of the respective output bank.
When HIGH, the output bank is disabled to HOLD-OFF or High-Z state; the
disable state is determined by MODE. When LOW, outputs 1Q[0:3] and 2Q[0:5]
are enabled. See Table 5.
48,46, 1Q[0:3], 2Q[0:5]
32,30,
5,7,8,10
, 20,22
Output
LVTTL
Clock Outputs with Adjustable Phases and fNOM Divide Ratios. The output
frequencies and phases are determined by [1:2]DS[0:1], and 1F[0:3] and
2F[0:1], respectively. See Table 3 and Table 4.
44
QF
Output
LVTTL
Feedback Clock Output. This output is connected to the FBK input. The output
frequency and phase are determined by FBDS[0:1] and FBF0, respectively. See
Table 3 and Table 4.
52
LOCK
Output
LVTTL
PLL Lock Indicator. When HIGH, this output indicates that the internal PLL is
locked to the reference signal. When LOW, it indicates that the PLL is attempting
to acquire lock
25
MODE
Input
6,9,21,
31, 45,
47
VCCN
PWR
Power Supply for the Output Buffers
16,27,
41
VCCQ
PWR
Power Supply for the Internal Circuitry
PWR
Device Ground
4,11,15, GND
23,24,
33,43,4
9
Document Number: 38-07336 Rev. *F
Three level This pin determines the clock outputs’ disable state. When this input is
Input
HIGH, the clock outputs disables to high impedance state (High-Z). When this
input is LOW, the clock outputs disables to HOLD-OFF mode. When in MID, the
device enters factory test mode.
Page 3 of 11
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CY7B9945V
PRELIMINARY
Block Diagram Description
1F[0:1], that of 1Q[2:3] is controlled by 1F[2:3] and that of 2Q[0:5]
is controlled by 2F[0:1].
The PLL adjusts the phase and the frequency of its output signal
to minimize the delay between the reference (REFA/B+,
REFA/B-) and the feedback (FB) input signals.
The high fanout feedback output buffer (QF) connects to the
feedback input (FBK).This feedback output has one phase
function select input (FBF0) and two divider function selects
FBDS[0:1].
The CY7B9945V has a flexible REF input scheme. These inputs
enable the use of either differential LVPECL or single ended
LVTTL inputs. To configure as single ended LVTTL inputs, leave
the complementary pin open (internally pulled to 1.5V), then the
other input pin is used as a LVTTL input. The REF inputs are also
tolerant to hot insertion.
The REF inputs are changed dynamically. When changing from
one reference input to the other reference input of the same
frequency, the PLL is optimized to ensure that the clock outputs
period is not less than the calculated system budget (tMIN =
tREF (nominal reference period) – tCCJ (cycle-cycle jitter) –
tPDEV (max. period deviation)) while reacquiring lock.
The FS control pin setting determines the nominal operational
frequency range of the divide by one output (fNOM) of the
device. fNOM is directly related to the VCO frequency. The FS
setting for the device is shown in Table 1. For CY7B9945V, the
upper fNOM range extends from 96 MHz to 200 MHz.
Table 1. Frequency Range Select
fNOM (MHz)
FS[1]
Min
24
48
96
LOW
MID
HIGH
Max
52
100
200
Time Unit Definition
Selectable skew is in discrete increments of time unit (tU). The
value of a tU is determined by the FS setting and the maximum
nominal output frequency. The equation determines the tU value
as follows:
tU = 1/(fNOM*N).
N is a multiplication factor that is determined by the FS setting.
fNOM is nominal frequency of the device. N is defined in Table 2.
Table 2. N Factor Determination
FS
LOW
MID
HIGH
N
32
16
8
CY7B9945V
fNOM (MHz) at which tU = 1.0 ns
31.25
62.5
125
Divide and Phase Select Matrix
The Divide Select Matrix is comprised of three independent
banks: two of clock outputs and one for feedback. The Phase
Select Matrix, enables independent phase adjustments on
1Q[0:1], 1Q[2:3] and 2Q[0:5]. The frequency of 1Q[0:3] is
controlled by 1DS[0:1] while the frequency of 2Q[0:5] is
controlled by 2DS[0:1]. The phase of 1Q[0:1] is controlled by
Document Number: 38-07336 Rev. *F
The phase capabilities that are chosen by the phase function
select pins are shown in Table 3. The divide capabilities for each
bank are shown in Table 4.
Table 3. Output Phase Select
Control Signal
1F1
1F0
1F3
1F2
2F1
2F0
FBF0
LOW
LOW
LOW
MID
LOW
HIGH
MID
LOW
MID
MID
MID
HIGH
HIGH
LOW
HIGH
MID
HIGH
HIGH
Output Phase Function
1Q[0:1]
1Q[2:3]
2Q[0:5]
–4tU
–3tU
–2tU
–1tU
0tU
+1tU
+2tU
+3tU
+4tU
–4tU
–3tU
–2tU
–1tU
0tU
+1tU
+2tU
+3tU
+4tU
QF
–8tU
–4tU
–7tU
N/A
–6tU
N/A
BK1Q[0:1][2] N/A
0tU
0tU
BK1Q[2:3][2] N/A
+6tU
N/A
+7tU
N/A
+8tU
+4tU
Table 4. Output Divider Select
Control Signal
[1:2]DS1
[1:2]DS0
and FBDS1
and
FBDS0
LOW
LOW
LOW
MID
LOW
HIGH
MID
LOW
MID
MID
MID
HIGH
HIGH
LOW
HIGH
MID
HIGH
HIGH
Output Divider Function
Bank1
Bank2
Feedback
/1
/2
/3
/4
/5
/6
/8
/ 10
/ 12
/1
/2
/3
/4
/5
/6
/8
/ 10
/ 12
/1
/2
/3
/4
/5
/6
/8
/ 10
/ 12
Figure 1 shows the timing relationship of programmable skew
outputs. All times are measured with respect to REF with the
output used for feedback programmed with 0tU skew. The PLL
naturally aligns the rising edge of the FB input and REF input. If
the output used for feedback is programmed to another skew
position, then the whole tU matrix shifts with respect to REF. For
example, if the output used for feedback is programmed to shift
–4tU, then the whole matrix is shifted forward in time by 4tU.
Thus an output programmed with 4tU of skew gets effectively be
skewed 8tU with respect to REF.
Page 4 of 11
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CY7B9945V
PRELIMINARY
U
U
t 0 +8t
U
U
t 0 +5t
t 0 +7t
U
t 0 +4t
t 0 +6t
U
U
t 0 +2t
t 0 +3t
U
t 0 +1t
t0
t 0 – 1t U
t 0 – 2t U
t 0 – 3t U
t 0 – 4t U
t 0 – 5t U
t 0 – 6t U
t 0 – 7t U
t 0 – 8t U
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output[3]
FBInput
REFInput
1F[1:0]
1F[3:2]
2F[1:0]
(N/A)
LL
–8tU
(N/A)
LM
–7tU
(N/A)
LH
–6tU
LL
(N/A)
–4tU
LM
(N/A)
–3tU
LH
(N/A)
–2tU
ML
(N/A)
–1tU
MM
MM
0t U
MH
(N/A)
+1t U
HL
(N/A)
+2t U
HM
(N/A)
+3t U
HH
(N/A)
+4t U
(N/A)
HL
+6t U
(N/A)
HM
+7t U
(N/A)
HH
+8t U
Output Disable Description
The output of each output bank can be independently put into a
HOLD OFF or high impedance state. The combination of the
MODE and DIS[1:2] inputs determines the clock outputs’ state
for each bank. When the DIS[1:2] is LOW, the outputs of the
corresponding banks are enabled. When DIS[1:2] is HIGH, the
outputs for that bank are disabled to a high impedance (HI-Z) or
HOLD OFF state. Table 5 defines the disabled outputs functions.
The HOLD OFF state is a power saving feature. An output bank
is disabled to the HOLD OFF state in a maximum of six output
clock cycles from the time the disable input is HIGH. When
disabled to the HOLD OFF state, outputs are driven to a logic
LOW state on their falling edges. This makes certain that the
output clocks are stopped without a glitch. When a bank of
outputs is disabled to HI-Z state, the respective bank of outputs
go HI-Z immediately.
Table 5. DIS[1:2] Functionality
MODE
DIS[1:2]
1Q[0:3], 2Q[0:5]
HIGH/LOW
LOW
ENABLED
HIGH
HIGH
HI-Z
LOW
HIGH
HOLD-OFF
MID
X
FACTORY TEST
Notes
1. FB connected to an output selected for “Zero” skew (i.e., FBF0 = MID or XF[1:0] = MID).
2. The level set on FS is determined by the “nominal” operating frequency (fNOM) of the VCO and Phase Generator. fNOM always appears on an output when the output
is operating in the undivided mode. The REF and FB are at fNOM when the output connected to FB is undivided.
3. BK1Q denotes following the skew setting of indicated Bank1 outputs.
4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold the
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before
all data sheet limits are achieved.
5. This is for non-three level inputs.
Document Number: 38-07336 Rev. *F
Page 5 of 11
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CY7B9945V
PRELIMINARY
Lock Detect Output Description
The LOCK detect output indicates the lock condition of the
integrated PLL. Lock detection is accomplished by comparing
the phase difference between the reference and feedback
inputs. Phase error is declared when the phase difference
between the two inputs is greater than the specified device
propagation delay limit tPD.
When in the locked state, after four or more consecutive
feedback clock cycles with phase errors, the LOCK output is
forced LOW to indicate out-of-lock state.
When in the out-of-lock state, 32 consecutive phase errorless
feedback clock cycles are required to enable the LOCK output to
indicate lock condition (LOCK = HIGH).
If the feedback clock is removed after LOCK has gone HIGH, a
“Watchdog” circuit is implemented to indicate the out-of-lock
condition after a time-out period by deasserting LOCK LOW. This
time out period is based upon a divided down reference clock.
This assumes that there is activity on the selected REF input. If
there is no activity on the selected REF input then the LOCK
detect pin does not accurately reflect the state of the internal
PLL.
the divide, skew and frequency selection. All clock outputs stay
in High-Z mode and all FSMs stay in the deterministic state until
DIS2 is deasserted. This causes the device to reenter factory
test mode.
Safe Operating Zone
Figure 2 shows the operating condition of the device not
exceeding its allowable maximum junction temperature of
150°C. Figure 2 shows the maximum number of outputs that can
operate at 185 MHz (with 25 pF load and no air flow) or 200 MHz
(with 10-pF load and no air flow) at various ambient temperatures. At the limit line, all other outputs are configured to
divide-by-two (i.e., operating at 92.5 MHz) or lower frequencies.
The device operates below maximum allowable junction temperature of 150°C when its configuration (with the specified
constraints) falls within the shaded region (safe operating zone).
Figure 2 shows that at 85°C, the maximum number of outputs
that can operate at 200 MHz is 6.
Figure 2. Typical Safe Operating Zone
Typical Safe Operating Zone
(25-pF Load, 0-m/s air flow)
Factory Test Mode Description
When in the test mode, the device is reset to a deterministic state
by driving the DIS2 input HIGH. Doing so disables all outputs
and, after the selected reference clock pin has five positive
transitions, all internal finite state machines (FSM) are set at a
deterministic state. The states depend on the configurations of
Document Number: 38-07336 Rev. *F
100
Ambient Temperature (C)
The device enters factory test mode when the MODE is driven
to MID. In factory test mode, the device operates with its internal
PLL disconnected; input level supplied to the reference input is
used in place of the PLL output. In TEST mode the FB input is
tied LOW. All functions of the device remain operational in
factory test mode except the internal PLL and output bank
disables. The MODE input is designed as a static input. Dynamically toggling this input from LOW to HIGH temporarily causes
the device to go into factory test mode (when passing through
the MID state).
95
90
85
80
75
70
Safe Operating Zone
65
60
55
50
2
4
6
8
10
Number of Outputs at 185 MHz
Page 6 of 11
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CY7B9945V
PRELIMINARY
Absolute Maximum Conditions
Static Discharge Voltage........................................... > 1100V
(MIL-STD-883, Method 3015)
Operating outside these boundaries may affect the performance
and life of the device. These user guidelines are not tested.
Latch up Current.................................................. > ± 200 mA
Storage Temperature ................................. –40°C to +125°C
Ambient Temperature
with Power Applied ..................................... –40°C to +125°C
Operating Range
Range
Supply Voltage to Ground Potential................–0.5V to +4.6V
Commercial
DC Input Voltage ..................................... –0.3V to VCC+0.5V
Industrial
Ambient Temperature
VCC
0°C to +70°C
3.3V ±10%
–40°C to +85°C
3.3V ±10%
Output Current into Outputs (LOW) ............................. 40 mA
Electrical Characteristics Over the Operating Range
Description
LVTTL HIGH Voltage
(QF, 1Q[0:3], 2Q[0:5])
LOCK
LVTTL LOW Voltage
(QF, 1Q[0:3], 2Q[0:5])
LOCK
High impedance State Leakage Current
LVTTL Input HIGH
LVTTL Input LOW
LVTTL VIN >VCC
LVTTL Input HIGH Current
LVTTL Input LOW Current
Three level Input HIGH[4]
Three level Input MID[4]
Three level Input LOW[4]
Three level Input HIGH FS[0:2],IF[0:3],FBDS[0:1]
Current
2F[0:1],[1:2]DS[0:1],FBFO
Three level Input MID FS[0:2],IF[0:3],FBDS[0:1]
Current
2F[0:1],[1:2]DS[0:1],FBFO
Three level Input LOW FS[0:2],IF[0:3],FBDS[0:1]
Current
2F[0:1],[1:2]DS[0:1],FBFO
Input Differential Voltage
Highest Input HIGH Voltage
Lowest Input LOW Voltage
Common Mode Range (Crossing Voltage)
Internal Operating
CY7B9945V
Current
CY7B9945V
Output Current
Dissipation/Pair[4]
Document Number: 38-07336 Rev. *F
Test Conditions
VCC = Min, IOH = –30 mA
IOH = –2 mA, VCC = Min
Min
Max
Unit
2.4
–
V
–
0.5
0.5
100
VCC + 0.3
0.8
100
500
–
–
0.53 * VCC
0.13 * VCC
200
400
50
100
–
–
VCC
VCC
VCC – 0.4
VCC – 0.2
250
V
V
V
μA
V
V
μA
μA
μA
V
V
V
μA
μA
μA
μA
μA
μA
mV
V
V
V
mA
40
mA
2.4
–
–
–100
Min < VCC < Max
2.0
Min. < VCC < Max.
–0.3
VCC = GND, VIN = 3.63V
–
VCC = Max, VIN = VCC
–
VCC = Max, VIN = GND
–500
Min < VCC < Max
0.87 * VCC
Min < VCC < Max
0.47 * VCC
Min < VCC < Max
–
VIN = VCC
–
–
VIN = VCC/2
–50
–100
VIN = GND
–200
–400
400
1.0
GND
0.8
VCC = Max, fMAX[5]
–
VCC = Min, IOL= 30 mA
IOL= 2 mA, VCC = Min
VCC = Max, CLOAD = 25
pF, RLOAD = 50Ω at VCC/2,
fMAX
–
Page 7 of 11
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CY7B9945V
PRELIMINARY
Capacitance
Parameter
CIN
Description
Test Conditions
Min
Max
Unit
–
5
pF
TA = 25°C, f = 1 MHz, VCC = 3.3V
Input Capacitance
Switching Characteristics
Over the Operating Range [5, 7, 8, 9, 10]
Parameter
CY7B9945V-2 CY7B9945V-5
Description
Min
Max
Min
Max
Unit
fin
Clock Input Frequency
24
200
24
200
MHz
fout
Clock Output Frequency
24
200
24
200
MHz
Skew[12, 13],1Q[0:1],1Q[2:3],2Q[0:1],2Q[2:3],2Q[4:5]
tSKEWPR
Matched Pair
–
200
–
200
ps
tSKEWBNK
Intrabank Skew[12, 13]
–
250
–
250
ps
tSKEW0
Output-Output Skew (same frequency and phase, rise to rise, fall to fall)[12, 13]
–
250
–
550
ps
tSKEW1
Output-Output Skew (same frequency and phase, other banks at
different frequency, rise to rise, fall to fall)[12, 13]
–
250
–
650
ps
tSKEW2
Output-Output Skew (all output configurations outside of tSKEW0 and
tSKEW1)[10, 11]
–
500
–
800
ps
tCCJ1-3
Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 1, 2, 3)
–
150
–
150
ps
PeakPeak
tCCJ4-12
Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 4, 5,
6, 8, 10, 12)
–
100
–
100
ps
PeakPeak
tPD
Propagation Delay, REF to FB Rise
–250
250
–500
500
ps
–
500
–
700
ps
–
200
–
200
ps
tREFpwh
REF input (Pulse Width
HIGH)[5]
2.0
–
2.0
–
ns
tREFpwl
REF input (Pulse Width LOW)[5]
2.0
–
2.0
–
ns
phase)[14, 15]
TTB
Total Timing Budget window (same frequency and
tPDDELTA
Propagation Delay difference between two devices[16]
Time[17]
tr/tf
Output Rise/Fall
0.15
2.0
0.15
2.0
ns
tLOCK
PLL Lock TIme From Power Up
–
10
–
10
ms
tRELOCK1
PLL Relock Time (from same frequency, different phase) with Stable
Power Supply
–
500
–
500
μs
tRELOCK2
PLL Re-lock Time (from different frequency, different phase) with Stable
Power Supply[16]
–
1000
–
1000
μs
tODCV
Output duty cycle deviation from 50%[11]
–1.0
1.0
–1.0
1.0
ns
tPWH
Output HIGH time deviation from 50%[19]
–
1.5
–
1.5
ns
tPWL
[19]
Output LOW time deviation from 50%
–
2.0
–
2.0
ns
tPDEV
Period deviation when changing from reference to reference[20]
–
0.025
–
0.025
UI
1.0
10
1.0
10
ns
0.5
14
0.5
14
ns
ACTIVE[12, 21]
tOAZ
DIS[1:2] HIGH to output high-impedance from
tOZA
DIS[1:2] LOW to output ACTIVE from output is high impedance[21, 22]
Notes
6. Assumes 25 pF Maximum Load Capacitance up to 185 MHz. At 200 MHz the maximum load is 10 pF.
7. Both outputs of pair must be terminated, even if only one is being used.
8. Each package must be properly decoupled.
9. AC parameters are measured at 1.5V, unless otherwise indicated.
10. Test Load CL= 25 pF, terminated to VCC/2 with 50Ω up to185 MHz and 10 pF load to 200 MHz.
11. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase dellay has been selected when
all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
12. Tested initially and after any design or process changes that affect these parameters.
13. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew,
cycle-cycle jitter, and dynamic phase error. TTB is equal to or smaller than the maximum specified value at a given output frequency.
Document Number: 38-07336 Rev. *F
Page 8 of 11
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CY7B9945V
PRELIMINARY
AC Test Loads and Waveform
Figure 3. AC Test Loads and Waveforms [22]
3.3V
For LOCK output only
R1 = 910 Ω
R2 = 910 Ω
CL < 30 pF
For all other outputs
R1 = 100Ω
R2 = 100Ω
CL < 25 pF to 185 MHz
or 10 pF at 200 MHz
(Includes fixture and
probe capacitance)
R1
OUTPUT
CL
R2
(a) LVTTL AC Test Load
3.3V
2.0V
2.0V
0.8V
0.8V
GND
< 1 ns
< 1 ns
(b) TTL Input Test Waveform
AC Timing Diagram
Figure 4. AC Timing Diagram
tREFpwl
tREFpwh
[1:2]Q[0,2]
REF
t SKEWPR
t SKEWPR
t PWH
tPD
t PWL
[1:2]Q[1,3]
2.0V
FB
0.8V
tCCJ1-3,4-12
Q
[1:2]Q[0:3]
t SKEWBNK
t SKEWBNK
[1:2]Q[0:3]
REF TO DEVICE 1 and 2
tODCV
tODCV
tPD
Q
FB DEVICE1
tPDELTA
tPDELTA
t SKEW0,1
t SKEW0,1
Other Q
FB DEVICE2
.
Notes
14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affects these parameters.
15. Rise and fall times are measured between 2.0V and 0.8V.
16. fNOM must be within the frequency range defined by the same FS state.
17. tPWH is measured at 2.0V. tPWL is measured at 0.8V.
18. UI = unit interval. Examples: 1 UI is a full period. 0.1UI is 10% of period.
19. Measured at 0.5V deviation from starting voltage.
20. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 185 MHz or 10 pF to 200 MHz
21. These figures are for illustration purposes only. The actual ATE loads may vary.
Document Number: 38-07336 Rev. *F
Page 9 of 11
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CY7B9945V
PRELIMINARY
Ordering Information
Propagation
Delay (ps)
Max. Speed
(MHz)
250
200
Ordering Code
CY7B9945V-2AC
Package
Name
A52
Operating
Range
Package Type
52-Pb TQFP
Commercial
500
200
CY7B9945V-5AC
A52
52-Pb TQFP
Commercial
250
200
CY7B9945V-2AI
A52
52-Pb TQFP
Industrial
200
CY7B9945V-2AIT
A52
52-PbTQFP
Industrial
500
200
CY7B9945V-5AI [22.]
A52
52-Pb TQFP
Industrial
250
200
CY7B9945V-2AXC
AZ52
52-Pb TQFP
Commercial
200
CY7B9945V-2AXCT
AZ52
52-Pb TQFP – Tape and Reel
Commercial
250
200
CY7B9945V-2AXI
AZ52
52-PbTQFP
Industrial
200
CY7B9945V-2AXIT
AZ52
52-PbTQFP – Tape and Reel
Industrial
500
200
CY7B9945V-5AXC
AZ52
52-Pb TQFP
Commercial
200
CY7B9945V-5AXCT
AZ52
52-Pb TQFP – Tape and Reel
Commercial
Pb-free
Package Diagram
Figure 5. 52 - Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm) A52 and AZ52
51-85131-**
Note
22. Not for new designs.
Document Number: 38-07336 Rev. *F
Page 10 of 11
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PRELIMINARY
CY7B9945V
Document History Page
Document Title: CY7B9945V RoboClock® High Speed Multi-phase PLL Clock Buffer
Document Number: 38-07336
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
111747
03/04/02
CTK
New Data Sheet
*A
116572
09/05/02
HWT
Added TTB Features
*B
119078
10/16/02
HWT
Corrected the following items in the Electrical Characteristics table:
IIIL,IIIH,IIIM specifications from: three level input pins excluding FBFO to
FS[0:2],IF[0:3],FBDS[0:1] and FBFO to 2F[0:1],[1:2]DS[0:1],FBFO
Common Mode Range (VCOM) from VCC to VCC–0.2
Corrected typo TQFP to LQFP in Features
*C
124645
03/20/03
RGL
Corrected typo LQFP to TQFP in Features
*D
128464
07/25/03
RGL
Added clock input frequency (fin) specifications in the switching characteristics table.
Description of Change
*E
272075
See ECN
RGL
Minor Change: Fixed the Typical Outputs (Fig. 1) diagram
*F
1187144
See ECN
KVM
Updated Ordering Information table, primarily to add Pb-free devices
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07336 Rev. *F
Revised June 21, 2007
Page 11 of 11
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations.Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.All products and company names
mentioned in this document may be the trademarks of their respective holders. RoboClock is a registered trademark, and Total Timing Budget and TTB are trademarks of Cypress Semiconductor.
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