AD ADM7155 High psrr, rf linear regulator Datasheet

2 A, Ultralow Noise,
High PSRR, RF Linear Regulator
ADP7158
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUIT
Regulation to noise sensitive applications: phase-locked
loops (PLLs), voltage controlled oscillators (VCOs), and
PLLs with integrated VCOs
Communications and infrastructure
Backhaul and microwave links
GENERAL DESCRIPTION
The ADP7158 is a linear regulator that operates from 2.3 V to
5.5 V and provides up to 2 A of output current. Using an advanced
proprietary architecture, it provides high power supply rejection
and ultralow noise, achieving excellent line and load transient
response with only a 10 μF ceramic output capacitor.
There are 16 standard output voltages for the ADP7158. The
following voltages are available from stock: 1.2 V, 1.8 V, 2.0 V,
2.5 V, 2.8 V, 3.0 V and 3.3 V. Additional voltages available by
special order are 1.3 V, 1.5 V, 1.6 V, 2.2 V, 2.6 V, 2.7 V, 2.9 V,
3.1V and 3.2 V.
The ADP7158 regulator typical output noise is 0.9 μV rms
from 100 Hz to 100 kHz and 1.7 nV/√Hz for noise spectral
density from 10 kHz to 1 MHz. The ADP7158 is available in a
10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages,
making it not only a very compact solution, but also providing
excellent thermal performance for applications requiring up to
2 A of output current in a small, low profile footprint.
Rev. A
CIN
10µF
VIN
VOUT = 3.3V
VOUT
COUT
10µF
VOUT_SENSE
ON
EN
REF
OFF
CBYP
1µF
BYP
CREG
1µF
VREG
CREF
1µF
REF_SENSE
12896-001
GND (EPAD)
Figure 1.
Table 1. Related Devices
Model
ADP7159
ADP7156,
ADP7157
ADM7150,
ADM7151
ADM7154,
ADM7155
ADM7160
1
Input
Voltage
2.3 V to 5.5 V
Output
Current
2A
Fixed/
Adj1
Adj
2.3 V to 5.5 V
1.2 A
4.5 V to 16 V
800 mA
2.3 V to 5.5 V
600 mA
2.2 V to 5.5 V
200 mA
Fixed/
Adj
Fixed/
Adj
Fixed/
Adj
Fixed
Package
10-lead LFCSP/
8-lead SOIC
10-lead LFCSP/
8-lead SOIC
8-lead LFCSP/
8-lead SOIC
8-lead LFCSP/
8-lead SOIC
6-lead LFCSP/
5-lead TSOT
Adj means adjustable.
1k
CBYP
CBYP
CBYP
CBYP
100
= 1µF
= 10µF
= 100µF
= 1000µF
10
1
0.1
10
12896-002
APPLICATIONS
ADP7158
VIN = 3.8V
NOISE SPECTRAL DENSITY (nV/√Hz)
Input voltage range: 2.3 V to 5.5 V
16 standard voltages between 1.2 V and 3.3 V available
Maximum load current: 2 A
Low noise
0.9 μV rms total integrated noise from 100 Hz to 100 kHz
1.6 μV rms total integrated noise from 10 Hz to 100 kHz
Noise spectral density: 1.7 nV/√Hz from 10 kHz to 1 MHz
Power supply rejection ratio (PSRR)
70 dB from 1 kHz to 100 kHz; 50 dB at 1 MHz, VOUT = 3.3 V,
VIN = 4.0 V
Dropout voltage: 200 mV typical at IOUT = 2 A, VOUT = 3.3 V
Initial accuracy: ±0.6% at ILOAD = 10 mA
Accuracy over line, load, and temperature: ±1.5%
Quiescent current: IGND = 4.0 mA at no load, 9.0 mA at 2 A
Low shutdown current: 0.2 μA
Stable with a 10 μF ceramic output capacitor
10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages
Precision enable
Supported by ADIsimPower tool
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 2. Noise Spectral Density at Various Values of CBYP, VOUT = 3.3 V
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Last Content Update: 11/01/2016
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ADP7158
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 14
Applications ....................................................................................... 1
ADIsimPower Design Tool ....................................................... 14
General Description ......................................................................... 1
Capacitor Selection .................................................................... 14
Typical Application Circuit ............................................................. 1
Undervoltage Lockout (UVLO) ............................................... 15
Revision History ............................................................................... 2
Programmable Precision Enable .............................................. 16
Specifications..................................................................................... 3
Start-Up Time ............................................................................. 17
Input and Output Capacitors, Recommended Specifications 4
REF, BYP, and VREG Pins......................................................... 17
Absolute Maximum Ratings ............................................................ 5
Current-Limit and Thermal SHUTDOWN ........................... 17
Thermal Data ................................................................................ 5
Thermal Considerations............................................................ 17
Thermal Resistance ...................................................................... 5
Printed Circuit Board (PCB) Layout Considerations ................ 20
ESD Caution .................................................................................. 5
Outline Dimensions ....................................................................... 21
Pin Configurations and Function Descriptions ........................... 6
Ordering Guide .......................................................................... 22
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 13
REVISION HISTORY
5/2016—Rev. 0 to Rev. A
Added Note 1 to Table 2; Renumbered Sequentially ................... 4
Change to Figure 4 ........................................................................... 6
Change to Programmable Precision Enable Section ................. 16
3/2016—Revision 0: Initial Version
Rev. A | Page 2 of 22
Data Sheet
ADP7158
SPECIFICATIONS
VIN = VOUT + 0.5 V or 2.3 V, whichever is greater; VEN = VIN; ILOAD = 10 mA; CIN = COUT = 10 µF; CREG = CREF = CBYP = 1 µF;
TA = 25°C for typical specifications; TA = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 2.
Parameter
INPUT VOLTAGE RANGE
LOAD CURRENT
OPERATING SUPPLY CURRENT
Symbol
VIN
ILOAD
IGND
SHUTDOWN CURRENT
NOISE 1
Output Noise
IIN_SD
Noise Spectral Density
POWER SUPPLY REJECTION RATIO1
OUTNSD
PSRR
OUTPUT VOLTAGE ACCURACY
Output Voltage 2
Initial Accuracy
REGULATION
Line
Load 3
CURRENT-LIMIT THRESHOLD 4
REF
VOUT
DROPOUT VOLTAGE 5
PULL-DOWN RESISTANCE
VOUT
VREG
REF
BYP
START-UP TIME1, 6
VOUT
VREG
REF
THERMAL SHUTDOWN1
Threshold
Hysteresis
UNDERVOLTAGE THRESHOLDS
Input Voltage
Rising
Falling
Hysteresis
OUTNOISE
Test Conditions/Comments
ILOAD = 0 µA
ILOAD = 2 A
EN = GND
VOUT = 1.2 V to 3.3 V
10 Hz to 100 kHz
100 Hz to 100 kHz
10 kHz to 1 MHz
1 kHz to 100 kHz, VIN = 4.0 V, VOUT = 3.3 V,
ILOAD = 2 A
1 MHz, VIN = 4.0 V, VOUT = 3.3 V, ILOAD = 2 A
1 kHz to 100 kHz, VIN = 2.6 V, VOUT = 1.8 V,
ILOAD = 2 A
1 MHz, VIN = 2.6 V, VOUT = 1.8 V, ILOAD = 2 A
VOUT
ILOAD = 10 mA, TA = 25°C
10 mA < ILOAD < 2 A, TA = 25°C
10 mA < ILOAD < 2 A, TA = −40°C to +125°C
∆VOUT/∆VIN
∆VOUT/∆IOUT
ILIMIT
Min
2.3
VIN = VOUT + 0.5 V or 2.3 V, whichever is greater
to 5.5 V
IOUT = 10 mA to 2 A
4.0
9.0
0.2
VOUT_PULL
VREG_PULL
VREF_PULL
VBYP_PULL
µV rms
µV rms
nV/√Hz
dB
50
70
dB
dB
50
dB
−0.1
+0.1
%/V
0.3
%/A
3.8
170
280
mA
A
mV
mV
TJ rising
1.95
Rev. A | Page 3 of 22
1.6
0.9
1.7
70
V
%
%
%
IOUT = 1.2 A, VOUT = 3.3 V
IOUT = 2 A, VOUT = 3.3 V
EN = 0 V, VIN = 5.5 V
VOUT = 1 V,
VREG = 1 V
VREF = 1 V
VBYP = 1 V
VOUT = 3.3 V
UVLORISE
UVLOFALL
UVLOHYS
Unit
V
A
mA
mA
µA
3.3
+0.6
+1.0
+1.5
tSTART-UP
tREG_START-UP
tREF_START-UP
TSSD
TSSD_HYS
Max
5.5
2
8.0
14.0
4
1.2
−0.6
−1.0
−1.5
2.4
VDROPOUT
Typ
22
3
120
200
650
31
850
650
Ω
kΩ
Ω
Ω
1.2
0.6
0.5
ms
ms
ms
150
15
°C
°C
2.22
2.02
200
2.29
V
V
mV
ADP7158
Parameter
VREG UVLO THRESHOLDS7
Rising
Falling
Hysteresis
EN INPUT PRECISION
EN Input
Logic High
Logic Low
Logic Hysteresis
LEAKAGE CURRENT
REF_SENSE
EN
Data Sheet
Symbol
Test Conditions/Comments
VREGUVLORISE
VREGUVLOFALL
VREGUVLOHYS
Min
Typ
Max
Unit
1.94
V
V
mV
1.31
1.22
V
V
mV
1.60
185
2.3 V ≤ VIN ≤ 5.5 V
VEN_HIGH
VEN_LOW
VEN_HYS
IREF_SENSE_LKG
IEN_LKG
1.13
1.05
1.22
1.13
90
10
0.01
EN = VIN or GND
nA
μA
1
1
Guaranteed by characterization but not production tested.
The ADP7158 is available in 16 standard voltages between 1.2 V and 3.3 V, including 1.2 V, 1.3 V, 1.5 V, 1.6 V, 1.8 V, 2.0 V, 2.2 V, 2.5 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V,
3.2 V, and 3.3 V.
3
Based on an endpoint calculation using 10 mA and 2 A loads.
4
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
5
Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. Dropout voltage applies only for
output voltages greater than 2.3 V.
6
Start-up time is defined as the time between the rising edge of VEN to VOUT, VREG, or VREF being at 90% of its nominal value.
7
The output voltage is disabled until the VREG UVLO rise threshold is crossed. The VREG output is disabled until the input voltage UVLO rising threshold is crossed.
2
INPUT AND OUTPUT CAPACITORS, RECOMMENDED SPECIFICATIONS
Table 3.
Parameter
MINIMUM CAPACITANCE
Input1
Regulator
Output1
Bypass
Reference
CAPACITOR EFFECTIVE SERIES RESISTANCE (ESR)
COUT, CIN
CREG, CREF
CBYP
1
Symbol
Test Conditions/Comments
TA = −40°C to +125°C
CIN
CREG
COUT
CBYP
CREF
Min
Typ
Max
10.0
1.0
10.0
1.0
1.0
Unit
μF
μF
μF
μF
μF
TA = −40°C to +125°C
RESR
RESR
RESR
0.001
0.001
0.001
0.1
0.2
2.0
Ω
Ω
Ω
The minimum input and output capacitance must be greater than 7.0 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any low dropout regulator.
Rev. A | Page 4 of 22
Data Sheet
ADP7158
ABSOLUTE MAXIMUM RATINGS
Junction to ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction to ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit
board. See JESD51-7 and JESD51-9 for detailed information on
the board construction.
Table 4.
Parameter
VIN to Ground
VREG to Ground
VOUT to Ground
VOUT_SENSE to Ground
VOUT to VOUT_SENSE
BYP to VOUT
EN to Ground
BYP to Ground
REF to Ground
REF_SENSE to Ground
Storage Temperature Range
Operational Junction Temperature
Range
Soldering Conditions
Rating
−0.3 V to +7 V
−0.3 V to VIN, or +4 V
(whichever is less)
−0.3 V to VREG, or +4 V
(whichever is less)
−0.3 V to VREG, or +4 V
(whichever is less)
±0.3 V
±0.3 V
−0.3 V to +7 V
−0.3 V to VREG, or +4 V
(whichever is less)
−0.3 V to VREG, or +4 V
(whichever is less)
−0.3 V to +4 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP7158 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
need to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction to ambient thermal resistance of the
package (θJA).
ΨJB is the junction to board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. JESD51-12, Guidelines for
Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power
flowing through multiple thermal paths rather than a single
path as in thermal resistance, θJB. Therefore, ΨJB thermal paths
include convection from the top of the package as well as
radiation from the package, factors that make ΨJB more useful
in real-world applications. Maximum junction temperature (TJ)
is calculated from the board temperature (TB) and power
dissipation (PD) using the following formula:
TJ = TB + (PD × ΨJB)
See JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA, θJC, and ΨJB are specified for the worst case conditions, that
is, a device soldered in a circuit board for surface-mount
packages.
Table 5. Thermal Resistance
Package Type
10-Lead LFCSP
8-Lead SOIC
ESD CAUTION
Calculate the maximum junction temperature (TJ) from the
ambient temperature (TA) and power dissipation (PD) using the
following formula:
TJ = TA + (PD × θJA)
Rev. A | Page 5 of 22
θJA
53.8
50.4
θJC
15.6
42.3
ΨJB
29.1
30.1
Unit
°C/W
°C/W
ADP7158
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VOUT_SENSE 3
BYP 4
ADP7158
TOP VIEW
(Not to Scale)
EN 5
9
VIN
8
VREG
7
REF
6
REF_SENSE
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE. THE EXPOSED PAD ENHANCES THERMAL
PERFORMACE, AND IT IS ELECTRICALLY CONNECTED TO
GROUND INSIDE THE PACKAGE. CONNECT THE EXPOSED
PAD TO THE GROUND PLANE ON THE BOARD TO ENSURE
PROPER OPERATION.
VOUT 1
8
VIN
VOUT_SENSE 2
ADP7158
7
VREG
BYP 3
TOP VIEW
(Not to Scale)
6
REF
5
REF_SENSE
EN 4
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE. THE EXPOSED PAD ENHANCES THERMAL
PERFORMACE, AND IT IS ELECTRICALLY CONNECTED TO
GROUND INSIDE THE PACKAGE. CONNECT THE EXPOSED
PAD TO THE GROUND PLANE ON THE BOARD TO ENSURE
PROPER OPERATION.
12896-003
VOUT 2
12896-004
10 VIN
VOUT 1
Figure 4. 8-Lead SOIC Pin Configuration
Figure 3. 10-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions
LFCSP
1, 2
3
Pin No.
SOIC
1
2
Mnemonic
VOUT
VOUT_SENSE
4
3
BYP
5
4
EN
6
5
REF_SENSE
7
6
REF
8
7
VREG
9, 10
8
VIN
EP
Description
Regulated Output Voltage. Bypass VOUT to ground with a 10 μF or greater capacitor.
Output Sense. VOUT_SENSE is internally connected to VOUT with a 10 Ω resistor. Connect
VOUT_SENSE as close to the load as possible.
Low Noise Bypass Capacitor. Connect a 1 μF capacitor from the BYP pin to ground to reduce noise.
Do not connect a load to this pin.
Enable. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic
startup, connect EN to VIN.
Reference Sense. Connect REF_SENSE to the REF pin. Do not connect REF_SENSE to VOUT or
ground.
Low Noise Reference Voltage Output. Bypass REF to ground with a 1 μF or greater capacitor. Short
REF_SENSE to REF for fixed output voltages. Do not connect a load to this pin.
Regulated Input Supply Voltage to Low Dropout (LDO) Amplifier. Bypass VREG to ground with a
1 μF or greater capacitor.
Regulator Input Supply Voltage. Bypass VIN to ground with a 10 μF or greater capacitor.
Exposed Pad. The exposed pad is located on the bottom of the package. The exposed pad
enhances thermal performance, and it is electrically connected to ground inside the package.
Connect the exposed pad to the ground plane on the board to ensure proper operation.
Rev. A | Page 6 of 22
Data Sheet
ADP7158
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VOUT + 0.5 V or 2.3 V, whichever is greater; VEN = VIN; ILOAD = 10 mA; CIN = COUT = 10 μF; CREG = CREF = CBYP = 1 μF;
TA = 25°C unless otherwise noted.
3.35
1.0
2.3V
2.5V
3.0V
4.0V
5.0V
5.5V
0.8
3.32
VOUT (V)
0.6
0.5
0.4
3.31
3.30
3.29
0.3
3.28
0.2
3.27
0.1
–20
0
20
40
60
80
100
120
3.26
3.25
3.8
140
4.0
4.2
4.4
4.6
4.8
VIN (V)
TEMPERATURE (°C)
ILOAD = 0mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 600mA
ILOAD = 1200mA
ILOAD = 2000mA
3.34
3.33
5.6
13
12
11
10
9
IGND (mA)
3.31
3.30
3.29
8
7
6
5
3.28
4
3.27
3
3.26
–20
0
20
40
60
80
100
120
ILOAD = 0mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 600mA
ILOAD = 1200mA
ILOAD = 2000mA
2
12896-006
VOUT (V)
3.32
1
0
–40
140
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Ground Current (IGND) vs. Temperature
at Various Loads, VOUT = 3.3 V
Figure 6. Output Voltage (VOUT) vs. Temperature
at Various Loads, VOUT = 3.3 V
14
3.35
13
3.34
12
3.33
11
3.32
10
9
IGND (mA)
3.31
3.30
3.29
8
7
6
5
3.28
4
3.27
3
3.26
1m
10m
100m
1
12896-010
2
12896-007
VOUT (V)
5.4
14
3.35
3.25
0.1m
5.2
Figure 8. Output Voltage (VOUT) vs. Input Voltage (VIN)
at Various Loads, VOUT = 3.3 V
Figure 5. Shutdown Current (IIN_SD) vs. Temperature
at Various Input Voltages (VIN), VOUT = 1.8 V
3.25
–40
5.0
12896-009
0
–40
ILOAD = 0mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 600mA
ILOAD = 1200mA
ILOAD = 2000mA
3.33
12896-005
IIN_SD (µA)
0.7
3.34
12896-008
0.9
1
0
0.1m
10
ILOAD (A)
1m
10m
100m
1
10
ILOAD (A)
Figure 10. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 3.3 V
Figure 7. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 3.3 V
Rev. A | Page 7 of 22
ADP7158
Data Sheet
14
14
ILOAD = 0mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 600mA
ILOAD = 1200mA
ILOAD = 2000mA
13
12
11
10
13
12
11
10
9
7
6
8
7
6
5
5
4
4
3
3
2
2
1
0
3.8
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
1
0
3.1
5.6
ILOAD = 0mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 600mA
ILOAD = 1200mA
ILOAD = 2000mA
3.2
3.3
12896-014
IGND (mA)
8
12896-011
IGND (mA)
9
3.4
VIN (V)
Figure 11. Ground Current (IGND) vs. Input Voltage (VIN)
at Various Loads, VOUT = 3.3 V
3.6
3.7
3.8
Figure 14. Ground Current (IGND) vs. Input Voltage (VIN) at Various Loads in
Dropout, VOUT = 3.3 V
0.25
1.85
ILOAD = 0mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 600mA
ILOAD = 1200mA
ILOAD = 2000mA
1.84
0.20
1.83
1.82
0.15
VOUT (V)
VDROPOUT (V)
3.5
VIN (V)
0.10
1.81
1.80
1.79
1.78
0.05
0
10m
100
1
12896-015
12896-012
1.77
1.76
1.75
–40
10
–20
0
ILOAD (A)
20
40
60
80
100
120
140
TEMPERATURE (ºC)
Figure 12. Dropout Voltage (VDROPOUT) vs. Load Current (ILOAD), VOUT = 3.3 V
Figure 15. Output Voltage (VOUT) vs. Temperature at Various Loads, VOUT = 1.8 V
1.85
3.40
1.84
3.35
1.83
3.30
1.82
ILOAD = 0mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 600mA
ILOAD = 1200mA
ILOAD = 2000mA
3.20
3.15
3.10
1.81
1.80
1.79
1.78
1.76
12896-013
3.1
3.2
3.3
3.4
3.5
3.6
3.7
12896-016
1.77
3.05
3.00
3.0
VOUT (V)
VOUT (V)
3.25
1.75
0.1m
3.8
1m
10m
100m
1
10
ILOAD (A)
VIN (V)
Figure 13. Output Voltage (VOUT) vs. Input Voltage (VIN) at Various Loads in
Dropout, VOUT = 3.3 V
Rev. A | Page 8 of 22
Figure 16. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 1.8 V
Data Sheet
ADP7158
14
1.85
ILOAD = 0mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 600mA
ILOAD = 1200mA
ILOAD = 2000mA
1.84
1.83
12
11
10
9
IGND (mA)
1.81
1.80
1.79
8
7
6
5
1.78
4
1.77
3
2.7
3.1
3.5
3.9
4.3
VIN (V)
4.7
5.1
1
0
2.3
5.5
2.9
3.2
3.5
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
–10
12
11
–20
10
–30
PSRR (dB)
9
8
7
6
4.4
4.7
5
5.3
5.6
ILOAD = 0mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 600mA
ILOAD = 1200mA
ILOAD = 2000mA
3
2
1
–20
0
20
40
60
80
100
120
–40
–50
–60
–70
–80
12896-018
4
= 10mA
= 100mA
= 600mA
= 1200mA
= 2000mA
12896-021
5
–90
–100
140
1
10
100
TEMPERATURE (ºC)
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 18. Ground Current (IGND) vs. Temperature
at Various Loads, VOUT = 1.8 V
Figure 21. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various Loads, VOUT = 3.3 V, VIN = 4.0 V
14
0
13
–10
11
–20
10
–30
PSRR (dB)
9
8
7
6
5
–40
–50
–60
4
–70
3
–80
12896-019
2
1
1m
10m
100m
1
–90
–100
10
1
ILOAD (A)
Figure 19. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 1.8 V
900mV
800mV
700mV
600mV
500mV
12896-022
12
IGND (mA)
4.1
0
13
0
0.1m
3.8
Figure 20. Ground Current (IGND) vs. Input Voltage (VIN)
at Various Loads, VOUT = 1.8 V
14
IGND (mA)
2.6
VIN (V)
Figure 17. Output Voltage (VOUT) vs. Input Voltage (VIN)
at Various Loads, VOUT = 1.8 V
0
–40
12896-020
1.76
1.75
2.3
2
12896-017
VOUT (V)
1.82
ILOAD = 0mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 600mA
ILOAD = 1200mA
ILOAD = 2000mA
13
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 22. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various
Headroom Voltages, VOUT = 3.3 V, 2 A Load
Rev. A | Page 9 of 22
ADP7158
Data Sheet
–10
–20
–30
–20
–30
PSRR (dB)
–40
–50
–60
–40
–50
–60
–70
–70
–80
–80
–90
–100
0.5
0.6
0.7
0.8
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
–10
12896-023
PSRR (dB)
0
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
12896-026
0
–90
–100
0.5
0.9
0.6
0.7
HEADROOM VOLTAGE (V)
Figure 23. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage
at Various Frequencies, VOUT = 3.3 V, 2 A Load
0
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 600mA
ILOAD = 1200mA
ILOAD = 2000mA
–30
–10
–30
PSRR (dB)
–40
–50
–60
–50
–60
–80
–80
12896-024
–70
–90
–100
10
100
1k
10k
100k
1M
= 1µF
= 10µF
= 100µF
= 1000µF
–40
–70
1
CBYP
CBYP
CBYP
CBYP
–20
12896-027
–20
PSRR (dB)
0.9
Figure 26. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage
at Various Frequencies, VOUT = 1.8 V, 2 A Load
0
–10
–90
–100
10M
1
10
100
1k
FREQUENCY (Hz)
–10
1.8
–20
1.6
OUTPUT NOISE (µV rms)
2.0
900mV
800mV
700mV
600mV
500mV
–40
100k
1M
10M
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various CBYP Values, VOUT = 3.3 V, VIN = 4.0 V, 2 A Load
0
–30
10k
FREQUENCY (Hz)
Figure 24. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various Loads, VOUT = 1.8 V, VIN = 2.6 V
–50
–60
–70
10Hz TO 100kHz
1.4
1.2
1.0
100Hz TO 100kHz
0.8
0.6
0.4
–90
–100
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
12896-028
–80
12896-025
PSRR (dB)
0.8
HEADROOM VOLTAGE (V)
0.2
0
10m
100m
1
LOAD CURRENT (A)
Figure 25. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various Headroom Voltages, VOUT = 1.8 V, 2 A Load
Figure 28. RMS Output Noise vs. Load Current
Rev. A | Page 10 of 22
10
Data Sheet
ADP7158
1k
2.0
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 600mA
ILOAD = 1200mA
ILOAD = 2000mA
10Hz TO 100kHz
1.4
1.2
1.0
100Hz TO 100kHz
0.8
0.6
10
1
12896-029
0.4
100
0.2
0
1.0
1.5
2.0
2.5
3.0
12896-034
OUTPUT NOISE (µV rms)
1.6
NOISE SPECTRAL DENSITY (nV/√Hz)
1.8
0.1
10
3.5
100
OUTPUT VOLTAGE (V)
100k
1M
10M
Figure 32. Output Noise Spectral Density vs. Frequency at Various Loads,
10 Hz to 10 MHz
1k
CBYP
CBYP
CBYP
CBYP
SLEW RATE = 3A/µs
= 1µF
= 10µF
= 100µF
= 1000µF
IOUT
1
10
2
VOUT
0.1
10
12896-035
1
12896-032
NOISE SPECTRAL DENSITY (nV/√Hz)
10k
FREQUENCY (Hz)
Figure 29. RMS Output Noise vs. Output Voltage
100
1k
100
1k
10k
100k
1M
CH1 1.00A
10M
CH2 10.0mV
B
W
FREQUENCY (Hz)
Figure 30. Noise Spectral Density vs. Frequency at Various Values of CBYP
M4.00µs
A CH1
T 21.90%
1.00A
Figure 33. Load Transient Response, ILOAD = 100 mA to 2 A,
VOUT = 3.3 V, VIN = 4.0 V, Channel 1 = IOUT, Channel 2 = VOUT
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 600mA
ILOAD = 1200mA
ILOAD = 2000mA
10k
SLEW RATE = 2.2A/µs
IOUT
1k
1
100
10
2
VOUT
0.1
0.1
12896-036
1
12896-033
OUTPUT NOISE SPECTRAL DENSITY (nV/√Hz)
100k
1
10
100
1k
10k
100k
CH1 1.00A BW CH2 10.0mV
1M
FREQUENCY (Hz)
Figure 31. Output Noise Spectral Density at Various Loads, 0.1 Hz to 1 MHz
B
W
M4.00µs A CH1
T 22.60%
700mA
Figure 34. Load Transient Response, ILOAD = 100 mA to 2 A,
VOUT = 3.3 V, VIN = 4.0 V, COUT = 22 μF, Channel 1 = IOUT, Channel 2 = VOUT
Rev. A | Page 11 of 22
ADP7158
Data Sheet
SLEW RATE = 1V/µs
SLEW RATE = 3.3A/µs
VIN
1
IOUT
1
2
VOUT
12896-040
VOUT
12896-037
2
CH1 1.00A BW CH2 10.0mV
B
W
M4.00µs A CH1
T 20.800%
CH1 1.00V BW CH2 2.00mV
740mA
B
W
M10.0µs A CH1
T 21.80%
2.80A
Figure 38. Line Transient Response, 1 V Input Step, ILOAD = 2 A,
VOUT = 1.8 V, VIN = 2.5 V, Channel 1 = VIN, Channel 2 = VOUT
Figure 35. Load Transient Response, ILOAD = 100 mA to 2 A,
VOUT = 1.8 V, VIN = 2.5 V, Channel 1 = IOUT, Channel 2 = VOUT
3.5
3.0
SLEW RATE = 2.4A/µs
2.5
IOUT
2
VOUT (V)
1
VOUT
2.0
1.5
VEN
3.3V
2.5V
1.8V
1.0
CH1 1.00A BW CH2 10.0mV
B
W
M4.00µs A CH1
T 20.70%
0
–2
740mA
12896-041
12896-038
0.5
–1
0
1
2
3
4
5
6
7
8
18
20
TIME (ms)
Figure 36. Load Transient Response, ILOAD = 100 mA to 2 A,
VOUT = 1.8 V, VIN = 2.5 V, COUT = 22 μF, Channel 1= IOUT, Channel 2 = VOUT
Figure 39. VOUT Start-Up Time After VEN Rising
at Various Output Voltages, VIN = 5 V, CBYP = 1 μF
3.5
SLEW RATE = 1V/µs
3.0
VIN
VEN
1µF
4.7µF
10µF
VOUT (V)
2.5
VOUT
2.0
1.5
2
1.0
1
CH1 1.00V BW CH2 5.00mV
B
W
M10.0µs A CH1
T 21.10%
0
–2
4.42A
12896-042
12896-039
0.5
0
2
4
6
8
10
12
14
16
TIME (ms)
Figure 40. VOUT Start-Up Time Behavior at Various Values of CBYP,
VOUT = 3.3 V
Figure 37. Line Transient Response, 1 V Input Step, ILOAD = 2 A,
VOUT = 3.3 V, VIN = 3.8 V, Channel 1 = VIN, Channel 2 = VOUT
Rev. A | Page 12 of 22
Data Sheet
ADP7158
THEORY OF OPERATION
The ADP7158 is an ultralow noise, high PSRR linear regulator
targeting radio frequency (RF) applications. The input voltage
range is 2.3 V to 5.5 V, and it can deliver up to 2 A of load
current. Typical shutdown current consumption is 0.2 μA at
room temperature.
Optimized for use with 10 μF ceramic capacitors, the ADP7158
provides excellent transient performance.
The ADP7158 uses the EN pin to enable and disable the VOUT pin
under normal operating conditions. When EN is high, VOUT
turns on, and when EN is low, VOUT turns off. For automatic
startup, tie EN to VIN.
VOUT
INTERNAL
REGULATOR
CURRENT-LIMIT,
THERMAL
PROTECTION
VIN
VOUT_SENSE
7V
VREG
4V
REF
GND (EPAD)
REF_SENSE
BYP
REFERENCE
OTA
4V
BYP
4V
VOUT
SHUTDOWN
REF
EN
12896-043
REF_SENSE
4V
VOUT_SENSE
EN
7V
4V 4V 4V 4V 4V 4V 7V
GND (EPAD)
Figure 41. Simplified Internal Block Diagram
Internally, the ADP7158 consists of a reference, an error amplifier,
and a P-channel MOSFET pass transistor. Output current is
delivered via the PMOS pass device, which is controlled by the
error amplifier. The error amplifier compares the reference
voltage with the feedback voltage from the output and amplifies
the difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the gate of
the PMOS device is pulled higher, allowing less current to pass
and decreasing the output voltage.
12896-044
VIN
VREG
By heavily filtering the reference voltage, the ADP7158 can achieve
1.7 nV/√Hz typical output noise spectral density from 10 kHz
to 1 MHz. Because the error amplifier is always in unity gain,
the output noise is independent of the output voltage.
Figure 42. Simplified ESD Protection Block Diagram
The ESD protection devices are shown in the block diagram as
Zener diodes (see Figure 42).
Rev. A | Page 13 of 22
ADP7158
Data Sheet
APPLICATIONS INFORMATION
ADIsimPOWER DESIGN TOOL
Input and VREG Capacitor
The ADP7158 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs optimized for a specific design goal. These tools
enable the user to generate a full schematic, bill of materials,
and calculate performance within minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and device count,
taking into consideration the operating conditions and limitations of the IC and all real external components. For more
information about, and to obtain the ADIsimPower design
tools, visit www.analog.com/ADIsimPower.
Connecting a 10 μF capacitor from VIN to ground reduces the
circuit sensitivity to PCB layout, especially when long input
traces or high source impedance are encountered.
CAPACITOR SELECTION
BYP Capacitor
Multilayer ceramic capacitors (MLCCs) combine small size, low
ESR, low ESL, and wide operating temperature range, making
them an ideal choice for bypass capacitors. They are not without
faults, however. Depending on the dielectric material, the
capacitance can vary dramatically with temperature, dc bias,
and ac signal level. Therefore, selecting the proper capacitor
results in the best circuit performance.
The BYP capacitor, CBYP, is necessary to filter the reference
buffer. A 1 μF capacitor is typically connected between BYP and
ground. Capacitors as small as 0.1 μF can be used; however, the
output noise voltage of the LDO increases as a result.
The ADP7158 is designed for operation with ceramic capacitors
but functions with most commonly used capacitors when care
is taken with regard to the ESR value. The ESR of the output
capacitor affects the stability of the LDO control loop. A
minimum of 10 μF capacitance with an ESR of 0.1 Ω or less is
recommended to ensure the stability of the ADP7158. Output
capacitance also affects transient response to changes in load
current. Using a larger value of output capacitance improves the
transient response of the ADP7158 to large changes in load
current. Figure 43 shows the transient responses for an output
capacitance value of 10 μF.
REF Capacitor
The REF capacitor, CREF, is necessary to stabilize the reference
amplifier. Connect at 1 μF or greater capacitor between REF and
ground.
In addition, the BYP capacitor value can be increased to reduce
the noise below 1 kHz at the expense of increasing the start-up
time of the LDO regulator. Very large values of CBYP significantly reduce the noise below 10 Hz. Tantalum capacitors are
recommended for capacitors larger than approximately 33 μF
because solid tantalum capacitors are less prone to microphonic
noise issues. A 1 μF ceramic capacitor in parallel with the larger
tantalum capacitor is recommended to ensure good noise
performance at higher frequencies.
SLEW RATE = 3A/µs
IOUT
2.0
1.8
1.6
OUTPUT NOISE (µV rms)
Output Capacitor
To maintain the best possible stability and PSRR performance,
connect a 1 μF or greater capacitor from VREG to ground.
10Hz TO 100kHz
1.4
1.2
1.0
100Hz TO 100kHz
0.8
0.6
12896-046
0.4
1
0.2
0
1
10
100
CBYP (µF)
2
VOUT
12896-045
Figure 44. RMS Noise vs. Bypass Capacitance (CBYP)
CH1 1.00A
CH2 10.0mV
B
W M4.00µs
A CH1
1.00A
T 21.90%
Figure 43. Output Transient Response, VOUT = 3.3 V, COUT = 10 μF,
Channel 1 = Load Current, Channel 2 = VOUT
Rev. A | Page 14 of 22
1000
Data Sheet
ADP7158
CBYP
CBYP
CBYP
CBYP
100
Use Equation 1 to determine the worst case capacitance
accounting for capacitor variation over temperature,
component tolerance, and voltage.
= 1µF
= 10µF
= 100µF
= 1000µF
CEFF = CBIAS × (1 − tempco) × (1 − TOL)
1
0.1
10
(1)
where:
CEFF is the worst case capacitance.
CBIAS is the effective capacitance at the operating voltage.
tempco is the worst case capacitor temperature coefficient.
TOL is the worst case component tolerance.
10
12896-047
NOISE SPECTRAL DENSITY (nV/√Hz)
1k
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 45. Noise Spectral Density vs. Frequency at Various CBYP Values
In this example, the worst case temperature coefficient (tempco)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
CBIAS is 9.72 μF at 5 V, as shown in Figure 46.
Substituting these values in Equation 1 yields
Capacitor Properties
CEFF = 9.72 μF × (1 − 0.15) × (1 − 0.1) = 7.44 μF
Any good quality ceramic capacitors can be used with the
ADP7158 if they meet the minimum capacitance and maximum
ESR requirements. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with
a voltage rating of 6.3 V to 50 V are recommended. However,
Y5V and Z5U dielectrics are not recommended because of their
poor temperature and dc bias characteristics.
Figure 46 depicts the capacitance vs. dc bias voltage of a 1206,
10 μF, 10 V, X5R capacitor. The voltage stability of a capacitor is
strongly influenced by the capacitor size and voltage rating. In
general, a capacitor in a larger package or higher voltage rating
exhibits better stability. The temperature variation of the X5R
dielectric is ~±15% over the −40°C to +85°C temperature range
and is not a function of package or voltage rating.
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP7158, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
UNDERVOLTAGE LOCKOUT (UVLO)
The ADP7158 also incorporates an internal UVLO circuit to
disable the output voltage when the input voltage is less than the
minimum input voltage rating of the regulator. The upper and
lower thresholds are internally fixed with 200 mV (typical) of
hysteresis.
2.5
+125°C
+25°C
–40°C
2.0
VOUT (V)
12
1.0
8
0
1.9
4
12896-049
0.5
6
2.0
2.1
2.2
2.3
VIN (V)
2
Figure 47. Typical UVLO Behavior at Various Temperatures, VOUT = 3.3 V
0
0
2
4
6
8
DC BIAS VOLTAGE (V)
Figure 46. Capacitance vs. DC Bias Voltage
10
12896-048
CAPACITANCE (µF)
10
1.5
Figure 47 shows the typical behavior of the UVLO function.
This hysteresis prevents on/off oscillations that can occur when
caused by noise on the input voltage as it passes through the
threshold points.
Rev. A | Page 15 of 22
ADP7158
Data Sheet
1.250
PROGRAMMABLE PRECISION ENABLE
EN RISING
1.200
1.175
1.150
EN FALLING
1.125
1.100
2.5
3.5
–40°C
–5°C
25°C
85°C
125°C
3.0
4.0
4.5
5.0
5.5
Figure 50. Typical EN Precision Threshold vs. Input Voltage (VIN)
The upper and lower thresholds are user programmable and can
be set higher than the nominal 1.22 V threshold by using two
resistors. Determine the resistance values, REN1 and REN2, from
2.0
1.5
REN1 = REN2 × (VEN − 1.22 V)/1.22 V
12896-050
0.5
0
1.00
1.05
1.10
1.15
1.20
EN PIN VOLTAGE (V)
1.25
The hysteresis voltage increases by the factor
(REN1 + REN2)/REN2
For the example shown in Figure 51, the EN threshold is 2.44 V
with a hysteresis of 200 mV.
3.5
3.0
where:
REN2 typically ranges from 10 kΩ to 100 kΩ.
VEN is the desired turn-on voltage.
1.30
Figure 48. Typical VOUT Response to EN Pin Operation
VIN = 3.8V
VEN
VOUT
2.5
ON
2.0
OFF
REN1
100kΩ
REN2
100kΩ
CIN
10µF
CBYP
1µF
1.0
CREG
1µF
12896-051
0.5
–2
–1
0
1
2
3
4
5
6
7
TIME (ms)
Figure 49. Typical VOUT Response to EN Pin Operation (VEN),
VOUT = 3.3 V, VIN = 5 V, CBYP = 1 μF
8
ADP7158
VIN
VOUT
VOUT = 3.3V
VOUT_SENSE
EN
1.5
0
3.5
INPUT VOLTAGE (V)
1.0
VOUT (V)
3.0
BYP
REF
REF_SENSE
COUT
10µF
CREF
1µF
VREG
GND
12896-053
VOUT (V)
2.5
12896-052
The ADP7158 includes a discharge resistor on each VOUT,
VREG, REF, and BYP pin. These resistors turn on when the
device is disabled, which helps to discharge the associated
capacitor very quickly.
1.225
EN PRECISION THRESHOLD (V)
The ADP7158 uses the EN pin to enable and disable the VOUT pin
under normal operating conditions. As shown in Figure 48, when a
rising voltage on EN crosses the upper threshold, nominally
1.22 V, VOUT turns on. When a falling voltage on EN crosses the
lower threshold, nominally 1.13 V, VOUT turns off. The hysteresis
of the EN threshold is typically 90 mV.
Figure 51. Typical EN Pin Voltage Divider
Figure 51 shows the typical voltage divider configuration of the
EN pin. This configuration prevents on/off oscillations that can
occur due to noise on the EN pin as it passes through the
threshold points.
Rev. A | Page 16 of 22
Data Sheet
ADP7158
START-UP TIME
CURRENT-LIMIT AND THERMAL SHUTDOWN
The ADP7158 uses an internal soft start to limit the inrush current
when the output is enabled. The start-up time for a 3.3 V output is
approximately 1.2 ms from the time the EN active threshold is
crossed to when the output reaches 90% of its final value.
The ADP7158 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP7158 is designed to current limit when the
output load reaches 3 A (typical). When the output load exceeds
3 A, the output voltage is reduced to maintain a constant current
limit.
The rise time in seconds of the output voltage (10% to 90%) is
approximately
When the ADP7158 junction temperature exceeds 150°C, the
thermal shutdown circuit turns off the output voltage, reducing
the output current to zero. Extreme junction temperature can be
the result of high current operation, poor circuit board design or
high ambient temperature. A 15°C hysteresis is included so that
the ADP7158 does not return to operation after thermal shutdown
until the on-chip temperature falls below 135°C. When the
device exits thermal shutdown, a soft start is initiated to reduce
the inrush current.
0.0012 × CBYP
where CBYP is measured in microfarads.
3.5
3.0
VEN
1µF
4.7µF
10µF
VOUT (V)
2.5
2.0
1.5
1.0
0
–2
12896-054
0.5
0
2
4
6
8
10
12
14
16
18
20
TIME (ms)
3.5
3.0
VOUT (V)
2.5
2.0
1.5
VEN
10µF
47µF
100µF
0
–20
12896-055
0.5
0
20
40
60
80
100
120
140
THERMAL CONSIDERATIONS
In applications with a low input to output voltage differential,
the ADP7158 does not dissipate much heat. However, in applications with high ambient temperature and/or high input voltage,
the heat dissipated in the package may become large enough
that it causes the junction temperature of the die to exceed the
maximum junction temperature of 125°C.
Figure 52. Typical Start-Up Behavior with CBYP = 1 μF to 10 μF
1.0
Current limit and thermal shutdown protections are intended to
protect the device against accidental overload conditions. For
example, a hard short from VOUT to ground or an extremely
long soft start timer usually causes thermal oscillations between
the current limit and thermal shutdown.
160
TIME (ms)
Figure 53. Typical Start-Up Behavior with CBYP = 10 μF to 100 μF
REF, BYP, AND VREG PINS
REF, BYP, and VREG generate voltages internally (VREF, VBYP,
and VREG) that require external bypass capacitors for proper
operation. Do not, under any circumstances, connect any loads
to these pins, because doing so compromises the noise and
PSRR performance of the ADP7158. Using larger values of CBYP,
CREF, and CREG is acceptable but can increase the start-up time,
as described in the Start-Up Time section.
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to the power dissipation, as shown in Equation 2.
To guarantee reliable operation, the junction temperature of the
ADP7158 must not exceed 125°C. To ensure that the junction
temperature stays below this maximum value, the user must be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances between
the junction and ambient air (θJA). The θJA number is dependent
on the package assembly compounds that are used and the
amount of copper used to solder the exposed pad (ground) to
the PCB.
Rev. A | Page 17 of 22
ADP7158
Data Sheet
80
60
6400mm 2
500mm 2
25mm 2
TJ MAX
40
20
0
0
Device soldered to minimum size pin traces.
Figure 54. Junction Temperature vs. Total Power Dissipation for
the 10-Lead LFCSP, TA = 25°C
Table 8. Typical ΨJB Values
140
ΨJB (°C/W)
29.1
30.1
Calculate the junction temperature (TJ) of the ADP7158 from
the following equation:
TJ = TA + (PD × θJA)
(2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = ((VIN − VOUT) × ILOAD) + (VIN × IGND)
JUNCTION TEMPERATURE (°C)
Package
10-Lead LFCSP
8-Lead SOIC
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
TOTAL POWER DISSIPATION (W)
(3)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
100
80
60
6400mm 2
500mm 2
25mm 2
TJ MAX
40
20
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6
TOTAL POWER DISSIPATION (W)
Figure 55. Junction Temperature vs. Total Power Dissipation for
the 10-Lead LFCSP, TA = 50°C
(4)
As shown in Equation 4, for a given ambient temperature, input
to output voltage differential, and continuous load current, a
minimum copper size requirement exists for the PCB to ensure
that the junction temperature does not rise above 125°C.
The heat dissipation from the package can be improved by increasing the amount of copper attached to the pins and exposed pad
of the ADP7158. Adding thermal planes underneath the package
also improves thermal performance. However, as shown in Table 7,
a point of diminishing returns is eventually reached, beyond
which an increase in the copper area does not yield significant
reduction in the junction to ambient thermal resistance.
130
125
JUNCTION TEMPERATURE (°C)
Power dissipation caused by ground current is quite small and
can be ignored. Therefore, the junction temperature equation
simplifies to the following:
TJ = TA + (((VIN − VOUT) × ILOAD) × θJA)
120
Figure 54 to Figure 59 show junction temperature calculations
for various ambient temperatures, power dissipation, and areas
of PCB copper.
Rev. A | Page 18 of 22
120
115
110
105
100
6400mm 2
500mm 2
25mm 2
TJ MAX
95
90
12896-058
1
100
12896-057
Copper Size (mm2)
251
100
500
1000
6400
θJA (°C/W)
10-Lead LFCSP
8-Lead SOIC
130.2
123.8
93.0
90.4
65.8
66.0
55.6
56.6
44.1
45.5
120
12896-056
Table 7. Typical θJA Values
140
JUNCTION TEMPERATURE (°C)
Table 7 shows the typical θJA values of the 8-lead SOIC and
10-lead LFCSP packages for various PCB copper sizes. Table 8
shows the typical ΨJB values of the 8-lead SOIC and 10-lead
LFCSP.
85
80
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
TOTAL POWER DISSIPATION (W)
0.9
1.0
Figure 56. Junction Temperature vs. Total Power Dissipation for
the 10-Lead LFCSP, TA = 85°C
Data Sheet
ADP7158
140
Thermal Characterization Parameter (ΨJB)
When the evaluation board temperature is known, use the
thermal characterization parameter, ΨJB, to estimate the junction
temperature rise (see Figure 60 and Figure 61). Calculate the
maximum junction temperature (TJ) from the evaluation board
temperature (TB) and power dissipation (PD) using the following
formula:
100
80
60
TJ = TB + (PD × ΨJB)
6400mm 2
500mm 2
25mm 2
TJ MAX
20
0
0
0.2
0.4
0.6 0.8 1.0 1.2 1.4 1.6 1.8
TOTAL POWER DISSIPATION (W)
2.0
2.2
120
130
120
110
100
90
100
80
TB = 85°C
TB = 65°C
TB = 50°C
TB = 25°C
TJ MAX
60
40
80
0
6400mm 2
500mm 2
25mm 2
TJ MAX
70
60
0
0.4
0.6
0.8
1.0
1.2
1.4
TOTAL POWER DISSIPATION (W)
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Figure 60. Junction Temperature vs. Total Power Dissipation for
the 10-Lead LFCSP
12896-060
40
0.2
0.5
TOTAL POWER DISSIPATION (W)
50
0
12896-062
20
1.6
140
1.8
120
JUNCTION TEMPERATURE (°C)
Figure 58. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 50°C
130
125
120
115
110
100
80
TB = 85°C
TB = 65°C
TB = 50°C
TB = 25°C
TJ MAX
60
40
20
12896-063
JUNCTION TEMPERATURE (°C)
140
2.4
Figure 57. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 25°C
105
0
100
0
6400mm 2
500mm 2
25mm 2
TJ MAX
95
90
85
80
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
TOTAL POWER DISSIPATION (W)
0.9
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TOTAL POWER DISSIPATION (W)
Figure 61. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC
12896-061
JUNCTION TEMPERATURE (°C)
(5)
The typical value of ΨJB is 29.1°C/W for the 10-lead LFCSP
package and 30.1°C/W for the 8-lead SOIC package.
JUNCTION TEMPERATURE (°C)
40
12896-059
JUNCTION TEMPERATURE (°C)
120
1.0
Figure 59. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 85°C
Rev. A | Page 19 of 22
ADP7158
Data Sheet
PRINTED CIRCUIT BOARD (PCB) LAYOUT CONSIDERATIONS
12896-065
Place the input capacitor as close as possible between the
VIN pin and ground. Place the output capacitor as close as possible
between the VOUT pin and ground. Place the bypass capacitors
(CREG, CREF, and CBYP) for VREG, VREF, and VBYP close to the respective pins (VREG, REF, and BYP) and ground. The use of a 0805,
0603, or 0402 size capacitor achieves the smallest possible
footprint solution on boards where area is limited. Maximize
the amount of ground metal for the exposed pad, and use as
many vias as possible on the component side to improve thermal
dissipation.
12896-064
Figure 63. Sample 8-Lead SOIC PCB Layout
Figure 62. Sample 10-Lead LFCSP PCB Layout
Rev. A | Page 20 of 22
Data Sheet
ADP7158
OUTLINE DIMENSIONS
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1 INDEX
AREA
1.74
1.64
1.49
EXPOSED
PAD
0.50
0.40
0.30
1
5
SEATING
PLANE
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.30
0.25
0.20
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-05-2013-C
0.80
0.75
0.70
0.20 MIN
PIN 1
INDICATOR
(R 0.15)
BOTTOM VIEW
TOP VIEW
0.20 REF
Figure 64. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters
5.00
4.90
4.80
2.29
0.356
5
1
4
6.20
6.00
5.80
4.00
3.90
3.80
2.29
0.457
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
BOTTOM VIEW
1.27 BSC
3.81 REF
TOP VIEW
1.65
1.25
1.75
1.35
SEATING
PLANE
0.51
0.31
0.50
0.25
0.10 MAX
0.05 NOM
COPLANARITY
0.10
8°
0°
45°
0.25
0.17
1.04 REF
1.27
0.40
COMPLIANT TO JEDEC STANDARDS MS-012-A A
Figure 65. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters
Rev. A | Page 21 of 22
06-02-2011-B
8
ADP7158
Data Sheet
ORDERING GUIDE
Model1, 2
ADP7158ACPZ-1.2-R7
ADP7158ACPZ-1.8-R7
ADP7158ACPZ-2.0-R7
ADP7158ACPZ-2.5-R7
ADP7158ACPZ-2.8-R7
ADP7158ACPZ-3.0-R7
ADP7158ACPZ-3.3-R7
ADP7158ARDZ-1.2-R7
ADP7158ARDZ-1.8-R7
ADP7158ARDZ-2.0-R7
ADP7158ARDZ-2.5-R7
ADP7158ARDZ-2.8-R7
ADP7158ARDZ-3.0-R7
ADP7158ARDZ-3.3-R7
ADP7158CP-3.3EVALZ
1
2
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Output Voltage (V)
1.2
1.8
2.0
2.5
2.8
3.0
3.3
1.2
1.8
2.0
2.5
2.8
3.0
3.3
Package Description
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
Evaluation Board
Package Option
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
Branding
LSL
LSM
LTR
LSN
LSP
LSQ
LSR
Z = RoHS Compliant Part.
To order a device with voltage options of 1.3 V, 1.5 V, 1.6 V, 2.2 V, 2.6 V, 2.7 V, 2.9 V, 3.1 V, and 3.2 V, contact your local Analog Devices, Inc., sales or distribution
representative.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12896-0-5/16(A)
Rev. A | Page 22 of 22