BSI Very Low Power/Voltage CMOS SRAM 128K X 8 bit BS62LV1024 DESCRIPTION FEATURES • Wide Vcc operation voltage : 2.4V ~ 5.5V • Very low power consumption : Vcc = 3.0V C-grade : 20mA (Max.) operating current I- grade : 25mA (Max.) operating current 0.02uA (Typ.) CMOS standby current Vcc = 5.0V C-grade : 35mA (Max.) operating current I- grade : 40mA (Max.) operating current 0.4uA (Typ.) CMOS standby current • High speed access time : -70 70ns (Max.) at Vcc = 3.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE2, CE1, and OE options The BS62LV1024 is a high performance, very low power CMOS Static Random Access Memory organized as 131,072 words by 8 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.02uA and maximum access time of 70ns in 3V operation. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The BS62LV1024 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV1024 is available in DICE form, JEDEC standard 32 pin 450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP, 8mmx13.4mm STSOP and 8mmx20mm TSOP. PRODUCT FAMILY PRODUCT F A M ILY O P E R AT IN G T E M P E R AT U R E Vcc RANGE SPEED (n s ) V cc=3V B S 6 2 LV 1 0 2 4 S C B S 6 2 LV 1 0 2 4 T C B S 6 2 LV 1 0 2 4 S T C B S 6 2 LV 1 0 2 4 P C B S 6 2 LV 1 0 2 4 J C B S 6 2 LV 1 0 2 4 D C B S 6 2 LV 1 0 2 4 S I B S 6 2 LV 1 0 2 4 T I B S 6 2 LV 1 0 2 4 S T I B S 6 2 LV 1 0 2 4 P I B S 6 2 LV 1 0 2 4 J I B S 6 2 LV 1 0 2 4 D I + 0 O C to + 7 0 O C V cc=3V 3 .0 u A 1 .0 u A 35m A 20m A -4 0 O C to + 8 5 O C 2 .4 V ~ 5 .5 V 70 5 .0 u A 1 .5 u A 40m A 25m A • 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PKG TYPE (Ic c , M a x ) V cc=5V 70 32 31 30 29 28 BS62LV1024SC 27 BS62LV1024SI 26 BS62LV1024PC 25 BS62LV1024PI 24 BS62LV1024JC BS62LV1024JI 23 22 21 20 19 18 17 • A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ( Ic c S B 1 , M a x ) Vcc=5V V cc=3V 2 .4 V ~ 5 .5 V PIN CONFIGURATIONS NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND P O W E R D IS S IPAT IO N S ta n d b y O p e r a tin g BS62LV1024TC BS62LV1024STC BS62LV1024TI BS62LV1024STI S O P -3 2 T S O P -3 2 S T S O P -3 2 P D IP -3 2 S O J -3 2 D IC E S O P -3 2 T S O P -3 2 S T S O P -3 2 P D IP -3 2 S O J -3 2 D IC E BLOCK DIAGRAM VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A6 A7 A12 A14 A16 A15 A13 A8 A9 A11 Address Input Buffer 20 Row 1024 Memory Array 1024 x 1024 Decoder 1024 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 CE2 CE1 WE OE Vdd Gnd 8 8 Data Input Buffer Data Output Buffer Column I/O 8 8 Write Driver Sense Amp 128 Column Decoder 14 Control Address Input Buffer A5 A4 A3 A2 A1 A0 A10 Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. R0201-BS62LV1024 1 Revision 2.2 April 2001 BSI BS62LV1024 PIN DESCRIPTIONS Name Function A0-A16 Address Input These 17 address inputs select one of the 131,072 x 8-bit words in the RAM CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. DQ0-DQ7 Data Input/Output Ports These 8 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground TRUTH TABLE MODE WE CE1 CE2 OE Not selected (Power Down) X H X X X X L X Output Disabled H L H Read H L Write L L PARAMETER ICCSB, I CCSB1 H High Z I CC H L D OUT I CC H X D IN I CC OPERATING RANGE RATING UNITS -0.5 to Vcc+0.5 V V TERM Terminal Voltage with Respect to GND T BIAS Temperature Under Bias -40 to +125 O C T STG Storage Temperature -60 to +150 O C PT Power Dissipation 1.0 W I OUT DC Output Current 20 mA RANGE Commercial Industrial AMBIENT TEMPERATURE O O 0 C to +70 C O O -40 C to +85 C Vcc 2.4V ~ 5.5V 2.4V ~ 5.5V CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. R0201-BS62LV1024 Vcc CURRENT High Z ABSOLUTE MAXIMUM RATINGS(1) SYMBOL I/O OPERATION 2 CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V 6 pF VI/O=0V 8 pF 1. This parameter is guaranteed and not tested. Revision 2.2 April 2001 BSI BS62LV1024 DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC ) PARAMETER NAME VIL VIH PARAMETER Guaranteed Input Low Voltage(2) Guaranteed Input High Voltage(2) Vcc=3.0V Vcc=5.0V Vcc = Max, VIN = 0V to Vcc IOL Output Leakage Current Vcc = Max, CE1= VIH, CE2= VIL, or OE = VIH, VI/O = 0V to Vcc Output Low Voltage -- 0.8 V 2.0 2.2 -- Vcc+0.2 V -- -- 1 uA -- -- 1 uA -- -- 0.4 V 2.4 -- -- V Vcc=5.0V Input Leakage Current Vcc = Max, IOL = 2mA UNITS -0.5 Vcc=3.0V IIL VOL MIN. TYP. (1) MAX. TEST CONDITIONS Vcc=3.0V Vcc=5.0V Vcc=3.0V VOH Output High Voltage Vcc = Min, IOH = -1mA ICC Operating Power Supply Current CE1 = VIL, or CE2 = VIH, IDQ = 0mA, F = Fmax(3) Vcc=3.0V -- -- 20 Vcc=5.0V -- -- 35 ICCSB Standby Current-TTL CE1 = VIH, or CE2 = VIL, IDQ = 0mA, F = Fmax(3) Vcc=3.0V -- -- 1 Vcc=5.0V -- -- 2 ICCSB1 Standby Current-CMOS CE1ЊVcc-0.2V, CE2Љ0.2V, VINЊVcc-0.2V or VINЉ0.2V Vcc=3.0V -- 0.02 1 Vcc=5.0V -- 0.4 3 Vcc=5.0V mA mA uA 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC ) SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS VDR Vcc for Data Retention CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V, VIN Њ Vcc - 0.2V or VIN Љ 0.2V 1.5 -- -- V ICCDR Data Retention Current CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V, VIN Њ Vcc - 0.2V or VIN Љ 0.2V -- 0.02 0.3 uA tCDR Chip Deselect to Data Retention Time 0 -- -- ns -- -- ns tR See Retention Waveform Operation Recovery Time TRC (2) 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled ) Data Retention Mode Vcc VDR ≥ 1.5V Vcc CE1 Vcc tR t CDR CE1 ≥ Vcc - 0.2V VIH LOW VCC DATA RETENTION WAVEFORM (2) VIH ( CE2 Controlled ) Data Retention Mode Vcc VDR Њ 1.5V Vcc CE2 R0201-BS62LV1024 VIL Vcc tR t CDR CE2 Љ 0.2V 3 VIL Revision 2.2 April 2001 BSI BS62LV1024 KEY TO SWITCHING WAVEFORMS AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0V 5ns WAVEFORM INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L 1269 Ω MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H 5PF DON T CARE: ANY CHANGE PERMITTED CHANGE : STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE 0.5Vcc AC TEST LOADS AND WAVEFORMS 1269 Ω 3.3V 3.3V , OUTPUT OUTPUT 100PF INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE 1404 Ω 1404 Ω FIGURE 1A FIGURE 1B THEVENIN EQUIVALENT 667 Ω OUTPUT 1.73V ALL INPUT PULSES Vcc GND 10% → 10% 90% 90% → ← ← 5ns FIGURE 2 AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc=3.0V ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME tAVAX tAVQV t E1LQV t E2HOV tGLQV t E1LQX t E2HOX tGLQX t E1HQZ tE2HQZ tGHQZ t RC t AA t ACS1 t ACS2 t OE t CLZ1 t CLZ2 t OLZ t CHZ1 t CHZ2 t OHZ tAXOX t OH R0201-BS62LV1024 BS62LV1024-70 MIN. TYP. MAX. DESCRIPTION 70 Read Cycle Time -- UNIT -- ns -- -- 70 ns Chip Select Access Time (CE1) -- -- 70 ns Chip Select Access Time (CE2) -- -- 70 ns -- -- 50 ns Address Access Time Output Enable to Output Valid Chip Select to Output Low Z (CE1) 10 -- -- ns Chip Select to Output Low Z (CE2) 10 -- -- ns 10 -- -- ns Chip Deselect to Output in High Z (CE1) 0 -- 40 ns Chip Deselect to Output in High Z (CE2) 0 Output Enable to Output in Low Z 40 Output Disable to Output in High Z 0 -- 35 ns Output Disable to Address Change 10 -- -- ns 4 Revision 2.2 April 2001 BSI BS62LV1024 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t t t OH AA OH D OUT READ CYCLE2 (1,3,4) CE1 CE2 t t ACS1 t ACS2 t (5) (5) CHZ1, t CHZ2 CLZ D OUT READ CYCLE3 (1,4) t RC ADDRESS t AA OE t t CE1 t CE2 (5) t OH OLZ t ACS1 CLZ1 t t OE t OHZ (5) (1,5) t CHZ1 ACS2 t (5) (2,5) CHZ2 CLZ2 D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL . 5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. R0201-BS62LV1024 5 Revision 2.2 April 2001 BSI BS62LV1024 AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc=3.0V ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME BS62LV1024-70 MIN. TYP. MAX. DESCRIPTION UNIT tAVAX tWC Write Cycle Time 70 -- -- ns tE1LWH tCW Chip Select to End of Write 70 -- -- ns tAVWL tAS Address Set up Time 0 -- -- ns tAVWH tAW Address Valid to End of Write 70 -- -- ns tWLWH tWP Write Pulse Width 50 -- -- ns tWHAX tWR1 Write Recovery Time (CE1 , WE) 0 -- -- ns tE2LAX tWR2 Write Recovery Time (CE2) 0 -- -- ns tWLOZ tWHZ Write to Output in High Z 0 -- 30 ns tDVWH tDW Data to Write Time Overlap 30 -- -- ns tWHDX tDH Data Hold from Write Time 0 -- -- ns tGHOZ tOHZ Output Disable to Output in High Z 0 -- 30 ns tWHQX tOW End of Write to Output Active 5 -- -- ns SWITCHING WAVEFORMS (WRITE CYCLE) t WC WRITE CYCLE1 (1) ADDRESS t (3) WR1 OE (11) t CW (5) CE1 (5) CE2 t CW t WE (11) t WR2 AW t t AS (3) WP (2) (4,10) t OHZ D OUT t DH t DW D IN R0201-BS62LV1024 6 Revision 2.2 April 2001 BSI BS62LV1024 WRITE CYCLE2 (1,6) t WC ADDRESS (11) t (5) CW CE1 CE2 (5) (11) t t CW AW t WR2 t WP (3) (2) WE t t AS DH (4,10) t WHZ D OUT (7) (8) t DW t DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write. R0201-BS62LV1024 7 Revision 2.2 April 2001 BSI BS62LV1024 ORDERING INFORMATION BS62LV1024 X X ˀˀ Y Y SPEED 70: 70ns GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE J: SOJ S: SOP P: PDIP T: TSOP (8mm x 20mm) ST: Small TSOP (8mm x 13.4mm) D: DICE PACKAGE DIMENSIONS WITH PLATING b c c1 BASE METAL b1 SECTION A-A SOP -32 R0201-BS62LV1024 8 Revision 2.2 April 2001 BSI BS62LV1024 PACKAGE DIMENSIONS (continued) STSOP - 32 TSOP - 32 R0201-BS62LV1024 9 Revision 2.2 April 2001 BSI BS62LV1024 PACKAGE DIMENSIONS (continued) PDIP - 32 SOJ - 32 R0201-BS62LV1024 10 Revision 2.2 April 2001 BSI BS62LV1024 REVISION HISTORY Revision Description Date 2.2 2001 Data Sheet release Apr. 15, 2001 R0201-BS62LV1024 11 Note Revision 2.2 April 2001