ETC2 C2471 Rdfc controllers for offline applications up to 6 w Datasheet

C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
ADVANTAGES






Low system component count
High average efficiency
Low no load power consumption
EMI compliance without extra components
High isolation & surge voltage withstand
High power density in very small size
C2471LW1
PDIP-8
C2471LX2
SOT23-6
FEATURES






Highly integrated CMOS controller IC
Low cost package options
Drive suitable for low cost bipolar power transistors
Resonant switching for high efficiency and low EMI
Frequency optimised for power circuit parasitics
Protection against overload, over-temperature and under-voltage
APPLICATIONS
External AC/DC charger/adapter (single voltage input) e.g. cordless phones, low power adapters.
Embedded PSU (single voltage input), audio products, domestic appliances.
OVERVIEW
The C2471 controllers use CamSemi’s low power Resonant Discontinuous Forward Converter (RDFC)
topology to create a high efficiency, low cost alternative to line-frequency transformer PSUs, for applications
up to 6 W. By operating in resonant mode, EMI is greatly reduced, enabling the replacement of linear PSUs
in demanding applications such as audio products and cordless phone chargers. The C2471 controllers also
offer overload protection which is usually associated with more expensive switch mode solutions.
AUX
VDD
Vdd
Switch
saturation
sensing
Vdd
regulator
Base
drive
COL
Resonance
sensing
CS
Current
sensing
RDFC
Control
BAS
GND
Figure 1: Block Diagram of the C2471 Controller ICs
Product data
© Cambridge Semiconductor Ltd 2008
Page 1 of 18
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02-May-2008
C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
PIN DEFINITIONS
C2471LW1
PDIP-8
C2471LX2
SOT23-6
BAS
1
6
AUX
GND
2
5
VDD
4
CS
COL
3
GND
1
8
COL
NC
2
7
CS
NC
3
6
VDD
BAS
4
5
AUX
Figure 2: C2471 Pin Assignment
(drawings are not to scale)
VDD Pin
The VDD pin supplies power to the controller and is maintained at the correct voltage (nominally 3.3 V) by an
internal shunt regulator.
COL Pin
The COL pin is used to sense the collector voltage of the primary switching transistor, via a coupling
capacitor, to control the timing and current levels of the signals produced on the BAS pin.
CS Pin
The CS pin senses the primary switch current via the current sensing resistor. The voltage sensed on this
pin is used to control the operating modes to manage standby and overload protection. Operating
characteristics are programmed via two external resistors.
AUX Pin
The AUX pin provides the supply current for the internal base driver block. The AUX pin is connected to the
external supply rail via a current-limiting resistor to set the maximum base current.
BAS Pin
The BAS pin switches the external bipolar primary switch transistor on and off. The current supplied to the
switch transistor is controlled to minimize the switching losses and thereby help optimize overall system
efficiency.
GND Pin
GND pins provide the ground reference. Where the device has multiple GND pins, all must be connected to
a common, low impedance path.
Product data
© Cambridge Semiconductor Ltd 2008
Page 2 of 18
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C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
TYPICAL APPLICATION CIRCUIT
The C2471 controllers are intended primarily for single input voltage AC/DC applications, such as
replacement of line frequency linear transformer power supplies. These versatile controllers support a wide
range of applications at low cost. A typical circuit configuration is shown in Figure 3.
Csnub
Rsnub
HT
Dbridge
Lfilt
+
Dout
+
Cout
Rht2
Daux
Vauxs
Dcol1
+
+
Cin1
Fuse
Rdd
Caux
Cin2
RDFC
Controller IC
Rfuse
Cdd
VDD
Raux
AUX
GND
COL
CS
BAS
0V
Ccol
Rcol
R2
Q1
Cp
Dcol2
Rcs
Figure 3: Typical Low Power RDFC Application Schematic
Typical Cordless Phone Adapters Using C2471
The RDFC topology and CamSemi’s C2471 controller deliver class-leading performance in cordless phone
charger applications up to 6 W. Here are two examples of what can be typically achieved.
Input
Rated power
Output
110 Vac
230 Vac
6W
3W
9 Vdc, 660 mA
9 Vdc, 330 mA
Transformer core
E13
Average efficiency
80 %
No-load power input
EMI compliance
150 mW
EN 55022 and FCC part 68 (TIA-968-A)
Note: The C2471 controller is rated for applications up to 6 W.
Product data
© Cambridge Semiconductor Ltd 2008
Page 3 of 18
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02-May-2008
C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
PRINCIPLE OF OPERATION
Power-Up/Power-Down Sequences
The C2471 controllers are powered via their VDD pins. When mains voltage is first applied, a small amount
of current (IDDSLEEP) is drawn from the rectified mains input via high value start up resistors (Rht1 and Rht2 in
Figure 3). When the voltage on the VDD pin (VDD) reaches a level VOVDTHR the controller wakes up, demands
more supply current (IDDWAKE) and enters the Start-up state (see Figure 4). The controller stays in Start-up for
a short time during which internal circuit blocks are enabled and then changes to Active operation. In both
Start-up and Active states, the controller uses an internal shunt regulator to regulate the VDD rail voltage; the
regulator is disabled in Sleep. A higher regulation voltage is applied during Start-up (VDDREG(S)) than during
Active operation (VDDREG(R)) to help provide sufficient VDD before the Auxiliary supply from the transformer
rises to maintain VDD.
VDDREG(R)
VDDREG(S)
If the VDD pin voltage drops below VUVDTHR the controller goes back to Sleep, reducing the supply current
demand. The system will restart when input power is restored. To achieve a smooth power up sequence the
VDD reservoir capacitor needs to be large enough to sustain the supply above VUVDTHR over the Start-up
period.
Figure 4: VDD Pin Waveform (VDD) During Initial Power-up and Power-down
State
Description
Sleep
From initial application of power or from Active state if VDD falls below VUVDTHR, the
controller changes to Sleep state. Non-essential controller circuits are powered down
and the external switching transistor (Q1) is held off. Exit from Sleep state occurs when
VDD rises above VOVDTHR and the controller moves to the Start-up state.
Start-up
When the Start-up state is entered, internal controller circuits are activated and power
conversion begins (Standby mode – see Table 2). In Start-up the on-chip shunt
regulator stabilises VDD to an intermediate value, VDDREG(S). After a preset time, the
controller changes from Start-up to Active operation.
Active
Converter operation continues, the shunt regulator controls VDD to the lower VDDREG(R).
If VDD falls below VUVDTHR the controller ceases converter operation and reverts to
Sleep state.
Table 1: Summary of Low Power RDFC Controller States
Product data
© Cambridge Semiconductor Ltd 2008
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C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
Start-up and Active State Power Conversion Modes
In the Start-up and Active states the C2471 ICs have several modes for controlling power conversion that are
designed to achieve maximum efficiency and to limit power (current) across a wide range of loads. Refer to
Table 2 for a summary of each mode.
Mode
Typical Load
Range
Description
Standby
IOUT ≥ 0% to
~20% of rated
current
Standby mode reduces power consumption at low loads. It achieves this by
progressively reducing the on-time then by increasing the off-time as the load
decreases. As load increases, the converter duty is increased until the controller
returns to Normal mode. Typically, mains ripple causes change of operating mode
during each mains half-cycle, with the converter moving to lower-power modes
between peaks of the mains voltage.
Normal
IOUT > ~20% to
100% of rated
current
Normal mode is used for steady state power delivery. During Normal mode the power
device switches in a fully resonant minimum-voltage-switching waveform, with the offtime determined by the transformer resonance (TRES) and the on-time being equal to
75% of the off time. A low level of primary switch current, sensed via the CS pin
voltage, causes the controller to change to Standby mode and a high level to Overload
mode.
Overload
IOUT >~100%
rated current
Overload mode is activated at high output loads. In this mode the on-time of the
primary switch is terminated early (before 75% of TRES) when the primary current
exceeds a preset maximum, thereby protecting the primary switch and limiting the
output current. This results in reduction of the output voltage. Heavy overload (sensed
by the on-period of the primary switch reducing below a preset time) causes Foldback
mode to be entered.
Foldback
VOUT < ~70%
rated output
Foldback mode is entered from the Overload mode. In this mode the controller reduces
the on/off duty cycle to protect the power supply and any connected load by both
shortening the on-period and increasing the off-period of the primary switch. Converter
cycles continue to maintain auxiliary power to the controller. The controller exits the
Foldback mode and enters the Power Burst mode after a fixed number of power
conversion cycles.
Power
Burst
VOUT < ~70%
rated output
Power Burst mode is entered periodically from Foldback mode in order to restart the
power supply output. In Power Burst mode, the controller operates at maximum
delivered power for a set number of power converter cycles. At the end of the burst, if
the load is not excessive, the converter goes to Normal mode; otherwise it reverts to
Foldback mode.
Table 2: Summary of Active Operating Modes
When the controller goes from Sleep to Start-up state, its power conversion mode is set to Standby. Typically
the converter output voltage is low at this time so the primary switch current is high during the first few
converter cycles. This causes the operating mode to change quickly to Normal or Overload mode.
Product data
© Cambridge Semiconductor Ltd 2008
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C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
Low Power RDFC Power Supply I-V Characteristic
Figure 5 illustrates a typical low power RDFC power supply characteristic with the various Active state
modes of operation identified. INOM and VNOM are the nominal output voltage and current drawn by the load at
the rated power of the application circuit.
VOUT
Axes are labelled with percentage of nominal
application voltage and current output
Standby
Normal
(INOM,VNOM)
100%
Overload
Foldback
50%
Power
Burst
IOUT
Figure 5: Typical Low Power RDFC Power Supply Characteristic
Indicating Different Active Modes of Operation
The exact thresholds for transition between modes depend on specific application characteristics, controller
internal clock frequency (FCLK) and CS pin thresholds (VOCPH and VOCPL). These parameters and their effects
are explained later.
Product data
© Cambridge Semiconductor Ltd 2008
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C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
Switching Waveforms
Overload
Standby
Normal
The collector voltage (VCE) and current (IC) waveforms of the primary switching transistor (Q1 in Figure 3) are
shown in Figure 6. TRES is the duration of the transformer resonance during the off period. Note that in
Overload mode, the primary switch Q1 is turned off when the current exceeds the protection level OCPH
(sensed by the CS pin voltage).
Figure 6: Typical Switch (Q1) Collector Voltage (VCE) and Current (IC) Waveforms
Product data
© Cambridge Semiconductor Ltd 2008
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C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
Resonance Control
The natural resonance of the transformer and associated components is deduced from the current flowing
into and out of the COL pin via the collector coupling capacitor.
The voltage sensed on the COL pin is used to control saturation of the primary switch transistor (Q1 in
Figure 3) during the on-period (see “Optimised Base Drive”). During the off-period, timing of the resonance is
detected via the current in and out of the pin, which has a low impedance path to GND during this time. Rate
of change of voltage at the transformer primary causes current into or out of the COL pin, which is processed
to measure the resonance period TRES and to find the optimum turn-on time for the following conversion
cycle. The resonant period is also used to determine the maximum on-time of the primary switch transistor,
so that
TON = 0.75 x TRES
The maximum duty cycle (DNORMAL) is therefore nominally 43%. On-time of the switch is controlled to manage
power delivery and is reduced in both low-load and overload conditions. The minimum on-time in overload is
determined by the internal CS blanking, specified as TCSBLANK.
At turn-on of the primary switching transistor, its collector voltage can fall very rapidly, with correspondingly
large current out of or in to the COL pin via the coupling capacitor (Ccol). An on-chip clamp transistor,
controlled by an internal signal called ACTICLAMP, provides a low resistance path to GND. This transistor is
turned on shortly before turn-on of the primary switch and remains on until time TACT after turn-on of the
primary switch. It is then turned off during the remainder of the primary switch on-period. In some
applications, the current through the coupling capacitor may develop sufficient voltage across the clamp
transistor to cause conduction of the ESD protection diodes. This is permissible up to a limit ICOL which is
specified in ABSOLUTE MAXIMUM RATINGS. If, due to application design, the capacitor current could
exceed this level, external protection diodes and a resistor must be provided (Dcol1, Dcol2 and Rcol in
Figure 3).
Product data
© Cambridge Semiconductor Ltd 2008
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C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
Optimised Base Drive
To minimize losses in the primary switching transistor (Q1) its base current is carefully controlled. To
minimize turn-on losses, the base current is initially forced to a maximum value IBASMAX for a time TFON (the
force-on or “FON” pulse). For the remainder of the on-time the base current is reduced to a lower value such
that the on-state collector voltage is maintained at a preset target voltage, thereby minimizing turn-off time
and consequent losses. During this period, TPBD, the so called “proportional base drive” (PBD) current is
referred to as IBASPBD.
Aux Supply
Bypass transistor
Raux
AUX
Qon
PBD
BAS
Q1
FON
TPBD
Qoff
GND
0V
Figure 7: Primary Switch (Q1) Base Drive
The BAS pin (see Figure 7) is driven by two transistors, Qon and Qoff. Qon provides IBASMAX during TFON and
IBASPBD during the remainder of the on-period. Transistor Qoff provides a low-resistance (RBASCLAMP) path to
GND during the off-period to ensure rapid turn-off of the primary switch, Q1. IBASPBD is set by the PBD system
within the controller but IBASMAX is determined by the external resistor Raux and the Aux Supply voltage.
IBASMAX
IBAS
VCE
TFON
TPBD
Figure 8: Base Driver Current Waveforms
Product data
© Cambridge Semiconductor Ltd 2008
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C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
IBASPBD is controlled by monitoring the voltage at the COL pin during TPBD; base current is increased
progressively as VCOL rises above threshold VCREF(see Figure 9). The desired on-state VCE of the switching
transistor is set by capacitors Cp and Ccol (see Figure 3), the COL pin capacitance (CINCOL) and VCREF.
IBASPBD
VCREF
VCOL
Figure 9: IBASPBD characteristic
Power Control
Load conditions are sensed on a cycle-by-cycle basis via the CS pin. When low levels of output power
demand are detected, the controller progressively reduces the switching duty cycle to reduce power
consumption and to improve output voltage regulation. Power demand causes increase in duty up to the
maximum, or until Overload is detected.
The voltage at the CS pin is compared to two thresholds, one nominally at GND voltage (VOCPL) to generate
an internal signal OCPL and the other at a negative threshold (VOCPH) to generate an internal signal OCPH.
The controller samples OCPL a short time (TOCPL) after turn-on of the primary switch. A negative voltage at
the CS pin indicates power demand so the controller increases the switching duty up to the maximum;
conversely a positive voltage causes a decrease in duty.
Excessive primary switch current, detected via OCPH, terminates the on-period of the primary switch to limit
power delivery (Overload mode). High levels of overload (when the converter output voltage held is low by
the load) causes OCPH to trigger soon after turn-on of the primary switch. This condition is detected by the
controller sampling OCPH at time TFBTHR after turn-on. If OCPH triggers within this time, the controller
changes to Foldback mode. To prevent mis-triggering, OCPH is blanked for a short period TCSBLANK after
turn-on.
Product data
© Cambridge Semiconductor Ltd 2008
Page 10 of 18
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C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
The effective thresholds for current through the primary switch for both power reduction (OCPL) and
overload (OCPH) are programmed by the current-sense resistors connected to the CS pin as shown in
Figure 10.
ICSBIAS
OCPH
threshold (-ve)
OCPH
Current
sense
comparators
GND
CS
OCPL
GND
R2
Rcs
Primary
switch
current
Figure 10: Current Sense Diagram
The internal current source (ICSBIAS) develops an offset voltage across the series resistor (R2 in Figure 10) so
setting OCPL current threshold. Switch current in excess of overload (OCPH) is detected using a fixed
threshold voltage but the contribution from the offset voltage across R2 has to be taken into account.
IOCPL threshold current = (VOCPL + ICSBIAS.R2)/Rcs
IOCPH threshold current = (VOCPH + ICSBIAS.R2)/Rcs
R2 
VOCPH  I OCPL  VOCPL  I OCPH
I OCPH  I CSBIAS  I OCPL  I CSBIAS
Rcs 
VOCPH  VOCPL
I OCPH  I OCPL
Note: IOCPL, IOCPH, VOCPH ICSBIAS are all positive magnitude in these formulae
Product data
© Cambridge Semiconductor Ltd 2008
Page 11 of 18
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C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
Protection Features
Collector De-saturation (Over Voltage) Protection (COVP)
To protect the primary switch from excessive power dissipation, the on-state voltage of the primary switching
transistor is limited by the controller. The controller will go to Foldback mode if the COL pin voltage is greater
than VCOVP at the end of the on-time for four consecutive cycles.
Over-temperature Protection (OTP)
Temperature sensing is integrated with the controller. If the temperature of the die rises above the shutdown
temperature, TSH, the BAS output is inhibited. It restarts once the temperature has fallen more than TSH (HYST)
below TSH. In typical applications “hiccup” operation will occur. While BAS is inhibited, the device is active
and draws IDDWAKE. This causes VDD to fall since auxiliary power is not provided by the transformer. Once VDD
reaches VUVDTHR, the controller enters the Sleep state and IDD falls to IDDSLEEP allowing VDD to rise again (via
the resistors Vht1 and Vht2). When VDD reaches VOVDTHR reset occurs and the controller re-starts. If the die
temperature is below TSH, BAS operation continues but if it is still above TSH, BAS operation ceases after a
short period and the hiccup cycle repeats.
Primary Switch Over-current Protection (OCP)
To protect the primary switch, the base drive is turned off if the primary switch current rises too high, sensed
via the CS input voltage falling below a preset negative threshold VOCPH. See also Power Control on page
10.
Output Overload/Short-circuit Protection
If the application circuit is overloaded beyond a certain limit the controller goes into Foldback mode with
reduced duty cycle, protecting the primary switch by reducing its power dissipation. Transition to Foldback
mode is triggered by the CS pin voltage crossing the VOCPH threshold within a time TFBTHR of the start of the
FON pulse. This typically happens when the load holds the output voltage low. See also Power Control on
page 10.
Under Voltage Protection
The controller is prevented from operating if the VDD supply is inadequate (VDD < VUVDTHR). Once the
controller has stopped operation it will not restart until the VDD supply voltage rises above VOVDTHR.
Product data
© Cambridge Semiconductor Ltd 2008
Page 12 of 18
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C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
ABSOLUTE MAXIMUM RATINGS
CAUTION: Permanent damage may result if a device is subjected to operating conditions at or in excess of
absolute maximum ratings. Current flowing into a pin is taken to be positive.
Parameter
Symbol
Condition
Min
Max
Units
4.6
V
Supply voltage
VDD
Input voltage AUX
VAUX
-0.5
VDD + 0.5
V
Input voltage BAS
VBAS
-0.5
VDD + 0.5
V
Input voltage CS
VCS
-0.5
VDD + 0.5
V
Input voltage COL
VCOL
-0.5
VDD + 0.5
V
IDD
-100
30
mA
While Qon is on (Figure 7), duty
< 30 %, VBAS > 0 V
-100
260
mA
All other conditions
-100
100
mA
Tj < 125 °C
-100
220
mA
Tj < 100 °C
-100
400
mA
-260
100
mA
In FON
-190
100
mA
In PBD
-122
100
mA
-100
100
mA
-100
100
mA
During PBD: ESD diode limit, input is high
impedance
-100
100
mA
During turn-on transient (ACTICLAMP active)
-250
250
mA
During resonance off period
-125
250
mA
Pin current VDD
Pin current AUX
IAUX
While Qoff is on (Figure 7), duty
< 30%
Pin current BAS
IBAS
While Qon is on (Figure 7), duty
< 30 %, VBAS > 0 V
While Qon is on (Figure 7), duty
< 30 % VBAS < 0 V
All other conditions
Pin current CS
Pin current COL
ICS
ICOL
Junction
temperature
TJ
-25
125
o
C
Storage
temperature
TSTOR
-40
150
o
C
260
o
C
Lead temperature
(soldering, 10 s)
ESD withstand
TL
Human body model, JESD22-A114
Charged device model, ANSI-ESD-STM5.3.1
Product data
© Cambridge Semiconductor Ltd 2008
Page 13 of 18
2
kV
500
V
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C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
NORMAL OPERATING CONDITIONS
Parameter
Supply voltage
Symbol
Condition
Min
Typ
Max
Units
VDD
VDD pin, limited by internal regulator
3.1
3.3
3.5
V
TJ
Over temperature protection operates
at higher temperatures
-25
25
100
ºC
VDD=VDDREG(R)
6.7
11.7
MHz
Junction
temperature
Internal digital clock
frequency
Switching frequency,
Normal mode
FCLK
FCLKTC
FMAX
FMIN
TRESMIN
Transformer
resonance time
TRESMAX
Supply current
IDD
Temperature coefficient
-1
+13
Determined by TRES (FCLK in MHz)
Natural resonance of transformer and
associated capacitances. FCLK in MHz.
kHzC
FCLK / 61
MHz
FCLK / 490
MHz
35 / FCLK
µs
280 / FCLK
Limit externally
µs
30
mA
ELECTRICAL CHARACTERISTICS
Unless otherwise stated:
1. Min and Max electrical characteristics apply over normal operating conditions.
2. Typical electrical characteristics apply at TJ = TJTYP and VDD = VDDTYP
3. Functionality and performance is not defined when a device is subjected to conditions outside the
range of normal operating conditions and device reliability may be compromised.
4. For parameters dependent on FCLK, the value of FCLK,in MHz should be used in calculations.
VDD Pin
Parameter
Symbol
Condition
VDDREG(R)
Active state, 2.5 mA < IDD < 30 mA
VDDREG(S)
Start-up state, 2.5 mA < IDD < 30 mA
Quiescent current
IDDSLEEP
Sleep state, VDD < VUVDTHR
Residual supply current
IDDWAKE
Start-up & Active states, Normal mode
(VDDREG(R) – 300 mV) < VDD and
VDD < (VDDREG(R) - 100 mV), Tj<100 ºC
OVD threshold, Sleep
VOVDTHR
UVD threshold
VUVDTHR
Regulation voltage
VDDREG(R) - VUVDTHR
Min
Typ
Max
Units
3.1
3.3
3.5
V
4
V
8
µA
0.7
1.8
mA
Sleep state
3.5
4.5
V
Start-up and Active states
2.7
3.2
V
IDD < 30 mA
150
Min
mV
AUX Pin
Parameter
Symbol
Condition
AUX pin voltage
VAUXFON
BAS = 800 mV
Product data
© Cambridge Semiconductor Ltd 2008
IAUX = 10 mA
IAUX = 80 mA
Page 14 of 18
Typ
Max
1.05
1.21
1.48
Units
V
1.75
V
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C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
CS Pin
Parameter
Condition
Min
VOCPH
0 C < TJ < 100 C
OCPL comparator
threshold
VOCPL
TJ = 25 C
OCPH comparator
response time
TOCP
Step CS input from
VCS > -200 mV to VCS < -300 mV
OCPH comparator
threshold
Bias current
Symbol
ICSBIAS
Typ
Max
Units
-260
-235
mV
-6
6
mV
0.1
µs
-25 C < TJ < 100 C
35.0
70.0
µA
Tj = 25C
38.0
63.0
µA
TOCPL
FCLK in MHz
19 / FCLK
- 0.1
µs
TCSBLANK
FCLK in MHz
4 / FCLK
- 0.1
µs
TFBTHR
FCLK in MHz
26 / FCLK
- 0.1
µs
Parameter
Symbol
Condition
Base drive current
(FON)
IBASMAX
Base drive current
(PBD)
IBASPBD
Base clamp turn-off
resistance
RBASCLAMP
OCPL sampling time
Blanking period
Foldback threshold
time
BAS Pin
Duty cycle
DNORMAL
Min
VCOL = VDD, VAUX = 2.1 V
Typ
Max
Units
90
mA
22
mA
8.5
VBAS = 400 mV, -25 C < TJ < 100 C
Ω
Normal mode
43
%
Standby mode
150
ns
Normal, Foldback & Power Burst
modes
650
ns
Force-on period
(depends on FCLK)
TFON
Minimum on-period
TONMIN
Standby (FCLK in MHz)
20 / FCLK
µs
Maximum off-period
TOFFMAX
Standby (FCLK in MHz)
1920 / FCLK
+ TRES
µs
NBURST
Burst length, number of converter
cycles
22144
cycles
TBURSTCYCMIN
Minimum converter cycle period in
1
Power Burst mode (FCLK in MHz)
39 / FCLK
µs
NFOLD
Foldback duration between bursts,
number of converter cycles
18326
cycles
TFOLDCYCMIN
Converter period in Foldback mode
(FCLK in MHz)
900 / FCLK +
TRES
µs
TOFFEXTMIN
Extended off time (FCLK in MHz)
896 / FCLK
µs
Power Burst mode
Foldback mode
1
2
2
Minimum converter period = TRES + TONMIN
Minimum converter period = TRES + TOFFEXT + TONMIN
Product data
© Cambridge Semiconductor Ltd 2008
Page 15 of 18
DS-1639-0805
02-May-2008
C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
COL Pin
Parameter
Symbol
Rising edge
comparator
threshold
Condition
Min
ICRISE
-25 C < TJ < 100 C
Falling edge
comparator
threshold
ICFALL
-25 C < TJ < 100 C
Collector overvoltage comparator
threshold
VCOVP
PBD threshold
voltage
VCREF
Intercept of characteristic
5 mA < IBAS < 20mA
(see Figure 9)
Max
Units
0.25
1.00
mA
-1.00
-0.25
mA
0.7VDD
0.9VDD
V
1.10
V
0.76
PBD
transconductance
0.92
95
Input leakage
current
Input capacitance
Typ
-650
TJ < 100  C
CINCOL
ACTICLAMP
duration after FON
TACT
VCOL = 1 V
25
28
mAV
650
nA
31
pF
Standby mode (FCLK in MHz)
3 / FCLK –
0.1
µs
Normal, Foldback and Power Burst
modes (FCLK in MHz)
4 / FCLK –
0.1
µs
-1
THERMAL CIRCUIT PROTECTION
Parameter
Symbol
Condition
Min
Typ
Max
Units
Thermal shutdown
temperature
TSH
At junction
115
o
C
Thermal shutdown
hysteresis
TSH (HYST)
At junction
35
o
C
PACKAGE THERMAL RESISTANCE CHARACTERISTICS
Conditions:
1. Controller IC mounted on typical PCB (1.6 mm thick, 35 µm copper, CEM1);
2. θJP measured to pin terminal of device at the surface of the PCB.
Package
Junction-to-pin
θJP (Typical)
Junction-to-ambient
θJA (Typical)
Units
SOT23-6
60
170
°C / W
PDIP-8
35
105
°C / W
Product data
© Cambridge Semiconductor Ltd 2008
Page 16 of 18
DS-1639-0805
02-May-2008
C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
PACKAGE AND ORDERING INFORMATION
Package Marking
The PDIP-8 (C2471LW1) package is marked with the full product type number. The SOT23-6 package
(C2471LX2) is marked with a short code FB as illustrated in Figure 11.
C2471LX2 product
short code FB
Lot dependent
code XX (varies)
FBXX
Figure 11: C2471LX2 SOT23-6 Package Marking
Ordering
Type
Package
Packing Form
Order
C2471LX2
SOT23-6
7” Tape & Reel
C2471LX2-TR7
13” Tape & Reel
C2471LX2-TR13
Tube
C2471LW1-T1
C2471LW1
PDIP-8
For further package and ordering information please contact CamSemi.
Product data
© Cambridge Semiconductor Ltd 2008
Page 17 of 18
DS-1639-0805
02-May-2008
C2471 Datasheet
RDFC Controllers for Offline Applications up to 6 W
DATASHEET STATUS
The status of this Datasheet is shown in the footer. Always refer to the most current version.
Datasheet Status
Product
Status
Definition
Product preview
In development
The Datasheet contains target specifications relating to design and
development of the described IC product. Application circuits are illustrative
only. Specifications are subject to change without notice.
Preliminary
In qualification
The Datasheet contains preliminary specifications relating to functionality and
performance of the described IC product. Application circuits are illustrative
only. Specifications are subject to change without notice.
Product data
In production
The Datasheet contains specifications relating to functionality and
performance of the described IC product. Application circuits are illustrative
only. Specifications are subject to change without notice.
CONTACT DETAILS
Cambridge Semiconductor Ltd
St Andrew’s House
St Andrew’s Road
Cambridge
CB4 1DL
United Kingdom
Phone:
Fax:
Email:
Web:
+44 (0)1223 446450
+44 (0)1223 446451
[email protected]
www.camsemi.com
DISCLAIMER
The product information provided herein is believed to be accurate and is provided on an “as is” basis. Cambridge Semiconductor Ltd
(CamSemi) assumes no responsibility or liability for the direct or indirect consequences of use of the information in respect of any
infringement of patents or other rights of third parties. Cambridge Semiconductor Ltd does not grant any licence under its patent or
intellectual property rights or the rights of other parties.
Any application circuits described herein are for illustrative purposes only. In respect of any application of the product described herein
Cambridge Semiconductor Ltd expressly disclaims all warranties of any kind, whether express or implied, including, but not limited to,
the implied warranties of merchantability, fitness for a particular purpose and non-infringement of third party rights. No advice or
information, whether oral or written, obtained from Cambridge Semiconductor Ltd shall create any warranty of any kind. Cambridge
Semiconductor Ltd shall not be liable for any direct, indirect, incidental, special, consequential or exemplary damages, howsoever
caused including but not limited to, damages for loss of profits, goodwill, use, data or other intangible losses.
The products and circuits described herein are subject to the usage conditions and end application exclusions as outlined in Cambridge
Semiconductor Ltd Terms and Conditions of Sale which can be found at www.camsemi.com/legal .
Cambridge Semiconductor Ltd reserves the right to change specifications without notice. To obtain the most current product information
available visit www.camsemi.com or contact us at the address shown above.
Product data
© Cambridge Semiconductor Ltd 2008
Page 18 of 18
DS-1639-0805
02-May-2008