Fairchild FAN7384 Half-bridge gate-drive ic Datasheet

FAN7384
Half-Bridge Gate-Drive IC
Features
Description
„ Floating Channel for Bootstrap Operation to +600V
The FAN7384 is a monolithic half-bridge gate-drive IC
designed for high voltage, high speed driving MOSFETs
and IGBTs operating up to +600V.
„ Typically 250mA/500mA Sourcing/Sinking Current
Driving Capability for Both Channels
„ Extended Allowable Negative VS Swing to -9.8V for
„
„
„
„
„
„
„
„
„
„
Signal Propagation at VDD=VBS=15V
Matched Propagation Delay Below 50ns
Output In-Phase with Input Signal
3.3V and 5V Input Logic Compatible
Built-in Shoot-Through Prevention Logic
Built-in Common Mode dv/dt Noise Canceling Circuit
Built-in UVLO Functions for Both Channels
Built-in Cycle-by-Cycle Shutdown Function
Built-in Soft-Off Function
Built-in Bi-Directional Fault Function
Built-in Short-Circuit Protection Function
Fairchild’s high-voltage process and common-mode
noise canceling technique provide stable operation of
high-side drivers under high-dv/dt noise circumstances.
An advanced level-shift circuit allows high-side gate
driver operation up to VS = -9.8V (typical) for VBS =15V.
The UVLO circuits prevent malfunction when VDD and
VBS are lower than the specified threshold voltage.
Output drivers typically source/sink 250mA/500mA,
respectively, which is suitable for half-bridge and fullbridge applications in motor drive systems.
14-SOP
Applications
„ Motor Inverter Driver
„ Normal Half-Bridge and Full-Bridge Driver
1
„ Switching Mode Power Supply
Ordering Information
Part Number
FAN7384M
(1)
FAN7384MX
(1)
Package
14-Lead, Small Outline Integrated
Circuit (SOIC), Non-JEDEC, .150
Inch Narrow Body, 225SOP
Operating
Temperature
Range
Eco
Status
-40°C to +125°C
RoHS
Packing Method
Tube
Tape & Reel
Note:
1. These devices passed wave soldering test by JESD22A-111.
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
www.fairchildsemi.com
FAN7384 Half-Bridge Gate-Drive IC
October 2009
FAN7384 Half-Bridge Gate-Drive IC
Typical Application Diagrams
VDC
VCC
VDD
VDD
VB
HO
VDD
HO
HO
U
VS
HIN
LIN
FO
SD
VB
VS
HIN
LIN
FO
SD
FO
SD
LO
CSC
LO
CSC
GND
VSL
VSL
V
FAN7384
U
FAN7384
HIN
LIN
FAN7384
3-Phase
Motor
Controller
UU
UL
VU
UL
WU
WL
VS
W
W
LO
CSC
GND
V
VB
VSL
GND
FAN7384 Rev.03
Figure 1. 3-Phase Motor Drive Application
VDC
VCC
RPULLUP
VDD
VDD
VB
HIN
PHB
FO
FAULT
SHUTDOWN
VS
LIN
HIN
FO
SD
FAN7384
HIN
FAN7384
PHA
VB
HO
HO
VS
Forward
M
Reverse
SD
LO
300K
GND
VSL
LO
300K
CSC
GND
DC Motor
Controller
VSL
CSC
FAN7384 Rev.02
Figure 2. DC Motor Drive Application
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
www.fairchildsemi.com
2
14
VB
13
HO
12
VS
4
VDD
9
LO
8
VSL
5
FO
UVLO
HIN
3
SD
2
R
Q
UVLO
SHOOT-THROUGH
PREVENTION
GND/VSL
LEVEL SHIFTER
LS(ON/OFF)
CONTROL LOGIC
FAULT
LOGIC
DELAY
SOFT-OFF
ISOFT
6
ONE-SHOT
TRIGGER
0.5V
GND
S
SCHMITT
TRIGGER INPUT
VDD_UVLO
CSC
R
DRIVER
1
NOISE
CANCELLER
DRIVER
LIN
PULSE
GENERATOR
HS(ON/OFF)
ONE-SHOT
TRIGGER
VDD_UVLO
7
FAN7384 Rev.03
Figure 3. Functional Block Diagram
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
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3
FAN7384 Half-Bridge Gate-Drive IC
Internal Block Diagram
FAN7384 Half-Bridge Gate-Drive IC
Pin Configuration
1
14
VB
SD
2
13
HO
HIN
3
12
VS
VDD
4
11
NC
FO
5
10
NC
CSC
6
9
LO
GND
7
8
VSL
FAN7384
LIN
FAN7384 Rev.00
Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
1
LIN
Logic Input for low-side gate driver
2
SD
Shutdown control input with active low
3
HIN
Logic Input for high-side gate driver
4
VDD
Low-side power supply voltage
5
FO
Bi-direction fault pin with open drain
6
CSC
Short-circuit current detection input
7
GND
Ground
8
VSL
Low-side supply offset voltage
9
LO
Low-side gate driver output
10
NC
Not connection
11
NC
Not connection
12
VS
High-side floating supply offset voltage
13
HO
High-side gate driver output
14
VB
High-side floating supply voltage
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
www.fairchildsemi.com
4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified.
Symbol
Parameter
VS
High-side offset voltage VS
VB
High-side floating supply voltage VB
Min.
Max.
Unit
VB-25
VB+0.3
V
-0.3
625
V
VS-0.3
VB+0.3
V
Low-side and logic-fixed supply voltage
-0.3
25
V
Logic input voltage (HIN, LIN, SD)
-0.3
VDD+0.3
V
VCSC
Current sense input voltage
-0.3
VDD+0.3
V
VFO
Fault output voltage
-0.3
VDD+0.3
V
Allowable offset voltage slew rate
50
V/ns
Power dissipation
1.0
W
VHO
High-side floating output voltage
VDD
VIN
dVS/dt
PD(2)(3)(4)
θJA
Thermal resistance, junction-to-ambient
TJ
Junction temperature
TS
Storage temperature
-55
110
°C/W
+150
°C
+150
°C
Notes:
2. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).
3. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions - natural convection
JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages
4. Do not exceed PD under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Condition
Min.
Max.
Unit
VB
High-side floating supply voltage
VS+13
VS+20
V
VS
High-side floating supply offset voltage
6-VDD
600
V
13
20
V
VDD
Supply voltage
VHO
High-side output voltage
VS
VB
V
VLO
Low-side output voltage
GND
VDD
V
VIN
Logic input voltage (HIN, LIN, SD)
GND
VDD
V
VFO
Fault output voltage
-0.3
VDD+0.3
V
TA
Ambient temperature
-40
+125
°C
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
www.fairchildsemi.com
5
FAN7384 Half-Bridge Gate-Drive IC
Absolute Maximum Ratings
VBIAS (VDD, VBS) = 15.0V, TA = 25°C, unless otherwise specified. The VIN and IIN parameters are referenced to GND.
The VO and IO parameters are referenced to VS and GND and are applicable to the respective outputs HO and LO.
Symbol
Characteristics
Condition
Min. Typ. Max. Unit
LOW SIDE POWER SUPPLY SECTION
IQDD
Quiescent VDD supply current
VLIN=0V or 5V
600
800
μA
IPDD
Operating VDD supply current
fLIN=20kHz, rms value
950
1300
μA
VDDUV+
VDD supply under-voltage positive going
threshold
VDD=Sweep
10.9
11.9
12.9
V
VDDUV-
VDD supply under-voltage negative going
VDD=Sweep
threshold
10.4
11.4
12.4
V
VDDHYS
VDD supply under-voltage lockout
hysteresis
VDD=Sweep
0.5
V
BOOTSTRAPPED POWER SUPPLY SECTION
VBSUV+
VBS supply under-voltage positive going
threshold
VBS=Sweep
10.6
11.5
12.4
V
VBSUV-
VBS supply under-voltage negative going
VBS=Sweep
threshold
10.1
11.0
11.9
V
VBSHYS
VBS supply under-voltage lockout
hysteresis
VBS=Sweep
ILK
Offset supply leakage current
VB=VS=600V
IQBS
Quiescent VBS supply current
VHIN=0V or 5V
IPBS
Operating VBS supply current
fHIN=20kHz, rms value
0.5
V
10
μA
50
90
μA
400
600
μA
100
mV
100
mV
GATE DRIVER OUTPUT SECTION
VOH
High-level output voltage, VBIAS-VO
IO=0mA (No Load)
VOL
Low-level output voltage, VO
IO=0mA (No Load)
IO+
Output HIGH short-circuit pulse current
VO=0V, VIN=5V with PW<10µs
200
250
mA
IO-
Output LOW short-circuit pulsed current
VO=15V, VIN=0V with PW<10µs
420
500
mA
VS
Allowable negative VS pin voltage for IN
signal propagation to HO
-9.8
VSL-GND VSL-GND/GND-VSL voltage educability
SHUTDOWN CONTROL SECTION (SD)
SD+
Shutdown "1" input voltage
SD-
Shutdown "0" input voltage
-7.0
-7.0
V
7.0
V
1.2
V
2.5
V
2.5
V
LOGIC INPUT SECTION (HIN, LIN)
VIH
Logic "1" input voltage
VIL
Logic "0" input voltage
VINHYS
Logic input hysteresis voltage
V
20
μA
2.0
μA
0.5
IIN+
Logic "1" input bias current
VIN=5V
IIN-
Logic "0" input bias current
VIN=0V
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
1.2
10
15
V
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6
FAN7384 Half-Bridge Gate-Drive IC
Electrical Characteristics
VBIAS (VDD, VBS) = 15.0V, TA = 25°C, unless otherwise specified. The VIN and IIN parameters are referenced to GND.
The VO and IO parameters are referenced to GND and VS is applicable to HO and LO.
Symbol
Characteristics
Condition
Min. Typ. Max. Unit
SHORT-CIRCUIT PROTECTION
VCSCREF Short-circuit detector reference voltage
0.47
0.50
0.53
V
ICSCIN
Short-circuit input current
VCSCIN=1V, RCSCIN=100KΩ
5
10
15
μA
ISOFT
Soft turn-off source current
VDD=15V
5
10
15
mA
-VCSC
Negative CSC pin immunity(5)
Voltage on CSC pin up to -12V,
Time<2μs
-20
V
FAULT DETECTION SECTION
VFINH
Fault input high level voltage
VFINL
Fault input low level voltage
VFINHYS
Fault input hysteresis
2.5
1.2
voltage(5)
0.5
VFOH
Fault output high level voltage
VCSC=0V, RPULL-UP=4.7KΩ
VFOL
Fault output low level voltage
VCSC=1V, IFO=2mA
Fault output pulse width
VCSCIN=1V
tFO
V
V
V
4.7
V
60
0.8
V
100
µs
Note:
5. These parameters guaranteed by design.
Dynamic Electrical Characteristics
TA=25°C, VBIAS (VDD, VBS) = 15.0V, VS = GND, CLoad = 1000pF unless otherwise specified.
Symbol
ton
Parameter
Conditions
Turn-on propagation delay
Min. Typ. Max. Unit
VS=0V
ns
170
240
ns
Turn-on rise time
50
100
ns
tf
Turn-off fall time
30
80
ns
MT
Delay matching
50
ns
DT
Dead-time
tUVFLT
Under-voltage filtering time(5)
tCSCFLT
CSC pin filtering time(5)
VS=0V or
260
tr
toff
Turn-off propagation delay
180
600V (5)
80
(5)
120
170
ns
16
µs
300
ns
tCSCFO
Time from CSC triggering to FO
350
ns
tCSCLO
Time from CSC triggering to low-side From VCSC=1V to starting gate
gate output(5)
turn-off
600
ns
tSDFO
Shutdown to FO propagation delay(5)
60
ns
100
ns
tSDOFF
(5)
Shutdown to HIGH/LOW-side gate off
Note:
5. These parameters guaranteed by design.
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
www.fairchildsemi.com
7
FAN7384 Half-Bridge Gate-Drive IC
Electrical Characteristics (Continued)
13.0
13.0
12.5
12.5
VDDUV- [V]
VDDUV+ [V]
13.5
12.0
12.0
11.5
11.5
11.0
11.0
10.5
10.5
-40
-20
0
20
40
60
80
100
10.0
-40
120
-20
0
Temperature [°C]
Figure 5. VDD UVLO (+) vs. Temperature
40
60
80
100
120
Figure 6. VDD UVLO (-) vs. Temperature
1.0
13.0
12.5
VBSUV+ [V]
0.8
VDDHYS [V]
20
Temperature [°C]
0.6
0.4
12.0
11.5
11.0
0.2
0.0
-40
10.5
-20
0
20
40
60
80
100
10.0
-40
120
-20
0
Temperature [°C]
Figure 7. VDD UVLO Hysteresis vs. Temperature
40
60
80
100
120
Figure 8. VBS UVLO (+) vs. Temperature
1.0
12.5
12.0
0.8
VBSHYS [V]
VBSUV- [V]
20
Temperature [°C]
11.5
11.0
0.6
0.4
10.5
0.2
10.0
9.5
-40
-20
0
20
40
60
80
100
0.0
-40
120
Temperature [°C]
0
20
40
60
80
100
120
Temperature [°C]
Figure 9. VBS UVLO (-) vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
-20
Figure 10. VBS UVLO Hysteresis vs. Temperature
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8
FAN7384 Half-Bridge Gate-Drive IC
Typical Characteristics
800
80
IQBS [μA]
100
IQDD [μA]
1000
600
60
400
40
200
20
0
-40
-20
0
20
40
60
80
100
0
-40
120
-20
0
Temperature [°C]
Figure 11. VDD Quiescent Current vs. Temperature
40
60
80
100
120
Figure 12. VBS Quiescent Current vs. Temperature
1000
1600
1400
800
1200
IPBS [μA]
IPDD [μA]
20
Temperature [°C]
1000
600
400
800
200
600
400
-40
-20
0
20
40
60
80
100
0
-40
120
-20
0
Figure 13. VDD Operating Current vs. Temperature
40
60
80
100
120
Figure 14. VBS Operating Current vs. Temperature
30
20
25
16
20
ICSCIN [μA]
IIN+ [μA]
20
Temperature [°C]
Temperature [°C]
15
12
8
10
4
5
0
-40
-20
0
20
40
60
80
100
0
-40
120
Temperature [°C]
0
20
40
60
80
100
120
Temperature [°C]
Figure 15. Logic Input Current vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
-20
Figure 16. ICSCIN vs. Temperature
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9
FAN7384 Half-Bridge Gate-Drive IC
Typical Characteristics (Continued)
20
120
100
tr [nsec]
ISOFT [mA]
15
10
80
60
40
5
20
0
-40
-20
0
20
40
60
80
100
0
-40
120
-20
0
Temperature [°C]
Figure 17. ISOFT vs. Temperature
40
60
80
100
120
Figure 18. Turn-on Rising Time vs. Temperature
100
300
250
80
200
ton [nsec]
tf [nsec]
20
Temperature [°C]
60
150
40
100
20
0
-40
50
-20
0
20
40
60
80
100
0
-40
120
-20
0
Temperature [°C]
300
3.0
250
2.5
200
2.0
150
1.0
50
0.5
0
20
40
60
80
100
0.0
-40
120
80
100
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 21. Turn-off Delay Time vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
60
1.5
100
-20
40
Figure 20. Turn-on Delay Time vs. Temperature
VIH [V]
toff [nsec]
Figure 19. Turn-off Falling Time vs. Temperature
0
-40
20
Temperature [°C]
Figure 22. Logic Input High Voltage vs. Temperature
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10
FAN7384 Half-Bridge Gate-Drive IC
Typical Characteristics (Continued)
3.0
1.0
0.8
2.0
VINHYS [V]
VIL [V]
2.5
1.5
0.6
0.4
1.0
0.2
0.5
0.0
-40
-20
0
20
40
60
80
100
0.0
-40
120
-20
0
Temperature [°C]
3.0
3.0
2.5
2.5
2.0
1.5
0.5
0.5
20
40
60
80
100
120
1.5
1.0
0
60
2.0
1.0
-20
40
Figure 24. Logic Input Hysteresis vs. Temperature
SDBAR- [V]
SDBAR+ [V]
Figure 23. Logic Input Low Voltage vs. Temperature
0.0
-40
20
Temperature [°C]
80
100
0.0
-40
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 25. SD Positive Threshold vs. Temperature
Figure 26. SD Negative Threshold vs. Temperature
0.60
2.4
2.0
VFINH [V]
VCSCREF [V]
0.55
0.50
1.6
1.2
0.8
0.45
0.4
0.40
-40
-20
0
20
40
60
80
100
0.0
-40
120
Temperature [°C]
0
20
40
60
80
100
120
Temperature [°C]
Figure 27. VCSCREF vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
-20
Figure 28. Fault Input High Voltage vs. Temperature
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11
FAN7384 Half-Bridge Gate-Drive IC
Typical Characteristics (Continued)
6.0
1.0
0.8
VFOL [V]
VFOH [V]
5.6
5.2
0.6
0.4
0.2
4.8
-40
-20
0
20
40
60
80
100
0.0
-40
120
-20
0
Temperature [°C]
Figure 29. Fault Output High Voltage vs.
Temperature
40
60
80
100
120
Figure 30. Fault Output Low Voltage vs. Temperature
-7
200
-8
160
DT [nsec]
VS [V]
20
Temperature [°C]
-9
-10
120
80
-11
40
-12
-13
-40
-20
0
20
40
60
80
100
0
-40
120
Temperature [°C]
0
20
40
60
80
100
120
Temperature [°C]
Figure 31. Allowable Negative VS Voltage for Signal
Propagation to High Side vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
-20
Figure 32. Dead Time vs. Temperature
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12
FAN7384 Half-Bridge Gate-Drive IC
Typical Characteristics (Continued)
The overall switching timing waveforms definition of FAN7384 as shown Figure 33.
LIN
SD
Shutdown
Disable Skip
Low-Side Output
Disable
Low-Side Output
Disable
UVLO-
VDD
tUVFLT
0.5V
VCSC
tCSCFO
tCSCFO
tFO
tFO
FO
tCSCLO
LO
tCSCLO
Soft-Off
Operating
Soft-Off
Operating
Under-Voltage
Detection Point
Shutdown
Disable Point
Shutdown
Enable Point
Short-Circuit
Detection Point
FAN7384 Rev.03
Figure 33. Switching Timing Waveforms Definition
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
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13
FAN7384 Half-Bridge Gate-Drive IC
Switching Time Definitions
1. Protection Function
HIN/LIN
1.1 Under-Voltage Lockout (UVLO)
The high- and low-side drivers include under-voltage
lockout (UVLO) protection circuitry that monitors the
supply voltage (VDD) and bootstrap capacitor voltage
(VBS) independently. It can be designed to prevent
malfunction when VDD and VBS are lower than the
specified threshold voltage. Moreover, the UVLO
hysteresis prevents chattering during power supply
transitions. If the supply voltage (VDD) maintains an
under-voltage condition over under-voltage filtering times
(typically 16µs), the fault and soft-off circuits are
activated, as shown Figure 34.
LIN/HIN
Shoot-Through Prevent
HO/LO
After DT
LO/HO
FAN7384 Rev.01
LIN
Figure 36. Waveforms for Shoot-Through Prevention
UVLO+
UVLO-
VDD
1.3 Over-Current Protection Function
The FAN7384 has over-current detection circuitry that
monitors the current-by-current sensing resistor connected from the low-side switch source (VSL) to ground.
tUVFLT
tFO
tCSCFO
FO
90%
LO
FAN7384 Rev.01
It is a built-in time-filler from the over-current event to
prevent malfunction from a noise source, such as leading-edge pulse in inductive load application, as shown
Figure 37.
tCSCLO
t1
t2
t3
The sensing current is calculated as follows:
Figure 34. Waveforms for Under-Voltage Lockout
ICS =
VCSCREF
[ A]
RCS
(1)
1.2 Shoot-Through Prevention Function
where,
The FAN7384 has a shoot-through prevention circuitry
that monitors the high- and low-side inputs. It can be
designed to prevent outputs of high- and low-side turning
on at same time, as shown Figure 35 and 36.
VCSCREF: Reference voltage of current sense
comparator
RCS: Current sensing resistor
HIN/LIN
LIN
LIN/HIN
Low-Side Output
Disable
Shoot-Through Prevent
HO/LO
0.5V
VCSC
After DT
FO
tCSCFO
tFO
tCSCLO
LO/HO
LO
Soft-Off
Short-Circuit Operating
Detection Point
After DT
FAN7384 Rev.01
Figure 35. Waveforms for Shoot-Through Prevention
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
FAN7384 Rev.03
Figure 37. Waveforms for Short-Circuit Protection
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14
FAN7384 Half-Bridge Gate-Drive IC
Typical Application Information
2.2 Gate-Drive Loop
For optimum performance, considerations must be taken
during printed circuit board (PCB) layout.
Current loops behave like antennae, able to receive and
transmit noise. To reduce the noise coupling/emission
and improve the power switch turn-on and off performance, gate-drive loops must be reduced as much as
possible.
2.1 Supply Capacitors
If the output stages are able to quickly turn on a switching device with a high value of current, the supply capacitors must be placed as close as possible to the device
pins (VDD and GND for the ground-tied supply, VB and
VS for the floating supply) to minimize parasitic inductance and resistance.
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
2.3 Ground Plane
To minimize noise coupling, the ground plane should not
be placed under or near the high-voltage floating side.
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15
FAN7384 Half-Bridge Gate-Drive IC
2. Layout Considerations
8.76
8.36
0.65
A
7.62
14
6.00
B
8
5.60
4 .15
3.75
B
1.70
B
P IN O N E
IN D IC A T O R
(0.27)
#1
1.27
7
#1
0 .51
0 .36
1.27
T O P V IE W
0 .20
C B A
L A N D P A T T E R N R E C O M M E N D A T IO N
S E E D E T A IL A
1 .8 0 M A X
1 .65
1 .45
(R 0.20)
C
B
0 .0 5 M IN
1 .27
S ID E V IE W
0 .30
0 .15
E N D V IE W
0 .1 0 M A X C
NOTES:
A ) T H IS D R A W IN G C O M P LIE S W IT H JE D E C M S -012
EXCEPT AS NOTED.
B ) T H IS D IM E N S IO N IS O U T S ID E T H E JE D E C M S -0 12 V A L U E .
C ) A LL D IM E N S IO N S A R E IN M IL LIM E T E R S .
D ) D IM E N S IO N S A R E E X C L U S IV E O F B U R R S , M O LD F LA S H ,
A N D T IE B A R E X T R U S IO N S .
E ) LA N D P A T T E R N S T A N D A R D : S O IC 127P 600X 145-14M
F ) D R A W IN G F IL E N A M E A N D R E V IS IO N : M 14C R E V 1
8¡Æ
GAGE
PLANE
(R 0.10)
0.90
0.50
0.36
S E A T IN G
PLANE
D E T A IL A
Figure 38. 14-Lead, Small Outline Integrated Circuit (SOIC), Non-JEDEC, .150 Inch Narrow Body, 225SOP
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
www.fairchildsemi.com
16
FAN7384 Half-Bridge Gate-Drive IC
Package Dimensions
FAN7384 Half-Bridge Gate-Drive IC
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.7
www.fairchildsemi.com
17