LX1672 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET KEY FEATURES DESCRIPTION WWW . Microsemi .C OM Up to Three Independently Regulated Outputs DDR Termination Compliant Bi-phase Current Sharing Outputs As Low As 0.8V Generated From An Internal 1% Reference Multiphase High Current Output Reduces Required Capacitance Integrated High Current MOSFET Drivers 300KHz, 500KHz and 600KHz High Frequency Operation Minimizes External Component Requirements Independent Phase Programmable Soft-Start and Power Sequencing Adjustable Linear Regulator Driver Output No current-sense resistors This patented approach also gives system designers maximum flexibility with respect to MOSFET supply. Each phase can utilize different supply voltages, for efficient use of available supplies, while programming the ratio of current pulled from each using one of three methods (see application section). The LX1672 incorporates fully programmable soft-start sequencing capabilities. Each output can be configured to come up in any order necessary as required by the application. The LX1672 features an additional Linear Regulator Driver output, which when coupled with an inexpensive MOSFET is capable of supplying up to 5A for I/O, memory, and other supplies surrounding today’s micro-processor designs. Each regulator voltage output is programmed via a simple voltage-divider network. The LX1672, utilizing MOSFET RDS(ON) impedance, monitors maximum current limit conditions, in each PWM phase without the use of expensive current sense resistors. The LX1672 is a highly integrated power supply controller IC featuring two PWM switching regulator stages with an additional onboard linear regulator driver. The two constant frequency voltagemode PWM phases can be easily configured as a single Bi-Phase high current output, two independently regulated outputs, or as a DDR memory I/O supply with a tracking DDR termination voltage supply. Power loss and noise, due to the ESR of the input capacitors, are minimized by operating each PWM output 180° out of phase. This architecture also minimizes capacitor requirements while maximizing regulator response. In bi-phase operation, the high current output utilizes a patented current sharing architecture, called Forced Current Sharing†, to allow accurate current sharing without the use of expensive current sense resistors. APPLICATIONS/BENEFITS Multi-Output Power Supplies Video Card Power Supplies DDR, VDDQ and Termination Supply PC Peripherals Portable PC Processor and I/O Supply IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com † U.S Patents: 6,285,571,6,292,378 PRODUCT HIGHLIGHT DDR Termination Refer to Typical Application for complete circuit. Memory Core .... 12V 5V Graphics Controller LX1672 Memory Bus DDR Memory 3.3V TA (°C) Switching Frequency (kHz) 0 to 70 0 to 70 0 to 70 300 500 600 PW PACKAGE ORDER INFO Plastic TSSOP 28-Pin LQ Plastic MLPQ 38-Pin RoHS Compliant / Pb-free Transition DC: 0518 RoHS Compliant / Pb-free Transition DC: 0512 LX1672-03CPW LX1672-05CPW LX1672-03CLQ LX1672-06CLQ NOTE: Available in Tape & Reel. Append the letters “TR” to the part number (i.e. LX1672-06CLQ-TR) Copyright © 2000 Rev. 1.0, 2005-08-10 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 1 LX1672 I/O LX1672 ® TM Multiple Output LoadSHARE™ PWM P RODUCTION D ATA S HEET ABSOLUTE MAXIMUM RATINGS PACKAGE PIN OUT HO2 LO2 PG2 LDGD LDFB LDDIS DGND AGND DIS2 SS2 RF2 FB2 EO2 CS2 PW Plastic TSSOP 28-Pin THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA LQ 85°C/W Plastic MLPQ 38-Pin THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VC2 VC1 HO1 LO1 PG1 VCCL VCC VS1 CS1 EO1 FB1 SS1 DIS1 VS2 HO2 VC2 LDGD LDFB LDDIS DGND AGND RSVD SS2 RF2 FB2 EO2 1 38 37 LO1 HO1 VC1 N.C . N.C. LO2 PG1 (Top View) 36 35 34 33 32 31 2 30 3 29 4 28 5 27 Connect Bottom to Power GND 6 7 26 25 N.C. N.C. VCCL VCC DIS2 DIS1 N.C. 8 24 N.C. 9 23 10 22 PWGD N.C. 11 12 35°C/W Junction Temperature Calculation: TJ = TA + (PD x θJC). The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. 27 21 13 14 15 16 17 18 19 20 N.C. N.C. CS2 VS2 SS1 FB1 EO1 CS1 VS1 THERMAL DATA 28 2 PW PACKAGE Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of specified terminal. x= Denote Phases 1 & 2 1 WWW . Microsemi .C OM Supply Voltage (VCC) DC .................................................................-0.3V to 5.5V Driver Supply Voltage (VCx, VCCL) DC ............................................-0.3V to 12V Current Sense Inputs (VSX, CSX) ....................................................... -0.3V to 12V Error Amplifier Inputs (FBX, RF2, LDFB)........................................-0.3V to 5.5V Input Voltage (SS / Enable, LDDIS) .................................................-0.3V to5.5V Output Drive Peak Current Source (HOx, LOx)....................................1A (500ns) Output Drive Peak Current Sink (HOx, LOx) .......................................1A (500ns) Operating Junction Temperature.................................................................. 150°C Storage Temperature Range...........................................................-65°C to 150°C Peak Package Solder Reflow Temp.(40 second max. exposure) .... 260°C (+0, -5) (N.C. – No Internal Connection N/U – Not Used) RoHS / Pb-free 100% Matte Tin Lead Finish PACKAGE DATA Copyright © 2000 Rev. 1.0, 2005-08-10 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 2 LX1672 ® TM Multiple Output LoadSHARE™ PWM P RODUCTION D ATA S HEET NAME DESCRIPTION FB1 Bi-Phase Operation: Phase 1 and 2 Voltage Feedback Single Phase Operation: Phase 1 Voltage Feedback – connected to the output through a resistor network to set desired output voltage of Phase 1 EOX Error Amplifier Output – Sets external compensation for the corresponding phase denoted by “X”. FB2 Bi-phase Operation: Load Sharing Voltage Sense Feedback – Connect filtered phase 2 switching output (preinductor) to FB2 to ensure proper current sharing between phase 1 and phase 2. Single Phase Operation: Phase 2 Voltage Feedback – connected to the output through a resistor network (post inductor) to set desired output voltage of Phase 2. RF2 Bi-Phase Operation: Load Sharing Voltage Sense Feedback Reference – Sets reference for current sharing control loop. Connecting filtered phase 1 switching output (pre-inductor) to REF2 forces average current in phase 2 to be equal to phase 1. Single Phase Operation: Phase 2 Voltage Reference – connected to SS2 pin as reference. VCC IC supply voltage (nominal 5V). VCCL Power supply pin for all Low side drivers. LDFB Low Dropout Regulator Voltage Feedback – Sets output voltage of external MOSFET via resistor network. CSX Over-Current Limit Set – Connecting a resistor between CS pin and the source of the high-side MOSFET sets the current-limit threshold for the corresponding phase denoted by “X”. Exceeding the current-limit threshold forces the corresponding phase into hiccup mode protection. A minimum of 1KΩ must be in series with this input. SSX Soft-start/Hiccup Capacitor Pin – During start-up, the voltage on this pin controls the output voltage of its respective regulator. An internal 20kΩ resistor and the external capacitor set the time constant for soft-start function. The Soft-start function does not initialize until the supply voltage exceeds the UVLO threshold. When an over-current condition occurs, this capacitor is used for the timing of hiccup mode protection. AGND Analog ground reference. DGND Digital ground reference. LDGD Low Dropout Regulator Gate Drive – Connects to gate of external N-Channel MOSFET for linear regulator function. Driver Power Ground. Connects to the source of the bottom N-channel MOSFETS of phase 1 where X=1, and phase 2 where X=2 for the TSSOP. The MLPQ package has a common PG output . HOX High Side MOSFET Gate Driver – “X” denotes corresponding phase. LOX Low Side MOSFET Gate Driver – “X” denotes corresponding phase. VCX Phase High-Side MOSFET Gate Driver Supply – Connect to separate supply or boot strap supply to ensure proper high-side gate driver supply voltage. “X” denotes corresponding phase. If the phase is not used connect to VCC. LDDIS LDO Disable input. High disables the LDO output. This pin has a 100KΩ nominal pull down resistor VSX Voltage reference for Current sense. This is also the supply pin for the Current Sense Comparator. “X” denotes corresponding phase. This pin cannot be left floating, if the phase is not used connect to VCC DISX PWM Disable Input – High disables the PWM output. This pin has a nominal 80KΩ pull down resistor. “X” denotes corresponding phase. PWGD Copyright © 2000 Rev. 1.0, 2005-08-10 Open drain output , high at end of Soft Start and no Fault. Pulls low if any Fault condition occurs. This output is present on the MLP package only. Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 3 PACKAGE DATA PGX WWW . Microsemi .C OM FUNCTIONAL PIN DESCRIPTION LX1672 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET Parameter ` SWITCHING REGULATORS Input Voltage Input Voltage Operation Current Reference Voltage ` ` ` ` Symbol VCC Min LX1672 Typ 4.5 ICC VSS Static and Dynamic TA = 25°C 0°C < TA < 70°C TSSOP Package MLPQ Package LX1672-03 Load = 3000pF LX1672-05 Load = 3000pF LX1672-06 Load = 3000pF Common Mode Input Voltage = 1V 0.792 0.784 -1 -1 -6.0 3.5 VCSX = VVSX – 0.3V , VVSX = 5V Referenced to VSX , VVSX = 5V 45 260 0.808 0.816 1 1 250 150 6.0 70 16 3.8 200 .1 400 3.5 100 Current into VSX pins LX1672-03 LX1672-05 LX1672-06 10 0.8 85 75 70 I Source = 2mA I Sink = 10µA Input Offset Voltage < 20mV 0 and 3.5 V Common Mode Input Voltage Static Static CL = 3000pF ISOURCE = 20mA, VCCL = 12V ISINK = 20mA, VCCL = 12V Max 5.5 12 VCCL, VCX 10 255 425 510 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Units V V mA V % % nS nS % % % mV dB MHz V mV V nA 50 300 350 55 340 μA mV nS 2 5 mA 0.25 mA mA nS V V 2.5 3 50 11 0.15 300 500 600 1.25 345 575 690 KHz KHz KHz VPP Page 4 ELECTRICALS Line Regulation (Note 2) Load Regulation (Note 2) Minimum Pulse Width Minimum Pulse Width Maximum Duty Cycle Maximum Duty Cycle Maximum Duty Cycle ERROR AMPLIFIERS Input Offset Voltage Vos DC Open Loop Gain Unity Gain Bandwidth UGBW High Output Voltage VOH Low Output Voltage VOL Input Common Mode Range Input Bias Current IIN CURRENT SENSE Current Sense Bias Current ISET Trip Threshold VTRIP Current Sense Delay TCSD Current Sense Comparator ICSX Operating Current OUTPUT DRIVERS – N-CHANNEL MOSFETS Low Side Driver Operating Current IVCCL High Side Driver Operating Current IVCX Drive Rise Time, Fall Time TRF High Level Output Voltage VDH Low Level Output Voltage VDL OSCILLATOR PWM Switching Frequency FSW PWM Switching Frequency PWM Switching Frequency Ramp Amplitude VRAMP Copyright © 2000 Rev. 1.0, 2005-08-10 Test Conditions WWW . Microsemi .C OM ELECTRICAL CHARACTERISTICS Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C ≤ TA ≤ 70°C except where otherwise noted and the following test conditions: VCC = 5V, VCCL = 5V, VCX = 12V, HOX = LOX = 3000pF Load. LX1672 ® TM Multiple Output LoadSHARE™ PWM P RODUCTION D ATA S HEET Parameter ` ` ` Symbol UVLO AND SOFT-START (SS) Start-Up Threshold (VCX), (VCCL) Start-Up Threshold (VCC) Hysteresis Vcc SS Input Resistance RSS SS Shutdown Threshold VSHDN Hiccup Mode Duty Cycle LINEAR REGULATOR CONTROLLER Voltage Reference Tolerance Source Current IHDRV Sink Current ILDRV DISABLE INPUT PWM Disable DISX LDO Disable LDDIS Test Conditions Min 3.5 4.0 CSS = 0.1μF VLDFB = 0.8V, COUT = 330µF VOUT = 9V VOUT = 0.4V LX1672 Typ 4.0 4.25 0.1 20 0.15 10 2 Pull down Resistance 4.5 4.5 Units V V V KΩ V % 0.2 % mA mA 1.0 80 2.5 100 V ΚΩ V KΩ 6 Pull down Resistance Max WWW . Microsemi .C OM ELECTRICAL CHARACTERISTICS Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C ≤ TA ≤ 70°C except where otherwise noted and the following test conditions: VCC = 5V, VCCL = 5V, VCX = 12V, HOX = LOX = 3000pF Load Note 1 – X = Phase 1,2 Note 2 – System Specification ELECTRICALS Copyright © 2000 Rev. 1.0, 2005-08-10 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 5 LX1672 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET RSET ISET CS1 +12V CS Comp IRESET PWM + VTRIP VS1 V in ISET R Q S Q VC1 R2 CIN R1 HO1 V out 1 L1 ESR EO1 WWW . Microsemi .C OM BLOCK DIAGRAM COUT LO1 PG1 +5V Error Comp + FB1 VCCL Hiccup - + Amplifier/ Compensation VREF 16V 20k Ramp Oscillator UVLO 16V +5V UVLO VCC S F FAULT S S R 5.5V TEMP SS1 SS2 PWGD (MLP Only) DIS1 SS CSS Figure 1 – Block Diagram of PWM Phase 1 +V +12V LDGD VC1 VREF BLOCK DIAGRAM + VOUT3 LDFB - +5V LDDIS Figure 2 – LDO Controller Block Diagram Copyright © 2000 Rev. 1.0, 2005-08-10 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 6 LX1672 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET RSET WWW . Microsemi .C OM BLOCK DIAGRAM ISET +5V CS2 Vin CS Comp IRESET VS2 VTRIP PWM + R Q ISET S Q VC2 CIN HO2 L2 V out 2 EO2 LO2 LPF2 ESR COUT PG2 +5V Error Comp + FB2 VCCL Hiccup - + Amplifier/ Compensation VREF RF2 16V 20k Ramp Oscillator LPF1 UVLO +5V 16V UVLO VCC S F FAULT S R SS1 S TEMP 5.5V SS2 PHASE1 SS CSS DIS 2 Figure 3– Block Diagram of Phase 2 Connected in LoadSHARE Mode Note: With the MLPQ package there is only one PGX output (PG1 and PG2 are common) BLOCK DIAGRAM Copyright © 2000 Rev. 1.0, 2005-08-10 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 7 LX1672 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET HO2 LO2 PG2 LDGD +3.3V +5V +2.7V VC2 VC1 HO1 LO1 PG1 LDFB LDDIS VCCL DGND VCC AGND DIS2 SS2 RF2 +12V WWW . Microsemi .C OM APPLICATION CIRCUIT +5V + L1 + +5V VS1 CS1 FB2 EO1 FB1 SS1 EO2 DIS1 CS2 VS2 1.5VDC +3.3V + L2 + Figure 4 – Bi-Phase Operation With Phase 1 & 2 LoadSHARING™ From 5V & 3.3V APPLICATION Copyright © 2000 Rev. 1.0, 2005-08-10 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 8 LX1672 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET HO2 LO2 PG2 LDGD +3.3V +5V +2.7V LDFB LDDIS DGND AGND DIS2 SS2 RF2 FB2 VC2 VC1 HO1 LO1 PG1 VCCL VCC VS1 CS1 EO1 FB1 SS1 EO2 DIS1 CS2 VS2 +12V WWW . Microsemi .C OM APPLICATION CIRCUIT +5V + L1 + 2.8VDC +5V +5V + L2 + 1.40VDC Figure 5 – Bi-Phase Operation with Phase 2 Output Tracking The Output of Phase 1. APPLICATION Copyright © 2000 Rev. 1.0, 2005-08-10 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 9 LX1672 ® TM Multiple Output LoadSHARE™ PWM P RODUCTION D ATA S HEET GENERAL DESCRIPTION The LX1672 is a voltage-mode pulse-width modulation controller integrated circuit. The internal ramp generator frequency is fixed to 300kHz. The device has external compensation, for more flexibility of output current magnitude. UNDER VOLTAGE LOCKOUT (UVLO) At power up, the LX1672 monitors the supply voltage for VCC, VCCL, and VCX (there is no requirement for sequencing the supplies). Before all supplies reach their under-voltage lockout (UVLO) thresholds, the soft-start (SS) pin is held low to prevent soft-start from beginning, the oscillator is disabled and all MOSFETs are held off. There is an internal delay that will filter out transients less that 1.5µSec. SOFT-START Once the supplies are above the UVLO threshold, the soft-start capacitor begins to be charged by the reference through a 20kΩ internal resistor. The capacitor voltage at the SS pin rises as a simple RC circuit. The SS pin is connected to the error amplifier’s non-inverting input that controls the output voltage. The output voltage will follow the SS pin voltage if sufficient charging current is provided to the output capacitor. The simple RC soft-start allows the output to rise faster at the beginning and slower at the end of the soft-start interval. Thus, the required charging current into the output capacitor is less at the end of the soft-start interval. A comparator monitors the SS pin voltage and indicates the end of soft-start when SS pin voltage reaches 95% of VREF. OVER-CURRENT PROTECTION (OCP) AND HICCUP The LX1672 uses the RDS(ON) of the upper MOSFET, together with a resistor (RSET) to set the actual current limit point. The current sense comparator senses the MOSFET current 350nS after the top MOSFET is switched on in order to reduce inaccuracies due to ringing. A current source supplies a current (ISET), whose magnitude is 50µA. The set resistor RSET is selected to set the current limit for the application. RSET and VSX should be connected directly at the upper MOSFET drain and source to get an accurate measurement across the low resistance RDS(ON). Over-current protection can also be implemented using a sense resistor, instead of using the RDS(ON) of the upper MOSFET, for greater set-point accuracy. OSCILLATOR FREQUENCY An internal oscillator sets the PWM switching frequency at 300KHz, 500KHz, or 600KHz. THEORY OF OPERATION CONFIGURATION FOR A BI-PHASE, LOADSHARE The basic principle used in LoadSHARING™, in a multiple phase buck converter topology, is that if multiple, identical, inductors have the same identical voltage impressed across their leads, they must then have the same identical current passing through them. The current that we would like to balance between inductors is mainly the DC component along with as much as possible the transient current. All inductors in a multiphase buck converter topology have their output side tied together at the output filter capacitors. Therefore, this side of all the inductors have the same identical voltage. If the input side of the inductors can be forced to have the same equivalent DC potential on this lead, then they will have the same DC current flowing. To achieve this requirement, phase 1 will be the control phase that sets the output operating voltage, under normal PWM operation. To force the current of phase 2 to be equal to the current of phase 1, a second feedback loop is used. Phase 2 has a low pass filter connected from the input side of each inductor. This side of the inductors has a square wave signal that is proportional to its duty cycle. The output of each LPF is a DC (+ some AC) signal that is proportional to the magnitude and duty cycle of its respective inductor signal. The second feedback loop will use the output of the phase 1 LPF as a reference signal for an error amplifier that will compare this reference to the output of the phase 2 LPF. This error signal will be amplified and used to control the PWM circuit of phase 2. Therefore, the duty cycle of phase 2 will be set so that the equivalent voltage potential will be forced across the phase 2 inductor as compared to the phase 1 inductor. This will force the current in the phase 2 inductor to follow and be equal to the current in the phase 1 inductor. There are four methods that can be used to implement the LoadSHARE feature of the LX1672 in the Bi-Phase mode of operation. Copyright © 2000 Rev. 1.0, 2005-08-10 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 10 APPLICATION When the sensed voltage across RDS(ON) plus the set resistor exceeds the 300mV, VTRIP threshold, the OCP comparator outputs a signal to reset the PWM latch and to start hiccup mode. The soft-start capacitor (CSS) is discharged slowly (10 times slower than when being charged up by RSS). When the voltage on the SS pin reaches a 0.1V threshold, hiccup finishes and the circuit softstarts again. During hiccup both MOSFETs for that phase are held off. Hiccup is disabled during the soft-start interval, allowing start up with maximum current. If the rate of rise of the output voltage is too fast, the required charging current to the output capacitor may be higher than the limit-current. In this case, the peak MOSFET current is regulated to the limit-current by the currentsense comparator. If the MOSFET current still reaches its limit after the soft-start finishes, the hiccup is triggered again. When the output has a short circuit the hiccup circuit ensures that the average heat generation in both MOSFETs and the average current is much less than in normal operation. WWW . Microsemi .C OM THEORY OF OPERATION LX1672 ® TM Multiple Output LoadSHARE™ PWM P RODUCTION D ATA S HEET THEORY OF OPERATION (CONTINUED) BI-PHASE, LOADSHARE ( FEEDBACK DIVIDER METHOD) The first method is to change the ratio of the inductors equivalent series resistance, (ESR). As can be seen in the previous example, if the offset error is zero and the ESR of the two inductors are identical; then the two inductor currents will be identical. To change the ratio of current between the two inductors, the value of the inductor’s ESR can be changed to allow more current to flow through one inductor than the other. The inductor with the lower ESR value will have the larger current. The inductor currents are directly proportional to the ratio of the inductor’s ESR value. The following circuit description shows how to select the inductor ESR for each phase where a different amount of power is taken from two different input power supplies. A typical setup will have a +5V power supply connected to the phase 1 half bridge driver and a +3.3V power supply connected to the phase 2 half bridge driver. The combined power output for this core voltage is 18W (+1.5V @ 12A). For this example the +5V power supply will supply 7W and the +3.3V power supply will supply the other 11W. 7W @ 1.5V is a 4.67A current through the phase 1 inductor. 11W @ 1.5V is a 7.33A current through the phase 2 inductor. The ratio of inductor ESR is inversely proportional to the power level split. ESR1 I 2 = ESR 2 I1 The higher current inductor will have the lower ESR value. If the ESR of the phase 1 inductor is selected as 10mΩ, then the ESR value of the phase 2 inductor is calculated as: ⎛ 4.67 A ⎞ ⎜ ⎟ × 10 mΩ = 6.4 mΩ ⎝ 7.33 A ⎠ Depending on the required accuracy of this power sharing; inductors can be chosen from standard vendor tables with an ESR ratio close to the required values. Inductors can also be designed for a given application so that there is the least amount of compromise in the inductor’s performance. +5V @ 7W 6.4mΩ L2 VOUT As in Figure 7, the millivolts of DC offset created by the resistor divider network in the feedback path, appears as a voltage generator between the ESR of the two inductors. A divider in the feedback path from Phase 2 will cause the voltage generator to be positive at Phase 2. With a divider in the feedback path of Phase 1 the voltage generator becomes positive at Phase 1. The Phase with the positive side of the voltage generator will have the larger current. Systems that operate continuously above a 30% power level can use this method, a down side is that that the current difference between the two inductors still flows during a no load condition. This produces a low efficiency condition during a no load or light load state, this method should not be used if a wide range of output power is required. The following description and Figure 8 show how to determine the value of the resistor divider network required to generate the offset voltage necessary to produce the different current ratio in the two output inductors. The power sharing ratio is the same as that of Figure 7. The Offset Voltage Generator is symbolic for the DC voltage offset between Phase 1 & 2. This voltage is generated by small changes in the duty cycle of Phase 2. The output of the LPF is a DC voltage proportional to the duty cycle on its input. A small amount of attenuation by a resistor divider before the LPF of Phase 2 will cause the duty cycle of Phase 2 to increase to produce the added offset at V2. The high DC gain of the error amplifier will force LPF2 to always be equal to LPF1. The following calculations determine the value of the resistor divider necessary to satisfy this example. APPLICATION 10mΩ 1.5V + 46.7mV +3.3V @ 11W 4.67A L1 Sometimes it is desirable to use the same inductor in both phases while having a much larger current in one phase versus the other. A simple resistor divider can be used on the input side of the Low Pass Filter that is taken off of the switching side of the inductors. If the Phase 2 current is to be larger than the current in Phase 1; the resistor divider is placed in the feedback path before the Low Pass Filter that is connected to the Phase 2 inductor. If the Phase 2 current needs to be less than the current in Phase 1; the resistor divider is then placed in the feedback path before the Low Pass Filter that is connected to the Phase 1 inductor. 1.5V @ 12A 18W 7.33A Figure 7 – Ratio LoadSHARE™ Using Inductor ESR Copyright © 2000 Rev. 1.0, 2005-08-10 WWW . Microsemi .C OM BI-PHASE, LOADSHARE ( ESR METHOD) Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 11 LX1672 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET WWW . Microsemi .C OM THEORY OF OPERATION (CONTINUED) . +5V @ 7W L1, Switch Side Phase 2 Error Am p 100 62k 1.5V +46.7m V LPF1 PW M Input + Not Used Resistor Divider L2, Switch Side 62k Phase 1 LPF2 Offset Voltage Generator Vout1 1.5V @ 12A 18W + 62k 100 TBD 4.67A 4700pF - Resistor Divider ESR L1 10m Ω V1 1.5V +73.3m V 4700pF ESR L2 10m Ω V2 Phase 2 7.33A +3.3V @ 11W Figure 8 – LoadSHARE™ Using Feedback Divider Offset Where V1 = 1.5467 ; V2 = 1.5733 and K = V1 V2 then TBD = K × 100 1− K = 5.814 K APPLICATION Copyright © 2000 Rev. 1.0, 2005-08-10 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 12 LX1672 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET Also a speed up capacitor can be used between the offset amplifier output and the negative input of the Phase 2 error amplifier. This will improve the transient response of the Phase 2 output current, so that it will share more equally with phase 1 current during a transient condition. The use of a MOSFET input amplifier is required for the buffer to prevent loading the low pass filter. The gain of the offset amplifier, and the value of Ra and Rb, will determine the ratio of currents between the phases at full load. Two external amplifiers are required or this method. BI-PHASE, LOADSHARE™ ( PROPORTIONAL METHOD) The best topology for generating a current ratio at full load and proportional between full load and no load is shown in figure 9. The DC voltage difference between LPF1 and VOUT is a voltage that is proportional to the current flowing in the Phase 1 inductor. This voltage can be amplified and used to offset the voltage at LPF2 through a large impedance that will not significantly alter the characteristics of the low pass filter. At no load there will be no offset voltage and no offset current between the two phases. This will give the highest efficiency at no load. L1, Switch Side Offset Amp LPF1 + 62k + Rin - - Vos Rf Phase 2 Error Amp + RF2 +5V @ 7W 1.5V +46.7mV 4700pF L2, Switch Side WWW . Microsemi .C OM THEORY OF OPERATION (CONTINUED) ESR L1 10mΩ V1 4.67A Phase 1 PWM Input - Offset Voltage Generator - Vout 1.5V @ 12A 18W + FB2 62k LPF2 62k Ra 1.5V +73.3mV 4700pF 1M V2 Rb ESR L2 10mΩ Phase 2 7.33A +3.3V @ 11W Figure 9 –LoadSHARE™ Using Proportional Control APPLICATION Copyright © 2000 Rev. 1.0, 2005-08-10 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 13 LX1672 ® TM Multiple Output LoadSHARE™ PWM P RODUCTION D ATA S HEET THEORY OF OPERATION (CONTINUED) The first decision to be made is the current sharing ratio, follow the previous examples to understand the basics of LoadSHARE™. The most common reason to imbalance the current in the two phases is because of limitations on the available power from the input rails for each phase. Use the available input power and total required output power to determine the inductor currents for each phase. All references are to Figure 9 1) Calculate the voltages V1 and V2. V 1 = L 1 Current × L 1 ESR + Vout V 2 = L 2 Current × L 2 ESR + Vout 2) Select values for Ra and Rb (Ra is typically 62KΩ ; Rb is typically 1MΩ) BI-PHASE, LOADSHARE™ (SERIES RESISTOR METHOD) A fourth but less desirable way to produce the ratio current between the two phases is to add a resistor in series with one of the inductors. This will reduce the current in the inductor that has the resistor and increase the current in the inductor of the opposite phase. The example of Figure 7 can be used to determine the current ratio by adding the value of the series resistor to the ESR value of the inductor. The added resistance will lower the overall efficiency LoadSHARE ERROR SOURCES WWW . Microsemi .C OM The circuit in Figure 9 sums a current through a 1MΩ resistor (Rb) offsetting the phase 2 error amplifier to create an imbalance in the L1 and L2 currents. Although there are many ways to calculate component values the approach taken here is to pick Ra, Rb, RIN, VOUT, and inductor ESR. A value for the remaining resistor Rf can then be calculated. With the high DC feedback gain of this second loop, all phase timing errors, RDS(On) mismatch, and voltage differences across the half bridge drivers are removed from the current sharing accuracy. The errors in the current sharing accuracy are derived from the tolerance on the inductor’s ESR and the input offset voltage specification of the error amplifier. The equivalent circuit is shown next for an absolute worst case difference of phase currents between the two inductors. 3) Calculate the offset voltage Vos at the output of the offset amplifier Offset Error 5mV + ⎛ V 2 − V1⎞ ⎟ × (Ra + Rb ) ⎝ Ra ⎠ Vos = V 2 − ⎜ ESR L1 V1 Phase 1 VOUT ESR L2 V2 4) Calculate the value for Rf Phase 2 Figure 6 – Error Amplitude (select a value for RIN typically 5KΩ) Nominal ESR of 6mΩ. ESR ±5% ⎛ Vos − VOUT ⎞ ⎜ V − V1 ⎟⎟ ⎝ OUT ⎠ Max offset Error = 6mV Rf = R IN ⎜ +5% ESR L1 = 6.3 mΩ Due to the high impedances in this circuit layout can affect the actual current ratio by allowing some of the switching waveforms to couple into the current summing path. It may be necessary to make some adjustment in Rf after the final layout is evaluated. Also, the equation for Rf requires very accurate numbers for the voltages to insure an accurate result. -5% ESR L2 = 5.7 mΩ If phase 1 current = 12 A = V 1 − VOUT = 12 × 6.3 × 10 V 1 - VOUT ESRL 1 −3 = 75.6 mV V 2 = V1 + 6 mV = 81.6 mV APPLICATION Phase 2 current = V 2 - VOUT 81.6 x 10−3 = = 14.32 A ESR L 2 5.7 x 10−3 Phase 2 current is 2.32A greater than Phase 1. Input bias current also contributes to imbalance. Copyright © 2000 Rev. 1.0, 2005-08-10 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 14 LX1672 ® TM Multiple Output LoadSHARE™ PWM P RODUCTION D ATA S HEET OUTPUT INDUCTOR OUTPUT CAPACITOR The output inductor should be selected to meet the requirements of the output voltage ripple in steady-state operation and the inductor current slew-rate during transient. The peak-topeak output voltage ripple is: D The output capacitor is sized to meet ripple and transient performance specifications. Effective Series Resistance (ESR) is a critical parameter. When a step load current occurs, the output voltage will have a step that equals the product of the ESR and the current step, ΔI. In an advanced microprocessor power supply, the output capacitor is usually selected for ESR instead of capacitance or RMS current capability. A capacitor that satisfies the ESR requirements usually has a larger capacitance and current capability than strictly needed. The allowed ESR can be found by: fs ESR × I RIPPLE + ΔI < VEX VRIPPLE = ESR × I RIPPLE where ΔI = VIN − VOUT L × ( ) ΔI is the inductor ripple current, L is the output inductor value and ESR is the Effective Series Resistance of the output capacitor. Where IRIPPLE is the inductor ripple current, ΔI is the maximum load current step change, and VEX is the allowed output voltage excursion in the transient. ΔI should typically be in the range of 20% to 40% of the maximum output current. Higher inductance results in lower output voltage ripple, allowing slightly higher ESR to satisfy the transient specification. Higher inductance also slows the inductor current slew rate in response to the load-current step change, ΔI, resulting in more output-capacitor voltage droop. When using electrolytic capacitors, the capacitor voltage droop is usually negligible, due to the large capacitance Electrolytic capacitors can be used for the output capacitor, but are less stable with age than tantalum capacitors. As they age, their ESR degrades, reducing the system performance and increasing the risk of failure. It is recommended that multiple parallel capacitors be used, so that, as ESR increase with age, overall performance will still meet the processor’s requirements. The inductor-current rise and fall times are: TRISE = L× (V ΔI IN − VOUT ) and TFALL = L× ΔI VOUT The inductance value can be calculated by L= VIN − VOUT ΔI × WWW . Microsemi .C OM APPLICATION NOTE There is frequently strong pressure to use the least expensive components possible; however, this could lead to degraded longterm reliability, especially in the case of filter capacitors. Microsemi’s demonstration boards use the CDE Polymer AL-EL (ESRE) filter capacitors, which are aluminum electrolytic, and have demonstrated reliability. The OS-CON series from Sanyo generally provides the very best performance in terms of long term ESR stability and general reliability, but at a substantial cost penalty. The CDE Polymer AL-EL (ESRE) filter series provides excellent ESR performance at a reasonable cost. Beware of offbrand, very low-cost filter capacitors, which have been shown to degrade in both ESR and general electrolytic characteristics over time. D fs APPLICATION Copyright © 2000 Rev. 1.0, 2005-08-10 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 15 LX1672 ® TM Multiple Output LoadSHARE™ PWM P RODUCTION D ATA S HEET INPUT CAPACITOR The input capacitor and the input inductor, if used, are to filter the pulsating current generated by the buck converter to reduce interference to other circuits connected to the same 5V rail. In addition, the input capacitor provides local de-coupling for the buck converter. The capacitor should be rated to handle the RMS current requirements. The RMS current is: I RMS = I L Values of Css equal to .1µF or greater are unlikely to result in saturation of the output inductor unless very large output capacitors are used.. OVER-CURRENT PROTECTION Current limiting occurs at current level ICL when the voltage detected by the current sense comparator is greater than the current sense comparator threshold, VTRIP (300mV). d(1 − d) I CL × R DS(ON) + I SET × R SET = VTRIP Where IL is the inductor current and d is the duty cycle. The maximum value occurs when d = 50%, then IRMS =0.5IL. For 5V input and output in the range of 2 to 3V, the required RMS current is very close to 0.5IL. So, R SET = SOFT-START CAPACITOR The value of the soft-start capacitor determines how fast the output voltage rises and how large the inductor current is required to charge the output capacitor. The output voltage will follow the voltage at the SS pin if the required inductor current does not exceed the maximum allowable current for the inductor. The SS pin voltage can be expressed as: ( VSS = V ref 1 − e − t/R SSCSS ) Where RSS and CSS are the soft-start resistor and capacitor. The current required to charge the output capacitor during the soft start interval is. Iout = Cout dVss dt Taking the derivative with respect to time results in Iout = VrefCout − t/R SS C SS e RssCss I SET = 300 mV − I CL × R DS(ON) 50 µA Example: For 10A current limit, using FDS6670A MOSFET (10mΩ RDS(ON)): R SET = 0.3 − 10 × 0.010 50 × 10−6 = 4K Ω Note: Maximum RSET is 6KΩ. Any resistor 6KΩ or greater will not allow startup since ICL will equal zero (50µA x 6KΩ = 300mV). At higher PWM frequencies or low duty cycles, where the upper gate drive is less than 350nS wide, the 350nS delay for current limit enable may result in current pulses exceeding the desired current limit set point. If the upper MOSFET on time is less than 350nS and a short circuit condition occurs the duty cycle will increase, since VOUT will be low. The current limit circuit will be enabled when the upper gate drive exceeds 350nS although the actual peak current limit value will be higher than calculated with the above equation. Short circuit protection still exists due to the narrow pulse width even though the magnitude of the current pulses will be higher than the calculated value. and at t=0 Im ax = VTRIP − I CL × R DS(ON) VrefCout RssCss If OCP is not desired connect both VSX and VCX to VCC. Do not leave them floating. Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 APPLICATION The required inductor current for the output capacitor to follow the soft start voltage equals the required capacitor current plus the load current. The soft-start capacitor should be selected to provide the desired power on sequencing and insure that the overall inductor current does not exceed its maximum allowable rating. Copyright © 2000 Rev. 1.0, 2005-08-10 WWW . Microsemi .C OM APPLICATION NOTE (CONTINUED) Page 16 LX1672 ® TM Multiple Output LoadSHARE™ PWM P RODUCTION D ATA S HEET OUTPUT DISABLE The LX1672 PWM MOSFET driver outputs are shut off by pulling the disable (DISX) pins above 1.2V. The LDO voltage regulator has its own Disable pin (LDDIS) for control of this output voltage. Pulling this pin above 3V disables the LDO. PROGRAMMING THE OUTPUT VOLTAGE The output Voltage is sensed by the feedback pin (FBX) which is compared to a 0.8V reference. The output voltage can be set to any voltage above 0.8V (and lower than the input voltage) by means of a resistor divider R1 - R2 (see Figure 1). VOUT = VREF (1 + R 1 /R 2 ) The LX1672 can supply both voltages by using two of the three PWM phases. Since the currents for VTT and (VDD plus VDDQ) are quite often several amps, (2A to 6A is common) a switching regulator is a logical choice VTT for DDR memory can be generated with the LX1672 by using the positive input of the phase 2 error amplifier RF2 as a reference input from an external reference voltage VREF which is defined as one half of VDDQ. Using VREF as the reference input will insure that all voltages are correct and track each other as specified in the JEDEC (EIA/JESD8-9A) specification. The phase 2 output will then be equal to VREF and track the VDDQ supply as required. When an external reference is used the Soft Start will not be functional for that phase. WWW . Microsemi .C OM APPLICATION NOTE (CONTINUED) See Microsemi Application Note 17 for more details. Note: Keep R1 and R2 close to 1kΩ (order of magnitude) DDR VTT TERMINATION VOLTAGE Double Data Rate (DDR) SDRAM requires a termination voltage (VTT) in addition to the line driver supply voltage (VDDQ) and receiver supply voltage (VDD). Although it is not a requirement VDD is generally equal to VDDQ; so that only VTT and VDDQ are required.. APPLICATION Copyright © 2000 Rev. 1.0, 2005-08-10 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 17 LX1672 TM Multiple Output LoadSHARE™ PWM ® P RODUCTION D ATA S HEET APPLICATION NOTE CONSIDERATIONS The power N-MOSFET transistor’s total gate charge spec, (Qg) should not exceed 40Nc when VCx = +12V. This condition will guarantee operation over the specified ambient temperature range. The Qg value of the N-MOSFET is directly related to the amount of power dissipation inside the IC package, from the two sets of MOSFET drivers. The equation relating Qg to the power dissipation of a MOSFET driver is: Pd = f * Qg * Vd . f = 300KHs and Vd is the supply voltage for the MOSFET driver. The two bottom MOSFET drivers are powered by the VCCL pin that is connected to +5V. The upper MOSFET drivers can be connected to the +12V supply or to a bootstrap supply generated by its output bridge. The bootstrap supply will be at +17V. Depending on the thermal environment of the application circuit, the Qg value of the N-MOSFETs will have to be less than the 40nC value. A typical configuration of the input voltage rails to generate the output voltages required is having the 5volt supply on phase 1 and the 3.3 volt supply on phase 2. At the max Qg value, the two bottom MOSFET drivers will dissipate 60mw each. The upper MOSFET drivers for phases 1 and 2 operate off of +12volts. Their dissipation is 144mw each. The total power dissipation for gate drive is 408 mw. Icc x Vcc =15ma x 5 V= 75mW. Total package power dissipation = 483mW. Using the thermal equation of: TJ = TA + Pd * Oja, the Junction temperature for this IC package is = 23 + .483 * 85 which = 64°C. This means that the ambient temperature rise has to be less than 86°C. The Soft-Start reference input has a 300mv threshold, above which the PWM starts to operate. The internal operating reference level is set at 800mV. This means that the output voltage is 37.5% low when the PWM becomes active. This starts each phase up in the current limit mode without Hiccup operation. If more than one phase is using the 5volt rail for conversion, then their soft-start capacitor values should be changed so that the two phases do not start up together. This will help reduce the amount of 5 volt input capacitance required. Also the VCC pin and the VCCL pin should be kept separated and should be decoupled separately. This will prevent the VCC pin from drooping back below the UVLO set point during start up. 3. If a phase is not used connect VSX and VCX pins to VCC. Do not leave them floating. A floating VSX pin will result in operation resembling a hiccup condition. Copyright © 2000 Rev. 1.0, 2005-08-10 When phases 1 and 2 are used in the Bi-phase mode to current share into the same output load, the phase 2 current is forced to follow the phase 1 current. It is important to use a larger softstart capacitor on phase 2 than phase 1 so that the phase 1 current becomes active before phase 2 becomes active. This will minimize any start up transient. It is also important to disable phase 1 and 2 at the same time. Disabling phase 1 without disabling phase 2, in the Bi-phase mode, allows phase 2 to turn on and off randomly because it has lost its reference. 5. The minimum RSET resistor value is 1k ohm for the current limit sensing. If this resistor becomes shorted, it will do permanent damage to the IC. 6. A resistor has been put in series with the gate of the LDO pass transistor to reduce the output noise level. The resistor value can be changed to optimize the output transient response versus output noise. 7. The LDO controller inside the IC uses the voltage at VC1 as the drive voltage. Due to noise considerations ideally the voltage on the VC1 pin would be a fixed +12volt supply. When VC1 is connected to a bootstrap supply the LDO output will reflect significant switching noise without filtering. 8. To delay the turn on of the LDO controller output, a capacitor should be connected between the LDDIS pin and the +5volts. The LDDIS input has a 100K pull down resistor, which keeps the LDO active until this pin is pulled high. During the power up sequence the capacitor connected to the LDDIS pin will keep the LDO off until this capacitor, being charge by the 100K pull down resistor, goes through the low input threshold level. Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 APPLICATION 2. 4. WWW . Microsemi .C OM 1. Page 18 LX1672 Multiple Output LoadSHARE™ PWM ® TM P RODUCTION D ATA S HEET PW 28-Pin Thin Small Shrink Outline (TSSOP) Dim 3 2 1 P E F D A H SEATING PLANE LQ B L G C M A B C D E F G H L M P *LC MILLIMETERS MIN MAX 0.85 0.95 0.19 0.30 0.09 0.20 9.60 9.80 4.30 4.50 0.65 BSC 0.05 0.15 – 1.10 0.50 0.75 0° 8° 6.25 6.50 – 0.10 INCHES MIN MAX 0.033 0.037 0.007 0.012 0.003 0.008 0.378 0.390 0.169 .176 0.025 BSC 0.002 0.005 – 0.043 0.020 0.030 0° 8° 0.246 0.256 – 0.004 MILLIMETERS MIN MAX 0.20 REF 0.18 0.30 0.18 0.18 5.00 BSC 3.00 3.25 5.00 5.25 0.50 BSC 0 0.05 0.70 0.80 7.00 BSC INCHES MIN MAX 0.0078 REF 0.007 0.011 0.007 0.007 .196 BSC 0.118 0.127 0.196 0.206 0.019 BSC 0 0.19 0.027 0.031 0.275 BSC WWW . Microsemi .C OM PACKAGE DIMENSIONS 38-Pin Thin Micro Lead Quad Package (MLPQ) D Dim E P F 3 2 1 C G I H B A Note: Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(0.006”) on any side. Lead dimension shall not include solder coverage. Copyright © 2000 Rev. 1.0, 2005-08-10 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 19 MECHANICALS C A B C D E F G H I P LX1672 TM ® Multiple Output LoadSHARE™ PWM P RODUCTION D ATA S HEET WWW . Microsemi .C OM NOTES NOTES PRODUCTION DATA – Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time. Copyright © 2000 Rev. 1.0, 2005-08-10 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 20