Product Folder Order Now Support & Community Tools & Software Technical Documents DRV10983-Q1 SLVSD14 – JUNE 2017 DRV10983-Q1 Automotive, Three-Phase, Sensorless BLDC Motor Driver 1 Features • • 1 • • • • • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level 1C – Device CDM ESD Classification Level C4A Operation Voltage Range: – Motor Operation, 6.2 V to 28 V – Register Setting Preserved, 4.5 V to 45 V Supports Load Dump Voltage up to 45 V Total Driver H + L rDS(on) – 250 mΩ at TA = 25°C – 325 mΩ at TA = 125°C Drive Current: 2-A Continuous Winding Current (3-A Peak) Configurable Output PWM Slew Rate and Frequency for EMI Management Sensorless Proprietary Back Electromotive Force (BEMF) Control Scheme (No Need of Hall Sensors) Continuous Sinusoidal 180° Commutation Initial Position-Detect Algorithm to Avoid Back Spin During Start-Up No External Sense Resistor Required Flexible User Interface Options: – I2C Interface: Access Registers for Command and Feedback – Dedicated SPEED Pin: Accepts Either Analog or PWM Input – Dedicated FG Pin: Provides TACH Feedback – Spin-Up Profile Can Be Customized With EEPROM – Forward-Reverse Control With DIR Pin Integrated Buck Converter to Efficiently Provide 5‑V and 3.3-V LDOs for Internal and External Circuits Supply Current 8.5 mA With Standby Version (DRV10983SQ) Supply Current of 48 μA With Sleep Version (DRV10983Q) Protection Features – Overcurrent Protection (Protection for Phaseto-Phase, Phase-to-GND and Phase-to-VCC Shorts – Lock Detection • – Anti-Voltage Surge (AVS) Protection – UVLO Protection – Thermal Shutdown Protection Thermally Enhanced Package 2 Applications • • • • Small Automotive Pumps and Fans Seat Ventilation Fans Motorcycle Fuel Pumps HEV Battery Cooling Fans 3 Description The DRV10983-Q1 device is a 3-phase sensorless motor driver with integrated power MOSFETs, which can provide continuous drive current up to 2 A. The device is specifically designed for cost-sensitive, lownoise, low-external-component-count fan and pump applications.™ The DRV10983-Q1 device preserves register setting down to 4.5 V and delivers current to the motor with supply voltage as low as 6.2 V. If the power supply voltage is higher than 28 V, the device stops driving the motor and protects the DRV10983-Q1 circuitry. This function is able to handle a load dump condition up to 45 V. Device Options: • DRV10983Q: Sleep Version • DRV10983SQ: Standby Version Device Information PART NUMBER DRV10983-Q1 (1) PACKAGE BODY SIZE (NOM) HTSSOP (24) 7.80 mm × 6.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Figure 1. Application Schematic VCC 0.1 µF 10 nF 10 µF 5V 47 µH 1 µF 1 µF 4.75 kW 4.75 kW 1 VCP VCC 24 2 CPP VCC 23 3 CPN W 22 4 SW W 5 SWGND V 20 6 VREG V 19 U 18 21 7 V1P8 8 GND U 17 9 V3P3 PGND 16 10 SCL 11 SDA 12 FG 10 µF M PGND 15 DIR 14 SPEED 13 Interface to Microcontroller Copyright © 2017, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (Continued) ........................................ Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 5 7.1 7.2 7.3 7.4 7.5 7.6 5 5 6 6 7 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. 8.4 Device Functional Modes........................................ 17 8.5 Register Maps ......................................................... 43 9 Application and Implementation ........................ 60 9.1 Application Information............................................ 60 9.2 Typical Application ................................................. 60 10 Power Supply Recommendations ..................... 63 11 Layout................................................................... 63 11.1 Layout Guidelines ................................................. 63 11.2 Layout Example .................................................... 63 12 Device and Documentation Support ................. 64 12.1 12.2 12.3 12.4 12.5 Detailed Description ............................................ 10 8.1 Overview ................................................................. 10 8.2 Functional Block Diagram ....................................... 11 8.3 Feature Description................................................. 11 Trademarks ........................................................... Electrostatic Discharge Caution ............................ Receiving Notification of Documentation Updates Community Resources.......................................... Glossary ................................................................ 64 64 64 64 64 13 Mechanical, Packaging, and Orderable Information ........................................................... 64 4 Revision History 2 DATE REVISION June 2017 * Submit Documentation Feedback NOTES Initial release Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 5 Description (Continued) The DRV10983-Q1 device uses a proprietary sensorless control scheme to provide continuous sinusoidal drive, which significantly reduces the pure tone acoustics that typically occur as a result of commutation. The interface to the device is designed to be simple and flexible. The motor can be controlled directly through PWM, analog, or I2C inputs. Motor speed feedback is available through both the FG pin and the I2C interface simultaneously. The DRV10983-Q1 device features an integrated buck regulator to step down the supply voltage efficiently to 5 V for powering both internal and external circuits. The 3.3-V LDO also may be used to provide power for external circuits. The device is available in either a sleep mode or a standby mode version to conserve power when the motor is not running. The standby mode (8.5 mA) version (DRV10983SQ) leaves the regulator running and the sleep mode (48 μA) version (DRV10983Q) shuts the regulator off. Use the standby mode version in applications where the regulator is used to power an external microcontroller. Throughout this data sheet, the DRV10983-Q1 part number is used for both devices i.e. DRV10983Q (sleep version) and DRV10983SQ (standby version), except for specific discussions of sleep vs standby functionality. An I2C interface allows the user to reprogram specific motor parameters in registers and to program the EEPROM to help optimize the performance for a given application. The DRV10983-Q1 device is available in a thermally-efficient HTSSOP, 24-pin package with an exposed thermal pad. The operating ambient temperature is specified from –40°C to 125°C. 6 Pin Configuration and Functions PWP PowerPAD™ Package 24-Pin HTSSOP With Exposed Thermal Pad Top View VCP 1 24 VCC CPP 2 23 VCC CPN 3 22 W SW 4 21 W SWGND 5 20 V VREG 6 19 V 18 U Thermal V1P8 7 GND 8 17 U V3P3 9 16 PGND SCL 10 15 PGND SDA 11 14 DIR FG 12 13 SPEED Pad Not to scale Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 3 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com Pin Functions PIN N/AME TYPE HTSSOP DESCRIPTION (1) CPN 3 P Charge pump pin 1, use a ceramic capacitor between CPN and CPP CPP 2 P Charge pump pin 2, use a ceramic capacitor between CPN and CPP DIR 14 I Direction; When low, phase driving sequence is U → V → W When high, phase driving sequence is U → W → V FG 12 O FG signal output indicates speed of motor GND 8 P Digital and analog ground 15, 16 P Power ground SCL 10 I I2C clock signal SDA 11 I/O I2C data signal SPEED 13 I Speed control signal for PWM or analog input speed command SW 4 O Step-down regulator switching node output SWGND 5 P Step-down regulator ground U 17, 18 O Motor U phase V 19, 20 O Motor V phase V1P8 7 P Internal 1.8-V digital core voltage. V1P8 capacitor must connect to GND. This is an output, but is not specified to drive external loads. V3P3 9 P Internal 3.3-V supply voltage. V3P3 capacitor must connect to GND. This is an output and may drive external loads not to exceed IV3P3_MAX. VCC 23, 24 P Device power supply VCP 1 P Charge pump output, use a ceramic capacitor between VCP and VCC PGND VREG W Thermal pad (GND) (1) 4 6 P Step-down regulator output and feedback point 21, 22 O Motor W phase — P The exposed thermal pad must be electrically connected to the ground plane by soldering to the PCB for proper operation, and connected to the bottom side of the PCB through vias for better thermal spreading. I = Input, O = Output, I/O = Input/output, NC = No connect, P = Power Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 7 Specifications 7.1 Absolute Maximum Ratings over operating ambient temperature range Input voltage (2) (1) MIN MAX VCC –0.3 28 VCC during load dump (VCC slew rate < 1 V/µs) –0.3 45 SPEED –0.3 4 PGND, SWGND –0.3 0.3 SCL, SDA –0.3 4 DIR –0.3 4 –1 30 U, V, W SW Output voltage (2) –1 30 VREG –0.3 7 FG –0.3 4 VCP –0.3 VCC + 6 CPN –0.3 30 CPP –0.3 VCC + 6 V3P3 –0.3 4 UNIT V V V1P8 –0.3 2.5 TJ_MAX Maximum junction temperature –40 150 °C Tstg Storage temperature –55 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the ground terminal (GND) unless otherwise noted. 7.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human body model (HBM), per AEC Q100-002, all pins (1) Charged device model (CDM), per AEC Q100-011, all pins ±2000 ±750 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 5 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com 7.3 Recommended Operating Conditions Supply voltage Voltage range MIN NOM MAX VCC, register contents preserved 4.5 12 45 VCC, motor operational 6.2 12 28 U, V, W –0.7 SCL, SDA, FG, SPEED, DIR –0.1 PGND, GND, SWGND –0.1 0.1 VCP, CPP –0.1 VCC + 5 CPN –0.1 VCC SW –0.7 VCC TA 3.3 3.6 V 100 Step-down regulator output current (resistive mode) 5 V3P3 LDO output current (no load on VREG and V3P3 in resitive mode) 5 Operating ambient temperature V 29 Step-down regulator output current (buck mode) Current range UNIT –40 125 mA °C 7.4 Thermal Information DRV10983-Q1 THERMAL METRIC (1) PWP (HTSSOP) UNIT 24 PINS RθJA Junction-to-ambient thermal resistance 36.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 17.4 °C/W RθJB Junction-to-board thermal resistance 14.8 °C/W ψJT Junction-to-top characterization parameter 0.4 °C/W ψJB Junction-to-board characterization parameter 14.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.1 °C/W (1) 6 For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 7.5 Electrical Characteristics over operating voltage and ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 48 54 UNIT SUPPLY CURRENT (DRV10983Q) IVccSLEEP1 IVcc Sleep current Active current VSPEED = 0 V; VCC = 12 V; TA = 25℃ VSPEED = 0 V; VCC = 12 V; across temperature 81 VSPEED > 0 V; buck regulator with inductor; no motor load 10 15 VSPEED > 0 V; buck regulator with resistor; no motor load 13 16 VSPEED = 0 V; buck regulator with inductor 8.5 14 VSPEED = 0 V; buck regulator with resistor 11 15 VSPEED > 0 V; buck regulator with inductor; no motor load 10 15 VSPEED > 0 V; buck regulator with resistor; no motor load 13 16 µA mA SUPPLY CURRENT (DRV10983SQ) IVccSTBY IVcc Standby current Active current mA mA UVLO VUVLO_R UVLO rising threshold voltage 5.8 6 6.2 V VUVLO_F UVLO falling threshold voltage 5.6 5.8 6 V VUVLO_HYS UVLO threshold voltage hysteresis 170 195 220 mV VV1P8_UVLO_R V1P8 UVLO rising threshold 1.5 1.6 1.7 V VV1P8_UVLO_F V1P8 UVLO falling threshold 1.4 1.55 1.65 V VV3P3_UVLO_R V3P3 UVLO rising threshold 2.7 2.85 2.95 V VV3P3_UVLO_F V3P3 UVLO falling threshold 2.5 2.7 2.8 V VVREG_UVLO_R VREG UVLO rising threshold 4 4.2 4.3 V VVREG_UVLO_F VREG UVLO falling threshold 3.9 4.2 V LDO OUTPUT V3P3 Output voltage Buck regulator with inductor, 20-mA load 3.1 3.3 3.5 V 20 mA Buck regulator with resistor, no load IV3P3_MAX Maximum load from V3P3 Only with inductor mode of buck operation, with resistor mode no load V1P8 Output voltage No load 1.7 1.8 1.9 V 4.5 5 5.5 V 100 mA 5 mA STEP-DOWN REGULATOR LSW = 47 µH, CSW = 10 µF Iload = 100 mA VREG Regulator output voltage IREG_MAX_L Maximum load from VREG in switching mode LSW = 47 µH, CSW = 10 µF IREG_MAX_R Maximum load from VREG in linear mode RSW = 39 Ω, CSW = 10 µF RSW = 39 Ω, CSW = 10 µF Iload = 5 mA INTEGRATED MOSFET rDS(ON) Series resistance (H + L) TA = 25˚C; V(VCC) > 6.5 V; Io = 1 A 250 400 TA = 125˚C; V(VCC) > 6.5V; Io = 1 A 325 550 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 mΩ 7 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com Electrical Characteristics (continued) over operating voltage and ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SPEED – ANALOG MODE VAN/A_FS Analog full-speed voltage VAN/A_ZS Analog zero-speed voltage V(V3P3) × 0.9 V(V3P3) 0 100 V tSAM Sampling period for analog voltage on SPEED pin 320 µs VAN/A_RES Analog voltage resolution 6.5 mV mV SPEED – PWM DIGITAL MODE VDIG_IH PWM input high voltage VDIG_IL PWM input low voltage ƒPWM PWM input frequency 2.2 V 0.1 0.6 V 100 kHz 100 mV SLEEP/STANDBY CONDITION VEN_SL_SB Analog voltage to enter sleep/standby SpdCtrlMd = 0 (analog mode) VEX_SL Analog voltage to exit sleep SpdCtrlMd = 0 (analog mode) 2.2 VEX_SB Analog voltage to exit standby SpdCtrlMd = 0 (analog mode) 0.17 tEX_SL Time to exit from sleep mode SpdCtrlMd = 0 (analog mode) VSPEED > VEX_SL 2 tEX_SB Time to exit from standby mode SpdCtrlMd = 0 (analog mode) VSPEED > VEX_SB 700 tEX_SL_SB Time to exit from sleep or standby condition SpdCtrlMd = 1 (PWM mode) VSPEED > VDIG_IH 2 µs tEN_SL_SB Time to enter sleep or standby condition SpdCtrlMd = 1 (PMW mode) VSPEED < VDIG_IL 60 ms V 3.3 V µs 800 ms DIGITAL I/O (DIR INPUT, FG OUTPUT ) VDIR_H Input high VDIR_L Input low VFG_OH Output high voltage Io = 5 mA VFG_OL Output low voltage Io = 5 mA 2.2 V 0.6 3.3 V V 0.6 V I2C SERIAL INTERFACE VI2C_H Input high VI2C_L Input low fI2C I2C clock frequency 2.2 V 0 0.6 V 400 kHz LOCK DETECTION RELEASE TIME tLOCK_OFF Lock release time tLCK_ETR Lock enter time 5 s 0.3 s OVERCURRENT PROTECTION IOC_limit_HS HS overcurrent protection VCC < 28.5 V 3.5 4.25 5.5 A IOC_limit_LS LS overcurrent protection VCC < 28.5 V 3.5 4.25 5.5 A THERMAL SHUTDOWN TSDN Junction temperature shutdown threshold 150 165 180 °C TSDN_HYS Junction temperature shutdown hysteresis 15 20 25 °C TWARN Junction temperature warning threshold 115 125 140 °C 8 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 Electrical Characteristics (continued) over operating voltage and ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PHASE DRIVER SLPH_LH0 Phase slew rate switching low to high PHslew = 0; measure 20% to 80%; VCC = 12 V 85 120 145 V/µs SLPH_LH1 Phase slew rate switching low to high PHslew = 1; measure 20% to 80%; VCC = 12 V 60 80 100 V/µs SLPH_LH2 Phase slew rate switching low to high PHslew = 2; measure 20% to 80%; VCC = 12 V 38 50 62 V/µs SLPH_LH3 Phase slew rate switching low to high PHslew = 3; measure 20% to 80%; VCC = 12 V 27 35 44 V/µs SLPH_HL0 Phase slew rate switching high to low PHslew = 0; measure 80% to 20%; VCC = 12 V 85 120 145 V/µs SLPH_HL1 Phase slew rate switching high to low PHslew = 1; measure 80% to 20%; VCC = 12 V 59 80 100 V/µs SLPH_HL2 Phase slew rate switching high to low PHslew = 2; measure 80% to 20%; VCC = 12 V 36 50 60 V/µs SLPH_HL3 Phase slew rate switching high to low PHslew = 3; measure 80% to 20%; VCC = 12 V 25 35 45 V/µs LOAD DUMP PROTECTION VOV_R Load dump protection mode entry on rising VCC threshold 28.5 29.2 30 V VOV_F Load dump protection mode exit on falling VCC threshold 27.7 28.2 28.8 V VOV_HYS Load dump protection mode hysteresis 0.73 1 1.1 V 7.6 Typical Characteristics 5.2 IVCC Switching Regulator Output (V) Supply Current, Standby Mode (mA) 15 12 9 6 3 0 5.1 5 4.9 4.8 0 5 10 15 20 Power Supply (V) 25 30 0 D001 Figure 2. Supply Current vs Power Supply Voltage 5 10 15 20 Power Supply (V) 25 30 D002 Figure 3. Switching Regulator Output vs Power Supply Voltage Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 9 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com 8 Detailed Description 8.1 Overview The DRV10983-Q1 device is a three-phase sensorless motor driver with integrated power MOSFETs that provides drive-current capability up to 2 A continuously. The device is specifically designed for low-noise, lowexternal-component-count motor-drive applications. The device is configurable through a simple I2C interface to accommodate different motor parameters and spin-up profiles for different customer applications. A 180° sensorless control scheme provides continuous sinusoidal output voltages to the motor phases to enable ultra-quiet motor operation by keeping the electrically induced torque ripple small. The DRV10983-Q1 device features extensive protection and fault-detection mechanisms to ensure reliable operation. Voltage surge protection prevents the input VCC capacitor from overcharging, which is typical during motor deceleration. The device provides overcurrent protection without the need for an external current-sense resistor. Rotor-lock detection is available through several methods. These methods can be configured with register settings to ensure reliable operation. The device provides additional protection for undervoltage lockout (UVLO) and for thermal shutdown. The commutation control algorithm continuously measures the motor phase current and periodically measures the VCC supply voltage. The device uses this information for BEMF estimation, and the information is also provided through the I2C register interface for debug and diagnostic use in the system, if desired. A buck switching regulator efficiently steps down the supply voltage. The output of this regulator provides power for the internal circuits and can also be used to provide power for an external circuit such as a microcontroller. If providing power for an external circuit is not necessary (and to reduce system cost), configure the buck switching regulator as a linear regulator by replacing the inductor with a resistor. The DRV10983-Q1 device has a flexible interface, capable of supporting both analog and digital inputs. In addition to the I2C interface, the device has FG, DIR, and SPEED pins. SPEED is the speed command input pin. DIR is the direction control input pin. FG is the speed indicator output, which shows the frequency of the motor commutation. EEPROM is integrated in the DRV10983-Q1 device as memory for the motor parameter and operation settings. EEPROM data transfers to the registers after power-on and exit from sleep mode. The DRV10983-Q1 device can also operate in register mode. If the system includes a microcontroller communicating through the I2C interface, the device can dynamically update the motor parameters and operation settings by writing to the registers. In this configuration, the EEPROM data is bypassed by the register settings. 10 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 8.2 Functional Block Diagram SDA I2C Communication SCL Register EEPROM VCC SW VREG VCP Charge Pump 5-V Step-Down Regulator CPP SWGND CPN V3P3 3.3-V LDO V1P8 FG VCC 1.8-V LDO GND VCP Oscillator Band Gap U V W V/I Sensor U PreDriver ADC Logic Core VCC VCP SPEED PWM and Analog Speed Control V PreDriver DIR Lock VCC Overcurrent VCP Thermal UVLO GND PreDriver W PGND Copyright © 2017, Texas Instruments Incorporated 8.3 Feature Description 8.3.1 Regulators 8.3.1.1 Step-Down Regulator The DRV10983-Q1 device includes a step-down hysteretic voltage regulator that can operate with either an external inductor or with an external resistor. The best efficiency is achieved when an external inductor (see Figure 4) is used. The regulator output voltage is 5 V. When the regulated voltage drops by the hysteresis level, the high-side FET turns on to raise the regulated voltage back to the target of 5 V. The switching frequency of the hysteretic regulator is not constant and changes with load. If the step-down regulator is configured with an external inductor, it can deliver current to the load as specified by IREG_MAX_L. If the step-down regulator is configured with an external resistor it, can deliver current to the load as specified by IREG_MAX_R. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 11 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com Feature Description (continued) IC IC VCC VREG VCC VREG 47 µH 5V 39 Ω SW 10 µF Load SW 5V 10 µF SWGND SWGND Buck Regulator with External Inductor Buck Regulator with External Resistor Figure 4. Step-Down Regulator Configurations 8.3.1.2 3.3-V and 1.8-V LDO The DRV10983-Q1 device includes a 3.3-V LDO and a 1.8-V LDO. The 1.8-V LDO is for internal circuits only. The 3.3-V LDO is mainly for internal circuits, but can also drive external loads not to exceed IV3P3_MAX. For example, it can work as a pullup voltage for the FG, DIR, SDA, and SCL interface. Both the V1P8 and V3P3 capacitors must be connected to GND. 8.3.2 Protection Circuits 8.3.2.1 Thermal Shutdown The DRV10983-Q1 device has a built-in thermal shutdown function, which shuts down the device when the junction temperature is more than TSDN˚C and recovers operating conditions when the junction temperature falls to TSDN – TSDN_HYS˚C. The OverTemp status bit (address 0x00, bit 15) is set during thermal shutdown. In addition to the thermal shutdown function there is a warning bit that is set whenever the device exceeds TWARN and is indicated by the TempWarning bit of the FaultReg register (address 0x00, bit 14). 8.3.2.2 UVLO The DRV10983-Q1 device has a built-in UVLO function block. The device is locked out when VCC is below VUVLO_F and is unlocked when VCC is above VUVLO_R. The hysteresis of the UVLO threshold is VUVLO_HYS. In addition to the main supply, the step-down regulator, charge pump, and 3.3-V LDO all have undervoltage lockout monitors. 8.3.2.3 Current Protection The overcurrent shutdown function acts to protect the device if the current, as measured from the FETs, exceeds the IOC-limit threshold. It protects the device in the event of a short-circuit condition on the motor phases. This includes phase shorts to GND, phase shorts to phase, or phase shorts to VCC. The DRV10983-Q1 device places the output drivers into a high-impedance state until the lock time tLOCK_OFF has expired. The OverCurr status bit of the FaultReg register (address 0x00, bit 11) is set. The DRV10983-Q1 device also provides acceleration current-limit and lock-detection current-limit functions to protect the device and motor (see Current Limit and Lock Detect and Fault Handling ). 12 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 Feature Description (continued) 8.3.2.4 Lock When the motor is blocked or stopped by an external force, lock protection is triggered, and the device stops driving the motor immediately. After the lock release time tLOCK_OFF, the DRV10983-Q1 device resumes driving the motor again. If the lock condition is still present, it enters the next lock protection cycle, and repeats until the lock condition is removed. With this lock protection, the motor and device do not overheat or become damaged due to the motor being locked (see Lock Detect and Fault Handling ). During a lock condition the Status register indicates which of the locks has occurred. 8.3.3 Motor Speed Control The DRV10983-Q1 device offers four methods for indirectly controlling the speed of the motor by adjusting the output voltage amplitude. This can be accomplished by varying the supply voltage (VCC) or by controlling the speed command. The speed command can be controlled in one of three ways. The user can set the speed command by adjusting either the PWM input (PWM in) or the analog input (Analog) or by writing the speed command directly through the I2C serial port (I2C). The speed command is used to determine the PWM duty cycle output (PWM_DCO) (see Figure 6). The input PWM input (PWM in) can have a minimum duty cycle limit applied. DutyCycleLimit[1:0], accessible through the I2C interface, allows the user to configure the minimum duty cycle behavior. This behavior is illustrated in Figure 5. DutyCycleLimit[1:0], Reg0x95 00 - linear down to 5%, then holds at 5% until duty command is 1.5 %; 0 % for duty command below 1.5 %. 01 - linear down to 10%, then holds at 10% until duty command is 1.5 %; 0 % for duty command below 1.5 %. Output Duty Cycle (%) 100 10 10 5 5 0 Input Duty Cycle 0 1.5 5 10 Input Duty Cycle (%) DutyCycleLimit[1:0], Reg0x95 10 - linear down to 5%, then holds at 5% until duty command is 1.5 %; 100 % for duty command below 1.5 %. 11 - linear down to 10%, then holds at 10% until duty command is 1.5 %; 100 % for duty command below 1.5 %. Output Duty Cycle (%) 0 0 1.5 5 10 Input Duty Cycle (%) Figure 5. Duty Cycle Profile The speed command may not always be equal to the PWM_DCO because the DRV10983-Q1 device has the AVS function (see Anti Voltage Supression Function), the acceleration current-limit function (see Acceleration Current Limit), and the closed-loop accelerate function (see Closed-Loop Accelerate) to optimize the control performance. These functions can limit the PWM_DCO, which affects the output amplitude (see Figure 6). Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 13 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com Feature Description (continued) PWM in PWM duty Analog ADC AVS, Acceleration Current Limit Closed Loop Accelerate Speed Command 2 IC PWM_ DCO Motor Output Amplitude X VCC Figure 6. Multiplexing the Speed Command to the Output Amplitude Applied to the Motor The output voltage amplitude applied to the motor is developed through sine wave modulation so that the phaseto-phase voltage is sinusoidal. When any phase is measured with respect to ground, the waveform is sinusoidally coupled with third-order harmonics. This encoding technique permits one phase to be held at ground while the other two phases are pulse-width modulated. Figure 7 and Figure 8 show the sinusoidal encoding technique used in the DRV10983Q1 device. PWM Output Average Value Figure 7. PWM Output and the Average Value U-V U V-W V W-U W Sinusoidal voltage from phase to phase Sinusoidal voltage with third-order harmonics from phase to GND Figure 8. Representing Sinusoidal Voltages With Third-Order Harmonic Output The output amplitude is determined by the magnitude of VCC and the PWM duty cycle output (PWM_DCO). The PWM_DCO represents the peak duty cycle that is applied in one electrical cycle. The maximum amplitude is reached when PWM_DCO is at 100%. The peak output amplitude is VCC. When the PWM_DCO is at 50%, the peak amplitude is VCC / 2 (see Figure 9). 14 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 Feature Description (continued) 100% PWM DCO 50% PWM DC0 VCC VCC/2 Figure 9. Output Voltage Amplitude Adjustment Motor speed is controlled indirectly by controlling the output amplitude, which is achieved by either controlling VCC, or controlling the PWM_DCO. The DRV10983-Q1 device provides different options for the user to control the PWM_DCO: • Analog input (SPEED pin) • PWM encoded digital input (SPEED pin) • I2C serial interface. See the Closed Loop section for more information. 8.3.4 Load Dump Handling The recommended operation voltage of the DRV10983-Q1 device is from 6.2 V to 28 V. The device is able to drive the motor within this VCC range. In the load dump condition, VCC can rise up to 45 V. Once the DRV10983-Q1 device detects that VCC is higher than VOV_R3 , it stops driving the motor and protects its own circuitry. When VCC drops below VOV_F, the DRV10983-Q1 device continues to operate the motor based on the user’s command. 8.3.5 Sleep or Standby Condition The DRV10983-Q1 device is available in either a sleep mode (DRV10983Q) or standby mode version (DRV10983SQ). The DRV10983-Q1 device enters either sleep or standby to conserve energy. When the device enters either sleep or standby, the device stops driving the motor. The switching regulator is disabled in the sleep mode version to conserve more energy. The I2C interface is disabled and any register data not stored in EEPROM is reset for the sleep mode version. The switching regulator remains active in the standby mode version. The register data is maintained, and the I2C interface remains active for standby mode version. For different speed command modes, Table 1 shows the timing and command to enter the sleep or standby condition. Table 1. Conditions to Enter or Exit Sleep or Standby Condition SPEED COMMAND MODE ENTER SLEEP OR STANDBY CONDITION EXIT FROM STANDBY CONDITION EXIT FROM SLEEP CONDITION Analog SPEED pin voltage < VEN_SL_SB for tEN_SL_SB SPEED pin voltage > VEX_SB for tEX_ SB SPEED pin high (V > VDIG_IH) for tEX_SL_SB PWM SPEED pin low (V < VDIG_IL) for tEN_SL_SB SPEED pin high (V > VDIG_IH) for tEX_SL_SB SPEED pin high (V > VDIG_IH) for tEX_SL_SB (1) I2C SpdCtrl[8:0] is programmed as 0 for tEN_SL_SB SpdCtrl[8:0] is programmed as non-zero for tEX_SL_SB SPEED pin high (V > VDIG_IH) for tEX_SL_SB (1) See Table 2 for details on PWM duty cycle requirements to exit sleep mode. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 15 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com Note that when using the analog speed command, a higher voltage is required to exit from the sleep condition than from the standby condition. The I2C speed command cannot take the device out of the sleep condition because I2C communication is disabled during the sleep condition. Table 2. Minimum PWM Duty Cycle Requirement for Different PWM Frequency to Exit Sleep Condition INPUT PWM FREQUENCY (kHz) PWM DUTY CYCLE (%) 0.1 to 0.5 14 0.5 to 1 11 1 to 50 9 50 to 100 4 100 3.5 8.3.6 EEPROM Access The DRV10983-Q1 device has 112 bits (7 registers with 16-bit width) of EEPROM data, which are used to program the motor parameters as described in the I2C Serial Interface. The procedure for programming the EEPROM is as follows. TI recommends to perform the EEPROM programming without the motor spinning, cycle the power after the EEPROM write, and read back the EEPROM to verify the programming is successful. 1. Power up with any voltage within operating voltage range (6.2 V to 28 V) 2. (DRV10983Q only) Exit from sleep condition 3. Wait 10 ms 4. Write register 0x60 to set MTR_DIS = 1; this disables the motor driver. 5. Write register 0x31 with 0x0000 to clear the EEPROM access code 6. Write register 0x31 with 0xC0DE to enable access to EEPROM 7. Read register 0x32 for eeReadyStatus = 1 8. Case-A: Mass Write (a) Write all individual shadow registers (a) Write register 0x90 (CONFIG1) with CONFIG1 data (b) ... (c) Write register 0x96 (CONFIG7) with CONFIG7 data (b) Write the following to register 0x35 (a) ShadowRegEn = 0 (b) eeRefresh = 0 (c) eeWRnEn = 1 (d) EEPROM Access Mode = 10 (c) Wait for register 0x32 eeReadyStatus = 1 – EEPROM is now updated with the contents of the shadow registers. 9. Case-B: Mass Read (a) Write the following to register 0x35 (a) ShadowRegEn = 0 (b) eeRefresh = 0 (c) eeWRnEn = 0 (d) eeAccMode = 10 (b) Internally, the device starts reading the EEPROM and storing it in the shadow registers. (c) Wait for register 0x32 eeReadyStatus = 1 – shadow registers now contain the EEPROM values 10. Write register 0x60 to set MTR_DIS = 0; this re-enables the motor driver 16 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 8.4 Device Functional Modes This section includes the logic required to be able to reliably start and drive the motor. It describes the processes used in the logic core and provides the information needed to configure the parameters effectively to work over a wide range of applications. 8.4.1 Motor Parameters See the DRV10983-Q1 Tuning Guide for the motor parameter measurement. The motor resistance and motor velocity constants are two important parameters used to characterize a BLDC motor. The DRV10983-Q1 device requires these parameters to be configured in the register. The motor resistance is programmed by writing the values for Rm[6:0] (combination of RMShift[2:0] and RMValue[3:0]) in the Config1 register. The motor velocity constant is programmed by writing the values for Kt[6:0] (combination of KTShift[2:0] and KTValue[3:0]) in the Config2 register. 8.4.1.1 Motor Resistance For a wye-connected motor, the motor phase resistance refers to the resistance from the phase output to the center tap, RPH_CT (denoted as RPH_CT in Figure 10). Phase U RPH_CT RPH_CT RPH_CT Center Tap Phase V Phase W Figure 10. Wye-Connected Motor Resistance For a delta-connected motor, the motor phase resistance refers to the equivalent phase to center tap in the wye configuration. In Figure 11, it is denoted as RY. RPH_CT = RY. For both the delta-connected motor and the wye-connected motor, the easy way to get the equivalent RPH_CT is to measure the resistance between two phase terminals (RPH_PH), and then divide this value by two, RPH_CT = ½ RPH_PH. Phase U RY Rû Rû RY Phase V Center Tap Rû RY Phase W Figure 11. Delta-Connected Motor and the Equivalent Wye Connections Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 17 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com Device Functional Modes (continued) The motor resistance (RPH_CT) must be converted to a 7-bit digital register value Rm[6:0] to program the motor resistance value. The digital register value can be determined as follows: 1. Convert the motor resistance (RPH_CT) to a digital value where the LSB is weighted to represent 9.67 mΩ: Rmdig = RPH_CT / 0.00967. 2. Encode the digital value such that Rmdig = RMValue[3:0] << RMShift[2:0]. The maximum resistor value, RPH_CT, that can be programmed for the DRV10983-Q1 device is 18.5 Ω, which represents Rmdig = 1920 and an encoded Rm[6:0] value of 0x7Fh. The minimum resistor the DRV10983-Q1 device supports is 0.029 Ω, RPH_CT, which represents Rmdig = 3. For convenience, the encoded value for Rm[6:0] can also be obtained from Table 3. Table 3. Motor Resistance Look-Up Table RM[6:0] {RMShift[2:0], RMValue[3:0]} 18 BINARY HEX 000 0000 0x00 000 0001 0x01 000 0010 0x02 000 0011 000 0100 RPH_CT (Ω) RM[6:0] {RMShift[2:0], RMValue[3:0]} BINARY HEX 0 0101000 0x28 0.0097 010 1001 0x29 0.0194 010 1010 0x03 0.0291 0x04 0.0388 000 0101 0x05 000 0110 RPH_CT (Ω) RM[6:0] {RMShift[2:0], RMValue[3:0]} RPH_CT (Ω) BINARY HEX 0.3104 1011000 0x58 2.4832 0.3492 101 1001 0x59 2.7936 0x2A 0.388 101 1010 0x5A 3.104 010 1011 0x2B 0.4268 101 1011 0x5B 3.4144 010 1100 0x2C 0.4656 101 1100 0x5C 3.7248 0.0485 010 1101 0x2D 0.5044 101 1101 0x5D 4.0352 0x06 0.0582 010 1110 0x2E 0.5432 101 1110 0x5E 4.3456 000 0111 0x07 0.0679 010 1111 0x2F 0.582 101 1111 0x5F 4.656 000 1000 0x08 0.0776 011 1000 0x38 0.6208 110 1000 0x68 4.9664 000 1001 0x09 0.0873 011 1001 0x39 0.6984 110 1001 0x69 5.5872 000 1010 0x0A 0.097 011 1010 0x3A 0.776 110 1010 0x6A 6.208 000 1011 0x0B 0.1067 011 1011 0x3B 0.8536 110 1011 0x6B 6.8288 000 1100 0x0C 0.1164 011 1100 0x3C 0.9312 110 1100 0x6C 7.4496 000 1101 0x0D 0.1261 011 1101 0x3D 1.0088 110 1101 0x6D 8.0704 000 1110 0x0E 0.1358 011 1110 0x3E 1.0864 110 1110 0x6E 8.6912 000 1111 0x0F 0.1455 011 1111 0x3F 1.164 110 1111 0x6F 9.312 001 1000 0x18 0.1552 100 1000 0x48 1.2416 111 1000 0x78 9.9328 001 1001 0x19 0.1746 100 1001 0x49 1.3968 111 1001 0x79 11.1744 001 1010 0x1A 0.194 100 1010 0x4A 1.552 111 1010 0x7A 12.416 001 1011 0x1B 0.2134 100 1011 0x4B 1.7072 111 1011 0x7B 13.6576 001 1100 0x1C 0.2328 100 1100 0x4C 1.8624 111 1100 0x7C 14.8992 001 1101 0x1D 0.2522 100 1101 0x4D 2.0176 111 1101 0x7D 16.1408 001 1110 0x1E 0.2716 100 1110 0x4E 2.1728 111 1110 0x7E 17.3824 001 1111 0x1F 0.291 100 1111 0x4F 2.328 111 1111 0x7F 18.624 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 8.4.1.2 Motor Velocity Constant The motor velocity constant, Kt[6:0] describes the phase-to-phase BEMF voltage of the motor as a function of the motor velocity. Figure 12 shows the measurement technique for this constant as used in the DRV10983-Q1 device. PhU Rm Ep Lm Te Eu Ev Lm Kt = Ew Lm Rm Ep fe Ep = 1 te Rm PhV PhW Figure 12. KtPH Definition With the motor coasting, use an oscilloscope to capture the differential voltage waveform between any two phases. Derive the motor velocity constant used by the DRV10983-Q1 device as shown in Equation 1. KtPH = Ep × te where • • Ep is ½ the peak-to-peak amplitude of the measured voltage te is the electrical period (1) The measured motor velocity constant (KtPH) must be converted to a 7-bit digital register value Kt[6:0] (combination of KtShift[2:0] and KtValue[3:0]) to program the motor velocity constant value. The digital register value can be determined as follows: 1. Convert the measured KtPH to a weighted digital value: Ktph_dig = 1090 × KtPH 2. Encode the digital value such that Ktph_dig = KtValue[3:0] << KtShift[2:0]. The maximum KtPH that can be programmed is 1760 mV/Hz. This represents a digital value of 1920 and an encoded Kt[6:0] value of 0x7Fh. The minimum KtPH that can be programmed is 0.92 mV/Hz, which represents a digital value of 1 and an encoded Kt[6:0] value of 0x01h. For convenience, the encoded value of Kt[6:0] may also be obtained from Table 4. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 19 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com Table 4. Motor Velocity Constant Look-Up Table Kt[6:0] {KtShift[2:0], KtValue[3:0]} BINARY HEX 000 0000 0x00 000 0001 0x01 000 0010 0x02 000 0011 000 0100 KtPH (mV/Hz) Kt [6:0] {KtShift[2:0], KtValue[3:0]} BINARY HEX 0 010 1000 0x28 0.92 010 1000 0x29 1.84 010 1000 0x03 2.76 0x04 3.68 000 0101 0x05 000 0110 000 0111 KtPH (mV/Hz) Kt [6:0] {KtShift[2:0], KtValue[3:0]} KtPH (mV/Hz) BINARY HEX 29.44 101 1000 0x58 235.52 33.12 101 1000 0x59 264.96 0x2A 36.8 101 1000 0x5A 294.4 010 1000 0x2B 40.48 101 1000 0x5B 323.84 010 1000 0x2C 44.16 101 1000 0x5C 353.28 4.6 010 1000 0x2D 47.84 101 1000 0x5D 382.72 0x06 5.52 010 1000 0x2E 51.52 101 1000 0x5E 412.16 0x07 6.44 010 1000 0x2F 55.2 101 1000 0x5F 441.6 000 1000 0x08 7.36 011 1000 0x38 58.88 110 1000 0x68 471.04 000 1001 0x09 8.28 011 1000 0x39 66.24 110 1000 0x69 529.92 000 1010 0x0A 9.2 011 1000 0x3A 73.6 110 1000 0x6A 588.8 000 1011 0x0B 10.12 011 1000 0x3B 80.96 110 1000 0x6B 647.68 000 1100 0x0C 11.04 011 1000 0x3C 88.32 110 1000 0x6C 706.56 000 1101 0x0D 11.96 011 1000 0x3D 95.68 110 1000 0x6D 765.44 000 1110 0x0E 12.88 011 1000 0x3E 103.04 110 1000 0x6E 824.32 000 1111 0x0F 13.8 011 1000 0x3F 110.4 110 1000 0x6F 883.2 001 1000 0x18 14.72 100 1000 0x48 117.76 111 1000 0x78 942.08 001 1001 0x19 16.56 100 1000 0x49 132.48 111 1000 0x79 1059.84 001 1010 0x1A 18.4 100 1000 0x4A 147.2 111 1000 0x7A 1177.6 001 1011 0x1B 20.24 100 1000 0x4B 161.92 111 1000 0x7B 1295.36 001 1100 0x1C 22.08 100 1000 0x4C 176.64 111 1000 0x7C 1413.12 001 1101 0x1D 23.92 100 1000 0x4D 191.36 111 1000 0x7D 1530.88 001 1110 0x1E 25.76 100 1000 0x4E 206.08 111 1000 0x7E 1648.64 001 1111 0x1F 27.6 100 1000 0x4F 220.8 111 1000 0x7F 1766.4 8.4.2 Starting the Motor Under Different Initial Conditions The motor can be in one of three states when the DRV10983-Q1 device attempts to begin the start-up process. The motor may be stationary, or spinning in the forward or reverse directions. The DRV10983-Q1 device includes a number of features to allow for reliable motor start under all of these conditions. Figure 13 shows the motor start-up flow for each of the three initial motor states. 8.4.2.1 Case 1 – Motor is Stationary If the motor is stationary, the commutation logic must be initialized to be in phase with the position of the motor. The DRV10983-Q1 device provides for two options to initialize the commutation logic to the motor position. Initial position detect (IPD) determines the position of the motor based on the deterministic inductance variation, which is often present in BLDC motors. The align-and-go technique forces the motor into alignment by applying a voltage across a particular motor phase to force the motor to rotate in alignment with this phase. 8.4.2.2 Case 2 – Motor is Spinning in the Forward Direction If the motor is spinning forward with enough velocity, the DRV10983-Q1 device may be configured to go directly into closed loop. By resynchronizing to the spinning motor, the user achieves the fastest possible start-up time for this initial condition. 8.4.2.3 Case 3 – Motor is Spinning in the Reverse Direction If the motor is spinning in the reverse direction, the DRV10983-Q1 device provides several methods to convert it back to the forward direction. 20 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 One method, reverse drive, allows the motor to be driven so that it accelerates through zero velocity. The motor achieves the shortest possible spin-up time in systems where the motor is spinning in the reverse direction. If this feature is not selected, then the DRV10983-Q1 device may be configured either to wait for the motor to stop spinning or to brake the motor. After the motor has stopped spinning, the motor start-up sequence proceeds as it would for a motor which is stationary. Take care when using the reverse-drive or brake feature to ensure that the current is limited to an acceptable level and that the supply voltage does not surge as a result of energy being returned to the power supply. IPD Stationary Align and Go Spinning forward Direct closed loop Wait Spinning reversely Brake Reverse drive Figure 13. Start the Motor Under Different Initial Conditions Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 21 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com 8.4.3 Motor Start Sequence Figure 14 shows the motor-start sequence implemented in the DRV10983-Q1 device. Power on DIR pin change N ISDen Y ISD Y N Forward Speed < ISDThr N Y Y Speed > RvsDrThr Y N Motor Resynchronization RvsDrEn N BrkEn N Brake IPDEn Time > BrkDoneThr Y Y Y N N Align Accelerate RvsDr IPD N ClosedLoop Speed > Op2CIsThr Y Figure 14. Motor Starting-Up Flow Power-On State This is the initial power-on state of the motor start sequencer (MSS). The MSS starts in this state on initial power-up or whenever the DRV10983-Q1 device comes out of either standby or sleep mode. ISDen Judgment After power-on, the DRV10983-Q1 MSS enters the ISDen judgment where it checks to see if the initial speed detect (ISD) function is enabled (ISDen = 1). If ISD is disabled, the MSS proceeds directly to the BrkEn Judgment. If ISD is enabled, the motor start sequence advances to the ISD state. ISD State The MSS determines the initial condition of the motor (see Initial Speed Detect). Speed<ISDThr Judgment If the motor speed is lower than the threshold defined by ISDThr[1:0], then the motor is considered to be stationary and the MSS proceeds to the BrkEn judgment. If the speed is greater than the threshold defined by ISDThr[1:0], the start sequence proceeds to the Forward judgment. Forward Judgment The MSS determines whether the motor is spinning in the forward or the reverse direction. If the motor is spinning in the forward direction, the DRV10983-Q1 device executes the resynchronization (see Motor Resynchronization) process by transitioning directly into the ClosedLoop state. If the motor is spinning in the reverse direction, the MSS proceeds to the 22 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 Speed>RvsDrThr. Speed>RvsDrThr Judgment The motor start sequencer checks to see if the reverse speed is greater than the threshold defined by RvsDrThr[1:0]. If it is, then the MSS returns to the ISD state to allow the motor to decelerate. This prevents the DRV10983-Q1 device from attempting to reverse drive or brake a motor that is spinning too quickly. If the reverse speed of the motor is less than the threshold defined by RvsDrThr[1:0], then the MSS advances to the RvsDrEn judgment. RvsDrEn Judgment The MSS checks to see if the reverse drive function is enabled (RvsDrEn = 1). If it is, the MSS transitions into the RvsDr state. If the reverse drive function is not enabled, the MSS advances to the BrkEn judgment. RvsDr State The DRV10983-Q1 device drives the motor in the forward direction to force it to rapidly decelerate (see Reverse Drive). When it reaches zero velocity, the MSS transitions to the Accelerate state. BrkEn Judgment The MSS checks to determine whether the brake function is enabled (BrkDoneThr[2:0] ≠ 000). If the brake function is enabled, the MSS advances to the brake state. Brake State The device performs the brake function (see Motor Brake). Time>BrkDoneThr Judgment The MSS applies brake for a time configured by BRKDoneThr[2:0]. After brake state, the MSS advances to the IPDEn judgment. IPDEn Judgment The MSS checks to see if IPD has been enabled (IPDCurrThr[3:0] ≠ 0000). If the IPD is enabled, the MSS transitions to the IPD state. Otherwise, it transitions to the align state. Align State The DRV10983-Q1 device performs the align function (see Align). After the align completes, the MSS transitions to the Accelerate state. IPD State The DRV10983-Q1 device performs the IPD function. The IPD function is described in IPD. After the IPD completes, the MSS transitions to the accelerate state. Accelerate State The DRV10983-Q1 device accelerates the motor according to the settings of StAccel and StAccel2. After applying the accelerate settings, the MSS advances to the Speed>Op2ClsThr judgment. Speed>Op2ClsThr Judgment The motor accelerates until the drive rate exceeds the threshold configured by the Op2ClsThr[4:0] settings. When this threshold is reached, the DRV10983-Q1 device enters into the ClosedLoop state. ClosedLoop State In this state, the DRV10983-Q1 device drives the motor based on feedback from the commutation control algorithm. DIR Pin Change Judgment If the DIR pin is changed during any of above states, DRV10983-Q1 device stops driving the motor and restarts from the beginning. 8.4.3.1 Initial Speed Detect The ISD function is used to identify the initial condition of the motor. If the function is disabled, the DRV10983-Q1 device does not perform the initial speed detect function and treats the motor as if it is stationary. Phase-to-phase comparators are used to detect the zero crossings of the motor’s BEMF voltage while it is coasting (motor phase outputs are in the high-impedance state). Figure 15 shows the configuration of the comparators. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 23 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com 60 degrees ± V + U + ± W Figure 15. Initial Speed Detect Function If the UW comparator output is lagging the UV comparator by 60°, the motor is spinning forward. If the UW comparator output is leading the UV comparator by 60°, the motor is spinning in reverse. The motor speed is determined by measuring the time between two rising edges of either of the comparators. If neither of the comparator outputs toggles for a given amount of time, the condition is defined as stationary. The amount of time can be programmed by setting the register bits ISDThr[1:0]. 8.4.3.2 Motor Resynchronization The resynchronize function works when the ISD function is enabled and determines that the initial state of the motor is spinning in the forward direction. The speed and position information measured during ISD are used to initialize the drive state of the DRV10983-Q1 device, which can transition directly into the closed-loop running state without needing to stop the motor. 8.4.3.3 Reverse Drive The ISD function measures the initial speed and the initial position; the DRV10983-Q1 reverse drive function acts to reverse accelerate the motor through zero speed and to continue accelerating until the closed loop threshold is reached (see Figure 16). If the reverse speed is greater than the threshold configured in RvsDrThr[1:0], then the DRV10983-Q1 device waits until the motor coasts to a speed that is less than the threshold before driving the motor to reverse accelerate. Speed Closed loop Op2ClsThr Open loop Time RevDrThr Reverse Drive Coasting Figure 16. Reverse Drive Function 24 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 Reverse drive is suitable for applications where the load condition is light at low speed and relatively constant and where the reverse speed is low (that is, a fan motor with little friction). For other load conditions, the motor brake function provides a method for helping force a motor which is spinning in the reverse direction to stop spinning before a normal start-up sequence. 8.4.3.4 Motor Brake The motor brake function can be used to stop the spinning motor before attempting to start the motor. The brake is applied by turning on all three of the low-side driver FETs. Brake is enabled by configuring a non-zero BrkDoneThr[2:0]. Brake is applied for a time configured by BrkDoneThr[2:0] (forward or reverse). After the motor is stopped, the motor position is unknown. To proceed with restarting in the correct direction, the IPD or align-and-go algorithm must be implemented. The motor start sequence is the same as it would be for a motor starting in the stationary condition. The motor brake function can be disabled. The motor skips the brake state and attempts to spin the motor as if it were stationary. If this happens while the motor is spinning in either direction, the start-up sequence may not be successful. 8.4.3.5 Motor Initialization 8.4.3.5.1 Align The DRV10983-Q1 device aligns a motor by injecting dc current through a particular phase pattern which is current flowing into phase V, flowing out from phase W for a certain time (configured by AlignTime[2:0]). The current magnitude is determined by OpenLCurr[1:0]. The motor should be aligned at the known position. The time of align affects the start-up timing (see Start-Up Timing). A bigger-inertia motor requires longer align time. 8.4.3.5.2 IPD The inductive sense method is used to determine the initial position of the motor when IPD is enabled. IPD is enabled by selecting IPDCurrThr[3:0] to any value other than 0000. IPD can be used in applications where reverse rotation of the motor is unacceptable. Because IPD is not required to wait for the motor to align with the commutation, it can allow for a faster motor start sequence. IPD works well when the inductance of the motor varies as a function of position. Because it works by pulsing current to the motor, it can generate acoustics which must be taken into account when determining the best start method for a particular application. 8.4.3.5.2.1 IPD Operation The IPD operates by sequentially applying voltage across two of the three motor phases according to the following sequence: VW WV UV VU WU UW (see Figure 17). When the current reaches the threshold configured in IPDCurrThr[3:0], the voltage across the motor is stopped. The DRV10983-Q1 device measures the time it takes from when the voltage is applied until the current threshold is reached. The time varies as a function of the inductance in the motor windings. The state with the shortest time represents the state with the minimum inductance. The minimum inductance is because of the alignment of the north pole of the motor with this particular driving state. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 25 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com U IPDclk N V Clock S W Drive VW WV UV VU WU UW IPDCurrThr Current Search the Minimum Time Permanent Magnet Position Saturation Position of the Magnetic Field Smallest Inductance Minimum Time Figure 17. IPD Function 8.4.3.5.2.2 IPD Release Mode Two options are available for stopping the voltage applied to the motor when the current threshold is reached. If IPDRlsMd = 0, the recirculate mode is selected. The low-side (S6) MOSFET remains on to allow the current to recirculate between the MOSFET (S6) and body diode (S2) (see Figure 18). If IPDRlsMd = 1, the tri-state mode is selected. Both the high-side (S1) and low-side (S6) MOSFETs are turned off and the current flies back across the body diodes into the power supply (see Figure 19). In the high-impedance state, the phase current has a faster settle-down time, but that could result in a surge on VCC. Manage this with appropriate selection of either a clamp circuit or by providing sufficient capacitance between VCC and GND. If the voltage surge cannot be contained and if it is unacceptable for the application, then select the recirculate mode. When selecting the recirculate mode, select the IPDClk[1:0] bits to give the current in the motor windings enough time to decay to 0. S1 S3 S5 M U1 S2 Driving S1 S4 S6 S3 S5 M U1 S2 S4 S6 Brake (Recirculate) Figure 18. IPD Release Mode 0 26 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 S1 S3 S5 S1 M U1 S2 S4 S3 S5 M U1 S6 S2 Driving S4 S6 Hi-Z (Tri-State) Figure 19. IPD Release Mode 1 8.4.3.5.2.3 IPD Advance Angle After the initial position is detected, the DRV10983-Q1 device begins driving the motor at an angle specified by IPDAdvcAgl[1:0]. Advancing the drive angle anywhere from 0° to 180° results in positive torque. Advancing the drive angle by 90° results in maximum initial torque. Applying maximum initial torque could result in uneven acceleration to the rotor. Select the IPDAdvcAgl[1:0] to allow for smooth acceleration in the application (see Figure 20). Motor spinning direction U V N S W U N V U N V U N V U N S S S S W W W W Û DGYDQFH Û advance Û DGYDQFH V Û DGYDQFH Figure 20. IPD Advance Angle 8.4.3.5.3 Motor Start After it is determined that the motor is stationary and after completing the motor initialization with either align or IPD, the DRV10983-Q1 device begins to accelerate the motor. This acceleration is accomplished by applying a voltage determined by the open-loop current setting (OpenLCurr[1:0]) to the appropriate drive state and by increasing the rate of commutation without regard to the real position of the motor (referred to as open-loop operation). The function of the open-loop operation is to drive the motor to a minimum speed so that the motor generates sufficient BEMF to allow the commutation control logic to accurately drive the motor. Table 5 lists the configuration options that can be set in register to optimize the initial motor acceleration stage for different applications. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 27 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com Table 5. Configuration Options for Controlling Open-Loop Motor Start REG. NAME CONFIGURATION BITS MIN. VALUE MAX. VALUE Open- to closed-loop threshold CONFIG4 Op2ClsThr[4:0] 0.8 Hz 204.8 Hz Align time CONFIG4 AlignTime[2:0] 40 ms 5.3 s First-order accelerate CONFIG4 StAccel[2:0] 0.019 Hz/s 76 Hz/s Second-order accelerate CONFIG4 StAccel2[2:0] 0.0026 Hz/s2 57 Hz/s2 CONFIG3 OpenLCurr[1:0] 200 mA 1.6 A CONFIG3 OpLCurrRt[2:0] DESCRIPTION Open-loop current setting Align current setting Open-loop current ramping 150 mA 1.2 A 0.023 VCC/s 6 VCC/s 8.4.3.6 Start-Up Timing Start-up timing is determined by the align and accelerate time. The align time can be set by AlignTime[2:0]. The accelerate time is defined by the open-to-closed loop threshold Op2ClsThr[4:0] along with the first-order StAccel[2:0](A1) and second-order StAccel2[2:0](A2) accelerate rates. Figure 21 shows the motor start-up process. Speed Speed = 2 A1 ´ t + 0.5 A2 ´ t Close loop Op2ClsThr AlignTime Time Accelerate Time is determined by Op2ClsThr and A1, A2. Accelerate Time Figure 21. Motor Start-Up Process Select the first-order and second-order accelerate rates to allow the motor to reliably accelerate from zero velocity up to the closed-loop threshold in the shortest time possible. Using a slow accelerate rate during the first order accelerate stage can help improve reliability in applications where it is difficult to accurately initialize the motor with either align or IPD. Select the open-to-closed loop threshold to allow the motor to accelerate to a speed that generates sufficient BEMF for closed-loop control. This is determined by the velocity constant of the motor based on the relationship described in Equation 2. BEMF = KtPH × speed (Hz) (2) 8.4.4 Align Current During the align state, the measured align current is dependent on actual motor resistance and rDS(on) of the internal FETs. The relationship between measured align current and configured align current is derived from actual motor resistance, configured motor resistance and rDS(on). é ù Rm AlignCurrent _ Measured = AlignCurrent _ Configured ´ ê ú ëê R motor + rDS(on) ûú where • • • • • 28 AlignCurrent_Measured is the actual align current measured during the align state AlignCurrent_Configured is the align current configured by OpenLCurr[1:0] Rmotor is the actual motor resistance rDS(on) is the resistance between the drain and source of the FETs during the on-state Rm is configured by Rm[6:0] Submit Documentation Feedback (3) Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 8.4.5 Start-Up Current Setting The start-up current setting is to control the peak start-up during open loop. During open-loop operation, it is desirable to control the magnitude of drive current applied to the motor. This is helpful in controlling and optimizing the rate of acceleration. The limit takes effect during reverse drive, align, and acceleration. The start current is set by programming the OpenLCurr[1:0] bits. The current should be selected to allow the motor to reliably accelerate to the handoff threshold. Heavier loads may require a higher current setting, but it should be noted that the rate of acceleration is limited by the acceleration rate (StAccel[2:0], StAccel2[2:0]). If the motor is started with more current than necessary to reliably reach the handoff threshold, it results in higher power consumption. The start current is controlled based on the relationship shown in Equation 4 and Figure 22. The duty cycle applied to the motor is derived from the calculated value for ULimit and the magnitude of the supply voltage, VCC, as well as the drive state of the motor. ULimit ILimit u Rm Speed Hz u Kt where • • • • ILimit is configured by OpenLCurr[1:0] Rm is configured by Rm[6:0] Speed is variable based motor’s open loop acceleration profile Kt is configured by Kt[6:0] (4) Rm U = BEMF + I × Rm M BEMF = kt × speed Figure 22. Motor Start-Up Current 8.4.5.1 Start-Up Current Ramp-Up A fast change in the applied drive current may result in a sudden change in the driving torque. In some applications, this could result in acoustic noise. To avoid this, the DRV10983-Q1 device allows the option of limiting the rate at which the current is applied to the motor. OpLCurrRt[2:0] sets the maximum voltage ramp-up rate that is applied to the motor. The waveforms in Figure 23 show how this feature can be used to gradually ramp the current applied to the motor. Start driving with fast current ramp Start driving with slow current ramp Figure 23. Motor Start-Up Current Ramp 8.4.6 Closed Loop In closed loop operation, the DRV10983-Q1 device continuously samples the current in the U phase of the motor and uses this information to estimate the BEMF voltage that is present. The drive state of the motor is controlled based on the estimated BEMF voltage. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 29 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com 8.4.6.1 Half-Cycle Control and Full-Cycle Control The estimated BEMF used to control the drive state of the motor has two zero-crosses every electrical cycle. The DRV10983-Q1 device can be configured to update the drive state either once every electrical cycle or twice for every electrical cycle. When AdjMode is programmed to 1, half-cycle adjustment is applied. The control logic is triggered at both the rising edge and falling edge. When AdjMode is programmed to 0, full-cycle adjustment is applied. The control logic is triggered only at the rising edge (see Figure 24). Half-cycle adjustment provides a faster response when compared with full-cycle adjustment. Use half-cycle adjustment whenever the application requires operation over large dynamic loading conditions. Use the full-cycle adjustment for low-current (<1 A) applications because it offers more tolerance for current-measurement offset errors. Zero cross signal Estimated Position Real Driving Voltage Real Position Ideal Driving Voltage Zero cross signal Estimated Position Real Driving Voltage Adjustment (full cycle) Real Position Ideal Driving Voltage Adjustment (half cycle) Figure 24. Closed-Loop Control Commutation-Adjustment Mode 8.4.6.2 Analog-Mode Speed Control The SPEED input pin can be configured to operate as an analog input (SpdCtrlMd = 0). When configured for analog mode, the voltage range on the SPEED pin can be varied from 0 to V3P3. If SPEED > VANA_FS, the speed command is maximum. If VANA_ZS ≤ SPEED < VANA_FS the speed command changes linearly according to the magnitude of the voltage applied at the SPEED pin. If SPEED < VANA_ZS the speed command is to stop the motor. Figure 25 shows the speed command when operating in analog mode. Speed Command Maximum Speed Command Analog Input VANA-ZS VANA-FS Figure 25. Analog-Mode Speed Command 8.4.6.3 Digital PWM-Input-Mode Speed Control If SpdCtrlMd = 1, the SPEED input pin is configured to operate as a PWM-encoded digital input. The PWM duty cycle applied to the SPEED pin can be varied from 0 to 100%. The speed command is proportional to the PWM input duty cycle. The speed command stops the motor when the PWM input keeps at 0 for tEN_SL_SB (see Figure 26). The frequency of the PWM input signal applied to the SPEED pin is defined as fPWM. This is the frequency the device can accept to control motor speed. It does not correspond to the PWM output frequency that is applied to the motor phase. The PWM output frequency can be configured to be either 25 kHz when the PWMFreq bit is set to 0 or to 50 kHz when PWMFreq bit is set to 1. 30 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 Speed Command Maximum Speed Command PWM duty 0 100% Figure 26. PWM-Mode Speed Command 8.4.6.4 I2C-Mode Speed Control The DRV10983-Q1 device can also command the speed through the I2C serial interface. To enable this feature, the OverRide bit is set to 1. When the DRV10983-Q1 device is configured to operate in I2C mode, it ignores the signal applied to the SPEED pin. The speed command can be set by writing the SpdCtrl[8:0] bits. The 9-bit SpdCtrl [8:0] located in the SpeedCtrl registers is used to set the peak amplitude voltage applied to the motor. The maximum speed command is set when SpdCtrl [8:0] is set to 0x1FF (511). 8.4.6.5 Closed-Loop Accelerate To prevent sudden changes in the torque applied to the motor which could result in acoustic noise, the DRV10983-Q1 device provides the option of limiting the maximum rate at which the speed command changes. ClsLpAccel[2:0] can be programmed to set the maximum rate at which the speed command changes (shown in Figure 27). y% Speed command input x% y% Speed command after closed loop accelerate buffer x% Closed loop accelerate settings Figure 27. Closed Loop Accelerate 8.4.6.6 Control Coefficient The DRV10983-Q1 device continuously measures the motor current and uses this information to control the drive state of the motor when operating in closed-loop mode. In applications where noise makes it difficult to control the commutation optimally, the CtrlCoef[1:0] can be used to attenuate the feedback used for closed-loop control. The loop is less reactive to the noise on the feedback and provides for a smoother output. 8.4.6.7 Commutation Control Advance Angle To achieve the best efficiency, it is often desirable to control the drive state of the motor so that the motor phase current is aligned with the motor BEMF voltage. To align the motor phase current with the motor BEMF voltage, consider the inductive effect of the motor. The voltage applied to the motor should be applied in advance of the motor BEMF voltage (see Figure 28). The DRV10983-Q1 device provides configuration bits for controlling the time (tadv) between the driving voltage and BEMF. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 31 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com For motors with salient pole structures, aligning the motor BEMF voltage with the motor current may not achieve the best efficiency. In these applications, the timing advance should be adjusted accordingly. Accomplish this by operating the system at constant speed and load conditions and by adjusting tadv until the minimum current is achieved. Phase Voltage Phase BEMF Phase Current tadv Figure 28. Advance Time (tadv) Definition The DRV10983-Q1 device has two options for adjusting the motor commutate advance time. When CommAdvMode = 0, mode 0 is selected. When CommAdvMode = 1, mode 1 is selected. Mode 0: tadv is maintained to be a fixed time relative to the estimated BEMF zero cross as determined by Equation 5. tadv = tSETTING (5) Mode 1: tadv is maintained to be a variable time relative to the estimated BEMF zero cross as determined by Equation 6. tadv = tSETTING × (U - BEMF) / U. where • • U is the phase voltage amplitude BEMF is phase BEMF amplitude (6) tSETTING (in µs) is determined by the configuration of the TCtrlAdvShift [2:0] and TCtrlAdvValue [3:0] bits as defined in Equation 7. For convenience, the available tSETTING values are provided in Table 6. tSETTING = 2.5 µs × [TCtrlAdvValue[3:0]] << TCtrlAdvShift[2:0] 32 Submit Documentation Feedback (7) Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 Table 6. Configuring Commutation Advance Timing by Adjusting tSETTING TCtrlAdv [6:0] {TCtrlAdvShift[2:0], TCtrlAdvValue[3:0]} tSETTING (µs) TCtrlAdv [6:0] {TCtrlAdvShift[2:0], TCtrlAdvValue[3:0]} Binary Hex Binary Hex 000 0000 0x00 0.0 010 1000 0x28 000 0001 0x01 2.5 010 1001 000 0010 0x02 5 010 1010 000 0011 0x03 7.5 010 1011 000 0100 0x04 10 000 0101 0x05 000 0110 0x06 000 0111 0x07 000 1000 000 1001 000 1010 tSETTING (µs) TCtrlAdv [6:0] {TCtrlAdvShift[2:0], TCtrlAdvValue[3:0]} tSETTING (µs) Binary Hex 80 101 1000 0x58 640 0x29 90 101 1001 0x59 720 0x2A 100 101 1010 0x5A 800 0x2B 110 101 1011 0x5B 880 010 1100 0x2C 120 101 1100 0x5C 960 12.5 010 1101 0x2D 130 101 1101 0x5D 1040 15 010 1110 0x2E 140 101 1110 0x5E 1120 17.5 010 1111 0x2F 150 101 1111 0x5F 1200 0x08 20 011 1000 0x38 160 110 1000 0x68 1280 0x09 22.5 011 1001 0x39 170 110 1001 0x69 1440 0x0A 25 011 1010 0x3A 200 110 1010 0x6A 1600 000 1011 0x0B 27.5 011 1011 0x3B 220 110 1011 0x6B 1760 000 1100 0x0C 30 011 1100 0x3C 240 110 1100 0x6C 1920 000 1101 0x0D 32.5 011 1101 0x3D 260 110 1101 0x6D 2080 000 1110 0x0E 35 011 1110 0x3E 280 110 1110 0x6E 2240 000 1111 0x0F 37.5 011 1111 0x3F 300 110 1111 0x6F 2400 001 1000 0x18 40 100 1000 0x48 320 111 1000 0x78 2560 001 1001 0x19 45 100 1001 0x49 360 111 1001 0x79 2880 001 1010 0x1A 50 100 1010 0x4A 400 111 1010 0x7A 3200 001 1011 0x1B 55 100 1011 0x4B 440 111 1011 0x7B 3520 001 1100 0x1C 60 100 1100 0x4C 480 111 1100 0x7C 3840 001 1101 0x1D 65 100 1101 0x4D 520 111 1101 0x7D 4160 001 1110 0x1E 70 100 1110 0x4E 560 111 1110 0x7E 4480 001 1111 0x1F 75 100 1111 0x4F 600 111 1111 0x7F 4800 8.4.7 Current Limit The DRV10983-Q1 device has several current-limit modes to help ensure optimal control of the motor and to ensure safe operation. The various current-limit modes are listed in Table 7. Acceleration current limit is used to provide a means of controlling the amount of current delivered to the motor. This is useful when the system needs to limit the amount of current pulled from the power supply during motor start-up. The lock-detection current limit is a configurable threshold that can be used to limit the current applied to the motor. Overcurrent protection is used to protect the device; therefore, it cannot be disabled or configured to a different threshold. The current-limit modes are described in the following sections. Table 7. DRV10983-Q1 Current-Limit Modes CURRENT LIMIT MODE SITUATION ACTION FAULT DIAGNOSIS Acceleration current limit Motor start Limit the output voltage amplitude No fault Lock-detection current limit Motor locked Stop driving the motor and enter the lock state Mechanical rotation error Overcurrent shutdown Short circuit Stop driving the motor and enter the lock state Circuit connection 8.4.7.1 Acceleration Current Limit The acceleration current limit limits the voltage applied to the motor to prevent the current from exceeding the programmed threshold. The acceleration current limit threshold is configured by writing the SWiLimitThr[3:0] bits to select ILIMIT. The acceleration current limit does not use a direct measurement of current. It uses the programmed motor resistance, Rm, and programmed motor velocity constant, Kt, to limit the voltage applied to the motor, U, as shown in Figure 29 and Equation 8. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 33 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com When the acceleration current limit is active, it does not stop the motor from spinning nor does it trigger a fault. The functionality of the acceleration current limit is only available in closed-loop control. Rm ULIMIT ILIMIT M BEMF = Kt ´ speed Figure 29. Acceleration Current Limit ULIMIT = ILIMIT × Rm + Speed × Kt (8) 8.4.8 Lock Detect and Fault Handling The DRV10983-Q1 device provides several options for determining if the motor becomes locked as a result of some external torque. Five lock-detect schemes work together to ensure the lock condition is detected quickly and reliably. Figure 30 shows the logic which integrates the various lock-detect schemes. When a lock condition is detected, the DRV10983-Q1 device takes action to prevent continuously driving the motor in order to prevent damage to the system or the motor. In addition to detecting if there is a locked motor condition, the DRV10983-Q1 device also identifies and takes action if there is no motor connected to the system. Each of the five lock-detect schemes and the no-motor detection can be disabled by respective register bits LockEn[5:0]. When a lock condition is detected, the FaultReg register provides an indication of which of the six different conditions was detected on Lock5 to Lock0. These bits are reset when the motor restarts. The bits in the FaultReg register are set even if the lock detect scheme is disabled. The DRV10983-Q1 device reacts to either locked-rotor or no-motor-connected conditions by putting the output drivers into a high-impedance state. To prevent the energy in the motor from pumping the supply voltage, the DRV10983-Q1 device incorporates an anti-voltage-surge (AVS) process whenever the output stages transition into the high-impedance state. The AVS function is described in Anti Voltage Supression Function. After entering the high-impedance state as a result of a fault condition, the system tries to restart after tLOCK_OFF. LockEn (0, 1, 2, 3, 4, 5) Lock detection current limit Speed abnormal BEMF abnormal Or No motor fault Tri-state and restart logic Open loop stuck Closed loop stuck Set Register: FaultReg[5:0] Reset Figure 30. Lock Detect and Fault Diagnose 34 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 8.4.8.1 Lock0: Lock-Detection Current Limit Triggered The lock-detection current-limit function provides a configurable threshold for limiting the current to prevent damage to the system. This is often tripped in the event of a sudden locked-rotor condition. The DRV10983-Q1 device continuously monitors the current in the low-side drivers as shown in Figure 31. If the current goes higher than the threshold configured by the HWiLimitThr[2:0] bits, then the DRV10983-Q1 device stops driving the motor by placing the output phases into a high-impedance state. The Lock0 bit is set and a lock condition is reported. It retries after tLOCK_OFF. Set the lock-detection current limit to a higher value than the acceleration current limit. + DigitalCore – DAC Figure 31. Lock-Detection Current Limit 8.4.8.2 Lock1: Abnormal Speed If the motor is operating normally, the motor BEMF should always be less than the output amplitude. The DRV10983-Q1 device uses two methods of monitoring the BEMF in the system. The U phase current is monitored to maintain an estimate of BEMF based on the setting for Rm[6:0] {RmShift[2:0],RmValue[3:0]}. In addition, the BEMF is estimated based on the operation speed of the motor and the setting for Kt[6:0] {KtShift[2:0],KtValue[3:0]}. Figure 32 shows the method for using this information to detect a lock condition. If the motor BEMF is much higher than the output amplitude for a certain period of time, tLCK_ETR, it means the estimated speed is wrong, and the motor has gotten out of phase. Rm BEMF1 = U – I × Rm I U M BEMF2 = Kt × speed Lock detected if BEMF2 > U Figure 32. Lock Detection 1 8.4.8.3 Lock2: Abnormal Kt For any given motor, the integrated value of BEMF during half of an electrical cycle is constant. The value is determined by the motor velocity constant (KtPH) (see Figure 33). The motor velocity constant is the same regardless of whether the motor is running fast or slow. This constant value is continuously monitored by calculation and used as a criterion to determine the motor lock condition, and is referred to as Ktc. Based on the KtPH value programmed, create a range from Kt_low to Kt_high. If Ktc goes beyond the range for a certain period of time, tLCK_ETR, lock is detected. Kt_low and Kt_high are determined by KtLckThr[1:0] (see Figure 34). Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 35 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com Figure 33. BEMF Integration Kt_high Ktc Kt Kt_low Lock detect Figure 34. Abnormal-Kt Lock Detect 8.4.8.4 Lock3 (Fault3): No-Motor Fault The phase U current is checked after transitioning from open loop to closed loop. If phase U current is not greater than 140 mA then the motor is not connected as shown in Figure 35. This condition is treated and reported as a fault. DRV10983-Q1 M Figure 35. No Motor Error 8.4.8.5 Lock4: Open-Loop Motor-Stuck Lock Lock4 is used to detect locked-motor conditions while the motor start sequence is in open loop. For a successful startup, motor speed should be equal to the open-to-closed-loop handoff threshold when the motor is transitioning into closed loop. However, if the motor is locked, the motor speed is not able to match the open-loop drive rate. If the motor BEMF is not detected for one electrical cycle after the open-loop drive rate exceeds the threshold, then the open loop was unsuccessful as a result of a locked-rotor condition. 8.4.8.6 Lock5: Closed Loop Motor Stuck Lock If the motor suddenly becomes locked, motor speed and Ktc are not able to be refreshed because the BEMF zero cross of the motor may not appear after the lock. In this condition, lock can also be detected by the following scheme: if the current commutation period is 2× longer than the previous period. 36 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 8.4.9 Anti Voltage Supression Function When a motor is driven, energy is transferred from the power supply into the motor. Some of this energy is stored in the form of inductive energy or as mechanical energy. The DRV10983-Q1 device includes circuits to prevent this energy from being returned to the power supply, which could result in pumping up the VCC voltage. This function is referred to as the AVS and acts to protect the DRV10983-Q1 device as well as other circuits that share the same VCC connection. Two forms of AVS protection are used to prevent both the mechanical energy and the inductive energy from being returned to the supply. Each of these modes can be independently disabled through the register configuration bits AVSMEn and AVSIndEn. 8.4.9.1 Mechanical AVS Function If the speed command suddenly drops such that the BEMF voltage generated by the motor is greater than the voltage that is applied to the motor, then the mechanical energy of the motor is returned to the power supply and the VCC voltage surges. The mechanical AVS function works to prevent this from happening. The DRV10983-Q1 device buffers the speed command value and limits the resulting output voltage, UMIN, so that it is not less than the BEMF voltage of the motor. The BEMF voltage in the mechanical AVS function is determined using the programmed value for the motor Kt (Kt[6:0]) along with the speed. Figure 36 shows the criteria used by the mechanical AVS function. Rm IMIN = 0 U M BEMF UMIN = BEMF + IMIN ´ Rm = BEMF Figure 36. Mechanical AVS The mechanical AVS function can operate in one of two modes, which can be configured by the register bit AVSMMd: AVSMMd = 0 – AVS mode is always active to prevent the applied voltage from being less than the BEMF voltage. AVSMMd = 1 – AVS mode becomes active when VCC reaches 24 V. The motor acts as a generator and returns energy into the power supply until VCC reaches 24 V. This mode can be used to enable faster deceleration of the motor in applications where returning energy to the power supply is allowed. 8.4.9.2 Inductive AVS Function When the DRV10983-Q1 device transitions from driving the motor into a high-impedance state, the inductive current in the motor windings continues to flow and the energy returns to the power supply through the intrinsic body diodes in the FET output stage (see Figure 37). S1 S3 S5 S4 S6 S1 M U1 S2 Driving State S3 S5 S4 S6 M U1 S2 High Impedance State Figure 37. Inductive-Mode Voltage Surge To prevent the inductive energy from being returned to the power supply, the DRV10983-Q1 system transitions from driving to a high-impedance state by first turning off the active high-side drivers, and then after a fixed period of time (BrkDoneThr[2:0]), turning off the low-side drivers (see Figure 38). Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 37 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com S1 S3 S5 M U1 S2 S1 S4 Driving S6 S3 S5 M U1 S2 S4 S6 AVS State Figure 38. Inductive AVS In this example, current is applied to the motor through the high-side driver on phase U (S1) and returned through the low-side driver on phase W (S6). The high-side driver on phase U is turned off and after a period of time (to allow the inductive energy in the resulting LR circuit to decay) the low-side driver on phase W is turned off. If BrkDoneThr[2:0] = 000, no brake will be applied and the device will not protect from inductive energy even with the inductive AVS feature enabled. 8.4.10 PWM Output The DRV10983-Q1 device has 32 options for PWM dead time. These options can be used to configure the time between one of the bridge FETs turning off and the complementary FET turning on. Deadtime[4:0] can be used to configure dead times between 40 and 1280 ns. Take care that the dead time is long enough to prevent the bridge FETs from shooting through. The DRV10983-Q1 device offers two options for PWM switching frequency. When the configuration bit PWMFreq is set to 0, the output PWM frequency is 25 kHz, and when PWMFreq is set to 1, the output PWM frequency is 50 kHz. 8.4.11 FG Customized Configuration The DRV10983-Q1 device provides information about the motor speed through the frequency generate (FG) pin. FG also provides information about the driving state of the DRV10983-Q1 device. 8.4.11.1 FG Output Frequency The FG output frequency can be configured by FGcycle[3:0]. The default FG toggles once every electrical cycle (FGcycle = 0000). Many applications configure the FG output so that it provides two pulses for every mechanical rotation of the motor. The configuration bits provided in the DRV10983-Q1 device can accomplish this for 2-pole, 4-pole, 6-pole, and 8-pole motors up to 32-pole motors. This is illustrated in Figure 39 for 2, 4, 6, and 8-pole motors. Figure 39 shows the DRV10983-Q1 device has been configured to provide FG pulses once every electrical cycle (4 poles), twice every three electrical cycles (6 poles), once every two electrical cycles (8 poles), and once every three electrical cycles (12 poles). Note that when it is set to two FG pulses every three electrical cycles, the FG output is not 50% duty cycle. Motor speed is able to be measured by monitoring the rising edge of the FG output. 38 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 Motor phase driving voltage FGCycle = 0000 2 pole FGCycle = 0001 4 pole FGCycle = 0010 6 pole FGCycle = 0011 8 pole Figure 39. FG Frequency Divider 8.4.11.2 FG Open Loop and Lock Behavior Note that the FG output reflects the driving state of the motor. During normal closed-loop behavior, the driving state and the actual state of the motor are synchronized. During open-loop acceleration, however, this may not reflect the actual motor speed. During a locked-motor condition, the FG output is driven high. The DRV10983-Q1 device provides three options for controlling the FG output during open loop, as shown in Figure 40. The selection of these options is determined by the FGOLSel[1:0] setting. • Option0: Open-loop, FG output based on driving frequency • Option1: Open-loop, no FG output (keep high) • Option2: FG output based on driving frequency at the first power-on startup, and no FG output (keep high) for any subsequent restarts Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 39 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com Open loop Closed loop Motor phase driving voltage FGOLset = 00 FGOLset = 01 Open loop Closed loop Open loop Closed loop Motor phase driving voltage FGOLset = 10 Start-up after power-on or wake up from sleep/standby mode Rest of the startups Figure 40. FG Behavior During Open Loop 8.4.12 Diagnostics and Visibility The DRV10983-Q1 device offers extensive visibility into the motor system operation conditions stored in internal registers. This information can be monitored through the I2C interface. Information can be monitored relating to the device status, motor speed, supply voltage, speed command, motor phase-voltage amplitude, fault status, and others. The data is updated on the fly. 8.4.12.1 Motor-Status Readback The motor FaultReg register provides information on overtemperature (OverTemp), overcurrent (OverCurr), and locked rotor (Lock0–Lock5). 8.4.12.2 Motor-Speed Readback The motor operation speed is automatically updated in register MotorSpeed while the motor is spinning. The value is determined by the period for calculated BEMF zero crossings on phase U. The electrical speed of the motor is denoted as Velocity (Hz) and is calculated as shown in Equation 9. Velocity (Hz) = {MotorSpeed} / 10 (9) As an example consider the following: MotorSpeed = 0x01FF; Velocity = 512 (0x01FF) / 10 = 51 Hz 51 For a 4-pole motor, this translates to: 40 ecycles 1 mechcycle sec ond u u 60 sec ond 2 ecycle minute Submit Documentation Feedback 1530 RPM Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 8.4.12.3 Motor Electrical-Period Readback The motor-operation electrical period is automatically updated in register MotorPeriod while the motor is spinning. The electrical period is measured as the time between calculated BEMF zero crossings for phase U. The electrical period of the motor is denoted as tELE_PERIOD (µs) and is calculated as shown in Equation 10. tELE_PERIOD (µs) = {MotorPeriod} × 10 (10) As an example consider the following: MotorPeriod = 0x01FF; tELE_PERIOD = 512 (0x01FF) × 10 = 5120 µs The motor electrical period and motor speed satisfies the condition of Equation 11. tELE_PERIOD (s) × Velocity (Hz) = 1 (11) 8.4.12.4 Motor Velocity Constant Read Back For any given motor, the integrated value of BEMF during half of an electronic cycle is a constant, Ktc (see Lock2: Abnormal Kt ). The integration of the motor BEMF is processed periodically (updated every electrical cycle) while the motor is spinning. The result is stored in register MotorKt. The relationship is shown in . Ktc (V/Hz) = {MotorKt} / 2 / 1090 (12) 8.4.12.5 Motor Estimated Position by IPD After inductive sense is executed, the rotor position is detected within 60 electrical degrees of resolution. The position is stored in register IPDPosition. The value stored in IPDPosition corresponds to one of the six motor positions plus the IPD advance angle as shown in Table 8. For more information about IPD, see IPD. Table 8. IPD Position Read Back V U V U S U V U V U V U N S N W W W W W W Rotor position (°) 0 60 120 180 240 300 Data1 0 43 85 128 171 213 IPD advance angle 30 60 90 120 Data2 22 44 63 85 Register data V (Data1 + Data2) mod (256) 8.4.12.6 Supply-Voltage Readback The power supply is monitored periodically during motor operation. This information is available in register SupplyVoltage. The power supply voltage is recorded as shown in Equation 13. VPOWERSUPPLY (V) = Supply Voltage × 30 V / 256 (13) Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 41 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com 8.4.12.7 Speed-Command Readback The DRV10983-Q1 device converts the various types of speed command into a speed command value (SpeedCmd) as shown in Figure 41. By reading SpeedCmd, the user can observe PWM input duty (PWM digital mode), analog voltage (analog mode), or I2C data (I2C mode). This value is calculated as shown in Equation 14. Equation 14 shows how the speed command as a percentage can be calculated and set in SpeedCmd. DutySPEED (%) = SpeedCmd × 100 / 255 where • • DutySPEED = Speed command as a percentage SpeedCmd = Register value (14) 8.4.12.8 Speed-Command Buffer Readback If acceleration current limit and AVS are enabled, the PWM duty cycle output (read back at spdCmdBuffer) may not always match the input command (read back at SpeedCmd) shown in Figure 41. See Anti Voltage Supression Function and Current Limit. By reading the value of spdCmdBuffer, the user can observe buffered speed command (output PWM duty cycle) to the motor. Equation 15 shows how the buffered speed is calculated. DutyOUTPUT (%) = spdCmdBuffer × 100 / 255 where • • DutyOUTPUT = The maximum duty cycle of the output PWM, which represents the output amplitude in percentage. spdCmdBuffer = Register value PWM in PWM duty Analog ADC (15) AVS, Acceleration Current Limit Closed Loop Accelerate Speed Command 2 IC SpeedCmd spdCmdBuffer PWM_DCO Figure 41. SpeedCmd and spdCmdBuffer Registers 8.4.12.9 Fault Diagnostics See Lock Detect and Fault Handling. 42 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 8.5 Register Maps 8.5.1 I2C Serial Interface The DRV10983-Q1 device provides an I2C slave interface with slave address 101 0010. TI recommends a pullup resistor of 4.7 kΩ to 3.3 V for I2C interface ports SCL and SDA. The protocol for the I2C interface is given in Figure 42. I2C Write Start 7 bit Slave Add R/W=0 ACK 8 bit Reg Add ACK 8 bit Data ACK 8 bit Data ACK Stop Internal Reg write happens I2C Read Start 7 bit Slave Add R/W=0 ACK 8 bit Reg Add ACK Start 7 bit Slave Add R/W=1 8 bit Data ACK 8 bit Data ACK Stop Data from Reg is loaded to the buffer Figure 42. I2C Protocol Seven read/write registers (0x30:0x36) are used to set motor speed and control device registers and EEPROM. Device operation status can be read back through nine read-only registers (0x0:0x08). Another seven EEPROM registers (0x90:0x96) can be accessed to program motor parameters and optimize the spin-up profile for the application. 8.5.2 Register Map REGISTER NAME FaultReg ADDR. (1) (2) 0x00 D15 D14 D13 D12 D11 D7 D6 D5 D4 D3 D2 OverTemp TempWarni ng VCC_OV VREG_OC OverCurr CP_UVLO V3P3_UVL O Reserved Lock5 Lock4 Lock3 Lock2 MotorSpeed (1) 0x01 MotorSpeed[15:0] MotorPeriod (1) 0x02 MotorPeriod[15:0] MotorKt (1) 0x03 (1) MotorCurrent D10 D9 D8 D1 D0 VREG_UVL VCC_UVLO O Lock1 Lock0 MotorKt[15:0] 0x04 Reserved MotorCurrent[10:8] MotorCurrent[7:0] IPDPosition / SupplyVoltage (1) 0x05 SpeedCmd / spdCmdBuffer (1) 0x06 AnalogInLvl (1) IPDPosition[7:0] SupplyVoltage[7:0] SpeedCmd[7:0] spdCmdBuffer[7:0] 0x07 Reserved commandSenseAdc[9:8] commandSenseAdc[7:0] Device ID / Revision ID (1) SpeedCtrl (3) 0x08 DieID[7:0] RevisionID[7:0] 0x30 OverRide Reserved SpeedCtrl[8 ] SpeedCtrl[7:0] EEPROM Programming1 (1) (2) (3) (3) 0x31 ENPROGKEY[15:0] Read only Fault Register requires 0xFF to be written to the register to clear the bits. R/W Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 43 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com Register Maps (continued) REGISTER NAME ADDR. EEPROM Programming2 (3) EEPROM Programming3 (3) EEPROM Programming4 (3) EEPROM Programming5 (3) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0x32 Reserved Reserved 0x33 eeReadySt atus Reserved eeIndAddress[7:0] 0x34 eeIndWData[15:0] 0x35 Reserved ShadowRe gEn Reserved Reserved EEPROM Programming6 EECTRL (3) eeWRnEn 0x36 0x60 eeRefresh eeAccMode[1:0] eeIndRData[15:0] MTR_DIS Reserved Reserved CONFIG1 (4) 0x90 SSMConfig[1:0] FGOLSel[1:0] ClkCycleAdj ust CONFIG2 (4) 0x91 (4) 0x92 CONFIG4 (4) 0x93 CONFIG3 FGCycle[3:0] RMShift[2:0] RMValue[3:0] Reserved KtShift[2:0] KtValue[3:0] CommAdv Mode TCtrlAdvShift[2:0] TCtrlAdvValue[3:0] ISDThr[1:0] BrkCurrThr Sel OpenLCurr[1:0] Reserved AccelRange Sel BEMF_HYS ISDEn RvsDrEn RvsDrThr[1:0] OpLCurrRt[2:0] BrkDoneThr[2:0] StAccel2[2:0] StAccel[2:0] Op2ClsThr[4:0] CONFIG5 (4) 0x94 OTWarning_ILimit[1:0] LockEn5 AlignTime[2:0] LockEn4 LockEn3 SwILimit[3:0] CONFIG6 (4) 0x95 SpdCtlrMd PWMFreq CLoopDis CONFIG7 (4) 0x96 (4) 44 KtLckThr[1:0] AvSIndEn ClsLpAccel[2:0] IPDAdvcAg[1:0] Reserved LockEn2 LockEn1 HwILimit[2:0] AVSMEn DutyCycleLimit[1:0] IPDCurrThr[3:0] CtrlCoef[1:0] LockEn0 IPDasHwILi mit AVSMMd IPDRIsMd SlewRate[1:0] IPDClk[1:0] DeadTime[4:0] EEPROM Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 Table 9. Default EEPROM Values ADDRESS DEFAULT VALUE 0x90 0x1048 0x91 0x2F3B 0x92 0x0050 0x93 0x1B8A 0x94 0x3FAF 0x95 0x3C43 0x96 0x016A 8.5.3 Register Descriptions Table 10. Access Type Codes ACCESS TYPE CODE DESCRIPTION READ TYPE R R Read W W Write W1C W 1C Write 1 to clear WRITE TYPE RESET OR DEFAULT VALUE -n Value after reset or the default value 8.5.3.1 FaultReg Register (address = 0x00) [reset = 0x00] Figure 43. FaultReg Register 15 OverTemp R/W1C-0 14 TempWarning R//W1C-0 13 VCC_OV R/W1C-0 12 VREG_OC R/W1C-0 11 OverCurr R/W1C-0 10 CP_UVLO R/W1C-0 9 VREG_UVLO R/W1C-0 8 VCC_UVLO R/W1C-0 7 V3P3_UVLO R/W1C-0 6 Reserved R/W1C-0 5 Lock5 R/W1C-0 4 Lock4 R/W1C-0 3 Lock3 R/W1C-0 2 Lock2 R/W1C-0 1 Lock1 R/W1C-0 0 Lock0 R/W1C-0 Table 11. FaultReg Register Field Descriptions Bit Field Type Reset Description 15 OverTemp R//W1C 0 Bit to indicate device temperature is over the limit. 14 TempWarning R/W1C 0 Bit to indicate device temperature is over the warning limit. 13 VCC_OV R/W1C 0 Bit to indicate the supply voltage is above the upper limit. 12 VREG_OC R/W1C 0 Bit to indicate that the switching regulator is in an overcurrent condition. 11 OverCurr R/W1C 0 Bit to indicate that an overcurrent event happened. 10 CP_UVLO R/W1C 0 Bit to indicate that the charge pump is in an undervoltage fault condition. 9 VREG_UVLO R/W1C 0 Bit to indicate that the switching regulator (VREG) is in an undervoltage fault condition. 8 VCC_UVLO R/W1C 0 Bit to indicate that the supply (VCC) is in an undervoltage fault condition. 7 V3P3_UVLO R/W1C 0 Bit to indicate that the 3.3 V LDO regulator is in an undervoltage fault condition. 6 Reserved R/W1C 0 Do not access this bit. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 45 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com Table 11. FaultReg Register Field Descriptions (continued) Bit Field Type Reset Description 5 Lock5 R/W1C 0 Stuck in closed loop fault 4 Lock4 R/W1C 0 Stuck in open loop fault 3 Lock3 R/W1C 0 No motor fault 2 Lock2 R/W1C 0 Kt abnormal fault 1 Lock1 R/W1C 0 Speed abnormal fault 0 Lock0 R/W1C 0 Hardware current-limit fault 8.5.3.2 MotorSpeed Register (address = 0x01) [reset = 0x00] Figure 44. MotorSpeed Register 15 14 13 12 11 10 MotorSpeed[15] MotorSpeed[14] MotorSpeed[13] MotorSpeed[12] MotorSpeed[11] MotorSpeed[10] R-0 R-0 R-0 R-0 R-0 R-0 9 MotorSpeed[9] R-0 8 MotorSpeed[8] R-0 7 MotorSpeed[7] R-0 1 MotorSpeed[1] R-0 0 MotorSpeed[0] R-0 6 MotorSpeed[6] R-0 5 MotorSpeed[5] R-0 4 MotorSpeed[4] R-0 3 MotorSpeed[3] R-0 2 MotorSpeed[2] R-0 Table 12. MotorSpeed Register Field Descriptions Bit 15:0 Field Type Reset Description MotorSpeed[15:0] R 0x00 16-bit value indicating the motor speed. Motor speed in Hz = MotorSpeed[15:0] / 10 8.5.3.3 MotorPeriod Register (address = 0x02) [reset = 0x00] Figure 45. MotorPeriod Register 15 14 13 12 11 10 MotorPeriod[15] MotorPeriod[14] MotorPeriod[13] MotorPeriod[12] MotorPeriod[11] MotorPeriod[10] R-0 R-0 R-0 R-0 R-0 R-0 9 MotorPeriod[9] R-0 8 MotorPeriod[8] R-0 7 MotorPeriod[7] R-0 1 MotorPeriod[1] R-0 0 MotorPeriod[0] R-0 6 MotorPeriod[6] R-0 5 MotorPeriod[5] R-0 4 MotorPeriod[4] R-0 3 MotorPeriod[3] R-0 2 MotorPeriod[2] R-0 Table 13. MotorPeriod Register Field Descriptions Bit 15:0 46 Field Type Reset Description MotorPeriod[15:0] R 0x00 16-bit value indicating the motor period. Motor period = MotorPeriod[15:0] × 10 = period in μs Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 8.5.3.4 MotorKt Register (address = 0x03) [reset = 0x00] Figure 46. MotorKt Register 15 MotorKt[15] R-0 14 MotorKt[14] R-0 13 MotorKt[13] R-0 12 MotorKt[12] R-0 11 MotorKt[11] R-0 10 MotorKt[10] R-0 9 MotorKt[9] R-0 8 MotorKt[8] R-0 7 MotorKt[7] R-0 6 MotorKt[6] R-0 5 MotorKt[5] R-0 4 MotorKt[4] R-0 3 MotorKt[3] R-0 2 MotorKt[2] R-0 1 MotorKt[1] R-0 0 MotorKt[0] R-0 Table 14. MotorKt Register Field Descriptions Bit 15:0 Field Type Reset Description MotorKt[15:0] R 0x00 16-bit value indicating the motor measured velocity constant. Ktc (V/Hz) = {MotorKt[15:0]} / 2 / 1090 8.5.3.5 MotorCurrent Register (address = 0x04) [reset = 0x00] Figure 47. MotorCurrent Register 15 Reserved 14 Reserved 13 Reserved 12 Reserved 11 Reserved R-0 R-0 R-0 R-0 R-0 10 MotorCurrent[1 0] R-0 9 8 MotorCurrent[9] MotorCurrent[8] R-0 R-0 7 6 5 4 3 2 1 0 MotorCurrent[7] MotorCurrent[6] MotorCurrent[5] MotorCurrent[4] MotorCurrent[3] MotorCurrent[2] MotorCurrent[1] MotorCurrent[0] R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 Table 15. MotorCurrent Register Field Descriptions Bit Field Type Reset Description 15:11 Reserved R 0 Do not access these bits. 10:0 MotorCurrent[10:0] R 0x00 11-bit value indicating the motor current. Current (A) = 3 × (MotorCurrent[10:0] –- 1023) / 2048 8.5.3.6 IPDPosition–SupplyVoltage Register (address = 0x05) [reset = 0x00] Figure 48. IPDPosition–SupplyVoltage Register 15 IPDPosition [7] R-0 14 IPDPosition [6] R-0 13 IPDPosition [5] R-0 12 IPDPosition [4] R-0 11 IPDPosition [3] R-0 10 IPDPosition [2] R-0 9 IPDPosition [1] R-0 8 IPDPosition [0] R-0 7 SupplyVoltage[ 7] R-0 6 SupplyVoltage[ 6] R-0 5 SupplyVoltage[ 5] R-0 4 SupplyVoltage[ 4] R-0 3 SupplyVoltage[ 3] R-0 2 SupplyVoltage[ 2] R-0 1 SupplyVoltage[ 1] R-0 0 SupplyVoltage[ 0] R-0 Table 16. IPDPosition–SupplyVoltage Register Field Descriptions Field Type Reset Description 15:8 Bit IPDPosition [7:0] R 0x0 8-bit value indicating the estimated motor position during IPD plus the IPD advance angle (see Table 8) 7:0 SupplyVoltage[7:0] R 0x0 8-bit value indicating the supply voltage VPOWERSUPPLY (V) = SupplyVoltage[7:0] × 30 V / 255 For example, SupplyVoltage[7:0] = 0x67, VPOWERSUPPLY (V) = 0x67 (102) × 30 / 255 = 12 V Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 47 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com 8.5.3.7 SpeedCmd–spdCmdBuffer Register (address = 0x06) [reset = 0x00] Figure 49. SpeedCmd–spdCmdBuffer Register 15 SpeedCmd[7] R-0 14 SpeedCmd[6] R-0 13 SpeedCmd[5] R-0 12 SpeedCmd[4] R-0 11 SpeedCmd[3] R-0 10 SpeedCmd[2] R-0 9 SpeedCmd[1] R-0 8 SpeedCmd[0] R-0 7 6 5 4 3 2 1 0 spdCmdBuffer[[ spdCmdBuffer[[ spdCmdBuffer[[ spdCmdBuffer[[ spdCmdBuffer[[ spdCmdBuffer[[ spdCmdBuffer[[ spdCmdBuffer[[ 7] 6] 5] 4] 3] 2] 1] 0] R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 Table 17. SpeedCmd–spdCmdBuffer Register Field Descriptions Field Type Reset Description 15:8 Bit SpeedCmd[7:0] R 0x0 8-bit value indicating the speed command based on analog or PWMin or I2C. FF indicates 100% speed command. 7:0 spdCmdBuffer[7:0] R 0x0 8-bit value indicating the speed command after buffer output. FF indicates 100% speed command. 8.5.3.8 AnalogInLvl Register (address = 0x07) [reset = 0x00] Figure 50. AnalogInLvl Register 15 Reserved 14 Reserved 13 Reserved 12 Reserved 11 Reserved 10 Reserved R-0 9 commandSnsA DC[9] R-0 8 commandSnsA DCt[8] R-0 R-0 R-0 R-0 R-0 R-0 7 commandSnsA DC[7] R-0 6 commandSnsA DC[6] R-0 5 commandSnsA DC[5] R-0 4 commandSnsA DC[4] R-0 3 commandSnsA DC[3] R-0 2 commandSnsA DC[2] R-0 1 commandSnsA DC[1] R-0 0 commandSnsA DC[0] R-0 Table 18. AnalogInLvl Register Field Descriptions Bit 15:10 9:0 Field Type Reset Description Reserved R 0 Do not access these bits. commandSnsADC[9:0] R 0x00 10-bit value indicating the analog speed input converted to a digital word. AnalogSPEED (V) = AnalogInLvl × V3P3 / 1024 8.5.3.9 DeviceID–RevisionID Register (address = 0x08) [reset = 0x00] Figure 51. DeviceID–RevisionID Register 15 DieID[7] R-0 14 DieID[6] R-0 13 DieID[5] R-0 12 DieID[4] R-0 11 DieID[3] R-0 10 DieID[2] R-0 9 DieID[1] R-0 8 DieID[0] R-0 7 RevisionID[7] R-0 6 RevisionID[6] R-0 5 RevisionID[5] R-0 4 RevisionID[4] R-0 3 RevisionID[3] R-0 2 RevisionID[2] R-0 1 RevisionID[1] R-0 0 RevisionID[0] R-0 48 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 Table 19. DeviceID–RevisionID Register Field Descriptions Bit 15:10 9:0 Field Type Reset Description DieID[7:0] R 0 8-bit unique device identification. RevisionID[7:0] R 0x00 8-bit revision ID for the device 0000 0000 → REV A 0000 0001 → REV B ... 8.5.3.10 DeviceID–RevisionID Register (address = 0x08) [reset = 0x00] Figure 52. DeviceID–RevisionID Register 15 DieID[7] R-0 14 DieID[6] R-0 13 DieID[5] R-0 12 DieID[4] R-0 11 DieID[3] R-0 10 DieID[2] R-0 9 DieID[1] R-0 8 DieID[0] R-0 7 RevisionID[7] R-0 6 RevisionID[6] R-0 5 RevisionID[5] R-0 4 RevisionID[4] R-0 3 RevisionID[3] R-0 2 RevisionID[2] R-0 1 RevisionID[1] R-0 0 RevisionID[0] R-0 Table 20. DeviceID–RevisionID Register Field Descriptions Field Type Reset Description 15:8 Bit DieID[7:0] R 0x0 8-bit unique device identification. 7:0 RevisionID[7:0] R 0x0 8-bit revision ID for the device 0000 0000 → REV A 0000 0001 → REV B ... 8.5.3.11 Unused Registers (addresses = 0x011 Through 0x2F) Registers 0x09 through 0x2F are not used. 8.5.3.12 SpeedCtrl Register (address = 0x30) [reset = 0x00] Figure 53. SpeedCtrl Register 15 14 13 12 11 10 9 8 OverRide R/W-0 Reserved R-0 Reserved R-0 Reserved R-0 Reserved R-0 Reserved R-0 Reserved R-0 SpeedCtrl[8] R/W-0 7 SpeedCtrl[7] R/W-0 6 SpeedCtrl[6] R/W-0 5 SpeedCtrl[5] R/W-0 4 SpeedCtrl[4] R/W-0 3 SpeedCtr[3] R/W-0 2 SpeedCtrl[2] R/W-0 1 SpeedCtrl[1] R/W-0 0 SpeedCtrl[0] R/W-0 Table 21. SpeedCtrl Register Field Descriptions Bit Field Type Reset Description 15 OverRide R/W 0 Used to control the SpdCtrl[8:0] bits. If OverRide = 1, the user can write the speed command directly through I2C. 14:9 Reserved R 0x0 Do not access this bit. 8:0 SpeedCtrl[8:0] R/W 0x00 9-bit value used for the motor speed. If OverRide = 1, speed command can be written by the user through I2C. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 49 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com 8.5.3.13 EEPROM Programming1 Register (address = 0x31) [reset = 0x00] Figure 54. EEPROM Programming1 Register 15 ENPROGKEY [15] R/W-0 14 ENPROGKEY [14] R/W-0 13 ENPROGKEY [13] R/W-0 12 ENPROGKEY [12] R/W-0 11 ENPROGKEY [11] R/W-0 10 ENPROGKEY [10] R/W-0 9 ENPROGKEY [9] R/W-0 8 ENPROGKEY [9] R/W-0 7 ENPROGKEY [7] R/W-0 6 ENPROGKEY [6] R/W-0 5 ENPROGKEY [5] R/W-0 4 ENPROGKEY [4] R/W-0 3 ENPROGKEY [3] R/W-0 2 ENPROGKEY [2] R/W-0 1 ENPROGKEY [1] R/W-0 0 ENPROGKEY [0] R/W-0 Table 22. EEPROM Programming1 Register Field Descriptions Bit 15:0 Field Type Reset Description ENPROGKEY[15:0] R/W 0x00 EEPROM access key 0xCODE → access key for customer space; registers 0x90 to 0x96 8.5.3.14 EEPROM Programming2 Register (address = 0x32) [reset = 0x00] Figure 55. EEPROM Programming2 Register 15 Reserved R-0 14 Reserved R-0 13 Reserved R-0 12 Reserved R-0 11 Reserved R-0 10 Reserved R-0 9 Reserved R-0 8 Reserved R-0 7 Reserved R-0 6 Reserved R-0 5 Reserved R-0 4 Reserved R-0 3 Reserved R-0 2 Reserved R-0 1 Reserved R-0 0 eeReadyStatus R-0 Table 23. EEPROM Programming2 Register Field Descriptions Bit 15:1 0 Field Type Reset Description Reserved R 0x00 Do not access these bits. eeReadyStatus R 0 EEPROM status bit. 0: EEPROM not ready for read/write access 1: EEPROM ready for read/write access 8.5.3.15 EEPROM Programming3 Register (address = 0x33) [reset = 0x00] Figure 56. EEPROM Programming3 Register 15 Reserved R-0 14 Reserved R-0 13 Reserved R-0 12 Reserved R-0 11 Reserved R-0 10 Reserved R-0 9 Reserved R-0 8 Reserved R-0 7 eeIndAddress [7] R-0 6 eeIndAddress [6] R-0 5 eeIndAddress [5] R-0 4 eeIndAddress [4] R-0 3 eeIndAddress [3] R-0 2 eeIndAddress [2] R-0 1 eeIndAddress [1] R-0 0 eeIndAddress [0] R-0 50 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 Table 24. EEPROM Programming3 Register Field Descriptions Field Type Reset Description 15:8 Bit Reserved R 0x0 Do not access these bits. 7:0 eeIndAddress[7:0] R 0x0 EEPROM individual access address. Contents of this register define the address of EEPROM for the individual access operation. For example, for writing/reading CONFIG1 in individual access mode happens if eeIndAddress = 0x90. 8.5.3.16 EEPROM Programming4 Register (address = 0x34) [reset = 0x00] Figure 57. EEPROM Programming4 Register 15 eeIndWData [15] R/W-0 14 eeIndWData [14] R/W-0 13 eeIndWData [13] R/W-0 12 eeIndWData [12] R/W-0 11 eeIndWData [11] R/W-0 10 eeIndWData [10] R/W-0 9 eeIndWData[9] 8 eeIndWData[8] R/W-0 R/W-0 7 eeIndWData[7] R/W-0 6 eeIndWData[6] R/W-0 5 eeIndWData[5] R/W-0 4 eeIndWData[4] R/W-0 3 eeIndWData[3] R/W-0 2 eeIndWData[2] R/W-0 1 eeIndWData[1] R/W-0 0 eeIndWData[0] R/W-0 Table 25. EEPROM Programming4 Register Field Descriptions Bit 15:0 Field Type Reset Description eeIndWData[15:0] R/W 0x00 EEPROM individual access write data Contents of this register are used to write to EEPROM data of the registers specified by eeIndAddress. 8.5.3.17 EEPROM Programming5 Register (address = 0xYY) [reset = 0x00] Figure 58. EEPROM Programming5 Register 15 Reserved R-0 14 Reserved R-0 13 Reserved R-0 12 ShadowRegEn R/W-0 11 Reserved R-0 10 Reserved R-0 9 Reserved R-0 8 R-0 7 Reserved R-0 6 Reserved R-0 5 Reserved R-0 4 Reserved R-0 3 Reserved R-0 2 eeWRnEn R/W-0 1 eeAccMode[1] R/W-0 0 eeAccMode[0] R/W-0 Table 26. EEPROM Programming5 Register Field Descriptions Bit Field Type Reset Description Reserved R 000 Do not access these bits. ShadowRegEn R/W 0 Enable shadow register. 0 : Shadow register is not used. 1 : Shadow register values are used for device operation (EEPROM contents are ignored). I2C read returns the contents of the shadow registers. 11:9 Reserved R 000 Do not access these bits. 8 eeRefresh R/W 0 EEPROM refresh 0 : normal operation 1 : Sync shadow registers with contents of EEPROM. 7:3 Reserved R 0x0 Do not access these bits. 2 eeWRnEn R/W 0 EEPROM refresh 0 : Normal operation 1 : Sync shadow registers with contents of EEPROM. 15:13 12 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 51 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com Table 26. EEPROM Programming5 Register Field Descriptions (continued) Bit Field Type Reset Description 1:0 eeAccMode[1:0] R/W 00 EEPROM access mode 00 : EEPROM access disabled 01 : EEPROM individual access enabled 10 : EEPROM mass access enabled 11 : Do not access these bits. 8.5.3.18 EEPROM Programming6 Register (address = 0x36) [reset = 0x00] Figure 59. EEPROM Programming6 Register 15 14 13 12 11 10 eeIndRData[15] eeIndRData[14] eeIndRData[13] eeIndRData[12] eeIndRData[11] eeIndRData[10] R-0 R-0 R-0 R-0 R-0 R-0 9 eeIndRData[9] R-0 8 eeIndRData[8] R-0 7 eeIndRData[7] R-0 1 eeIndRData[1] R-0 0 eeIndRData[0] R-0 6 eeIndRData[6] R-0 5 eeIndRData[5] R-0 4 eeIndRData[4] R-0 3 eeIndRData[3] R-0 2 eeIndRData[2] R-0 Table 27. EEPROM Programming6 Register Field Descriptions Bit 15:0 Field Type Reset Description eeIndRData[15:0] R 0x00 EEPROM Individual Access Read Data Contents of this register reflect the value of EEPROM location accessed through the individual read. 8.5.3.19 Unused Registers (addresses = 0x37 Through 0x5F) Registers 0x37 through 0x5F are not used. 8.5.3.20 EECTRL Register (address = 0x60) [reset = 0x00] Figure 60. EECTRL Register 15 MTR_DIS W-0 14 Reserved R-0 13 Reserved R-0 12 Reserved R-0 11 Reserved R-0 10 Reserved R-0 9 Reserved R-0 8 Reserved R-0 7 Reserved R-0 6 Reserved R-0 5 Reserved R-0 4 Reserved R-0 3 Reserved R-0 2 Reserved R-0 1 Reserved R-0 0 Reserved R-0 Table 28. EECTRL Register Field Descriptions Bit Field Type Reset Description 15 MTR_DIS W 0 Control to disable motor without going to sleep. For use during EEPROM programming. This bit is write-only (cannot be read). 0: Motor control is enabled. 1: Motor control is disabled. 14:0 Reserved R 0x00 Do not access these bits. 8.5.3.21 Unused Registers (addresses = 0x61 Through 0x8F) Registers 0x61 through 0x8F are not used. 52 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 8.5.3.22 CONFIG1 Register (address = 0x90) [reset = 0x00] Figure 61. CONFIG1 Register 15 SSMConfig[1] R/W-0 14 SSMConfig[0] R/W-0 13 FGOLSel[1] R/W-0 12 FGOLSel[0] R/W-0 11 FGCycle[3] R/W-0 10 FGCycle[2] R/W-0 9 FGCycle[1] R/W-0 8 FGCycle[0] R/W-0 7 ClkCycleAdjust R/W-0 6 RMShift[2] R/W-0 5 RMShift[1] R/W-0 4 RMShift[0] R/W-0 3 RMValue[3] R/W-0 2 RMValue[2] R/W-0 1 RMValue[1] R/W-0 0 RMValue[0] R/W-0 Table 29. CONFIG1 Register Field Descriptions Field Type Reset Description 15:14 Bit SSMConfig[1:0] R/W 00 Spread spectrum modulation control 00: No spread spectrum 01: ±5% dithering 1:0: ±10% dithering 11: ±15% dithering 13:12 FGOLSel[1:0] R/W 00 FG open-loop output select 00: FG outputs in both open loop and closed loop 01: FG outputs only in closed loop 10: FG outputs closed loop and the first open loop 11: Reserved 11:8 FGCycle[3:0] R/W 0x0 FG motor pole option n: FG output is electrical speed / (n + 1) 0: FG / 1 (2 pole) 1: FG / 2 (4 pole) 2: FG / 3 (6 pole) 3: FG / 4 (8 pole) ... 15: FG / 16 (32 pole) ClkCycleAdjust R/W 0 0: Full-cycle adjust 1: Half-cycle adjust 6:4 RMShift[2:0] R/W 000 Number of shift bits to determine the motor phase resistance. RM = RmValue << RmShift Rm' = (bin) {RPhase / 0.009615} After calculating Rm' value, split the value with shift number and significant number according the length of the Rm' value. If the length of Rm' is within 4 bits; RmValue[3:0] = Rm'; RmShift[2:0] = 000 If the length of Rm' is 5 bits; RmValue[3:0] = Rm'[4:1]; RmShift[2:0] = 001 and so on. 3:0 RMValue[3:0] R/W 0x0 Significant portion of the motor resistor, used in conjunction with RmShift[2:0] 7 8.5.3.23 CONFIG2 Register (address = 0x91) [reset = 0x00] Figure 62. CONFIG2 Register 15 Reserved R-0 7 CommAdvMod e R/W-0 14 KtShift[2] R/W-0 13 KtShift[1] R/W-0 12 KtShift[0] R/W-0 6 5 4 TCtrlAdvShift[2] TCtrlAdvShift[1] TCtrlAdvShift[0] R/W-0 R/W-0 R/W-0 11 KtValue[3] R/W-0 10 KtValue[2] R/W-0 9 KtValue[1] R/W-0 8 KtValue[0] R/W-0 3 2 1 0 R-0 R-0 R-0 R-0 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 53 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com Table 30. CONFIG2 Register Field Descriptions Bit Field Type Reset Description 15 Reserved R 0 Do not access this bit 14:12 KtShift[2:0] R/W 000 Number of shift bits to determine the motor BEMF constant. Kt = KtValue << KtShift 11:8 KtValue[3:0] R/W 0x0 CommAdvMode R/W 0 Commutation advance mode 0: Voltage advance is maintained at a fixed time (1) relative to the estimated BEMF. 1: Voltage advance is maintained at a variable time relative to the estimated BEMF based on: tadv = tsetting × (U-BEMF) / U 6:4 TCtrlAdvShift[2:0] R/W 000 Number of shift bits to determine the commutation advance timing tadv = TCtrlAdvValue << TCtrlAdvShift 3:0 TCtrlAdvValue[3:0] R/W 0x0 Commutation advance value. 7 (1) EEPROM 8.5.3.24 CONFIG3 Register (address = 0x92) [reset = 0x00] Figure 63. CONFIG3 Register 15 ISDThr[1] R/W-0 14 ISDThr[0] R/W-0 13 BrkCurThrSel R/W-0 12 BEMF_HYS R/W-0 11 ISDEn R/W-0 10 RvsDrEn R/W-0 9 RvsDrThr[1] R/W-0 8 RvsDrThr[0] R/W-0 7 OpenLCurr[1] R/W-0 6 OpenLCurr[0] R/W-0 5 OpLCurrRt[2] R/W-0 4 OpLCurrRt[1] R/W-0 3 OpLCurrRt[0] R/W-0 2 BrkDoneThr[2] R/W-0 1 BrkDoneThr[1] R/W-0 0 BrkDoneThr[0] R/W-0 Table 31. CONFIG3 Register Field Descriptions Bit Field Type Reset Description ISDThr[1:0] R/W 00 ISD stationary judgment threshold 00: 6 Hz (80 ms, no zero cross) 01: 3 Hz (160 ms, no zero cross) 10: 1.6 Hz (320 ms, no zero cross) 11: 0.8 Hz (640 ms, no zero cross) 13 BrkCurThrSel R/W 0 Brake current-level-threshold selection. 0: 24 mA 1: 48 mA 12 BEMF_HYS R/W 0 0: Low hysteresis for BEMF comparator (approximately 10 mV) 1: High hysteresis for BEMF comparator (approximately 20 mV) 11 ISDEn R/W 0 0: Initial speed detect (ISD) disabled 1: ISD enabled 10 RvsDrEn R/W 0 0: Reverse drive disabled 1: Reverse drive enabled 9:8 RvsDrThr[1:0] R/W 00 The threshold where device starts to process revers drive (RvsDr) or brake. 00: 6.3 Hz 01: 13 Hz 10: 26 Hz 11: 51 Hz 15:14 54 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 Table 31. CONFIG3 Register Field Descriptions (continued) Bit Field Type Reset Description 7:6 OpenLCurr[1:0] R/W 00 Open-loop current setting. 00: 0.2 A 01: 0.4 A 10: 0.8 A 11: 1.6 A Align current setting. 00: 0.15 A 01: 0.3 A 10: 0.6 A 11: 1.2 A 5:3 OpLCurrRt[2:0] R/W 000 Open-loop current ramp-up setting. 000: 6 VCC/s 001: 3 VCC/s 010: 1.5 VCC/s 011: 0.7 VCC/s 100: 0.34 VCC/s 101: 0.16 VCC/s 110: 0.07 VCC/s 111: 0.023 VCC/s 2:0 BrkDoneThr[2:0] R/W 000 Braking mode setting. 000: No brake (BrkEn = 0) 001: 2.7 s 010: 1.3 s 011: 0.67 s 100: 0.33 s 101: 0.16 s 110: 0.08 s 111: 0.04 s 8.5.3.25 CONFIG4 Register (address = 0x93) [reset = 0x00] Figure 64. CONFIG4 Register 15 Reserved R-0 14 AccelRangeSel R/W-0 13 StAccel2[2] R/W-0 12 StAccel2[1] R/W-0 11 StAccel2[0] R/W-0 10 StAccel[2] R/W-0 9 StAccel[1] R/W-0 8 StAccel[0] R/W-0 7 Op2ClsThr[4] R/W-0 6 Op2ClsThr[3] R/W-0 5 Op2ClsThr[2] R/W-0 4 Op2ClsThr[1] R/W-0 3 Op2ClsThr[0] R/W-0 2 AlignTime[2] R/W-0 1 AlignTime[1] R/W-0 0 AlignTime[0] R/W-0 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 55 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com Table 32. CONFIG4 Register Field Descriptions 56 Bit Field Type Reset Description 15 Reserved R 0 Do not access this bit 14 AccelRangeSel R/W 0 Acceleration range selection 0: Fast 1: Slow 13:11 StAccel2[2:0] R/W 000 Open-loop start-up acceleration (second-order) AccelRangeSel = 0; 000: 57 Hz/s2 AccelRangeSel = 0; 001 = 29 Hz/s2 AccelRangeSel = 0; 010 = 14 Hz/s2 AccelRangeSel = 0; 011 = 6.9 Hz/s2 AccelRangeSel = 0; 100 = 3.3 Hz/s2 AccelRangeSel = 0; 101 = 1.6 Hz/s2 AccelRangeSel = 0; 110 = 0.66 Hz/s2 AccelRangeSel = 0; 111 = 0 Hz/s2 AccelRangeSel = 1; 000 = 0.22 Hz/s2 AccelRangeSel = 1; 001 = 0.11 Hz/s2 AccelRangeSel = 1; 010 = 0.055 Hz/s2 AccelRangeSel = 1; 011 = 0.027 Hz/s2 AccelRangeSel = 1; 100 = 0.013 Hz/s2 AccelRangeSel = 1; 101 = 0.0063 Hz/s2 AccelRangeSel = 1; 110 = 0.0026 Hz/s2 AccelRangeSel = 1; 111 = 0 Hz/s2 10:8 StAccel[2:0] R/W 0 Open-loop start-up acceleration (first-order) AccelRangeSel = 0; 000 = 76 Hz/s AccelRangeSel = 0; 001 = 38 Hz/s AccelRangeSel = 0; 010 = 19 Hz/s AccelRangeSel = 0; 011 = 9.2 Hz/s AccelRangeSel = 0; 100 = 4.5 Hz/s AccelRangeSel = 0; 101 = 2.1 Hz/s AccelRangeSel = 0; 110 = 0.9 Hz/s AccelRangeSel = 0; 111 = 0.3 Hz/s AccelRangeSel = 1; 000 = 4.8 Hz/s AccelRangeSel = 1; 001 = 2.4 Hz/s AccelRangeSel = 1; 010 = 1.2 Hz/s AccelRangeSel = 1; 011 = 0.58 Hz/s AccelRangeSel = 1; 100 = 0.28 Hz/s AccelRangeSel = 1; 101 = 0.13 Hz/s AccelRangeSel = 1; 110 = 0.056 Hz/s AccelRangeSel = 1; 111 = 0.019 Hz/s 7:3 Op2ClsThr[4:0] R/W 0 Open- to closed-loop threshold 0 xxxx = Range 0: n × 0.8 Hz 0 0000 = N/A 0 0001 = 0.8 Hz 0 0111 = 5.6 Hz 0 1111 = 12 Hz 1 xxxx = Range 1: (n + 1) × 12.8 Hz 1 0000 = 12.8 Hz 1 0001 = 25.6 Hz ... 1 0111 = 192 Hz 1 1111 = 204.8 Hz 2:0 AlignTime[2:0] R/W 0 Align time. 000 = 5.3 s 001 = 2.7 s 010 = 1.3 s 011 = 0.67 s 100 = 0.33 s 101 = 0.16 s 110 = 0.08 s 111 = 0.04 s Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 8.5.3.26 CONFIG5 Register (address = 0x94) [reset = 0x00] Figure 65. CONFIG5 Register 15 OTWarning Limit[1] R/W-0 14 OTWarning Limit[0] R/W-0 13 LockEn5 12 LockEn4 11 LockEn3 10 LockEn2 9 LockEn1 8 LockEn0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 SWiLimitThr [3] R/W-0 6 SWiLimitThr [2] R/W-0 5 SWiLimitThr [1] R/W-0 4 SWiLimitThr [0] R/W-0 3 2 1 HWiLimitThr [2] HWiLimitThr [1] HWiLimitThr [0] R/W-0 R/W-0 R/W-0 0 IPDasHwILimit R/W-0 Table 33. CONFIG5 Register Field Descriptions Bit Field Type Reset Description OTWarningLimit[1:0] R/W 00 Overtemperature warning current limit 00: No temperature-based current-limit function, uses SWILimitThr 01: Limit current to 1 A when overtemperature warning reached 10: Limit current to 1.6 A when overtemperature warning reached 11: Limit current to 2 A when overtemperature warning reached 13 LockEn5 R/W 0 Stuck in closed loop (no zero cross detected). Enabled when high 12 LockEn4 R/W 0 Open loop stuck (no zero cross detected). Enabled when high 11 LockEn3 R/W 0 No motor fault. Enabled when high 10 LockEn2 R/W 0 Abnormal Kt. Enabled when high 9 LockEn1 R/W 0 Abnormal speed. Enabled when high 8 15:14 LockEn0 R/W 0 Lock-detection current limit. Enabled when high. 7:4 SWiLimitThr[3:0] R/W 0x0 Acceleration current limit threshold 0000: No acceleration current limit 0001: 0.2-A current limit 0010 to 1111: n × 0.2 A current limit 3:1 HWiLimitThr[2:0] R/W 000 HWILimitThr: Current limit for lock detection If IPDasHwILimit = 0 then x00: 2.5 A x01: 1.9 A x10: 1.5 A x11: 0.9 A If IPDasHwILimit = 1 then 000: 0.4 A 001: 0.8 A 010: 1.2 A 011: 1.6 A 100: 2 A 101: 2.4 A 110: 2.8 A 111: 3.2 A IPDasHwILimit R/W 0 0: Range1 of current limit for lock detection 1: Range2 of current limit for lock detection 0 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 57 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com 8.5.3.27 CONFIG6 Register (address = 0x95) [reset = 0x00] Figure 66. CONFIG6 Register 15 SpdCtrlMd R/W-0 14 PWMFreq R/W-0 13 KtLckThr[1] R/W-0 12 KtLckThr[0] R/W-0 7 CLoopDis 6 ClsLpAccel[2] 5 ClsLpAccel[1] 4 ClsLpAccel[0] R/W-0 R/W-0 R/W-0 R/W-0 11 AVSIndEn R/W-0 10 AVSMEn R/W-0 3 2 DutyCycleLimit[ DutyCycleLimit[ 1] 0] R/W-0 R/W-0 9 AVSMMd R/W-0 8 IPDRlsMd R/W-0 1 SlewRate[1] 0 SlewRate[0] R/W-0 R/W-0 Table 34. CONFIG6 Register Field Descriptions Bit Field Type Reset Description 15 SpdCtrlMd R/W 0 Speed input mode 0: Analog input expected at SPEED pin 1: PWM input expected at SPEED pin 14 PWMFreq R/W 0 PWM Frequency Control 0: PWM frequency = 25 kHz 1: PWM frequency = 50 kHz KtLckThr[1:0] R/W 0 Abnormal Kt lock detect threshold 00: Kt_high = 3/2Kt. Kt_low = 3/4Kt 01: Kt_high = 2Kt. Kt_low = 3/4Kt 10: Kt_high = 3/2Kt. Kt_low = 1/2Kt 11: Kt_high = 2Kt. Kt_low = 1/2Kt 11 AVSIndEn R/W 0 Inductive AVS enable. Enabled when high 10 AVSMEn R/W 0 Mechanical AVS enable. Enabled when high 9 AVSMMd R/W 0 Mechanical AVS mode 0: AVS to VCC 1: AVS to 24 V 8 IPDRlsMd R/W 0 IPD release mode 0: Brake when inductive release 1: Hi-z when inductive release 7 CLoopDis R/W 0 0: Transfer to closed loop at Op2ClsThr speed 1: No transfer to closed loop. Keep in open loop 6:4 ClsLpAccel[2:0] R/W 0 Closed-loop accelerate 000: Immediate change 001: 48 VCC/s 010: 48 VCC/s 011: 0.77 VCC/s 100: 0.37 VCC/s 101: 0.19 VCC/s 110: 0.091 VCC/s 111: 0.045 VCC/s 3:2 DutyCycleLimit[1:0] R/W 0 Minimum duty-cycle limit 00: Linear down to 5%, then holds at 5% until duty command is 1.5 %; 0 % for duty command below 1.5 %. 01: Linear down to 10%, then holds at 10% until duty command is 1.5 %; 0 % for duty command below 1.5 %. 10: Linear down to 5%, then holds at 5% until duty command is 1.5 %; 100 % for duty command below 1.5 %. 11: Linear down to 10%, then holds at 10% until duty command is 1.5 %; 100 % for duty command below 1.5 %. 1:0 SlewRate[1:0] R/W 0 Slew-rate control for phase node 00: Typical slew rate for VCC at 12 01: Typical slew rate for VCC at 12 10: Typical slew rate for VCC at 12 11: Typical slew rate for VCC at 12 13:12 58 Submit Documentation Feedback V V V V = 35 V/μs = 50 V/μs = 80 V/μs = 120 V/μs Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 8.5.3.28 CONFIG7 Register (address = 0x96) [reset = 0x00] Figure 67. CONFIG7 Register 15 IPDAdvcAg[1] R/W-0 14 IPDAdvcAg[0] R/W-0 13 IPDCurrThr[3] R/W-0 12 IPDCurrThr[2] R/W-0 11 IPDCurrThr[1] R/W-0 10 IPDCurrThr[0] R/W-0 9 IPDClk[1] R/W-0 8 IPDClk[0] R/W-0 7 Reserved R-0 6 CtrlCoef[1] R/W-0 5 CtrlCoef[0] R/W-0 4 DeadTime[4] R/W-0 3 DeadTime[3] R/W-0 2 DeadTime[2] R/W-0 1 DeadTime[1] R/W-0 0 DeadTime[0] R/W-0 Table 35. CONFIG7 Register Field Descriptions Field Type Reset Description 15:14 Bit IPDAdvcAg[1:0] R/W 00 Advance angle after inductive sense. 00: 30 degrees 01: 60 degrees 10: 90 degrees 11: 120 degrees 13:10 IPDCurrThr[3:0] R/W 0x0 IPD (inductive sense) current threshold 0000: No IPD function. Align and go 0001: 0.4-A current threshold. 0010 to 1111: 0.2 A × (n + 1) current threshold. IPDClk[1:0] R/W 00 Inductive sense clock 00: IPD clock 12 Hz; IPD measurement resolution = 2.56 µs 01: IPD clock = 24 Hz; IPD measurement resolution = 1.28 µs 10: IPD clock = 47 Hz; IPD measurement resolution = 0.64 µs 11: IPD clock = 95 Hz; IPD measurement resolution = 0.32 µs 9:8 Reserved R 0 Do not access this bit. 6:5 7 CtrlCoef[1:0] R/W 00 SCORE control constant 00: 0.25 01: 0.5 10: 0.75 11: 1 4:0 DeadTime[4:0] R/W 0x0 Driver dead time (n + 1) × 40 ns 40 ns to 1.204 μs Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 59 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The DRV10983-Q1 device is used in sensorless 3-phase BLDC motor control. The driver provides a highperformance, high-reliability, flexible, and simple solution for appliance fan, pump, and HVAC applications. The following design shows a common application of the DRV10983-Q1 device. 9.2 Typical Application VCC 0.1 µF 10 nF 10 µF 5V 47 µH 1 µF 1 µF 4.75 kW 4.75 kW 1 VCP VCC 24 2 CPP VCC 23 3 CPN W 22 4 SW W 5 SWGND V 20 21 6 VREG V 19 7 V1P8 U 18 8 GND U 17 9 V3P3 PGND 16 10 SCL 11 SDA 12 FG 10 µF M PGND 15 DIR 14 SPEED 13 Interface to Microcontroller Copyright © 2017, Texas Instruments Incorporated Figure 68. Typical Application Schematic 9.2.1 Design Requirements Table 36 provides design input parameters and motor parameters for system design. 60 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 Typical Application (continued) Table 36. Recommended Application Range Motor voltage MIN TYP MAX 6.2 12 28 UNIT V 0.001 1.8 V/Hz Motor velocity constant Phase to phase, measured while motor is coasting Motor resistance 1 phase, measured ph-ph and divided by 2 0.3 19 Ω Motor electrical constant 1 phase; inductance divided by resistance, measured ph-ph is equal to 1 ph 100 5000 µs Operating closed loop speed Electrical frequency 1 1000 Hz 0.1 2 A 3 A Motor operating current (RMS) Absolute maximum current During start-up or locked condition Table 37. External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVCC VCC GND 10-µF ceramic capacitor rated for VCC CVCP VCP VCC 0.1-µF ceramic capacitor rated for 10 V CCP CPP CPN 10-nF ceramic capacitor rated for VCC × 2 LSW-VREG SW VREG 47-µH ferrite rated for 1.15A (inductive mode) RSW-VREG SW VREG 39-Ω series resistor rated for ¼ W (resistor mode) CVREG VREG GND 10-µF ceramic capacitor rated for 10 V CV1P8 V1P8 GND 1-µF ceramic capacitor rated for 5 V CV3P3 V3P3 GND 1-µF ceramic capacitor rated for 5 V RSCL SCL V3P3 4.75-kΩ pullup to V3P3 RSDA SDA V3P3 4.75-kΩ pullup to V3P3 RFG FG V3P3 4.75-kΩ pullup to V3P3 9.2.2 Detailed Design Procedure 1. See the Design Requirements section and make sure your system meets the recommended application range. 2. See the DRV10983-Q1 Tuning Guide and measure the motor parameters. 3. See the DRV10983-Q1 Tuning Guide. Configure the parameters using the DRV10983-Q1 GUI, and optimize the motor operation. The Tuning Guide takes the user through all the configurations step by step, including: start-up operation, closed-loop operation, current control, initial positioning, lock detection, and anti-voltage surge. 4. Build your hardware based on Layout Guidelines . 5. Connect the device into a system and validate your system solution. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 61 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com 9.2.3 Application Curves FG Phase current Phase voltage Figure 69. DRV10983-Q1 Start-Up Waveform 62 Figure 70. DRV10983-Q1 Operation Current Waveform Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 DRV10983-Q1 www.ti.com SLVSD14 – JUNE 2017 10 Power Supply Recommendations The DRV10983-Q1 device is designed to operate from an input voltage supply, VCC, in a range between 8 V and 28 V. The user must place a 10-µF ceramic capacitor rated for VCC as close as possible to the VCC and GND pins. If the power supply ripple is more than 200 mV, in addition to the local decoupling capacitors, a bulk capacitance is required and must be sized according to the application requirements. If the bulk capacitance is implemented in the application, the user can reduce the value of the local ceramic capacitor to 1 µF. 11 Layout 11.1 Layout Guidelines • • • • • Place the VCC, GND, U, V, and W pins with thick traces because high current passes through these traces. Place the 10-µF capacitor between VCC and GND, and as close to the VCC and GND pins as possible. Place the capacitor between CPP and CPN, and as close to the CPP and CPN pins as possible. Connect the GND, PGND, and SWGND under the thermal pad. Keep the thermal pad connection as large as possible, on both the bottom side and top sides. It should be one piece of copper without any gaps. 11.2 Layout Example CVCC (10 µF) CVCP (0.1 µF) VCP VCC CPP VCC CPN W SW W SWGND V VREG V V1P8 U GND U CCP (10 nF) LSW_VREG (47 µH) CVREG (10 µF) CV1P8 (1 µF) CV3P3 (1 µF) V3P3 RSCL (4.75 kW) SCL RSDA (4.75 kW) SDA RFG (4.75 kW) FG PGND PGND DIR SPEED Figure 71. Layout Diagram Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 63 DRV10983-Q1 SLVSD14 – JUNE 2017 www.ti.com 12 Device and Documentation Support 12.1 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. is a trademark of ~other. 12.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane. 64 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: DRV10983-Q1 PACKAGE OPTION ADDENDUM www.ti.com 20-Jun-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DRV10983QPWPRQ1 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 DRV10983Q DRV10983SQPWPRQ1 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 10983SQ1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 20-Jun-2017 OTHER QUALIFIED VERSIONS OF DRV10983-Q1 : • Catalog: DRV10983 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 21-Jun-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ HTSSOP PWP 24 2000 330.0 16.4 DRV10983SQPWPRQ1 HTSSOP PWP 24 2000 330.0 16.4 DRV10983QPWPRQ1 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 8.3 1.6 8.0 16.0 Q1 6.95 8.3 1.6 8.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Jun-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV10983QPWPRQ1 HTSSOP PWP 24 2000 367.0 367.0 38.0 DRV10983SQPWPRQ1 HTSSOP PWP 24 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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