Renesas ISL8277MEVAL1Z Digital dc/dc pmbus 25a module Datasheet

DATASHEET
ISL8277M
FN8923
Rev.1.00
Aug 17, 2017
Digital DC/DC PMBus 25A Module
Features
The ISL8277M is a 25A step-down DC/DC power supply module
with an integrated digital PWM controller, synchronous power
switches, an inductor, and passives. Only bulk input and output
capacitors are needed to finish the design. The 25A of
continuous output current can be delivered without a need of
airflow or a heatsink. The thermally enhanced HDA module is
capable of dissipating heat directly into the PCB.
• Complete digital switch mode power supply
- Wide VIN range: 4.5V to 14V
- Programmable VOUT range: 0.6V to 5V
• PMBus compliant I2C communication interface
- Programmable VOUT, margining, UV/OV, IOUT limit,
soft-start/stop, sequencing, and external synchronization
- Monitor: VIN, VOUT, IOUT, temperature, duty cycle,
switching frequency, and faults
The ISL8277M uses ChargeMode™ control architecture, which
responds to a transient load within a single switching cycle.
The ISL8277M comes with a preprogrammed configuration for
operating in a pin-strap mode. Output voltage, switching
frequency, and device SMBus address can be programmed
with external resistors. More configuration such as soft-start
and fault limits can be easily programmed or changed using
the PMBus compliant serial bus interface. PMBus can be used
to monitor voltages, current, temperatures, and fault status.
The ISL8277M is supported by PowerNavigator™ software, a
graphical user interface (GUI) that can be used to configure
modules to a desired solution.
• ChargeMode control architecture
• ±1.0% VOUT accuracy over line, load, and temperature
• Power-good indicator
• Over-temperature protection
• Internal nonvolatile memory and fault logging
• Patented thermally enhanced HDA package
• Intuitive configuration via PowerNavigator
The ISL8277M is available in a 41-pin compact 17mmx19mm
HDA module with very low profile height of 3.6mm, suitable for
automated assembly by standard surface mount equipment.
The ISL8277M is RoHS compliant by exemption.
Applications
• Server, telecom, storage, and datacom
• Industrial/ATE and networking equipment
• General purpose power for ASIC, FPGA, DSP, and memory
Related Literature
• For a full list of related documents, visit our website
- ISL87277M product page
-
VIN
CIN
VIN
VOUT
VDD
VSEN+
VSEN-
VOUT
COUT
VDRVIN
VDRVOUT
10µF
ENABLE
ISL8277M
VR55
10µF
SCL
SDA
SALRT
EN
SGND
PGND
NOTE:
1. Only bulk input and output capacitors are required to finish the design.
FIGURE 1. COMPLETE DIGITAL SWITCH-MODE POWER SUPPLY
FN8923 Rev.1.00
Aug 17, 2017
17
VCC
PMBUS
INTERFACE
10µF
m
m
3.6mm
mm
19
FIGURE 2. SMALL PACKAGE FOR HIGH POWER DENSITY
Page 1 of 57
ISL8277M
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ISL8277M Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Efficiency Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transient Response Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Derating Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
11
12
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Undervoltage Lockout (UVLO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus Module Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Prebias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitoring Via SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Snapshot Parameter Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nonvolatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
17
18
18
18
19
19
20
20
20
20
21
21
21
21
21
21
21
PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Layout Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stencil Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflow Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
22
23
23
23
23
PMBus Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PMBus Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PMBus Use Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PMBus Command Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Firmware Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
FN8923 Rev.1.00
Aug 17, 2017
Page 2 of 57
ISL8277M
Ordering Information
PART NUMBER
(Notes 2, 3, 4)
PART
MARKING
TEMP RANGE
(°C)
ISL8277MAIRZ
ISL8277MA
-40 to +85
ISL8277MEVAL1Z
Evaluation Board
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
41 Ld 17x19 HDA
Y41.17x19
NOTES:
2. Add “-T” suffix for 500 unit or “-T1” suffix for 100 unit tape and reel options. Refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products are RoHS compliant by EU exemption 7C-I and 7A. They employ special Pb-free material sets;
molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), see the product information page for ISL8277M. For more information on MSL, see tech brief TB363.
ISL
xxxxM
F
T
R
Z
S
INTERSIL DEVICE DESIGNATOR
SHIPPING OPTION
BLANK: BULK
T: TAPE AND REEL
BASE PART NUMBER
ROHS
FIRMWARE REVISION
Z: ROHS COMPLIANT
A: FC01
PACKAGE DESIGNATOR
OPERATING TEMPERATURE
R: HIGH DENSITY ARRAY (HDA)
I: INDUSTRIAL (- 40°C TO +85°C)
TABLE 1. TABLE OF DIFFERENCES AMONG THE FAMILY OF PARTS
PARAMETERS
ISL8278M
ISL8271M
ISL8270M
ISL8277M
VIN (min) (V)
4.5
4.5
4.5
4.5
VIN (max) (V)
14
14
14
14
VOUT (min) (V)
0.6
0.6
0.6
0.6
VOUT (max) (V)
5
5
5
5
IOUT (max) (A)
33
33
25
25
IQ (mA)
40
40
40
40
Peak Efficiency (%)
96
96
96
96
POR
Yes
Yes
Yes
Yes
Switching Freq. (min) (MHz)
0.296
0.296
0.296
0.296
Switching Freq. (max) MHz
1.067
1.067
1.067
1.067
Control Type
Digital
Digital
Digital
Digital
SYNCH Capability
Yes
Yes
Yes
Yes
Current Sharing
No
No
No
No
Tracking
No
No
No
No
Digital
Yes
Yes
Yes
Yes
Qualification Level
Standard
Standard
Standard
Standard
FN8923 Rev.1.00
Aug 17, 2017
Page 3 of 57
ISL8277M
Pin Configuration
PGND
NC
SA
SALRT
SDA
SCL
EN
VDD
2
MGN
ASCR
VSET
1
NC
DDC
SGND
ISL8277M
(41 LD HDA)
TOP VIEW
27
26
25
24
23
22
21
20
19
18
17
16
28 PG
NC
5
VSEN+
6
VSEN -
7
38
37
36
VR6
SS/UVLO
VR5
29
4
VDDC
3
NC
SYNC 39
V25
NC
35
40
SGND
15
VDRVOUT
8
VDRVIN
99
41
30
34
PGND
PHASE
VCC
10
VIN
11
SGND
VR55
33
NC
31
32
NC
VOUT 14
PGND
PGND
12
VSWH
13
Pin Descriptions
PIN
LABEL
TYPE
DESCRIPTION
1
DDC
I/O
A Digital-DC™ bus. This dedicated bus provides the communication channel between devices for features such as
sequencing and fault spreading. The DDC pin on all Digital-DC devices should be connected together. A pull-up
resistor is required for this application.
2
ASCR
I
ChargeMode control ASCR parameters selection pin. Used to set ASCR gain and residual values.
6
VSEN+
I
Differential output voltage sense feedback. Connect to positive output regulation point.
7
VSEN-
I
Differential output voltage sense feedback. Connect to negative output regulation point.
8
VDRVOUT
PWR
Output of internal regulator for powering internal MOSFET driver. Connect a 10µF bypass capacitor to this pin. The
regulator output is dedicated to powering internal MOSFET drivers. Do not use this regulator for any other purpose.
For applications with VIN less than 5.2V, use an external 5V supply or connect this pad to VIN.
9
VDRVIN
PWR
Input supply to internal regulator for powering internal MOSFET drivers. Connect this pad to VIN.
10
VCC
PWR
Bias pin for internal regulator. Connect VCC pad to VR55 pin directly with a short loop trace. Not recommended to
power external circuit.
11
VIN
PWR
Main input supply. Refer to “PCB Layout Guidelines” on page 21 for the decoupling capacitors placement from VIN
to PGND.
12, 23, 31,
34
PGND
PWR
Power ground. Refer to “PCB Layout Guidelines” on page 21 for the PGND pad connections and decoupling
capacitors placement.
13
VSWH
PWR
Switch node. Refer to “PCB Layout Guidelines” on page 21 for connecting VSWH pads to electrically isolated PCB
copper island to dissipate internal heat.
FN8923 Rev.1.00
Aug 17, 2017
Page 4 of 57
ISL8277M
Pin Descriptions
(Continued)
PIN
LABEL
TYPE
DESCRIPTION
14
VOUT
PWR
Power supply output. Range: 0.6V to 5V. Refer to the “Derating Curves” on page 12 for maximum recommended
output current at various output voltages.
15, 27, 40
SGND
PWR
Controller signal ground. Refer to “PCB Layout Guidelines” on page 21for the SGND pad connections.
16
VDD
PWR
Input supply to digital controller. Connect VDD pad to VIN supply. Refer to “PCB Layout Guidelines” on page 21 for
the decoupling capacitors placement from VDD to SGND.
17
EN
I
18
SCL
I/O
Serial clock input. A pull-up resistor is required for this application.
19
SDA
I/O
Serial data. A pull-up resistor is required for this application.
20
SALRT
O
Serial alert. A pull-up resistor is required for this application.
21
SA
I
Serial bus address select pin. Refer to Table 9 on page 19 for list of resistor values to set various serial bus address.
24
MGN
I
External VOUT margin control pin. Active high (> 2V) signal at this pin sets VOUT margin high, active low (< 0.8V)
sets VOUTmargin low, and high impedance (float) will bring VOUT back to nominal voltage. Factory default range
for margining is nominal VOUT ±5%. When using PMBus to control margin command, leave this pin as no connect.
25
VSET
I
Output voltage selection pin. Refer to Table 4 on page 17 for list of resistor values to set various output voltages.
28
PG
O
Power-good output. Power-good output can be an open drain that requires pull-up resistor or push-pull output that
can drive a logic input.
29
SS/UVLO
I
Soft-start/stop and undervoltage lockout selection pin. Used to set turn on/off delay and ramp time as well as
input UVLO threshold levels. Refer to Table 5 and Table 8 for list of resistors.
30
PHASE
PWR
Switch node pad for DCR sensing. Electrically shorted inside to VSWH, but for higher current sensing accuracy
connect PHASE pad to VSWH pad externally. Refer to “PCB Layout Guidelines” on page 21.
35
VR6
PWR
6V Internal reference supply voltage.
36
VR5
PWR
5V Internal reference supply voltage.
37
VDDC
PWR
VDD Clean. Noise at the VDD pin is filtered by an internal ferrite bead and capacitor. For VDD > 6V, leave this pin
as no connect. For 5.5 ≤ VDD ≤ 6V, connect the VDDC pin to the VR6 pin. For 4.5 ≤ VDD < 5.5V, connect the VDDC
pin to the VR6 and VR5 pin.
38
V25
PWR
2.5V Internal reference supply voltage.
39
SYNC
I/O
SYNC pin can be input to external clock for frequency synchronization or output to supply clock signal to other
modules for synchronization. Refer to Table 6 on page 18 for list of resistor values to program various switching
frequencies.
41
VR55
PWR
Internal 5.5V bias for internal regulator use only. Connect VR55 pin directly to VCC pin. Not recommended to power
external circuit.
3, 4, 5, 22,
26, 32, 33
NC
FN8923 Rev.1.00
Aug 17, 2017
External enable input. Logic high enables the module.
These are test pins and are not electrically isolated. Leave these pins as no connect.
Page 5 of 57
ISL8277M
ASCR
SS/UVLO
VSET
OV/UV
VIN
VDRVOUT
LDO
INTERLEAVE
OT/UT OC/UC
POWER
MANAGEMENT
SNAPSHOT
FAULT SPREADING
MARGINING
VIN
SS
EN
PG
DDC
MGN
REGULATOR
FB
VDRVIN
VCC
V25
VR5
VR55
VR6
VDDC
VDD
ISL8277M Internal Block Diagram
SEQUENCE
PLL
0.3µH
LOGIC
SYNC
SYNC
OUT
VOUT
PWM OUT
D-PWM
PGND
NVM
SUPERVISOR
DRIVER AND FETS
ChargeMode
CONTROL
PROTECTION
CSA
332
ADC-10
VSEN+
VSA
VSEN-
ADC-10
VDD
VDRVOUT
SCL
SDA
SALRT
2
PMBus/I C
INTERFACE
INTERNAL TEMP
SENSOR
SA
SGND
PGND
SGND
DIGITAL CONTROLLER
FIGURE 3. BLOCK DIAGRAM
FN8923 Rev.1.00
Aug 17, 2017
Page 6 of 57
ISL8277M
Absolute Maximum Ratings
Thermal Information
Input Supply Voltage, VIN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V
Input Supply Voltage for Controller, VDD, VDDC Pin. . . . . . . . . -0.3V to 17V
Input Gate Driver Supply Voltage, VDRVIN Pin . . . . . . . . . . . . . -0.3V to 17V
Output Voltage, VOUT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Output Gate Driver Supply Voltage, VDRVOUT Pin . . . . . . . . . . . -0.3V to 6V
Switch Node Referenced to PGND Pin, VSWH Pin . . . . . . . . . -0.3V to 25V
Switch Node for DCR Sensing Referenced to SGND Pin,
PHASE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 25V
Input Bias Voltage for internal Regulator, VCC Pin . . . . . . . . -0.3V to 6.5V
6V Internal Reference Supply Voltage, VR6 Pin . . . . . . . . . . . -0.3V to 6.6V
Internal Reference Supply Voltage, VR5, VR55 Pin . . . . . . . . -0.3V to 6.5V
2.5V Internal Reference Supply Voltage, V25 Pin . . . . . . . . . . . -0.3V to 3V
Logic I/O Voltage for DDC, EN, MNG, PG, ASCR,
SA, SCL, SDA, SALRT, SYNC, SS/UVLO, VSET . . . . . . . . . . . -0.3V to 6.0V
Analog Input Voltages for
VSEN+, XTEMP+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
VSEN-, XTEMP- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
ESD Rating
Human Body Model (Tested per JS-001-2014) . . . . . . . . . . . . . . . . 2000V
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JS-002-2014) . . . . . . . . . . . . . . 750V
Latch-Up (Tested per JESD78E; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
41 LD HDA Package (Notes 5, 6) . . . . . . . .
7.5
2.2
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to Figure 31
Recommended Operating Conditions
Input Supply Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 14V
Input Supply Voltage Range for Controller, VDD . . . . . . . . . . . 4.5V to 14V
Output Voltage Range, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.6V to 5V
Output Current Range, IOUT(DC) (Note 9) . . . . . . . . . . . . . . . . . . . . 0A to 25A
Operating Junction Temperature Range, TJ. . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured in free air with the module mounted on an evaluation board 3x4.5 inch in size with 2oz surface and 2oz buried planes and multiple
via interconnects as specified the ISL8277MEVAL1Z Evaluation Board User Guide on the ISL8277M product page.
6. For JC, the “case temp” location is the center of the package underside.
Electrical Specifications VIN = VDD= 12V, fSW = 533kHz, COUT = 1340µF, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
Input Supply Current for Controller
IDD
VIN = VDD = 12V, VOUT = 0V, module not
enabled
6V Internal Reference Supply Voltage
VR6
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
40
50
mA
6.1
6.6
V
INPUT AND SUPPLY CHARACTERISTICS
Internal Regulator Output Voltage
VDRVOUT
5V Internal Reference Supply Voltage
VR5
2.5V Internal Reference Supply Voltage
V25
5.5V Internal Reference Supply Voltage
VR55
Input Supply Voltage for Controller
Readback Resolution
VDD_READ_RES
Input Supply Voltage for Controller
Readback Total Error (Note 10)
VDD_READ_ERR
5.5
VCC connected to VR55
IVR5 < 5mA
5.2
V
4.5
5.2
5.5
V
2.25
2.50
2.75
V
VDD > 6V; 0 - 80mA
PMBus read
5.7
V
10
Bits
±2
%FS
OUTPUT CHARACTERISTICS
Output Voltage Adjustment Range
VOUT_RANGE
VIN > VOUT + 1.8V
Output Voltage Set-Point Range
VOUT_RES
Configured using PMbus
Output Voltage Set-Point Accuracy
(Notes 8, 10)
VOUT_ACCY
Includes line, load, and temperature
Output Voltage Readback Resolution
FN8923 Rev.1.00
Aug 17, 2017
0.54
5.50
±0.025
-1
V
%
+1
%VOUT
(-20°C ≤ TA ≤ +85°C)
VOUT_READ_RES
10
Bits
Page 7 of 57
ISL8277M
Electrical Specifications VIN = VDD= 12V, fSW = 533kHz, COUT = 1340µF, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
Output Voltage Readback Total Error
(Note 10)
VOUT_READ_ERR
Output Current Readback Resolution
IOUT_READ_RES
Output Current Range (Note 9)
Output Current Readback Total Error
TEST CONDITIONS
PMBus read
MIN
(Note 7)
TYP
-2
MAX
(Note 7)
UNIT
+2
%VOUT
10
IOUT_RANGE
Bits
25
IOUT_READ_ERR
PMBus read at max load
tON_DELAY
Configured using PMBus
±2
A
A
SOFT-START AND SEQUENCING
Delay Time From Enable to VOUT Rise
tON_DELAY Accuracy
tON_DELAY_ACCY
Output Voltage Ramp-Up Time
tON_RISE
Output Voltage Ramp-Up Time
Accuracy
tON_RISE_ACCY
Delay Time From Disable to VOUT Fall
tOFF_DELAY Accuracy
Output Voltage Fall Time
Output Voltage Fall Time Accuracy
2
tOFF_DELAY
±2
Configured using PMBus
0.5
Configured using PMBus
100.0
2
5000
0.5
tON_FALL_ACCY
ms
µs
±2
Configured using PMBus
ms
ms
±250
tOFF_DELAY_ACCY
tOFF_FALL
5000
ms
ms
100.0
±250
ms
µs
POWER-GOOD
Power-Good Delay
VPG_DELAY
Configured using PMBus
0
5000
ms
Temperature Sense Range
TSENSE_RANGE
Configurable via PMBus
-50
150
C
Internal Temperature Sensor Accuracy
INT_TEMPACCY
Tested at +100°C
-5
+5
C
4.18
16
V
TEMPERATURE SENSE
FAULT PROTECTION
VDD Undervoltage Threshold Range
VDD_UVLO_RANGE
Measured internally
VDD Undervoltage Threshold Accuracy
(Note 10)
VDD_UVLO_ACCY
±2
%FS
VDD Undervoltage Response Time
VDD_UVLO_DELAY
10
µs
VOUT Overvoltage Threshold Range
VOUT_OV_RANGE
VOUT + 15
%
Factory default
Configured using PMBus
VOUT Undervoltage Threshold Range
VOUT_UV_RANGE
Factory default
Configured using PMBus
VOUT OV/UV Threshold Accuracy
(Note 8)
VOUT_OV/UV_ACCY
VOUT OV/UV Response Time
VOUT_OV/UV_DELAY
VOUT + 5
VOUT_MAX
VOUT - 15
%
%
0
VOUT - 5
%
-2
+2
%
10
µs
±10
%FS
Output Current Limit Set-Point
Accuracy (Note 10)
ILIMIT_ACCY
Tested at IOUT_OC_FAULT_LIMIT = 30A
Output Current Fault Response Time
(Note 11)
ILIMIT_DELAY
Factory default
5
tSW
TJUNCTION
Factory default
125
C
Over-temperature Protection Threshold
(Controller Junction Temperature)
Thermal Protection Hysteresis
FN8923 Rev.1.00
Aug 17, 2017
Configured using PMBus
TJUNCTION_HYS
-40
125
15
C
C
Page 8 of 57
ISL8277M
Electrical Specifications VIN = VDD= 12V, fSW = 533kHz, COUT = 1340µF, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
OSCILLATOR AND SWITCHING CHARACTERISTICS
Switching Frequency Range
Switching Frequency Set-Point
Accuracy
fSW_RANGE
296
1067
kHz
fSW_ACCY
-5
+5
%
Measured at 50% amplitude
150
EXT_SYNCDRIFT
External SYNC clock equal to 500kHz is
not supported
-10
+10
%
Bias Current at the Logic Input Pins
ILOGIC_BIAS
DDC, EN, MGN, PG, SA, SCL, SDA,
SALRT, SYNC, UVLO, VMON, VSET
-100
+100
nA
Logic Input Low Threshold Voltage
VLOGIC_IN_LOW
0.8
V
Logic Input High Threshold Voltage
VLOGIC_IN_HIGH
Logic Output Low Threshold Voltage
VLOGIC_OUT_LOW
2mA sinking
Logic Output High Threshold Voltage
VLOGIC_OUT_HIGH
2mA sourcing
Minimum Pulse Width Required from
External SYNC Clock
EXT_SYNCPW
Drift Tolerance for External SYNC Clock
ns
LOGIC INPUT/OUTPUT CHARACTERISTICS
2.0
V
0.5
2.25
V
V
PMBus INTERFACE TIMING CHARACTERISTIC
PMBus Operating Frequency
fSMB
100
400
kHz
NOTES:
7. Compliance to datasheet limits is assured by one or more methods: Production test, characterization, and/or design.
8. VOUT measured at the termination of the VSEN+ and VSEN- sense points.
9. The MAX load current is determined by the thermal “Derating Curves” on page 12.
10. “FS” stand for full scale of recommended maximum operation range.
11. “tSW” stands for time period of operation switching frequency.
FN8923 Rev.1.00
Aug 17, 2017
Page 9 of 57
ISL8277M
Typical Performance Curves
Efficiency Performance
Operating condition: TA= +25°C, No air flow. COUT = 1340µF. Typical values are used unless otherwise noted.
100
95
EFFICIENCY (%)
EFFICIENCY (%)
90
85
80
75
70
65
0.8V
1V
1.2V
1.8V
2.5V
3.3V
60
1
3
5
7
9
11
13
15
17
19
21
23
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
0.8V
1.5V
3.3V
SWITCHING FREQUENCY (kHz)
FIGURE 4. EFFICIENCY vs OUTPUT CURRENT AT VIN = 5V,
fSW = 533kHz FOR VARIOUS OUTPUT VOLTAGES
FIGURE 5. EFFICIENCY vs SWITCHING FREQUENCY AT VIN = 5V,
IOUT = 25A FOR VARIOUS OUTPUT VOLTAGES
100
95
EFFICIENCY (%)
EFFICIENCY (%)
90
85
80
75
0.8V
1.8V
5V
65
1V
2.5V
1.2V
3.3V
60
1
3
5
7
9
11
13
15
17
19
21
23
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
0.8V
1.5V
3.3V
FIGURE 7. EFFICIENCY vs SWITCHING FREQUENCY AT VIN = 9V,
IOUT = 25A FOR VARIOUS OUTPUT VOLTAGES
100
95
EFFICIENCY (%)
EFFICIENCY (%)
90
85
80
75
0.8V
1.8V
5V
60
1
3
5
7
9
11
13
1V
2.5V
15
17
1.2V
3.3V
19
21
23
I OUT (A)
FIGURE 8. EFFICIENCY vs OUTPUT CURRENT AT VIN = 12V,
fSW = 533kHz FOR VARIOUS OUTPUT VOLTAGES
FN8923 Rev.1.00
Aug 17, 2017
1.2V
2.5V
SWITCHING FREQUENCY (kHz)
FIGURE 6. EFFICIENCY vs OUTPUT CURRENT AT VIN = 9V,
fSW = 533kHz FOR VARIOUS OUTPUT VOLTAGES
65
1V
1.8V
5V
300 350 400 450 500 550 600 650 700 750 800 850 900
25
IOUT (A)
70
1.2V
2.5V
300 350 400 450 500 550 600 650 700 750 800 850 900
25
IOUT (A)
70
1V
1.8V
25
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
0.8V
1.5V
3.3V
1V
1.8V
5V
1.2V
2.5V
300 350 400 450 500 550 600 650 700 750 800 850 900
SWITCHING FREQUENCY (kHz)
FIGURE 9. EFFICIENCY vs SWITCHING FREQUENCY AT VIN = 12V,
IOUT = 25A FOR VARIOUS OUTPUT VOLTAGES
Page 10 of 57
ISL8277M
Typical Performance Curves
Transient Response Performance
Typical values are used unless otherwise noted.
(Continued)
Operating conditions: IOUT = 0/12.5A, IOUT Slew rate > 20A/µs, TA = +25°C, OLFM airflow.
ASCR GAIN = 300
RESIDUAL = 90
ASCR GAIN = 350
RESIDUAL = 90
VOUT: 100mV/DIV
VOUT: 100mV/DIV
IOUT: 5A/DIV
IOUT: 5A/DIV
50µs/DIV
FIGURE 10. 5VIN to 1VOUT TRANSIENT RESPONSE, fSW=533kHz,
COUT = 4x100µF CERAMIC + 2x470µF POSCAP
50µs/DIV
FIGURE 11. 5VIN TO 1.8VOUT TRANSIENT RESPONSE, fSW = 615kHz,
COUT = 3x100µF CERAMIC + 2x470µF POSCAP
ASCR GAIN = 300
RESIDUAL = 90
ASCR GAIN = 300
RESIDUAL = 90
VOUT: 100mV/DIV
VOUT: 100mV/DIV
IOUT: 5A/DIV
IOUT: 5A/DIV
50µs/DIV
FIGURE 12. 12VIN TO 1VOUT TRANSIENT RESPONSE, fSW = 533kHz,
COUT = 4x100µF CERAMIC + 2x470µF POSCAP
ASCR GAIN = 300
RESIDUAL = 90
ASCR GAIN = 350
RESIDUAL = 90
VOUT: 100mV/DIV
VOUT: 100mV/DIV
IOUT: 5A/DIV
IOUT: 5A/DIV
50µs/DIV
FIGURE 14. 12VIN TO 3.3VOUT TRANSIENT RESPONSE,
fSW = 615kHz, COUT = 3x100µF CERAMIC + 2x470µF
POSCAP
FN8923 Rev.1.00
Aug 17, 2017
50µs/DIV
FIGURE 13. 12VIN TO 1.8VOUT TRANSIENT RESPONSE, fSW = 615kHz,
COUT = 3x100µF CERAMIC + 2x470µF POSCAP
50µs/DIV
FIGURE 15. 12VIN TO 5VOUT TRANSIENT RESPONSE, fSW = 727kHz,
COUT = 3x100µF CERAMIC + 2x470µF POSCAP
Page 11 of 57
ISL8277M
Typical Performance Curves
Derating Curves
(Continued)
All of the following curves were plotted at TJ = +115°C, fSW = 533kHz
25
20
LOAD CURRENT (A)
LOAD CURRENT (A)
25
400 LFM
15
0 LFM
10
5
0
200 LFM
60
70
80
90
100
110
20
400 LFM
15
10
0 LFM
5
0
120
200 LFM
60
70
TEMPERATURE (°C)
FIGURE 16. 5VIN TO 1VOUT
400 LFM
15
0 LFM
10
5
20
10
0 LFM
5
200 LFM
70
80
90
100
110
0
120
60
70
80
90
100
110
120
TEMPERATURE (°C)
FIGURE 18. 5VIN TO 1.2VOUT
FIGURE 19. 12VIN TO 1.2VOUT
25
25
20
400 LFM
LOAD CURRENT (A)
LOAD CURRENT (A)
120
15
TEMPERATURE (°C)
15
200 LFM
10
5
0
110
400 LFM
200 LFM
0
60
100
25
LOAD CURRENT (A)
LOAD CURRENT (A)
90
FIGURE 17. 12VIN TO 1VOUT
25
20
80
TEMPERATURE (°C)
0 LFM
60
70
80
90
100
TEMPERATURE (°C)
FIGURE 20. 5VIN TO 1.8VOUT
FN8923 Rev.1.00
Aug 17, 2017
110
120
20
400 LFM
15
0 LFM
10
5
0
200 LFM
60
70
80
90
100
110
TEMPERATURE (°C)
FIGURE 21. 12VIN TO 1.8VOUT
Page 12 of 57
ISL8277M
Typical Performance Curves
Derating Curves
(Continued)
All of the following curves were plotted at TJ = +115°C, fSW = 533kHz
25
20
400 LFM
LOAD CURRENT (A)
LOAD CURRENT (A)
25
15
0 LFM
10
200 LFM
5
0
60
70
80
90
100
110
20
400 LFM
15
0 LFM
10
5
200 LFM
0
60
120
70
TEMPERATURE (°C)
FIGURE 22. 5VIN TO 2.5VOUT
100
110
25
20
400 LFM
LOAD CURRENT (A)
LOAD CURRENT (A)
90
FIGURE 23. 12VIN TO 2.5VOUT
25
15
0 LFM
10
5
0
80
TEMPERATURE (°C)
200 LFM
60
70
80
90
100
110
20
400 LFM
15
10
0 LFM
5
0
50
120
200 LFM
60
TEMPERATURE (°C)
70
80
90
100
110
TEMPERATURE (°C)
FIGURE 24. 5VIN TO 3.3VOUT
FIGURE 25. 12VIN TO 3.3VOUT
30
LOAD CURRENT (A)
25
20
400 LFM
15
200 LFM
10
5
0 LFM
0
50
60
70
80
90
100
TEMPERATURE (°C)
FIGURE 26. 12VIN TO 5VOUT, 727kHz
FN8923 Rev.1.00
Aug 17, 2017
Page 13 of 57
ISL8277M
Typical Application Circuit
Note 15
VOUT_COMMAND = 1.2V
PMBus ADDRESS = 0x28
10µ
VR6
VSET
ISL8277M
SA
VSWH
PHASE
VDRVOUT
C3
VDRVIN
VCC
VR55
VDD
VOUT
10µ
VIN
VSEN+
VSEN-
VIN
4.5V TO 13.2V
R1
2.2
Note 16
VR5
SGND
C4 1µ
V25
VDDC
PGND
C5
MGN
DDC
SCL
SDA
SALRT
SS/UVLO
R3
SYNC
R4
PMBus
INTERFACE
R6 R5
EN
R3,R4,R5, R6 = 4.7k
VAUX
3.3V TO 5V
ASCR
Note 12, 13
C6
10µ
C7
Note 14
C8 2x470µ
+ (POSCAP)
R7
C1
C2 +
220µ
2x22µ
VOUT
1.2V 25A
4x100µ
200
NOTES:
12. R4 and R5 are not required if the PMBus host already has I2C pull-up resistors.
13. Only one R3 per DDC bus is required when DDC bus is shared with other modules.
14. R7 is optional but recommended to sink possible ~100µA back-flow current from the VSEN+ pin. Back-flow current is present only when the
module is in a disabled state with power still available at the VDD pin.
15. Unused pins (SYNC, ASCR, MGN, SS/UVLO) can be no connect.
16. Internal reference supply pins (V25, VDDC, VR5, VR6) do not need external capacitors and can be no connect. Refer to “PCB Layout Guidelines”
on page 21 for more information.
FIGURE 27. TYPICAL SINGLE-PHASE APPLICATION CIRCUIT FOR 1.2V/25A OUTPUT
FN8923 Rev.1.00
Aug 17, 2017
Page 14 of 57
ISL8277M
TABLE 2. ISL8277M DESIGN GUIDE MATRIX AND OUTPUT VOLTAGE RESPONSE
RECOVERY STEP LOAD
VOUT
(A)
TIME
DEVIATION
(Note 19)
(uS)
(mV)
FREQUENCY
VIN
(V)
VOUT
(V)
CIN
(BULK)
(Note 17)
CIN
(CERAMIC)
COUT
(BULK)
COUT
(CERAMIC)
ASCR
GAIN
(Note 18)
ASCR
RESIDUAL
(Note 18)
5
0.8
2x150µF
3x22µF
2x470µF
4x100µF
160
90
364
80
25
12.5A
5
0.8
2x150µF
3x22µF
2x470µF
4x100µF
300
90
533
60
15
12.5A
5
0.9
2x150µF
3x22µF
2x470µF
4x100µF
160
90
364
80
25
12.5A
5
1
2x150µF
3x22µF
2x470µF
4x100µF
160
90
364
80
25
12.5A
5
1
2x150µF
3x22µF
2x470µF
4x100µF
300
90
533
60
18
12.5A
5
1.05
2x150µF
3x22µF
2x470µF
4x100µF
200
90
421
76
25
12.5A
5
1.1
2x150µF
3x22µF
2x470µF
4x100µF
250
90
471
72
20
12.5A
5
1.2
2x150µF
3x22µF
2x470µF
4x100µF
250
90
533
60
15
12.5A
5
1.3
2x150µF
3x22µF
2x470µF
4x100µF
300
90
533
58
20
12.5A
5
1.5
2x150µF
3x22µF
2x470µF
4x100µF
350
90
533
58
20
12.5A
5
1.8
2x150µF
3x22µF
2x470µF
3x100µF
350
90
615
62
30
12.5A
5
2.5
2x150µF
3x22µF
2x470µF
3x100µF
350
90
615
64
25
12.5A
5
3.3
2x150µF
3x22µF
2x470µF
3x100µF
300
90
615
70
35
12.5A
5
1.8
2x150µF
3x22µF
1x470µF
3x100µF
200
90
615
100
30
12.5A
5
2.5
2x150µF
3x22µF
1x470µF
3x100µF
200
90
615
100
35
12.5A
5
3.3
2x150µF
3x22µF
1x470µF
3x100µF
200
90
615
100
40
12.5A
12
0.8
2x150µF
3x22µF
2x470µF
4x100µF
160
90
364
80
18
12.5A
12
0.8
2x150µF
3x22µF
2x470µF
4x100µF
300
90
533
60
15
12.5A
12
0.9
2x150µF
3x22µF
2x470µF
4x100µF
160
90
364
80
18
12.5A
12
1
2x150µF
3x22µF
2x470µF
4x100µF
160
90
364
80
20
12.5A
12
1
2x150µF
3x22µF
2x470µF
4x100µF
300
90
533
60
12
12.5A
12
1.05
2x150µF
3x22µF
2x470µF
4x100µF
200
90
421
80
15
12.5A
12
1.1
2x150µF
3x22µF
2x470µF
4x100µF
200
90
471
78
15
12.5A
12
1.2
2x150µF
3x22µF
2x470µF
4x100µF
250
90
533
75
15
12.5A
12
1.3
2x150µF
3x22µF
2x470µF
4x100µF
300
90
533
72
12
12.5A
12
1.5
2x150µF
3x22µF
2x470µF
4x100µF
300
90
533
75
12
12.5A
12
1.8
2x150µF
3x22µF
2x470µF
3x100µF
300
90
615
78
10
12.5A
12
2.5
2x150µF
3x22µF
2x470µF
3x100µF
300
90
615
80
10
12.5A
12
3.3
2x150µF
3x22µF
2x470µF
3x100µF
300
90
615
82
10
12.5A
12
5
2x150µF
3x22µF
2x470µF
3x100µF
350
90
727
95
10
12.5A
12
1.8
2x150µF
3x22µF
1x470µF
3x100µF
200
90
615
102
12
12.5A
12
2.5
2x150µF
3x22µF
1x470µF
3x100µF
200
90
615
110
12
12.5A
12
3.3
2x150µF
3x22µF
1x470µF
3x100µF
200
90
615
118
12
12.5A
12
5
2x150µF
3x22µF
1x470µF
3x100µF
250
90
727
120
12
12.5A
NOTES:
17. CIN bulk capacitor is optional only for energy buffer from the long input power supply cable.
18. ASCR gain and residual are selected to ensure that the phase margin is higher than 60° and gain margin is higher than 6dB at -40°C, +25°C, +85°C,
and full load (25A).
19. Output voltage response is tested with load step slew rate higher than 20A/µs.
FN8923 Rev.1.00
Aug 17, 2017
Page 15 of 57
ISL8277M
TABLE 3. RECOMMENDED I/O CAPACITOR IN Table 2
VENDORS
VALUE
PART NUMBER
MURATA, Input Ceramic
47µF, 16V, 1210
GRM32ER61C476ME15L
MURATA, Input Ceramic
22µF, 16V, 1210
GRM32ER61E226KE15L
TAIYO YUDEN, Input Ceramic
47µF, 16V, 1210
EMK325BJ476MM-T
TAIYO YUDEN, Input Ceramic
22µF, 25V, 1210
TMK325BJ226MM-T
MURATA, Output Ceramic
100µF, 6.3V, 1210
GRM32ER60J107M
TDK, Output Ceramic
100µF, 6.3V, 1210
C3225X5R0J107M
AVX, Output Ceramic
100µF, 6.3V, 1210
12106D107MAT2A
SANYO POSCAP, Input Bulk
150µF, 16V
16TQC150MYF
SANYO POSCAP, Output Bulk
470µF, 4V
4TPE470MCL
SANYO POSCAP, Output Bulk
470µF, 6.3V
6TPF470MAH
FN8923 Rev.1.00
Aug 17, 2017
Page 16 of 57
ISL8277M
Functional Description
TABLE 4. OUTPUT VOLTAGE RESISTOR SETTINGS (Continued)
SMBus Communications
The ISL8277M provides an SMBus digital interface that enables
the user to configure all aspects of the module operation as well
as monitor the input and output parameters. The ISL8277M can
be used with any SMBus host device. In addition, the module is
compatible with PMBus Power System Management Protocol
Specification Parts I & II version 1.2. The ISL8277M accepts most
standard PMBus commands. When controlling the device with
PMBus commands, it is recommended that the enable pin be
tied to SGND.
The SMBus device address is the only parameter that must be
set by external pins. All other device parameters can be set with
PMBus commands.
Output Voltage Selection
The output voltage may be set to a voltage between 0.6V and 5V
provided that the input voltage is higher than the desired output
voltage by an amount sufficient to maintain regulation.
The VSET pin is used to set the output voltage to levels as shown
in Table 4. The RSET resistor is placed between the VSET pin and
SGND. A standard 1% resistor is recommend.
TABLE 4. OUTPUT VOLTAGE RESISTOR SETTINGS
VOUT
(V)
RSET
(kΩ)
0.60
10
0.65
11
0.70
12.1
0.75
13.3
0.80
14.7
0.85
16.2
0.90
17.8
0.95
19.6
1.00
21.5, or Connect to SGND
1.05
23.7
1.10
26.1
1.15
28.7
1.20
31.6, or OPEN
1.25
34.8
1.30
38.3
1.40
42.2
1.50
46.4
1.60
51.1
1.70
56.2
1.80
61.9
1.90
68.1
2.00
75
FN8923 Rev.1.00
Aug 17, 2017
VOUT
(V)
RSET
(kΩ)
2.10
82.5
2.20
90.9
2.30
100
2.50
110, or Connect to V25
2.80
121
3.00
133
3.30
147
4.00
162
5.00
178
The output voltage may also be set to any value between 0.6V
and 5V using a PMBus command VOUT_COMMAND.
By default, VOUT_MAX is set 110% higher than VOUT set by the
pin-strap resistor, which can be changed to any value up to 5.5V
with PMBus Command VOUT_MAX.
Soft-Start Delay and Ramp Times
The ISL8277M follows an internal start-up procedure after power
is applied to the VDD pin. The module requires approximately
60ms to 70ms to check for specific values stored in its internal
memory and programmed by pin-strap resistors. Once this
process is completed, the device is ready to accept commands
via the PMBus interface and the module is ready to be enabled. If
the module is to be synchronized to an external clock source, the
clock frequency must be stable prior to asserting the EN pin.
It may be necessary to set a delay from when an enable signal is
received until the output voltage starts to ramp to its target
value. In addition, the designer may wish to precisely set the time
required for VOUT to ramp to its target value after the delay
period has expired. These features may be used as part of an
overall in-rush current management strategy or to precisely
control how fast a load IC is turned on. The ISL8277M gives the
system designer several options for precisely and independently
controlling both the delay and ramp time periods. The soft-start
delay period begins when the EN pin is asserted and ends when
the delay time expires.
The soft-start delay and ramp times can be programmed to
custom values with PMBus commands TON_DELAY and
TON_RISE. When the delay time is set to 0ms, the device begins
its ramp-up after the internal circuitry has initialized
(approximately 2ms). When the soft-start ramp period is set to
0ms, the output ramps up as quickly as the output load
capacitance and loop settings allow. It is generally
recommended to set the soft-start ramp to a value greater than
500µs to prevent inadvertent fault conditions due to excessive
in-rush current.
Similar to the soft-start delay and ramp-up time, the delay and
ramp-down time for soft-stop/off can be programmed with the
PMBus commands TOFF_DELAY and TOFF_FALL. In addition, the
module can be configured as “immediate off” with the command
Page 17 of 57
ISL8277M
ON_OFF_CONFIG, such that the internal MOSFETs are turned off
immediately after the delay time expires.
TABLE 6. SWITCHING FREQUENCY RESISTOR SETTINGS (Continued)
The SS/UVLO pin can be used to program the soft- start/stop
delay time and ramp time to some typical values as shown in
Table 5.
TABLE 5. SOFT-START/STOP RESISTOR SETTINGS
DELAY TIME
(ms)
RAMP TIME
(ms)
RSET
(kΩ)
5
2
12.1, 26.1, 56.2, or
connect to SGND
fSW
(V)
RSET
(kΩ)
421
21.5
471
23.7
533
26.1 or OPEN
571
28.7
615
31.6
727
34.8
10
2
16.2, 34.8, 75
800
38.3
5
5
13.3, 28.7, 61.9, or OPEN
842
42.2
10
5
17.8, 38.3, 82.5
889
46.4
20
5
21.5, 46.4, 100
1067
51.1 or Connect to V25
5
10
14.7, 31.6, 68.1
10
10
19.6, 42.2, 90.9, or
connect to V25
20
10
23.7, 51.1, 110
Power-Good
The ISL8277M provides a Power-Good (PG) signal that indicates
the output voltage is within a specified tolerance of its target
level and no fault condition exists. By default, the PG pin asserts
if the output is within 10% of the target voltage. These limits and
the polarity of the pin may be changed with PMBus command
POWER_GOOD_ON.
A PG delay period is defined as the time from when all conditions
within the ISL8277M for asserting PG are met to when the PG pin
is actually asserted. This feature is commonly used instead of
using an external reset controller to control external digital logic.
A PG delay can be programmed with PMBus command
POWER_GOOD_DELAY.
Switching Frequency and PLL
The device’s switching frequency is set from 296kHz to 1067kHz
using the pin-strap method as shown in Table 6, or by using a
PMBus command FREQUENCY_SWITCH. The ISL8277M
incorporates an internal Phase-Locked Loop (PLL) to clock the
internal circuitry. The PLL can be driven by an external clock source
connected to the SYNC pin. When using the internal oscillator, the
SYNC pin can be configured as a clock source that is an external
sync to other modules. Refer to “SYNC_CONFIG (E9h)” on page 47
for more information.
TABLE 6. SWITCHING FREQUENCY RESISTOR SETTINGS
fSW
(V)
RSET
(kΩ)
296
14.7 or connect to SGND
320
16.2
364
17.8
400
19.6
FN8923 Rev.1.00
Aug 17, 2017
Loop Compensation
The module loop response is programmable via the PMBus
command ASCR_CONFIG or by using the pin-strap method (ASCR
pin) according to Table 7. The ISL8277M uses the ChargeMode
control algorithm that responds to output current changes within
a single PWM switching cycle, achieving a smaller total output
voltage variation with less output capacitance than traditional
PWM controllers.
TABLE 7. ASCR RESISTOR SETTINGS
ASCR GAIN
ASCR RESIDUAL
RSET (kΩ)
120
90
10
160
90
11, or Connect to SGND
200
90
12.1
250
90
13.3, or OPEN
300
90
14.7
350
90
16.2
400
90
17.8
500
90
19.6
600
90
21.5
120
80
23.7
160
80
26.1
200
80
28.7
250
80
31.6
300
80
34.8
350
80
38.3
400
80
42.2
80
70
46.4
120
70
51.1
160
70
56.2
200
70
61.9
Page 18 of 57
ISL8277M
TABLE 7. ASCR RESISTOR SETTINGS (Continued)
SMBus Module Address Selection
250
70
68.1
300
70
75
120
100
82.5
160
100
90.9
200
100
100
250
100
110, or Connect to V25
RSA
(kΩ)
SMBus
ADDRESS
300
100
121
10
19h
350
100
133
11
1Ah
400
100
147
12.1
1Bh
500
100
162
13.3
1Ch
600
100
178
14.7
1Dh
16.2
1Eh
17.8
1Fh
19.6
20h
21.5
21h
23.7
22h
26.1
23h
Fault response to an input undervoltage fault can be programmed
with PMBus command VIN_UV_FAULT_RESPONSE.
28.7
24h
31.6
25h
TABLE 8. UVLO RESISTOR SETTINGS
34.8 or connect to SGND
26h
38.3
27h
42.2 or Open
28h
46.4
29h
Input Undervoltage Lockout (UVLO)
The Input Undervoltage Lockout (UVLO) prevents the ISL8277M
from operating when the input falls below a preset threshold,
indicating the input supply is out of its specified range. The UVLO
threshold (VUVLO) can be set between 4.18V and 16V using the
pin-strap method as shown in Table 8, or by using a PMBus
command VIN_UV_FAULT_LIMIT.
Each module must have its own unique serial address to
distinguish between other devices on the bus. The module
address is set by connecting a resistor between the SA pin and
SGND. Table 9 lists the available module addresses.
TABLE 9. SMBus ADDRESS RESISTOR SELECTION
UVLO
(V)
RUVLO
(kΩ)
4.5
12.1, 13.3, 14.7, 16.2, 17.8, 19.6,
21.5, 23.7, OPEN, Connect to V25
and SGND
51.1
2Ah
4.3
26.1
56.2
2Bh
4.59
28.7
61.9
2Ch
5.06
31.6
68.1
2Dh
5.57
34.8
75
2Eh
6.13
38.3
82.5
2Fh
6.75
42.2
90.9
30h
7.42
46.4
100
31h
8.18
51.1
10.8
56.2
10.8
61.9
10.8
68.1
10.8
75
10.8
82.5
10.8
90.9
10.8
100
FN8923 Rev.1.00
Aug 17, 2017
Page 19 of 57
ISL8277M
Output Overvoltage Protection
The ISL8277M offers an internal output overvoltage protection
circuit that can be used to protect sensitive load circuitry from
being subjected to a voltage higher than its prescribed limits. A
hardware comparator is used to compare the actual output
voltage (seen at the VSEN+ and VSEN- pins) to a threshold set to
15% higher than the target output voltage (the default setting).
Fault threshold can be programmed to a desired level with
PMBus command VOUT_OV_FAULT_LIMIT. If the VSEN+ voltage
exceeds this threshold, the module will initiate an immediate
shutdown without retry. Retry settings can be programmed with
PMBus command VOUT_OV_FAULT_RESPONSE.
Internal to the module, two 100Ω resistors are populated from
VOUT to VSEN+ and SGND to VSEN to protect the device from
overvoltage conditions in case of an open at VSENSE pins and
differential remote sense traces due to assembly error. As long
as differential remote sense traces have low resistance, VOUT
regulation accuracy is not sacrificed.
VOUT
DESIRED OUTPUT
VOLTAGE
PRE-BIAS
VOLTAGE
TIME
TONDELAY
TONRISE
VPREBIAS < VTARGET
VOUT
PRE-BIAS
VOLTAGE
DESIRED OUTPUT
VOLTAGE
Output Prebias Protection
An output prebias condition exists when an externally applied
voltage is present on a power supply’s output before the power
supply’s control IC is enabled. Certain applications require that
the converter not be allowed to sink current during start-up if a
prebias condition exists at the output. The ISL8277M provides
prebias protection by sampling the output voltage prior to
initiating an output ramp.
If a prebias voltage lower than the target voltage exists after the
preconfigured delay period has expired, the target voltage is set
to match the existing prebias voltage, and both drivers are
enabled. The output voltage is then ramped to the final
regulation value at the preconfigured ramp rate.
The actual time the output takes to ramp from the prebias
voltage to the target voltage varies, depending on the prebias
voltage, however, the total time elapsed from when the delay
period expires and when the output reaches its target value will
match the preconfigured ramp time (see Figure 28).
If a prebias voltage is higher than the target voltage after the
preconfigured delay period has expired, the target voltage is set
to match the existing prebias voltage, and both drivers are
enabled with a PWM duty cycle that would ideally create the
prebias voltage.
Once the preconfigured soft-start ramp period has expired, the
PG pin is asserted (assuming the prebias voltage is not higher
than the overvoltage limit). The PWM then adjusts its duty cycle
to match the original target voltage, and the output ramps down
to the preconfigured output voltage.
If a prebias voltage is higher than the overvoltage limit, the
device does not initiate a turn-on sequence and declares an
overvoltage fault condition. The device then responds based on
the output overvoltage fault response setting programmed with
PMBus command VOUT_OV_FAULT_RESPONSE.
TIME
TONDELAY
TONRISE
VPREBIAS > VTARGET
FIGURE 28. OUTPUT RESPONSES TO PRE-BIAS VOLTAGES
Output Overcurrent Protection
The ISL8277M can protect the power supply from damage if the
output is shorted to ground or if an overload condition is imposed
on the output. Average output overcurrent fault threshold can be
programmed with PMBus command IOUT_OC_FAULT_LIMIT. The
module automatically programs the peak inductor current fault
threshold by reading real-time input voltage, switching frequency,
and VOUT_COMMAND to calculate the inductor ripple current.
When the peak inductor current crosses the peak inductor
current fault threshold for five successive cycle modules, it will
initiate an immediate shutdown.
The default response from an overcurrent fault is an immediate
shutdown without retry. Retry settings can be programmed with
PMBus command MFR_IOUT_OC_FAULT_RESPONSE.
Thermal Overload Protection
The ISL8277M includes a thermal sensor that continuously
measures the internal temperature of the module and shuts
down the controller when the temperature exceeds the preset
limit. The default temperature limit is set to +125°C in the
factory, but can be changed with PMBus command
OT_FAULT_LIMIT.
The default response from an over-temperature fault is an
immediate shutdown without retry. Retry settings can be
programmed with PMBus command OT_FAULT_RESPONSE.
If the user has configured the module to retry, the controller
waits the preset delay period and then checks the module
temperature. If the temperature has dropped below a threshold
that is approximately +15°C lower than the selected
temperature fault limit, the controller attempts to restart. If the
FN8923 Rev.1.00
Aug 17, 2017
Page 20 of 57
ISL8277M
temperature still exceeds the fault limit, the controller waits the
preset delay period and retries the temperature.
Digital-DC Bus
The Digital-DC Communications (DDC) bus is used to
communicate between Intersil digital power modules and digital
controllers. This dedicated bus provides the communication
channel between devices for features such as sequencing and
fault spreading. The DDC pin on all Digital-DC devices in an
application should be connected together. A pull-up resistor is
required on the DDC bus to ensure the rise time as shown in
Equation 1:
Rise Time = R PU C LOAD  1s
(EQ. 1)
Fault Spreading
Digital DC modules and devices can be configured to broadcast a
fault event over the DDC bus to the other devices in the group
with PMBus command DDC_GROUP. When a non-destructive
fault occurs and the device is configured to shutdown on a fault,
the device shuts down and broadcasts the fault event over the
DDC bus. The other devices on the DDC bus shutdown
simultaneously, if configured to do so, and attempt to restart in
their prescribed order.
Monitoring Via SMBus
A system controller can monitor a wide variety of different
ISL8277M system parameters with PMBus commands:
where RPU is the DDC bus pull-up resistance and CLOAD is the
bus loading. The pull-up resistor may be tied to an external 3.3V
or 5V supply as long as this voltage is present before or during
device power-up. In principle, each device connected to the DDC
bus presents approximately 10pF of capacitive loading, and each
inch of FR4 PCB trace introduces approximately 2pF. The ideal
design uses a central pull-up resistor that is well-matched to the
total load capacitance.
• READ_VIN
Phase Spreading
• READ_FREQEUNCY
When multiple point-of-load converters share a common DC
input supply, it is desirable to adjust the clock phase offset of
each device, such that not all devices start to switch
simultaneously. Setting each converter to start its switching cycle
at a different point in time can dramatically reduce input
capacitance requirements and efficiency losses. Because the
peak current drawn from the input supply is effectively spread
out over a period of time, the peak current drawn at any given
moment is reduced, and the power losses proportional to the
IRMS2 are reduced dramatically.
To enable phase spreading, all converters must be synchronized
to the same switching clock. The phase offset of each device
may also be set to any value between 0° and 360° in 22.5°
increments with PMBus command INTERLEAVE.
Output Sequencing
A group of Digital-DC modules or devices may be configured to
power-up in a predetermined sequence. This feature is especially
useful for preventing latch-up when powering advanced
processors (FPGAs and ASICs that require one supply to reach its
operating voltage) prior to another supply reaching its operating
voltage. Multi-device sequencing can be achieved by configuring
each device with PMBus command SEQUENCE. Multiple device
sequencing is configured by issuing PMBus commands to assign
the preceding device in the sequencing chain as well as the
device that follows in the sequencing chain.
The Enable pins of all devices in a sequencing group must be tied
together and driven high to initiate a sequenced turn-on of the
group. Enable must be driven low to initiate a sequenced turnoff
of the group.
• READ_VOUT
• READ_IOUT
• READ_INTERNAL_TEMP
• READ_EXTERNAL_TEMP
• READ_DUTY_CYCLE
• MFR_READ_VMON
Snapshot Parameter Capture
The ISL8277M offers a special feature to capture parametric data
and some fault status following a fault. A detailed description is
provided in “SNAPSHOT (EAh)” on page 48.
Nonvolatile Memory
The ISL8277M has internal nonvolatile memory that stores user
configurations. Integrated security measures ensure that users
can only restore the module to a level that has been made
available to them. During the initialization process, the ISL8277M
checks for stored values contained in its internal nonvolatile
memory.
Modules are shipped with factory default configurations. Most
settings can be overwritten with PMBus commands and can be
stored in nonvolatile memory with the PMBus command
STORE_USER_ALL.
PCB Layout Guidelines
To achieve stable operation, low losses, and good thermal
performance, some layout considerations are necessary.
• For VDD > 6V, the recommended PCB layout is shown in
Figure 29. Leave V25, VDDC, VR5, and VR6 as “No Connect
(NC)”.
• For 5.5V  VDD  6V, connect VDDC pin to VR6 pin. For
4.5  VDD < 5.5V, connect VDDC pin to VR6 and VR5 pin. An RC
filter is required at the input of VDRVIN pin if input supply is
shared with the VIN pin.
• Establish a separate SGND plane and PGND plane, then
connect the SGND to the PGND plane as shown in Figure 30 in
the middle layer. For making connections between
SGND/PGND on the top layer and other layers, use multiple
FN8923 Rev.1.00
Aug 17, 2017
Page 21 of 57
ISL8277M
CONNECT SGND TO PGND IN
THE MIDDLE LAYER
SGND
vias for each pin to connect to the inner SGND/PGND layer. Do
not connect SGND directly to PGND on a top layer. Connecting
SGND directly to PGND without establishing an SGND plane
will bypass the decoupling capacitor at internal reference
supplies, making the controller susceptible to noise.
• Connect differential remote-sensing traces to the regulation point
to achieve a tight output voltage regulation. Route a trace from
and VSEN+ to the point-of-load where the tight output voltage is
desired. Avoid routing any sensitive signal traces, such as the
VSENSE signal near VSWH pads.
UVLO
VR5
PHASE
C
VR6
VR55
V DRVIN
A
B
C
SGND
VDDC
SGND
V DRVOUT
C
R
SYNC
PG
VR25
C
VDD
CVDD
DDC
ASCR
NC
NC
NC
VSEN+
VSEN -
PGND
SGND
NC
VSET
MGN
PGND
NC
SA
SALRT
SDA
SCL
EN
SGND
• For noise sensitive applications, it is recommended that the
user connect the VSWH pads only on the top layer; however,
thermal performance will be sacrificed. External airflow might
be required to keep module heat at desired level. For
applications where switching noise is less critical, an excellent
thermal performance can be achieved in the ISL8277M
module by increasing copper mass attached to VSWH pad. To
increase copper mass on the VSWH node, create copper
islands in the middle and bottom layers under the VSWH pad
and connect them to the top layer with multiple vias. Make
sure to shield those copper islands with a PGND layer to avoid
any interference to noise sensitive signals.
PGND
VCC
NC
VSWH
PGND
CVIN
VOUT
NC
VIN
PGND
CVOUT
SGND
PGND
PGND
PGND
PGND
• Use large copper areas for power path (VIN, PGND, VOUT) to
minimize conduction loss and thermal stress. Also, use
multiple vias to connect the power planes in different layers.
Extra ceramic capacitors at VIN and VOUT can be placed on the
bottom layer under VIN and VOUT pads when multiple vias are
used for connecting copper pads on top and bottom layers.
SGND
SGND
• Place ceramic capacitors between VIN and PGND, VOUT and
PGND, and the bypass capacitors between VDD and the
ground plane, as close to the module as possible to minimize
high frequency noise.
FIGURE 30. RECOMMENDED LAYOUT - CONNECT SGND TO PGND IN
THE MIDDLE PCB LAYER AFTER ESTABLISHING
SEPARATE SGND AND PGND
Thermal Considerations
Experimental power loss curves, along with θJA from thermal
modeling analysis, can be used to evaluate the thermal
consideration for the module. The derating curves are derived
from the maximum power allowed while maintaining the
temperature below the maximum junction temperature of
+125°C. In actual application, other heat sources and design
margins should be considered.
Package Description
The structure of the ISL8277M belongs to the High Density Array
(HDA) no-lead package. This kind of package has advantages,
such as good thermal and electrical conductivity, low weight, and
small size. The HDA package is applicable for surface mounting
technology and is being more readily used in the industry. The
ISL8277M contains several types of devices, including resistors,
capacitors, inductors, and control ICs. The ISL8277M is a copper
lead-frame based package with exposed copper thermal pads,
which have good electrical and thermal conductivity. The copper
lead frame and multi-component assembly is over-molded with
polymer mold compound to protect these devices.
The package outline, a typical PCB land pattern design, and a
typical stencil opening edge position are shown in the “Package
Outline Drawing” section starting on page 51. The module has a
small size of 17mmx19mmx3.6mm. Figure 31 shows typical
reflow profile parameters. These guidelines are general design
rules. Users can modify parameters according to their
application.
FIGURE 29. RECOMMENDED LAYOUT - TOP PCB LAYER
FN8923 Rev.1.00
Aug 17, 2017
Page 22 of 57
ISL8277M
PCB Layout Pattern Design
Reflow Parameters
The bottom of the ISL8277M is a lead-frame footprint, which is
attached to the PCB by surface mounting process. The PCB land
pattern is shown in the “Package Outline Drawing” section
starting on page 51.
Due to the low mount height of the HDA, a “No Clean” Type 3
solder paste per ANSI/J-STD-005 is recommended. Nitrogen
purge is also recommended during reflow. A system board reflow
profile depends on the thermal mass of the entire populated
board, thus it is not practical to define a specific soldering profile
just for the HDA. The profile given in Figure 31 is provided as a
guideline, to be customized for varying manufacturing practices
and applications
The PCB layout pattern is an array of solder mask defined PCB
lands which align with the perimeters of the HDA exposed pads
and I/O termination dimensions. The thermal lands on the PCB
layout also feature an array of solder mask defined lands and
should match 1:1 with the package exposed die pad perimeters.
The exposed solder mask defined PCB land area should be
50-80% of the available module I/O area.
.
300
Thermal Vias
250
TEMPERATURE (°C)
A grid of 1.0mm to 1.2mm pitch thermal vias, which drops down
and connects to buried copper plane(s), should be placed under the
thermal land. The vias should be about 0.3mm to 0.33mm in
diameter with the barrel plated to about 1.0 ounce copper. Although
adding more vias (by decreasing via pitch) will improve the thermal
performance, diminishing returns will be seen as more and more
vias are added. Simply use as many vias as practical for the thermal
land size and that your board design rules will allow.
200
SLOW RAMP (3°C/s MAX)
AND SOAK FROM +150°C
TO +200°C FOR 60s~180s
150
100
RAMP RATE 1.5°C FROM +70°C TO +90°C
50
Stencil Pattern Design
Reflowed solder joints on the perimeter I/O lands should have
about a 50µm to 75µm (2mil to 3mil) standoff height. The solder
paste stencil design is the first step in developing optimized,
reliable solder joints.
The stencil aperture size to solder mask defined PCB land size
ratio should typically be 1:1. The aperture width can be reduced
slightly to help prevent solder bridging between adjacent I/O
lands. A typical solder stencil pattern is shown in the “Package
Outline Drawing” section starting on page 51.
PEAK TEMPERATURE ~+245°C;
TYPICALLY 60s-150s ABOVE +217°C
KEEP LESS THAN 30s WITHIN 5°C OF PEAK TEMP.
0
0
100
150
200
250
300
350
DURATION (s)
FIGURE 31. TYPICAL REFLOW PROFILE
*
The user should consider the symmetry of the whole stencil
pattern when designing its pads. A laser cut, stainless steel
stencil with electropolished trapezoidal walls is recommended.
Electropolishing “smooths” the aperture walls resulting in
reduced surface friction and better paste release, which reduces
voids. Using a Trapezoidal Section Aperture (TSA) also promotes
paste release and forms a “brick like” paste deposit that assists
in firm component placement. A 0.1mm to 0.15mm stencil
thickness is recommended for this large pitch (1.3mm) HDA.
FN8923 Rev.1.00
Aug 17, 2017
Page 23 of 57
ISL8277M
PMBus Command Summary
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
DEFAULT
SETTING
PAGE
01h
OPERATION
Sets Enable, Disable, and VOUT
Margin modes.
R/W BYTE
BIT
02h
ON_OFF_CONFIG
Configures the EN pin and PMBus
commands to turn the unit
ON/OFF.
R/W BYTE
BIT
03h
CLEAR_FAULTS
Clears fault indications.
SEND BYTE
29
15h
STORE_USER_ALL
Stores all PMBus values written
since last restore at user level.
SEND BYTE
29
16h
RESTORE_USER_ALL
Restores PMBus settings that
were stored using
STORE_USER_ALL.
SEND BYTE
29
20h
VOUT_MODE
Preset to defined data format of
VOUT commands.
READ BYTE
BIT
21h
VOUT_COMMAND
Sets the nominal value of the
output voltage.
R/W WORD
L16u
23h
VOUT_CAL_OFFSET
Applies a fixed offset voltage to
the VOUT_COMMAND.
R/W WORD
L16s
24h
VOUT_MAX
Sets the maximum possible value
of VOUT. 110% of pin-strap VOUT.
R/W WORD
25h
VOUT_MARGIN_HIGH
Sets the value of the VOUT during
a margin high.
26h
VOUT_MARGIN_LOW
27h
28
17h
28
Linear Mode,
Exponent = -13
29
Pin-strap
29
0V
30
L16u
1.1 * VOUT
Pin-strap
30
R/W WORD
L16u
1.05 * VOUT
Pin-strap
30
Sets the value of the VOUT during
a margin low.
R/W WORD
L16u
0.95 * VOUT
Pin-strap
30
VOUT_TRANSITION_RATE
Sets the transition rate during
margin or other change of VOUT.
R/W WORD
L11
BA00h
1V/ms
30
28h
VOUT_DROOP
Sets the loadline (V/I Slope)
resistance for the rail.
R/W WORD
L11
0000h
0mV/A
31
33h
FREQUENCY_SWITCH
Sets the switching frequency.
R/W WORD
L11
Pin-strap
31
37h
INTERLEAVE
Configures a phase offset
between devices sharing a SYNC
clock.
R/W WORD
BIT
Set based on
PMBus Address
31
38h
IOUT_CAL_GAIN
Sense resistance for inductor DCR
current sensing.
R/W WORD
L11
B380h
0.875mΩ
31
39h
IOUT_CAL_OFFSET
Sets the current-sense offset.
R/W WORD
L11
0000h
0A
31
40h
VOUT_OV_FAULT_LIMIT
Sets the VOUT overvoltage fault
threshold.
R/W WORD
L16u
1.15 * VOUT
Pin-strap
32
41h
VOUT_OV_FAULT_RESPONSE
Configures the VOUT overvoltage
fault response.
R/W BYTE
BIT
Disable and
No Retry
32
42h
VOUT_OV_WARN_LIMIT
Sets the VOUT overvoltage warn
threshold.
R/W WORD
L16u
1.10 * VOUT
Pin-strap
32
43h
VOUT_UV_WARN_LIMIT
Sets the VOUT undervoltage warn
threshold.
R/W WORD
L16u
0.9 * VOUT
Pin-Strap
32
44h
VOUT_UV_FAULT_LIMIT
Sets the VOUT undervoltage fault
threshold.
R/W WORD
L16u
0.85 * VOUT
Pin-strap
32
45h
VOUT_UV_FAULT_RESPONSE
Configures the VOUT undervoltage
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
33
46h
IOUT_OC_FAULT_LIMIT
Sets the IOUT average overcurrent
fault threshold.
R/W WORD
L11
DBC0h
30A
33
4Bh
IOUT_UC_FAULT_LIMIT
Sets the IOUT average
undercurrent fault threshold.
R/W WORD
L11
DC3Fh
-30A
33
4Fh
OT_FAULT_LIMIT
Sets the over-temperature fault
threshold.
R/W WORD
L11
EBE8h
+125°C
33
FN8923 Rev.1.00
Aug 17, 2017
13h
Hardware Enable,
Immediate Off
0000h
80h
Page 24 of 57
ISL8277M
PMBus Command Summary (Continued)
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
R/W BYTE
BIT
80h
50h
OT_FAULT_RESPONSE
Configures the over -temperature
fault response.
51h
OT_WARN_LIMIT
Sets the over-temperature
warning limit.
R/W WORD
L11
52h
UT_WARN_LIMIT
Sets the under-temperature
warning limit.
R/W WORD
53h
UT_FAULT_LIMIT
Sets the under-temperature fault
threshold.
54h
UT_FAULT_RESPONSE
Configures the
under-temperature fault
response.
55h
VIN_OV_FAULT_LIMIT
56h
DEFAULT
SETTING
PAGE
Disable and
No Retry
33
Eb70h
+110°C
34
L11
DC40h
-30°C
34
R/W WORD
L11
E530h
-45°C
34
R/W BYTE
BIT
80h
Disable and
No Retry
34
Sets the VIN overvoltage fault
threshold.
R/W WORD
L11
D3A0h
14.5V
34
VIN_OV_FAULT_RESPONSE
Configures the VIN overvoltage
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
35
57h
VIN_OV_WARN_LIMIT
Sets the input overvoltage
warning limit.
R/W WORD
L11
D343h
13.05V
35
58h
VIN_UV_WARN_LIMIT
Sets the input undervoltage
warning limit.
R/W WORD
L11
1.10*VIN
UV Fault Limit
35
59h
VIN_UV_FAULT_LIMIT
Sets the VIN undervoltage fault
threshold.
R/W WORD
L11
Pin-Strap
35
5Ah
VIN_UV_FAULT_RESPONSE
Configures the VIN undervoltage
fault response.
R/W BYTE
BIT
Disable and
No Retry
36
5Eh
POWER_GOOD_ON
Sets the voltage threshold for
Power-good indication.
R/W WORD
L16u
0.9*VOUT
Pin-strap
36
60h
TON_DELAY
Sets the delay time from ENABLE
to start of VOUT rise.
R/W WORD
L11
Pin-Strap
36
61h
TON_RISE
Sets the rise time of VOUT after
ENABLE and TON_DELAY.
R/W WORD
L11
Pin-Strap
36
64h
TOFF_DELAY
Sets the delay time from DISABLE
to start of VOUT fall.
R/W WORD
L11
Pin-Strap
36
65h
TOFF_FALL
Sets the fall time for VOUT after
DISABLE and TOFF_DELAY.
R/W WORD
L11
Pin-Strap
37
78h
STATUS_BYTE
Returns an abbreviated status for
fast reads.
READ BYTE
BIT
00h
No Faults
37
79h
STATUS_WORD
Returns information with a
summary of the unit's fault
condition.
READ WORD
BIT
0000h
No Faults
38
7Ah
STATUS_VOUT
Returns the VOUT specific status.
READ BYTE
BIT
00h
No Faults
38
7Bh
STATUS_IOUT
Returns the IOUT specific status.
READ BYTE
BIT
00h
No Faults
39
7Ch
STATUS_INPUT
Returns specific status specific to
the input.
READ BYTE
BIT
00h
No Faults
39
7Dh
STATUS_TEMP
Returns the temperature specific
status.
READ BYTE
BIT
00h
No Faults
39
7Eh
STATUS_CML
Returns the Communication,
Logic, and Memory specific
status.
READ BYTE
BIT
00h
No Faults
40
80h
STATUS_MFR_SPECIFIC
Returns the VMON and External
Sync clock specific status.
READ BYTE
BIT
00h
No Faults
40
80h
88h
READ_VIN
Returns the input voltage reading. READ WORD
L11
40
8Bh
READ_VOUT
Returns the output voltage
reading.
L16u
40
FN8923 Rev.1.00
Aug 17, 2017
READ WORD
Page 25 of 57
ISL8277M
PMBus Command Summary (Continued)
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
DEFAULT
SETTING
PAGE
8Ch
READ_IOUT
Returns the output current
reading.
READ WORD
L11
41
8Dh
READ_INTERNAL_TEMP
Returns the temperature reading
internal to the device.
READ WORD
L11
41
8Eh
READ_EXTERNAL_TEMP
Returns the temperature reading
from external monitor source.
READ WORD
L11
41
94h
READ_DUTY_CYCLE
Returns the duty cycle reading
during the ENABLE state.
READ WORD
L11
41
95h
READ_FREQUENCY
Returns the measured operating
switch frequency.
READ WORD
L11
41
99h
MFR_ID
Sets a user defined identification. R/W BLOCK
ASCII
Null
41
9Ah
MFR_MODEL
Sets a user defined model.
R/W BLOCK
ASCII
Null
42
9Bh
MFR_REVISION
Sets a user defined revision.
R/W BLOCK
ASCII
Null
42
9Ch
MFR_LOCATION
Sets a user defined location
identifier.
R/W BLOCK
ASCII
Null
42
9Dh
MFR_DATE
Sets a user defined date.
R/W BLOCK
ASCII
Null
42
9Eh
MFR_SERIAL
Sets a user defined serialized
identifier.
R/W BLOCK
ASCII
Null
42
A8h
LEGACY_FAULT_GROUP
Broadcast faults when mixed with
old generation modules
R/W BLOCK
BIT
B0h
USER_DATA_00
Sets a user defined data.
R/W BLOCK
ASCII
D0h
ISENSE_CONFIG
Configures ISENSE related
features.
R/W BYTE
BIT
D1h
USER_CONFIG
Configures several user-level
features.
R/W BYTE
D3h
DDC_CONFIG
Configures the DDC bus.
D4h
POWER_GOOD_DELAY
DFh
00000000h
43
Null
43
05h
256ns Blanking
Time, Mid Range
44
BIT
00h
Open-drain PG,
XTEMP Disabled
44
R/W BYTE
BIT
00h
Set based on
PMBus Address
45
Sets the delay between VOUT > PG
threshold and asserting the PG
pin.
R/W WORD
L11
CA00h
4ms
45
ASCR_CONFIG
Configures ASCR control loop.
R/W BLOCK
CUS
Pin-Strap
45
E0h
SEQUENCE
Identifies the Rail DDC ID to
perform multi-rail sequencing.
R/W WORD
BIT
0000h
Prequel and
Sequel Disabled
46
E2h
DDC_GROUP
Sets rail DDC IDs to obey faults
and margining spreading
information.
R/W BLOCK
BIT
000000h
Broadcast
Disabled
46
E4h
DEVICE_ID
Returns the 16-byte (character)
device identifier string.
READ
BLOCK
ASCII
Reads Device
Version
47
E5h
MFR_IOUT_OC_FAULT_RESPONSE
Configures the IOUT overcurrent
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
47
E6h
MFR_IOUT_UC_FAULT_RESPONSE
Configures the IOUT undercurrent
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
47
E9h
SYNC_CONFIG
Configures the Sync pin.
R/W BYTE
BIT
00h
EAh
SNAPSHOT
Returns 32-byte read-back of
parametric and status values.
READ
BLOCK
BIT
EBh
BLANK_PARAMS
Returns recently changed
parameter values.
READ
BLOCK
BIT
F3h
SNAPSHOT_CONTROL
Snapshot feature control
command.
W BYTE
BIT
F4h
RESTORE_FACTORY
Restores device to the factory
default values.
WRITE
BLOCK
FN8923 Rev.1.00
Aug 17, 2017
47
48
FF…FFh
48
48
49
Page 26 of 57
ISL8277M
PMBus Command Summary (Continued)
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
DEFAULT
SETTING
PAGE
F5h
MFR_VMON_OV_FAULT_LIMIT
Returns the VMON overvoltage
threshold.
READ WORD
L11
CB00h
6V
49
F6h
MFR_VMON_UV_FAULT_LIMIT
Returns the VMON undervoltage
threshold.
READ WORD
L11
CA00h
4V
49
F7h
MFR_READ_VMON
READ WORD
Returns the VMON voltage
reading. VMON is used to monitor
VDRVOUT (Pin 8) voltage through
an internal 16:1 resistor divider.
L11
F8h
VMON_OV_FAULT_RESPONSE
Returns the VMON overvoltage
response.
READ BYTE
BIT
80h
Disable and
No Retry
49
F9h
VMON_OV_FAULT_RESPONSE
Returns the VMON undervoltage
response.
READ BYTE
BIT
80h
Disable and
No Retry
49
49
PMBus Data Formats
Linear-11 (L11)
L11 data format uses 5-bit two’s compliment exponent (N) and 11-bit two’s compliment mantissa (Y) to represent real world decimal
value (X).
Data Byte High
7 6 5 4 3 2 1 0
Exponent (N)
Data Byte Low
7 6 5 4 3 2 1 0
Mantissa (Y)
Relation between real world decimal value (X), N and Y is: X = Y · 2N
Linear-16 Unsigned (L16u)
The L16u data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit unsigned integer mantissa (Y) to represent real world
decimal value (X). Relation between real world decimal value (X), N and Y is: X = Y · 2-13
Linear-16 Signed (L16s)
The L16s data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit two’s compliment mantissa (Y) to represent real
world decimal value (X).
Relation between real world decimal value (X), N, and Y is: X = Y · 2-13
Bit Field (BIT)
A break down of Bit Field is provided in PMBus on “PMBus Command Descriptions” on page 28.
Custom (CUS)
A break down of custom data format is provided in PMBus “PMBus Command Descriptions” on page 28. A combination of Bit Field and
integer are common type of custom data format.
ASCII (ASC)
A variable length string of text characters that uses the ASCII data format.
FN8923 Rev.1.00
Aug 17, 2017
Page 27 of 57
ISL8277M
PMBus Use Guidelines
The PMBus is a powerful tool that allows the user to optimize circuit performance by configuring devices for their application. When
configuring a device in a circuit, the device should be disabled whenever most settings are changed with PMBus commands. Some
exceptions to this recommendation are OPERATION, ON_OFF_CONFIG, CLEAR_FAULTS, VOUT_COMMAND, VOUT_MARGIN_HIGH,
VOUT_MARGIN_LOW, and ASCCR_CONFIG. Any command can be read while the device is enabled. Many commands do not take effect
until after the device has been re-enabled, hence the recommendation that commands that change device settings are written while
the device is disabled.
When sending the STORE_DEFAULT_ALL, STORE_USER_ALL, RESTORE_DEFAULT_ALL, and RESTORE_USER_ALL commands, it is
recommended that no other commands are sent to the device for 100ms after sending STORE or RESTORE commands.
In addition, there should be a 2ms delay between repeated READ commands sent to the same device. When sending any other
command, a 5ms delay is recommended between repeated commands sent to the same device.
Summary
All commands can be read at any time.
Always disable the device when writing commands that change device settings. Exceptions to this rule are commands intended to be
written while the device is enabled, for example, VOUT_MARGIN_HIGH.
To be sure a change to a device setting has taken effect, write the STORE_USER_ALL command, then cycle input power and re-enable.
PMBus Command Descriptions
OPERATION (01h)
Definition: Sets Enable, Disable, and VOUT Margin settings. Data values of OPERATION that force margin high or low only take effect
when the MGN pin is left open (i.e., in the NOMINAL margin state).
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value:
Units: N/A
SETTINGS
ACTIONS
04h
Immediate off (no sequencing)
44h
Soft off (with sequencing)
84h
On - Nominal
94h
On - Margin low
A4h
On - Margin high
ON_OFF_CONFIG (02h)
Definition: Configures the interpretation and coordination of the OPERATION command and the ENABLE pin (EN).
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 17h (Device starts from ENABLE pin with immediate off)
Units: N/A
SETTINGS
ACTIONS
00h
Device starts any time power is present regardless of ENABLE pin or OPERATION command states.
16h
Device starts from ENABLE pin with soft off.
17h
Device starts from ENABLE pin with immediate off.
1Ah
Device starts from OPERATION command.
FN8923 Rev.1.00
Aug 17, 2017
Page 28 of 57
ISL8277M
CLEAR_FAULTS (03h)
Definition: Clears all fault bits in all registers and releases the SALRT pin (if asserted) simultaneously. If a fault condition still exists, the
bit will reassert immediately. This command will not restart a device if it has shut down, it will only clear the faults.
Data Length in Bytes: 0 Byte
Data Format: N/A
Type: Send only
Default Value: N/A
Units: N/A
Reference: N/A
STORE_USER_ALL (15h)
Definition: Stores all PMBus settings from the operating memory to the nonvolatile USER store memory. To clear the USER store,
perform a RESTORE_FACTORY then STORE_USER_ALL. To add to the USER store, perform a RESTORE_USER_ALL, write commands to
be added, then STORE_USER_ALL. This command can be used during device operation, but the device will be unresponsive for 20ms
while storing values.
Data Length in Bytes: 0
Data Format: N/A
Type: Send only
Default Value: N/A
Units: N/A
RESTORE_USER_ALL (16h)
Definition: Restores all PMBus settings from the USER store memory to the operating memory. Command performed at power-up.
Security level is changed to Level 1 following this command. This command can be used during device operation, but the device will be
unresponsive for 20ms while storing values.
Data Length in Bytes: 0
Data Format: N/A
Type: Send only
Default Value: N/A
Units: N/A
VOUT_MODE (20h)
Definition: Reports the VOUT mode and provides the exponent used in calculating several VOUT settings. Fixed with linear mode with
default exponent (N) = -13
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default Value: 13h (Linear Mode, N = -13)
Units: N/A
VOUT_COMMAND (21h)
Definition: Sets or reports the target output voltage. This command cannot set a value higher than either VOUT_MAX or 110% of the pinstrap VOUT setting.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: Pin-strap setting
Units: Volts
Range: 0V to VOUT_MAX
FN8923 Rev.1.00
Aug 17, 2017
Page 29 of 57
ISL8277M
VOUT_CAL_OFFSET (23h)
Definition: Applies a fixed offset voltage to the output voltage command value. This command is typically used by the user to calibrate
a device in the application circuit.
Data Length in Bytes: 2
Data Format: L16s
Type: R/W
Default Value: 0000h
Units: Volts
VOUT_MAX (24h)
Definition: Sets an upper limit on the output voltage the unit can command regardless of any other commands or combinations. The
intent of this command is to provide a safeguard against a user accidentally setting the output voltage to a possibly destructive level
rather than to be the primary output overprotection. Default value can be changed via PMBus.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 1.10xVOUT_COMMAND pin--strap setting
Units: Volts
Range: 0V to 6V
VOUT_MARGIN_HIGH (25h)
Definition: Sets the value of the VOUT during a margin high. This VOUT_MARGIN_HIGH command loads the unit with the voltage to
which the output is to be changed when the OPERATION command is set to “Margin High”.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W word
Default value: 1.05 x VOUT_COMMAND pin-strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_MARGIN_LOW (26h)
Definition: Sets the value of the VOUT during a margin low. This VOUT_MARGIN_LOW command loads the unit with the voltage to which
the output is to be changed when the OPERATION command is set to “Margin Low”.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default value: 0.95 x VOUT_COMMAND pin-strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_TRANSITION_RATE (27h)
Definition: Sets the rate at which the output should change voltage when the device receives an OPERATION command (Margin High,
Margin Low) that causes the output voltage to change. The maximum possible positive value of the two data bytes indicates that the
device should make the transition as quickly as possible.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default value: BA00h (1.0 V/ms)
Units: V/ms
Range: 0.1 to 4V/ms
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ISL8277M
VOUT_DROOP (28h)
Definition: Sets the effective load line (V/I slope) for the rail in which the device is used. It is the rate, in mV/A, at which the output
voltage decreases (or increases) with increasing (or decreasing) output current for use with Adaptive Voltage Positioning schemes.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default value: 0000h (0mV/A)
Units: mV/A
Range: 0 to 40mV/A
FREQUENCY_SWITCH (33h)
Definition: Sets the switching frequency of the device. Initial default value is defined by a pin-strap and this value can be overridden by
writing this command via PMBus. If an external SYNC is utilized, this value should be set as close as possible to the external clock value.
The output must be disabled when writing this command.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin-strap setting
Units: kHz
Range: 300kHz to 1066MHz
INTERLEAVE (37h)
Definition: Configures the phase offset of a device that is sharing a common SYNC clock with other devices. A value of 0 for the number
in group field is interpreted as 16 to allow for phase spreading groups of up to 16 devices.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Default Value: Pin-strap setting
Units: kHz
BITS
PURPOSE
VALUE
15:2
Reserved
0
DESCRIPTION
11:8
Group Number
0 to 15
Sets a number to a group of interleaved rails
7:4
Number in Group
0 to 15
Sets the number of rails in the group A value of 0 is interpreted as 16
3:0
Position in Group
0 to 15
Sets position of the device's rail within the group
Reserved
IOUT_CAL_GAIN (38h)
Definition: Sets the effective impedance across the current sense circuit for use in calculating output current at +25°C.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: B380h (0.875mΩ)
Units: mΩ
IOUT_CAL_OFFSET (39h)
Definition: Used to null out any offsets in the output current-sensing circuit, and to compensate for delayed measurements of current
ramp due to Isense blanking time.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: 0000h (0A)
Units: A
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ISL8277M
VOUT_OV_FAULT_LIMIT (40h)
Definition: Sets the VOUT overvoltage fault threshold.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 1.15xVOUT_COMMAND pin-strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_OV_FAULT_RESPONSE (41h)
Definition: Configures the VOUT overvoltage fault response. Note that the device cannot be set to ignore this fault mode.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units: N/A
SETTINGS
ACTIONS
80h
Disable with no retry
BFh
Disable and continuous retry with 70ms delay
VOUT_OV_WARNING_LIMIT (42h)
Definition: Sets the VOUT overvoltage wring threshold. Power-good signal is pulled low when output voltage goes higher than this
threshold.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 1.1xVOUT_COMMAND pin-strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_UV_WARNING_LIMIT (43h)
Definition: Sets the VOUT undervoltage warning threshold. Power-good signal is pulled low when output voltage goes lower than this
threshold.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 0.9xVOUT_COMMAND pin-strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_UV_FAULT_LIMIT (44h)
Definition: Sets the VOUT undervoltage fault threshold. This fault is masked during ramp or when disabled.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 0.85xVOUT_COMMAND pin-strap setting
Units: V
Range: 0V to VOUT_MAX
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ISL8277M
VOUT_UV_FAULT_RESPONSE (45h)
Definition: Configures the VOUT undervoltage fault response.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable, no retry)
Units: N/A
SETTINGS
ACTIONS
80h
Disable with no retry
BFh
Disable and continuous retry with 70ms delay
IOUT_OC_FAULT_LIMIT (46h)
Definition: Sets the IOUT average overcurrent fault threshold. Device will automatically calculate peak inductor overcurrent fault limit.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: DBC0h 30A
Units: A
Range: -100 to 100A
IOUT_UC_FAULT_LIMIT (4Bh)
Definition: Sets the IOUT average undercurrent fault threshold. Device will automatically calculate valley inductor undercurrent fault limit.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: DC3Fh -30A
Units: A
Range: -100 to 100A
OT_FAULT_LIMIT (4Fh)
Definition: Sets the temperature at which the device should indicate an over-temperature fault. Note that the temperature must drop
below OT_WARN_LIMIT to clear this fault.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: EBE8h (+125˚C)
Units: Celsius
Range: 0°C to +175°C
OT_FAULT_RESPONSE (50h)
Definition: Instructs the device on what action to take in response to an over-temperature fault.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Fault Value: 80h (Disable and no retry)
Units: N/A
SETTINGS
FN8923 Rev.1.00
Aug 17, 2017
ACTIONS
80h
Disable with no retry
BFh
Disable and continuous retry with 70ms delay
Page 33 of 57
ISL8277M
OT_WARN_LIMIT (51h)
Definition: Sets the temperature at which the device should indicate an over-temperature warning alarm. In response to the
OT_WARN_LIMIT being exceeded, the device: Sets the TEMPERATURE bit in STATUS_WORD, sets the OT_WARNING bit in
STATUS_TEMPERATURE, and notifies the host.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: EB70h (+110°C)
Units: Celsius
Range: 0°C to +175°C
UT_WARN_LIMIT (52h)
Definition: Sets the temperature at which the device should indicate an under-temperature warning alarm. In response to the
UT_WARN_LIMIT being exceeded, the device: Sets the TEMPERATURE bit in STATUS_WORD, sets the UT_WARNING bit in
STATUS_TEMPERATURE, and notifies the host.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: DC40h (-30°C)
Units: Celsius
Range: -55°C to +25°C
UT_FAULT_LIMIT (53h)
Definition: Sets the temperature, in degrees Celsius, of the unit where it should indicate an under-temperature fault. Note that the
temperature must rise above UT_WARN_LIMIT to clear this fault.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: E530h (-45°C)
Units: Celsius
Range: -55°C to +25°C
UT_FAULT_RESPONSE (54h)
Definition: Configures the under-temperature fault response as defined by the following table. The delay time is the time between
restart attempts.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable, no retry)
Units: N/A
SETTINGS
ACTIONS
80h
Disable with no retry
BFh
Disable and continuous retry with 70ms delay
VIN_OV_FAULT_LIMIT (55h)
Definition: Sets the VIN overvoltage fault threshold.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: D3A0h (14.5V)
Units: V
Range: 0V to 16V
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ISL8277M
VIN_OV_FAULT_RESPONSE (56h)
Definition: Configures the VIN overvoltage fault response as defined by the following table. The delay time is the time between restart
attempts.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units: N/A
SETTINGS
ACTIONS
80h
Disable with no retry
BFh
Disable and continuous retry with 70ms delay
VIN_OV_WARN_LIMIT (57h)
Definition: Sets the VIN overvoltage warning threshold as defined by the table below. In response to the OV_WARN_LIMIT being
exceeded, the device: Sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD, sets the VIN_OV_WARNING bit in STATUS_INPUT,
and notifies the host.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Protectable: Yes
Default Value: D343h (13.05V)
Units: V
Range: 0V to 16V
VIN_UV_WARN_LIMIT (58h)
Definition: Sets the VIN undervoltage warning threshold. If a VIN_UV_FAULT occurs, the input voltage must rise above
VIN_UV_WARN_LIMIT to clear the fault, which provides hysteresis to the fault threshold. In response to the UV_WARN_LIMIT being
exceeded, the device: Sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD, sets the VIN_UV_WARNING bit in STATUS_INPUT,
and notifies the host.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Default Value: 1.1 x VIN_UV_FAULT_LIMIT pin-strap setting
Units: V
Range: 0V to 12V
VIN_UV_FAULT_LIMIT (59h)
Definition: Sets the VIN undervoltage fault threshold.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin-strap setting
Units: V
Range: 0V to 12V
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ISL8277M
VIN_UV_FAULT_RESPONSE (5Ah)
Definition: Configures the VIN undervoltage fault response as defined by the following table. The delay time is the time between restart
attempts.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units: N/A
SETTINGS
ACTIONS
80h
Disable with no retry
BFh
Disable and continuous retry with 70ms delay
POWER_GOOD_ON (5Eh)
Definition: Sets the voltage threshold for Power-good indication. Power-good asserts when the output voltage exceeds
POWER_GOOD_ON and de-asserts when the output voltage is less than VOUT_UV_FAULT_LIMIT.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 0.9xVOUT_COMMAND pin-strap setting
Units: V
TON_DELAY (60h)
Definition: Sets the delay time from when the device is enabled to the start of VOUT rise.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: CA80h, 5 ms
Units: ms
Range: 0 to 500ms
TON_RISE (61h)
Definition: Sets the rise time of VOUT after ENABLE and TON_DELAY.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: CA80h, 5 ms
Units: ms
Range: 0 to 200ms
TOFF_DELAY (64h)
Definition: Sets the delay time from DISABLE to start of VOUT fall.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: CA80h, 5 ms
Units: ms
Range: 0 to 500 seconds
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ISL8277M
TOFF_FALL (65h)
Definition: Sets the fall time for VOUT after DISABLE and TOFF_DELAY.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: CA80h, 5 ms
Units: ms
Range: 0 to 200ms
STATUS_BYTE (78h)
Definition: Returns one byte of information with a summary of the most critical faults.
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
7
BUSY
MEANING
6
OFF
5
VOUT_OV_FAULT
An output overvoltage fault has occurred.
4
IOUT_OC_FAULT
An output overcurrent fault has occurred.
A fault was declared because the device was busy and unable to respond.
This bit is asserted if the unit is not providing power to the output, regardless of
the reason, including simply not being enabled.
3
VIN_UV_FAULT
An input undervoltage fault has occurred.
2
TEMPERATURE
A temperature fault or warning has occurred.
1
CML
0
NONE OF THE ABOVE
FN8923 Rev.1.00
Aug 17, 2017
A communications, memory, or logic fault has occurred.
A fault or warning not listed in Bits 7:1 has occurred.
Page 37 of 57
ISL8277M
STATUS_WORD (79h)
Definition: Returns two bytes of information with a summary of the unit's fault condition. Based on the information in these bytes, the
host can get more information by reading the appropriate status registers. The low byte of the STATUS_WORD is the same register as
the STATUS_BYTE (78h) command.
Data Length in Bytes: 2
Data Format: BIT
Type: Read only
Default Value: 0000h
Units: N/A
BIT NUMBER
STATUS BIT NAME
15
VOUT
14
IOUT/POUT
13
INPUT
12
MFG_SPECIFIC
11
POWER_GOOD#
10
FANS
MEANING
An output voltage fault or warning has occurred.
An output current or output power fault or warning has occurred.
An input voltage, input current, or input power fault or warning has occurred.
A manufacturer specific fault or warning has occurred.
The POWER_GOOD signal, if present, is negated.
A fan or airflow fault or warning has occurred.
9
OTHER
8
UNKNOWN
A bit in STATUS_OTHER is set.
7
BUSY
6
OFF
5
VOUT_OV_FAULT
4
IOUT_OC_FAULT
An output overcurrent fault has occurred.
3
VIN_UV_FAULT
An input undervoltage fault has occurred.
2
TEMPERATURE
A temperature fault or warning has occurred.
1
CML
0
NONE OF THE ABOVE
A fault type not given in Bits 15:1 of the STATUS_WORD has been detected.
A fault was declared because the device was busy and unable to respond.
This bit is asserted if the unit is not providing power to the output, regardless of
the reason, including simply not being enabled.
An output overvoltage fault has occurred.
A communications, memory or logic fault has occurred.
A fault or warning not listed in Bits 7:1 has occurred.
STATUS_VOUT (7Ah)
Definition: Returns one data byte with the status of the output voltage.
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
7
VOUT_OV_FAULT
6
VOUT_OV_WARNING
Indicates an output overvoltage warning.
5
VOUT_UV_WARNING
Indicates an output undervoltage warning.
4
VOUT_UV_FAULT
3:0
N/A
FN8923 Rev.1.00
Aug 17, 2017
MEANING
Indicates an output overvoltage fault.
Indicates an output undervoltage fault.
These bits are not used.
Page 38 of 57
ISL8277M
STATUS_IOUT (7Bh)
Definition: Returns one data byte with the status of the output current.
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
MEANING
7
IOUT_OC_FAULT
6
IOUT_OC_LV_FAULT
An output overcurrent and low voltage fault has occurred.
An output overcurrent fault has occurred.
5
IOUT_OC_WARNING
An output overcurrent warning has occurred.
4
IOUT_UC_FAULT
3:0
N/A
An output undercurrent fault has occurred.
These bits are not used.
STATUS_INPUT (7Ch)
Definition: Returns input voltage and input current status information.
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
7
VIN_OV_FAULT
MEANING
6
VIN_OV_WARNING
An input overvoltage warning has occurred.
5
VIN_UV_WARNING
An input undervoltage warning has occurred.
4
VIN_UV_FAULT
3:0
N/A
An input overvoltage fault has occurred.
An input undervoltage fault has occurred.
These bits are not used.
STATUS_TEMP (7Dh)
Definition: Returns one byte of information with a summary of any temperature related faults or warnings.
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
MEANING
7
OT_FAULT
6
OT_WARNING
An over-temperature warning has occurred.
5
UT_WARNING
An under-temperature warning has occurred.
4
UT_FAULT
3:0
N/A
FN8923 Rev.1.00
Aug 17, 2017
An over-temperature fault has occurred.
An under-temperature fault has occurred.
These bits are not used.
Page 39 of 57
ISL8277M
STATUS_CML (7Eh)
Definition: Returns one byte of information with a summary of any Communications, Logic, and/or Memory errors.
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default Value: 00h
Units: N/A
BIT NUMBER
MEANING
7
Invalid or unsupported PMBus command was received.
6
The PMBus command was sent with invalid or unsupported data.
5
4:2
Packet error was detected in the PMBus command.
Not used.
1
A PMBus command tried to write to a Read only or protected command, or a communication fault other than the ones listed
in this table has occurred.
0
Not used.
STATUS_MFR_SPECIFIC (80h)
Definition: Returns one byte of information providing the status of the device's voltage monitoring and clock synchronization faults.
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default value: 00h
Units: N/A
BIT NUMBER
FIELD NAME
7:6
Reserved
MEANING
5
VMON UV Warning
The voltage on the VDRVOUT pin has dropped below 4.4V.
4
VMON OV Warning
The voltage on the VDRVOUT pin has risen above 5.5V.
3
External Switching Period Fault
2
Reserved
1
VMON UV Fault
The voltage on the VMON pin has dropped below the level set by
VMON_UV_FAULT.
0
VMON OV Fault
The voltage on the VMON pin has risen above the level set by VMON_OV_FAULT.
Loss of external clock synchronization has occurred.
READ_VIN (88h)
Definition: Returns the input voltage reading.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Units: V
READ_VOUT (8Bh)
Definition: Returns the output voltage reading.
Data Length in Bytes: 2
Data Format: L16u
Type: Read only
Units: V
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ISL8277M
READ_IOUT (8Ch)
Definition: Returns the output current reading.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Default Value: N/A
Units: A
READ_INTERNAL_TEMP (8Dh)
Definition: Returns the controller junction temperature reading from internal temperature sensor.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Units: °C
READ_EXTERNAL_TEMP (8Eh)
Definition: Returns the temperature reading from the external temperature device connected to XTEMP pins.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Units: °C
READ_DUTY_CYCLE (94h)
Definition: Reports the actual duty cycle of the converter during the enable state.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Units: %
READ_FREQUENCY (95h)
Definition: Reports the actual switching frequency of the converter during the enable state.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Units: kHz
MFR_ID (99h)
Definition: Sets user defined identification. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION, MFR_LOCATION,
MFR_DATE, MFR_SERIAL, and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This limitation includes
multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this command, then
perform a STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASCII
Type: Block R/W
Default Value: null
Units: N/A
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ISL8277M
MFR_MODEL (9Ah)
Definition: Sets a user defined model. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION, MFR_LOCATION,
MFR_DATE, MFR_SERIAL, and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This limitation includes
multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this command, then
perform a STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASCII
Type: Block R/W
Default Value: null
Units: N/A
MFR_REVISION (9Bh)
Definition: Sets a user defined revision. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION, MFR_LOCATION,
MFR_DATE, MFR_SERIAL, and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This limitation includes
multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this command, then
perform a STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASCII
Type: Block R/W
Default Value: null
Units: N/A
MFR_LOCATION (9Ch)
Definition: Sets a user defined location identifier. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL, and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then, perform a STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASCII
Type: Block R/W
Default Value: null
Units: N/A
MFR_DATE (9Dh)
Definition: Sets a user defined date. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE,
MFR_SERIAL, and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This limitation includes multiple writes
of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this command, then perform a
STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASCII
Type: Block R/W
Default Value: null
Units: N/A
Reference: N/A
MFR_SERIAL (9Eh)
Definition: Sets a user defined serialized identifier. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL, and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command, then perform a STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASCII
Type: Block R/W
Default Value: null
Units: N/A
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ISL8277M
LEGACY_FAULT_GROUP (A8h)
Definition: This command is used only when the power system is created by mixing the ISL8277M module with old generation digital
modules (ZL9101M, ZL9117M, ZL9006M, ZL9010M) to power various rails. This command provides an ability to power down the
system by broadcast faults between old and new generation digital modules.
New generation module uses group ID to broadcast faults between each other. Refer to DDC_GROUP(E2h) command. Old generation
module uses rail ID to broadcast fault. When new and old modules are mixed, ISL8277M can use GROUP-ID (new generation module)
and/or RAIL-ID (old generation module) to execute shutdown as response to fault to selected GROUP_ID or RAIL-ID. A module can listen
to multiple RAIL-IDs by writing 1 to a bit location representing RAIL-ID of old generation modules.
NOTE; Bit-5 in DDC_GROUP command should be programmed 1 to activate fault broadcast.
Data length in Bytes: 4
Data Format: BIT
Type: R/W Block
Default Value: 00000000h
Units: N/A
BIT
DESCRIPTION
BIT
DESCRIPTION
BIT
DESCRIPTION
BIT
DESCRIPTION
31
Listen to Rail-31
23
Listen to Rail-23
15
Listen to Rail-15
7
Listen to Rail-7
30
Listen to Rail-30
22
Listen to Rail-22
14
Listen to Rail-14
6
Listen to Rail-6
29
Listen to Rail-29
21
Listen to Rail-21
13
Listen to Rail-13
5
Listen to Rail-5
28
Listen to Rail-28
20
Listen to Rail-20
12
Listen to Rail-12
4
Listen to Rail-4
27
Listen to Rail-27
19
Listen to Rail-19
11
Listen to Rail-11
3
Listen to Rail-3
26
Listen to Rail-26
18
Listen to Rail-18
10
Listen to Rail-10
2
Listen to Rail-2
25
Listen to Rail-25
17
Listen to Rail-17
9
Listen to Rail-9
1
Listen to Rail-1
24
Listen to Rail-24
16
Listen to Rail-16
8
Listen to Rail-8
0
Listen to Rail-0
USER_DATA_00 (B0h)
Definition: Sets a user defined data. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE,
MFR_SERIAL, and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This limitation includes multiple writes
of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this command then perform a
STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASCII
Type: Block R/W
Default Value: null
Units: N/A
FN8923 Rev.1.00
Aug 17, 2017
Page 43 of 57
ISL8277M
ISENSE_CONFIG (D0h)
Definition: Configures current sense circuitry.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W byte
Default Value: 05h
Units: N/A
BIT
FIELD NAME
VALUE
7:4
Reserved
000
3:2
Current Sense
Blanking Time
00
192ns
01
256ns
10
412ns
1:0
Current Sense Range
SETTING
11
640ns
00
Low Range
DESCRIPTION
Sets the blanking time current sense blanking time.
±25mV
01
Mid Range
±35mV
10
High Range
±50mV
11
Not Used
USER_CONFIG (D1h)
Definition: Configures several user-level features. This command overrides the CONFIG pin settings.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W byte
Default Value: 00h
Units: N/A
BIT
FIELD NAME
VALUE
SETTING
7:5
Reserved
0
4:3
Ramp-Up and
Ramp-Down Minimum
Duty Cycle
00
0.39%
01
0.78%
2
1
0
10
1.17%
11
1.56%
Minimum Duty Cycle
Control
0
Disable
1
Enable
Power-Good Pin
Configuration
0
Open Drain
1
Push-Pull
0
Disable
1
Enable
XTEMP Enable
FN8923 Rev.1.00
Aug 17, 2017
DESCRIPTION
Reserved
Sets the minimum duty-cycle during start-up and shutdown ramp.
Must be enabled with Bit 10.
Control for minimum duty cycle.
0 = PG is an open-drain output.
1 = PG is a push-pull output.
Enable external temperature monitoring.
Page 44 of 57
ISL8277M
DDC_CONFIG (D3h)
Definition: Configures DDC addressing.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 00h
Units: N/A
BIT
FIELD NAME
VALUE
SETTING
7:5
4:0
Reserved
00
Reserved
Rail ID
0 to 31 (00 to 1Fh)
0
DESCRIPTION
Reserved
Configures DDC address
POWER_GOOD_DELAY (D4h)
Definition: Sets the delay applied between the output exceeding the PG threshold (POWER_GOOD_ON) and asserting the PG pin. The
delay time can range from 0ms up to 500s, in steps of 125ns. A 1ms minimum configured value is recommended to apply proper
de-bounce to this signal.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: 4ms
Units: ms
Range: 0 to 5s
ASCR_CONFIG (DFh)
Definition: Allows user configuration of ASCR settings.
Data Length in Bytes: 4
Data Format: CUS
Type: R/W
Default Value: 015A0100h
BIT
PURPOSE
31:25
Unused
24
ASCCR Enable
DATA FORMAT
BIT
23:16
ASCR Residual Setting
Integer
15:0
ASCR Gain Setting
Integer
FN8923 Rev.1.00
Aug 17, 2017
VALUE
0000000h
DESCRIPTION
Unused
1
Enable
0
Disable
Page 45 of 57
ISL8277M
SEQUENCE (E0h)
Definition: Identifies the Rail DDC ID of the prequel and sequel rails when performing multi-rail sequencing. The device will enable its
output when its EN or OPERATION enable states, as defined by ON_OFF_CONFIG, are set and the prequel device has issued a
Power-good event on the DDC bus. The device will disable its output (using the programmed delay values) when the sequel device has
issued a Power-down event on the DDC bus.
The data field is a two-byte value. The most significant byte contains the 5-bit Rail DDC ID of the prequel device. The least significant
byte contains the 5-bit Rail DDC ID of the sequel device. The most significant bit of each byte contains the enable of the prequel or
sequel mode. This command overrides the corresponding sequence configuration set by the CONFIG pin settings.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Default Value: 0000h (Prequel and Sequel disabled)
BIT
FIELD NAME
15
Prequel Enable
VALUE
SETTING
DESCRIPTION
0
Disable
Disable, no prequel preceding this rail.
1
Enable
Enable, prequel to this rail is defined by Bits 12:8.
14:13
Reserved
0
Reserved
12:8
Prequel Rail DDC ID
0-31
DDC ID
7
Sequel Enable
Reserved
Set to the DDC ID of the prequel rail.
0
Disable
Disable, no sequel following this rail.
1
Enable
Enable, sequel to this rail is defined by Bits 4:0.
6:5
Reserved
0
Reserved
4:0
Sequel Rail DDC ID
0-31
DDC ID
Reserved
Set to the DDC ID of the sequel rail.
DDC_GROUP (E2h)
Definition: Configures fault spreading group ID and enable, broadcast OPERATION group ID and enable, and broadcast
VOUT_COMMAND group ID and enable.
Data Length in Bytes: 3
Data Format: BIT
Type: R/W
Default Value: 000000h (Ignore BROADCAST VOUT_COMMAND and OPERATION, Sequence shutdown on POWER_FAIL event)
BITS
23:22
21
PURPOSE
Reserved
BROADCAST_VOUT_COMMAND Response
VALUE
0
DESCRIPTION
Reserved
1
Responds to BROADCAST_VOUT_COMMAND with same Group ID.
0
Ignores BROADCAST_VOUT_COMMAND.
20:16
BROADCAST_VOUT_COMMAND Group ID
15:14
Reserved
0
Reserved
BROADCAST_OPERATION Response
1
Responds to BROADCAST_OPERATION with same Group ID.
0
Ignores BROADCAST_OPERATION.
13
12:8
7:6
BROADCAST_OPERATION Group ID
0-31d
0-31d
Group ID sent as data for broadcast BROADCAST_VOUT_COMMAND events.
Group ID sent as data for broadcast BROADCAST_OPERATION events.
Reserved
0
Reserved
5
POWER_FAIL Response
1
Responds to POWER_FAIL events with same Group ID by shutting down
immediately.
4:0
POWER_FAIL group ID
0-31d
0
FN8923 Rev.1.00
Aug 17, 2017
Responds to POWER_FAIL events with same Group ID with sequenced shutdown.
Group ID sent as data for broadcast POWER_FAIL events.
Page 46 of 57
ISL8277M
DEVICE_ID (E4h)
Definition: Returns the 16-byte (character) device identifier string.
Data Length in Bytes: 16
Data Format: ASCII
Type: Block Read
Default Value: Part number/Die revision/Firmware revision
MFR_IOUT_OC_FAULT_RESPONSE (E5h)
Definition: Configures the IOUT overcurrent fault response as defined by the following table. The command format is the same as the
PMBus standard fault responses except that it sets the overcurrent status bit in STATUS_IOUT.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable, and no retry)
Units: N/A
SETTINGS
ACTIONS
80h
Disable with no retry.
BFh
Disable and continuous retry with 70ms delay.
MFR_IOUT_UC_FAULT_RESPONSE (E6h)
Definition: Configures the IOUT undercurrent fault response as defined by the following table. The command format is the same as the
PMBus standard fault responses except that it sets the undercurrent status bit in STATUS_IOUT.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units: N/A
SETTINGS
ACTIONS
80h
Disable with no retry.
BFh
Disable and continuous retry with 70ms delay.
SYNC_CONFIG (E9h)
Definition: Sets options for SYNC output configurations.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Default Value: 00h
SETTINGS
00h
FN8923 Rev.1.00
Aug 17, 2017
ACTIONS
Use internal clock. Clock frequency is set by pin-strap or PMBus command.
02h
Use internal clock and output internal clock.
04h
Use external clock.
Page 47 of 57
ISL8277M
SNAPSHOT (EAh)
Definition: A 32-byte read-back of parametric and status values. It allows monitoring and status data to be stored to flash following a
fault condition. In case of a fault, the most recently updated values are stored to the flash memory. When SNAPSHOT STATUS byte 22 is
set stored, the device will no longer automatically capture parametric and status values following a fault until stored data are erased.
Use the SNAPSHOT_CONTROL command to erase stored data and clear the status bit before the next ramp up. Data erased is not
allowed when the module is enabled.
Data Length in Bytes: 32
Data Format: Bit field
Type: Block Read
BYTE NUMBER
31:23
VALUE
PMBUS COMMAND
FORMAT
Reserved
Reserved
00h
22
Flash Memory Status Byte
FF - Not Stored
00 - Stored
N/A
BIT
21
Manufacturer Specific Status Byte
STATUS_MFR_SPECIFIC (80h)
Byte
20
CML Status Byte
STATUS_CML (7Eh)
Byte
19
Temperature Status Byte
STATUS_TEMPERATURE (7Dh)
Byte
18
Input Status Byte
STATUS_INPUT (7Ch)
Byte
17
IOUT Status Byte
STATUS_IOUT (7Bh)
Byte
16
VOUT Status Byte
STATUS_VOUT (7Ah)
Byte
15:14
Switching Frequency
READ_FREQUENCY (95h)
L11
13:12
External Temperature
READ_EXTERNAL_TEMP (8Eh)
L11
11:10
Internal Temperature
READ_INTERNAL_TEMP (8Dh)
L11
9:8
Duty Cycle
READ_DUTY_CYCLE (94h)
L11
7:6
Highest Measured Output Current
N/A
L11
5:4
Output Current
READ_IOUT (8Ch)
L11
3:2
Output Voltage
READ_VOUT (8Bh)
L16u
1:0
Input Voltage
READ_VIN (88h)
L11
BLANK_PARAMS (EBh)
Definition: Returns a 16-byte string indicating which parameter values were either retrieved by the last RESTORE operation or have
been written since that time. Reading BLANK_PARAMS immediately after a restore operation allows the user to determine which
parameters are stored in that store. A “1” indicates the parameter is not present in the store and has not been written since the
RESTORE operation.
Data Length in Bytes: 16
Data Format: BIT
Type: Block Read
Default Value: FF…FFh
SNAPSHOT_CONTROL (F3h)
Definition: Erases parametric and status values stored at SNAPSHOT, flash memory location.
Data Length in Bytes: 1
Data Format: BIT
Type: W Byte
VALUE
03h
FN8923 Rev.1.00
Aug 17, 2017
DESCRIPTION
Erase parametric and status values stored in SNAPSHOT.
Page 48 of 57
ISL8277M
RESTORE_FACTORY (F4h)
Definition: Restores the device to the hard-coded factory default values and pin-strap definitions. The device retains the DEFAULT and
USER stores for restoring. Security level is changed to Level 1 following this command.
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
MFR_VMON_OV_FAULT_LIMIT (F5h)
Definition: Reads the VMON OV fault threshold.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Default Value: CB00h (6V)
Units:
Range: 4V to 6V
MFR_VMON_UV_FAULT_LIMIT (F6h)
Definition: Reads the VMON UV fault threshold.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Default Value: CA00h (4V)
Units: V
Range: 4V to 6V
MFR_READ_VMON (F7h)
Definition: Reads the VMON voltage. VMON is used to monitor VDRVOUT (Pin 8) voltage through an internal 16:1 resistor divider.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Default Value: N/A
Units: V
Range: 4V to 6V
VMON_OV_FAULT_RESPONSE (F8h)
Definition: Reads the VMON OV fault response.
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default Value: 80h (Disable and no retry)
Units: N/A
VMON_UV_FAULT_RESPONSE (F9h)
Definition: Reads the VMON UV fault response.
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default Value: 80h (Disable and no retry)
Units: N/A
FN8923 Rev.1.00
Aug 17, 2017
Page 49 of 57
ISL8277M
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE
REVISION
CHANGE
Aug 17, 2017
FN8923.1
Added Table 1 on page 3.
Changed the default value for 46h “IOUT_OC_FAULT_LIMIT” on page 24 to DBC0h, 30A.
Changed the default value for 4Bh “IOUT_UC_FAULT_LIMIT” on page 24 to DC3Fh, -30A.
Changed the type for F4h “RESTORE_FACTORY” on page 26 to Write Block.
Changed the name of F5h “VMON_OV_FAULT_LIMIT” to “MFR_VMON_OV_FAULT_LIMIT” on page 27.
Changed the name of F6h “VMON_UV_FAULT_LIMIT” to “MFR_VMON_UV_FAULT_LIMIT” on page 27.
Changed the name of F7h “READ_VMON” to “MFR_READ_VMON” on page 27.
In Table 5, changed the RSET for the 5-5 entry to 13.3, 28.7, 61.9, or OPEN.
In Table 8, changed the UVLO value for the last seven entries to 10.8
Changed the default value for “SYNC_CONFIG (E9h)” on page 47 from 0000h to 00h.
Changed the type for “SNAPSHOT_CONTROL (F3h)” on page 48 from R/W BYTE to W BYTE.
Changed the range maximum for “VOUT_MAX (24h)” on page 30 from 4V to 6V.
Changed the default value for “VOUT_OV_WARNING_LIMIT (42h)” on page 32 from 0.85 to 1.1.
Changed the default value for “VOUT_UV_WARNING_LIMIT (43h)” on page 32 from 0.85 to 0.9.
Updated Table 7 on page 18 with new values.
Updated Figures 10 through 15.
Updated Table 2 on page 15 with new values.
Updated Table 5 on page 18 with new values.
Updated Table 7 on page 18 with new values.
Updated Table 8 on page 19 with new values.
Changed the type for “DEVICE_ID” on page 26 from ASC to ASCII.
Updated the descriptions for bits 4 and 5 in “STATUS_MFR_SPECIFIC” on page 25.
Feb 28, 2017
FN8923.0
Initial release
Firmware Revision History
FIRMWARE REVISION CODE
ISL8277-0-G0100
CHANGE DESCRIPTION
NOTE
Initial release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets.
For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information
page found at www.intersil.com.
For a listing of definitions and abbreviations of common terms used in our documents, visit: www.intersil.com/glossary.
You can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2017. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8923 Rev.1.00
Aug 17, 2017
Page 50 of 57
ISL8277M
Package Outline Drawing
For the most recent package outline drawing, see Y41.17x19.
Y41.17x19
41 I/O 17.0mm x 19.0mm x 3.6mm HDA MODULE
Rev 1, 5/16
PIN 1 INDICATOR
DATUM A
A
17.00 BSC
SEE
DETAIL A
B
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
TERMINAL #A1
INDEX AREA
9.00
18.50 ±0.15
0.10 M C A B
0.475
19.00 BSC
2.975
1.300
1.350
0.10 C 2X
P
R
T
U
V
W
12.00
0.30 REF
0.30 REF
0.10 C 2X
M
N
DATUM B
0.20 REF
16.50 ±0.15
0.10 M C A B
TOP VIEW
BOTTOM VIEW
2
1.00 BSC
0.20 REF
3.6 ±0.1
// 0.10 C
0.08 C
C
0.20 REF
SEATING
PLANE
0.025 MAX
SIDE VIEW
21 x 0.60 ±0.05
3
3
21 x 0.60 ±0.05
0.10 M C A B
1.00 BSC
0.05 M C
TERMINAL TIP
DETAIL A
NOTES:
1. All dimensions are in millimeters.
2. Represents the basic land grid pitch.
3. The total number of I/O (excluding dummy pads).
4. Unless otherwise specified, tolerance: decimal ±0.10.
5. Dimensioning and tolerancing per ASME Y14.M-2009.
6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated.
The pin #1 identifier may be either a mold or mark feature.
FN8923 Rev.1.00
Aug 17, 2017
Page 51 of 57
2
ISL8277M
0.60
2.50
5.10
2X 1.60
0.60
2X 0.60
1.50
1.60
5.10
7.60
1.00
0.60
4X 1.60
1.00
4X
0.80
0.80
1.40
1.30
0.60
2.00
1.50
0.60
2.00
0.60
0.60
4.90
2.70
1.50
8.20
8.20
3.00
1.50
1.80
2.00
3.05
3.50
0.70
3.00
0.70
5.80
4.80
10.00
SIZE DETAILS FOR THE 16 EXPOSED DAPS
BOTTOM VIEW
FN8923 Rev.1.00
Aug 17, 2017
Page 52 of 57
ISL8277M
0.60
2.50
5.10
2X 1.60
0.60
2X 0.60
1.50
1.60
5.10
7.60
1.00
0.60
4X 1.60
0.80
1.40
1.00
0.60
2.00
4X
0.80
1.30
1.50
0.60
2.00
0.60
0.60
4.90
2.70
1.50
1.50
3.00
8.20
8.20
1.80
2.00
3.05
0.70
3.00
3.50
0.70
4.80
5.80
10.00
SIZE DETAILS FOR THE 16 EXPOSED DAPS
TOP VIEW
FN8923 Rev.1.00
Aug 17, 2017
Page 53 of 57
6.700
6.850
7.050
8.200
8.500
5.300
5.700
2.300
2.700
3.300
3.700
4.300
4.700
0.700
0.775
1.300
1.700
0.175
0.300
0.700
0.300
1.300
2.300
1.700
2.700
9.300
8.700
3.300
8.500
8.300
7.700
9.500
6.700
6.300
5.700
5.300
4.700
4.300
3.700
0.00
ISL8277M
8.300
7.700
9.500
7.300
9.300
8.700
8.300
7.700
6.700
6.300
5.700
7.300
5.300
4.700
4.300
5.550
5.350
3.700
3.600
3.400
3.300
2.700
1.650
1.450
0.044
0.000
0.400
0.556
1.000
1.400
2.000
2.675
0.600
0.000
0.300
1.000
2.900
3.100
3.275
4.025
5.000
5.200
5.900
7.100
4.625
7.300
7.450
7.650
9.200
8.500
8.200
6.350
6.550
4.700
3.000
1.600
1.400
1.600
1.400
1.000
0.200
0.000
2.800
2.700
4.400
3.500
3.000
5.100
4.900
5.400
5.350
5.550
6.300
9.500
8.300
7.600
7.400
8.500
5.900
6.150
7.575
7.775
7.900
8.500
9.200
9.500
RECOMMENDED SOLDER MASK DEFINED PCB LAND PATTERN (1)
TOP VIEW
FN8923 Rev.1.00
Aug 17, 2017
Page 54 of 57
6.000
5.200
2.200
0.433
0.633
0.000
1.133
1.333
2.550
2.900
6.800
7.300
ISL8277M
7.100
6.750
5.533
5.333
7.300
3.767
5.300
5.700
3.700
3.567
3.300
1.700
2.300
2.000
1.700
1.100
0.900
0.300
1.300
0.000
0.000
0.300
0.900
2.500
3.500
3.700
0.000
2.900
4.700
5.300
6.300
6.900
6.700
5.200
RECOMMENDED SOLDER MASK DEFINED PCB LAND PATTERN (2)
TOP VIEW
FN8923 Rev.1.00
Aug 17, 2017
Page 55 of 57
6.740
6.830
7.070
8.180
8.500
5.280
5.720
1.715
1.285
0.715
0.285
0.000
0.190
0.285
0.715
0.760
1.285
1.715
2.285
2.715
3.285
3.715
4.285
4.720
3.285
2.715
2.285
5.715
5.285
4.285
4.715
3.715
6.285
6.720
7.715
8.500
8.280
ISL8277M
9.500
9.280
8.720
8.280
7.720
7.285
9.500
8.720
8.285
7.720
6.715
6.285
7.260
5.715
5.285
5.590
5.310
4.715
4.285
3.715
3.285
3.640
3.360
2.715
1.690
0.000
0.980
1.420
1.410
0.585
0.024
0.015
0.000
0.260
0.420
0.536
1.040
1.980
2.860
3.140
4.960
5.240
5.940
6.180
7.060
7.545
7.805
7.340
7.860
8.530
9.170
9.500
8.500
8.160
6.590
6.310
4.740
2.960
1.640
1.360
0.000
0.040
1.420
2.680
6.960
6.320
5.580
5.380
5.320
5.140
4.860
4.420
3.530
3.040
8.500
8.280
8.270
7.630
7.370
9.160
RECOMMENDED STENCIL PATTERN (90% PASTE TO PAD) (1)
TOP VIEW
FN8923 Rev.1.00
Aug 17, 2017
Page 56 of 57
7.060
5.970
5.230
2.160
0.673
0.393
1.093
1.373
2.533
2.860
6.330
7.270
6.830
7.730
8.270
ISL8277M
7.270
6.733
5.730
5.573
5.293
5.270
3.807
3.730
3.527
2.270
2.040
1.730
1.070
3.270
1.730
1.270
0.930
0.000
0.270
0.270
0.870
2.530
2.690
3.260
3.470
3.740
4.040
4.610
5.160
5.930
7.420
7.680
1.585
1.370
1.015
0.230
1.630
4.660
2.940
2.770
5.340
6.660
6.330
6.940
8.260
9.170
RECOMMENDED STENCIL PATTERN (90% PASTE TO PAD) (2)
TOP VIEW
FN8923 Rev.1.00
Aug 17, 2017
Page 57 of 57