LTM4636-1 40A µModule Regulator with Overvoltage/ Overtemperature Protection DESCRIPTION FEATURES n n n n n n n n n n n n n n Overtemperature, Input/Output Overvoltage Protection Trips Upstream Power Source or Circuit Breaker Stacked Inductor Acts as Heat Sink Wide Input Voltage Range: 4.7V to 15V 0.6V to 3.3V Output Voltage Range ±1.3% Total DC Output Voltage Error (–40°C to 125°C) Differential Remote Sense Amplifier for Precision Regulation Current Mode Control/Fast Transient Response Frequency Synchronization Parallel Current Sharing (Up to 240A) 88% Efficiency (12VIN, 1VOUT) at 40A Overcurrent Foldback Protection Overtemperature Shutdown 16mm × 16mm × 7.07mm BGA Package The LTM®4636-1 is a 40A step-down µModule® (power module) switching regulator with stacked inductor as a heat sink for heat dissipation and cooler operation in a small package. The LTM4636-1 detects overtemperature and input/output overvoltage conditions and can trip an upstream power supply or circuit breaker to protect itself and its load. The exposed inductor as a heat sink permits direct contact with airflow from any direction. The LTM4636-1 can deliver 40W (12VIN, 1VOUT, 40A, 200LFM) with only 40°C rise over the ambient temperature. Full-power 40W is delivered up to 83°C ambient and half-power 20W is supported at 110°C ambient. The LTM4636-1 operates at 92%, 90% and 88% efficiency delivering 15A, 30A and 40A, respectively, to a 1V load (12VIN). The µModule regulator is scalable where four in current sharing deliver 160W with only 40°C rise and 88% efficiency (12VIN, 1VOUT, 400LFM). The LTM4636-1 is offered in 16mm × 16mm × 7.07mm BGA package. APPLICATIONS n n Telecom Servers and Networking Equipment Industrial Equipment and Medical Systems All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210, 8163643. TYPICAL APPLICATION 12VIN , 1VOUT Efficiency at 350kHz vs Output Current 1V, 40A DC/DC µModule Regulator VSYS 4.7V TO 15V HOT SWAP CIRCUIT BREAKER 4.5V TO 5.5V RANGE BIAS VIN ≤ 5.5V, TIE VIN AND PVCC TOGETHER, TIE RUNP TO GND. VIN > 5.5V, THEN OPERATE AS SHOWN + 22µF 16V ×5 100µF 25V 61.9k INTVCC PVCC 15k 0.1µF INTVCC OPTIONAL OVERTEMPERATURE AND OVERVOLTAGE FAULT SIGNAL 34.8k VIN PVCC 22µF 86.6k INTVCC BIAS PVCC RUNC RUNP HIZREG OVER_TEMP OVP_TRIP OTP_SET OVP_SET CROWBAR LTM4636-1 FREQ VOUT TRACK/SS VOUTS1+ MODE/PLLIN SNSP1 SNSP2 PINS NOT USED IN THIS CIRCUIT: CLKOUT, GMON, PGOOD, PHMODE, PWM, SW, TEST1, TEST2, TEST3, TMON 95 EFFICIENCY (%) UPSTREAM BIAS REGULATOR 100 VOUTS1– COMPA VFB COMPB TEMP+ TEMP– SGND PGND OPTIONAL CROWBAR 0.01µF 90 85 80 75 100k 70 1V + VOUT 1V, 40A 470µF 6.3V ×3 0 5 10 15 20 25 30 OUTPUT CURRENT (A) 35 40 46361 TA01b 100µF 6.3V ×4 7.5k 46361 TA01a OPTIONAL TEMP MONITOR See the LTM4636 for simpler circuit and fewer features. 46361fa For more information www.linear.com/LTM4636-1 1 LTM4636-1 ABSOLUTE MAXIMUM RATINGS (Note 1) VIN, SW, HZBREG, RUNP, OVR_TRIP, OVER TEMP ............................................... –0.3V to 16V VOUT .......................................................... –0.3V to 3.5V PGOOD, RUNC, TMON, PVCC, MODE/PLLIN, PHMODE, FREQ, TRACK/SS, TEST1, TEST2, VOUTS1–, VOUTS1+, SNSP1, SNSP2, TEST3, OVP_SET, CROWBAR.................... –0.3V to INTVCC (5V) VFB, COMPA, COMPB (Note 6) .................. –0.3V to 2.7V BIAS ............................................................. –0.3V to 6V PVCC Additional Output Current ................ 0mA to 50mA TEMP+, TEMP– .......................................... –0.3V to 0.8V INTVCC Peak Output Current (Note 6) ....................20mA Internal Operating Temperature Range (Note 2) .................................................. –40°C to 125°C Storage Temperature Range .................. –55°C to 125°C Reflow (Peak Body) Temperature .......................... 250°C Note: PWM, CLKOUT, and GMON are outputs only. PIN CONFIGURATION TOP VIEW VOUTS1– VOUTS1+ COMPB 1 3 2 4 5 6 A 8 9 10 11 OVER_TEMP OVP_TRIP CROWBAR OVP_SET PHMODE RUNP PVCC OTP_SET TEMP– TEMP+ GMON C TRACK/SS RUNC PGOOD D SNSP1 SNSP2 VFB COMPA E FREQ GND G H MODE/PLLIN GND INTVCC F SGND CLKOUT TEST3 L BIAS PWM TMON TEST1 GND J K 12 VOUT B TEST2 HIZREG 7 GND VIN SW M BGA PACKAGE 144-LEAD (16mm × 16mm × 7.07mm) TJMAX = 125°C, JA = 7.5°C/W, JCbottom = 3°C/W, JCtop = 15°C/W, JBA = 12°C/W JA = DERIVED FROM 95mm × 76mm PCB WITH 6 LAYERS, WEIGHT = 3.95g VALUES DETERMINED PER JESD51-12 Note: JA = ( JCbottom + JBA)|| JCtop; JBA is Board to Ambient ORDER INFORMATION http://www.linear.com/product/LTM4636-1#orderinfo LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTM4636-1EY#PBF LTM4636-1EY#PBF LTM4636-1 144-Lead (16mm × 16mm × 7.07mm) BGA –40°C to 125°C LTM4636-1IY#PBF LTM4636-1IY#PBF LTM4636-1 144-Lead (16mm × 16mm × 7.07mm) BGA –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ 2 46361fa For more information www.linear.com/LTM4636-1 LTM4636-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V, per the Typical Application in Figure 20. SYMBOL VIN VOUT VOUT(DC) PARAMETER Input DC Voltage VOUT Range DC Output Voltage, Total Variation with Line and Load Input Specifications RUNC Pin On Threshold VRUNC RUNC Pin On Hysteresis VRUNCHYS RUNP Pin On Threshold VRUNP RUNP HYS RUNP Pin Hysteresis HIZREG HIZREG Input Threshold HIZREG HYS HIZREG Hysteresis Input Supply Bias Current IQ(VIN) IS(VIN) Input Supply Current Output Specifications Output Continuous Current IOUT(DC) Range Line Regulation Accuracy ∆VOUT (Line) VOUT Load Regulation Accuracy ∆VOUT (Load) VOUT Output Ripple Voltage VOUT(AC) ∆VOUT(START) Turn-On Overshoot tSTART Turn-On Time ∆VOUTLS Peak Deviation for Dynamic Load tSETTLE Settling Time for Dynamic Load Step IOUTPK Output Current Limit Control Section VFB IFB VOVL ITRACK/SS tON(MIN) RFBHI Voltage at VFB Pin Current at VFB Pin Feedback Overvoltage Lockout Track Pin Soft-Start Pull-Up Current Minimum On-Time Resistor Between VOUTS1 and VFB Pins CONDITIONS VIN ≤ 5.5V, Tie VIN and PVCC Together, Tie RUNP to GND l l CIN = 22µF × 5 COUT = 100µF × 4 Ceramic, 470µF POSCAP × 3 RFB = 40.2k, MODE_PLLIN = GND VIN = 4.70V to 15V, IOUT = 0A to 40A (Note 4) l VRUNC Rising RUNP Pin Rising MIN 4.70 0.6 1.4805 1.1 l 0.7 VIN = 12V, RUNC = 5V, RUNP = VIN, VOUT = 1.5V VIN = 12V, RUNC = 5V, RUNP = VIN, VOUT = 1.5V VIN = 12V, VOUT = 1.5V, Burst Mode Operation, IOUT = 0.1A VIN = 12V, VOUT = 1.5V, Pulse-Skipping Mode, IOUT = 0.1A VIN = 12V, VOUT = 1.5V, Switching Continuous, IOUT = 0.1A Shutdown, RUN = 0, VIN = 12V VIN = 5V, VOUT = 1.5V, IOUT = 40A VIN = 12V, VOUT = 1.5V, IOUT = 40A VIN = 12V, VOUT = 1.5V (Note 4) TYP 1.50 1.22 150 0.8 60 2.3 0.8 16 23 105 30 14.7 5.66 0 MAX 15 3.3 1.5195 1.35 0.9 40 UNITS V V V V mV V mV V V mA mA mA µA A A A VOUT = 1.5V, VIN from 4.70V to 15V IOUT = 0A l 0.02 0.06 %/V VOUT = 1.5V, IOUT = 0A to 40A, VIN = 12V (Note 4) l 0.2 0.35 % IOUT = 0A, COUT = 100µF × 3 Ceramic, 470µF × 3 POSCAP, VIN = 12V, VOUT = 1.5V COUT = 100µF × 4 Ceramic, 470µF × 3 POSCAP, VOUT = 1.5V, IOUT = 0A, VIN = 12V, TRACK/SS = 0.1µF COUT = 100µF × 3 Ceramic, 470µF × 3 POSCAP, No Load, TRACK/SS = 0.001µF, VIN = 12V Load: 0% to 50% to 0% of Full Load COUT = 100µF × 4 Ceramic, 470µF × 3 POSCAP, VIN = 12V, VOUT = 1.5V, CFF = 22pF Load: 0% to 50% to 0% of Full Load, VIN = 5V, COUT = 100µF × 4 Ceramic, 470µF × 3 POSCAP, VIN = 12V, VOUT = 1.5V, CFF = 22pF VIN = 12V, VOUT = 1.5V VIN = 5V, VOUT = 1.5V IOUT = 0A, VOUT = 1.5V (Note 6) Measure at VOUTS1 TRACK/SS = 0V, Default 750µs Turn on with TRACK/SS Tied to INTVCC (Note 3) l 0.594 l 15 mVP-P 5 mV 750 µs 45 mV 25 µs 54 54 A A 5 0.600 –30 7.5 0.606 –100 10 V nA % 1.1 1.35 1.6 µA 100 4.99 ns kΩ 46361fa For more information www.linear.com/LTM4636-1 3 LTM4636-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V, per the typical application in Figure 20. SYMBOL PARAMETER Remote Sense Amplifier VFB Differential Gain A V(VFB) Gain Bandwidth Product GBP VFB Path General Control or Monitor Pins OVP ∆t OVP to OVP_TRIP Crowbar ∆t OVP to CROWBAR OVP Delay OVP to OVER_TEMP OVP_Trip Sink OVP_TRIP Sink Current OTP_Trip Sink OVER_TEMP Sink Current Crowbar Source CROWBAR Source Current OTP_SET Overtemperature Set Register OVP_SET Overvoltage Set Register ITMON ITMON(SLOPE) VPGOOD PGOOD Trip Level VPGL PGOOD Voltage Low VPGOOD High-to-Low Delay tPGOOD PGOOD Leakage Current IPGOOD(OFF) PGOOD Trip Level Hysteresis VPG1(HYST) INTVCC Linear Regulator Internal VCC Voltage Source VINTVCC VINTVCC Load Reg INTVCC Load Regulation UVLO HYS Controller UVLO Hysteresis Drivers and Power MOSFETs PVCC(UVLO) UVLO PVCC UVLO Hysteresis PVCC(HYS) Power Stage Bias PVCC BIAS External Bias for OTP and OVP Function 4 CONDITIONS MIN (Note 6) (Note 5) OVP Response Time OVP Response Time to CROWBAR OVP_TEMP to OVP_TEMP Response Time VCE ≤ 0.4V VCE ≤ 0.4V VCROWBAR ≥ 3.0V TYP MAX 1 4 V/V MHz 500 500 8 ns ns µs mA mA mA kΩ kΩ µA µA µA/°C 15 15 Temperature Monitor Current, TJ = 25°C Into 24.9kΩ Temperature Monitor Current, TJ = 150°C Into 24.9kΩ Temperature Monitor Current Slope, RTMON = 24.9kΩ VFB With Respect to Set Output VFB Ramping Negative VFB Ramping Positive IPGOOD = 2mA 38 VPGOOD = 5V –2 15 24.9 24.9 40.3 58 0.144 –7.5 7.5 0.2 65 44 % % 0.4 2 2.5 6V < VIN < 15V ICC = 0mA to 10mA (Note 6) PVCC Rising 12V Input, PVCC Load = 50mA Range Operating 5.3 UNITS 3.5 5.5 0.5 0.5 3.8 4 0.45 5.0 5.0 5.7 V µs µA % 4.1 V % V V 5.5 V V V 46361fa For more information www.linear.com/LTM4636-1 LTM4636-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V, per the typical application in Figure 20. SYMBOL PARAMETER Oscillator and Phase-Locked Loop Oscillator Frequency fOSC VPHSMD = 0V IFREQ RMODE/PLLIN VMODE/PLLIN FREQ Pin Output Current MODE_PLLIN Input Resistance PLLIN Input Threshold VCLKOUT Low Output Voltage High Output Voltage PWM-CLKOUT PWM to Clockout Phase Delay CONDITIONS MIN TYP MAX UNITS RFREQ = 30.1kΩ RFREQ = 47.5kΩ RFREQ = 54.9kΩ RFREQ = 75.0kΩ Maximum Frequency Minimum Frequency VFREQ = 0.8V 210 540 625 945 1.2 250 600 750 1.05 290 660 825 1.155 19 20 250 kHz kHz kHz MHz MHz MHz µA kΩ l l VMODE/PLLIN Rising VMODE/PLLIN Falling Verified Levels Measurements on CLKOUT VPHMODE = 0V VPHMODE = 1/4 INTVCC VPHMODE = Float VPHMODE = 3/4 INTVCC VPHMODE = INTVCC 0.2 21 2 1.2 0.2 5.2 90 90 120 60 180 V V V V Deg Deg Deg Deg Deg PWM/PWMEN Outputs PWM PWM Output High Voltage PWM Output Low Voltage Temperature Diode Diode Forward Voltage Diode VF TC Temperature Coefficient ILOAD = 500µA ILOAD = –500µA 5.0 I = 100µA, TEMP+ to TEMP– l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4636-1 is tested under pulsed load conditions such that TJ ≈ TA. The LTM4636-1E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the full –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4636-1I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature V V 0.5 0.598 –2.0 V mV/°C range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: The minimum on-time condition is specified for a peak-to-peak inductor ripple current of ~40% of IMAX Load. (See the Applications Information section) Note 4: See output current derating curves for different VIN, VOUT and TA. Note 5: Guaranteed by design. Note 6: 100% tested at wafer level. 46361fa For more information www.linear.com/LTM4636-1 5 LTM4636-1 TYPICAL PERFORMANCE CHARACTERISTICS 100 Efficiency vs Load Current with 8VIN 95 90 90 90 85 3.3VOUT, 500kHz 2.5VOUT, 500kHz 1.8VOUT, 450kHz 1.5VOUT, 425kHz 1.2VOUT, 300kHz 1VOUT, 300kHz 80 70 0 5 10 15 20 25 30 OUTPUT CURRENT (A) 35 85 3.3VOUT, 700kHz 2.5VOUT, 600kHz 1.8VOUT, 500kHz 1.5VOUT, 450kHz 1.2VOUT, 400kHz 1VOUT, 350kHz 80 75 40 70 0 5 10 15 20 25 30 OUTPUT CURRENT (A) 46361 G01 75 40 70 5 10 15 20 25 30 OUTPUT CURRENT (A) 50 40 0 1 40 46361 G03 10A/DIV 18A/µs STEP 46361 G06 46361 G05 60 35 50mV/DIV 50µs/DIV 10A/DIV 18A/µs STEP 70 0 1.2V Transient Response 50mV/DIV 50µs/DIV 80 3.3VOUT, 750kHz 2.5VOUT, 650kHz 1.8VOUT, 600kHz 1.5VOUT, 550kHz 1.2VOUT, 400kHz 1VOUT, 350kHz 80 1V Transient Response Burst Mode OPERATION VIN 12V VOUT 1.5V 90 35 Efficiency vs Load Current with 12VIN 85 46361 G02 Burst Mode Efficiency vs Load Current 100 EFFICIENCY (%) 95 75 EFFICIENCY (%) 100 95 EFFICIENCY (%) EFFICIENCY (%) 100 Efficiency vs Load Current with 5VIN 12V TO 1V TRANSIENT RESPONSE COUT = 4 × 100µF CERAMIC, 3 × 470µF 2.5V POSCAP 5mΩ CFF = 22pF, SW FREQ = 400kHz 12V TO 1.2V TRANSIENT RESPONSE COUT = 4 × 100µF CERAMIC, 3 × 470µF 2.5V POSCAP 5mΩ CFF = 22pF, SW FREQ = 400kHz CCOMP = 100pF 1.8V Transient Response 2.5V Transient Response 5 2 3 4 OUTPUT CURRENT (A) 46361 G04 1.5V Transient Response 50mV/DIV 50µs/DIV 50mV/DIV 100µs/DIV 100mV/DIV 100µs/DIV 10A/DIV 18A/µs STEP 10A/DIV 18A/µs STEP 10A/DIV 18A/µs STEP 46361 G07 12V TO 1.5V TRANSIENT RESPONSE COUT = 4 × 100µF CERAMIC, 3 × 470µF 2.5V POSCAP 5mΩ CFF = 22pF, SW FREQ = 425kHz CCOMP = 100pF 6 46361 G08 12V TO 1.8V TRANSIENT RESPONSE COUT = 6 × 100µF CERAMIC, 2 × 470µF 4V POSCAP 5mΩ CFF = 22pF, SW FREQ = 500kHz CCOMP = 100pF 46361 G09 12V TO 2.5V TRANSIENT RESPONSE COUT = 6 × 100µF CERAMIC, 2 × 470µF 4V POSCAP 5mΩ CFF = 22pF, SW FREQ = 650kHz CCOMP = 100pF 46361fa For more information www.linear.com/LTM4636-1 LTM4636-1 TYPICAL PERFORMANCE CHARACTERISTICS 3.3V Transient Response Start-Up with Soft-Start No-Load Start-Up with Soft-Start Full Load VOUT 0.5V/DIV 100mV/DIV 100µs/DIV VOUT 0.5V/DIV 10A/DIV 18A/µs STEP VIN 5V/DIV VIN 5V/DIV 20ms/DIV 46361 G10 20ms/DIV 46361 G11 46361 G12 12V TO 3.3V TRANSIENT RESPONSE COUT = 6 × 100µF CERAMIC, 2 × 470µF 4V POSCAP 5mΩ CFF = 22pF, SW FREQ = 750kHz CCOMP = 100pF RUN PIN CAPACITOR = 0.1µF TRACK/SS CAPACITOR = 0.1µF COUT = 4 × 100µF CERAMIC AND 3 × 470µF POSCAP RUN PIN CAPACITOR = 0.1µF TRACK/SS CAPACITOR = 0.1µF COUT = 4 × 100µF CERAMIC AND 3 × 470µF POSCAP 40A Load Short-Circuit Start-Up with 0.5V Output Pre-Bias No-Load Short-Circuit VOUT 0.5V/DIV VOUT 0.5V/DIV VOUT 0.5V/DIV LIN 200mA/DIV LIN 200mA/DIV VIN 5V/DIV 100µs/DIV 46361 G13 20ms/DIV 46361 G14 100µs/DIV 46361 G15 RUN PIN CAPACITOR = 0.1µF TRACK/SS CAPACITOR = 0.1µF COUT = 4 × 100µF CERAMIC AND 3 × 470µF 46361fa For more information www.linear.com/LTM4636-1 7 LTM4636-1 PIN FUNCTIONS PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY. VOUT (A1-A12, B1-B12, C1-C12, D1-D2, D11-D12): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance between these pins and GND pins. Review Table 4. MODE_PLLIN (H3): Forced Continuous Mode, Burst Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to INTVCC to enable pulse-skipping mode of operation. Connect to ground to enable forced continuous mode of operation. Floating this pin will enable Burst Mode operation. A clock on this pin will enable synchronization with forced continuous operation. See the Applications Information section. VOUTS1– (D3): VOUT Sense Ground for the Remote Sense Amplifier. This pin connects to the ground remote sense point. Connect to ground when not used. See the Applications Information section. VOUTS1+ (D4): This pin should connect to VOUT and is connected to VFB through a 4.99k resistor. This pin is used to connect to a remote sense point of the load for accurate voltage sensing. Either connect to remote sense point or directly to VOUT. See the Applications Information section for details. COMPB (D5): Internal compensation network provided that coincides with proper stability utilizing the values in Table 5. Just connect this pin to COMPA for internal compensation. In parallel operation with other LTM4636-1 devices, connect COMPA and COMPB pins together for internal compensation, then connect all COMPA pins together. GND (D6-D9, E6-E9, F7, F8, F10, F12, G1-G2, G6 G10, H1, H10-H12, J1-J3, J8-J12, K1-K3, K9-K10, K12, L1-L3, L9-L10, L12, M1-M3, M9-M12): Ground Pins for Both Input and Output Returns. PGOOD (E1): Output Voltage Power Good Indicator. Opendrain logic output is pulled to ground when the output voltage exceeds a ±7.5% regulation window. RUNC (E2): Run Control Pin. A voltage above 1.35V will turn on the control section of the module. A 10k resistor 8 to ground is internal to the module for setting the RUN pin threshold with a resistor to 5V, and allowing a pullup resistor to PVCC for enabling the device. See Figure 1 Block Diagram. TRACK/SS (E3): Output Voltage Tracking Pin and Soft-Start Inputs. The pin has a 1.25µA pull-up current source. A capacitor from this pin to ground will set a soft-start ramp rate. In tracking, the regulator output can be tracked to a different voltage. The different voltage is applied to a voltage divider then to the slave output’s track pin. This voltage divider is equal to the slave output’s feedback divider for coincidental tracking. Default soft-start of 750µs with TRACK/SS pin connected to INTVCC pin. See the Applications Information section. In PolyPhase® applications tie the TRACK/SS pins together. VFB (E4): The Negative Input of the Error Amplifier. Internally, this pin is connected to VOUTS1 with a 4.99k precision resistor. Different output voltages can be programmed with an additional resistor between VFB and VOSNS–. In PolyPhase operation, tying the VFB pins together allows for parallel operation. See the Applications Information section. COMPA (E5): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Tie all COMPA pins together for parallel operation. This pin allows external compensation. See the Applications Information section. OVP_TRIP (E10): This open-drain pin can be used to trip off and retry an input circuit breaker or alert the system to an output overvoltage programmed on the OVP_SET pin. See the Applications Information section. CROWBAR (E11): This pin can be optionally used to clamp the output voltage in an overvoltage condition to protect the load to tighter control of overvoltage. See the Applications Information section. SNSP2 (F1): Current Sense Signal Path. Connect this pin to SNSP1 (F2). SNSP1 (F2): Current Sense Signal Path. Connect this pin to SNSP2 (F1). Both pins are used to calibrate current sense matching and current limit at final test. 46361fa For more information www.linear.com/LTM4636-1 LTM4636-1 PIN FUNCTIONS HIZREG (F3): When this pin is pulled low the power stage is disabled into high impedance. Tie this pin to VIN or INTVCC for normal operation. and PVCC together. Then tie RUNP to GND. If VIN > 5.5V then operate PVCC regulator as normal. See the Typical Application examples. OVER_TEMP (D10): This overtemperature protection is programmable with an internal monitor that is referenced to the TMON pin and the OTP_SET pin. The OVER_TEMP pin can be used to alert the system if the module regulator overheats, and this signal can be used to trip off and retry an electronic circuit breaker in a fault condition. The pin is an open collector that pulls active low in response to OVER_TEMP. The OVER_TEMP pin can be left floating if not used. See the Applications Information section for details. OVP_SET (E12): This pin is used to set the output overvoltage trip point. This pin has a 24.9kΩ resistor on it to ground. See the Applications Information section. Float is not used. SGND (F4, G4): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the application. See layout guidelines in Figure 18. INTVCC (F6): Internal 5.5V LDO for Driving the Control Circuitry in the LTM4636-1. INTVCC is controlled and enabled when RUNC is activated high. FREQ (G5): A resistor can be applied from this pin to ground to set the operating frequency. This pin sources 20µA. See the Applications Information section. PHMODE (G7): This pin can be voltage programmed to change the phase relationship of the CLKOUT pin with reference to the internal clock or an input synchronized clock. The INTVCC (5.5V) output can be voltage divided down to the PHASMD pin to set the particular phase. The Electrical Characteristics show the different settings to select a particular phase. See the Applications Information section. RUNP (G8): This pin enables the PVCC supply. This pin can be connected to VIN, or tie to ground when connecting PVCC to VIN ≤ 5.5V. RUNP needs to sequence up before RUNC. A 15k resistor from PVCC to RUNC with a 0.1µF capacitor will provide enough delay. In parallel operation with multiple LTM4636-1s, the resistor can be reduced in value by N times and the 0.1µF can be increased N times. See Applications Information section. RUNP can be used to set the minimum UVLO with a voltage divider. See Figure 1. PVCC (F9): 5V Power Output and Power for Internal Power MOSFET Drivers. The regulator can power 50mA of external sourcing for additional use. Place a 22µF ceramic filter capacitor on this pin to ground. When VIN < 5.5V, tie VIN BIAS (G9): This pin is used to power the OTP and OVP circuitry independently of the main power feed. See the Applications Information section. TEMP+ (G12): Temperature Monitor. An internal diode connected NPN transistor. See the Applications Information section. OTP_SET (F11): This pin is used to set the overtemperature set point. The pin has a 24.9k resistor on it to ground. See Applications Information section. Float if not used. TEMP – (G11): Low Side of the Internal Temperature Monitor. CLKOUT (G3): Clock out signal that can be phase selected to the main internal clock or synchronized clock using the PHASMD pin. CLKOUT can be used for multiphase applications. See the Applications Information section. TEST1 (H4), TEST2 (F5), TEST3 (H2), GMON (H9):These are test pins used in the final production test of the part. Leave floating. VIN (H5-H6, J4-J7, K4-K8, L4-L8, M4-M8): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between VIN and GND pins. PWM (H7): PWM output that drives the power stage. Primarily used for test, but can be monitored in debug or testing. TMON (H8): Temperature Monitor Pin. Internal temperature monitor, varies from 1.0V at 25°C to 1.44V at 150°C, disables power stage at >150°C. The OTP_Trip signal is set to trip off at a value lower than 150°C. If the temperature monitor feature is not desired, then tie the TMON pin to GND. SW (L11, K11): These are pin connections to the internal switch node for test evaluation and monitoring. An R-C snubber can be placed from the switch pins to GND to eliminate any high frequency ringing. See the Applications Information section. For more information www.linear.com/LTM4636-1 46361fa 9 10k R6 3.24k RFREQ 40k INTVCC 0.1µF 15k PVCC SOFT-START 15k = (PVCC – 1.35V)(10k)/1.35V DISABLES AT ~ 3.75V PVCC = 5V UVLO EXAMPLE > 1.35V = ON INTVCC For more information www.linear.com/LTM4636-1 BIAS OVP_TRIP OVER_TEMP VFB SNSP1 INTVCC MODE_PLLIN TRACK/SS FREQ PHMODE CLKOUT HIZREG 5.5V COMPB INTERNAL COMP SGND COMPA RUNC PGOOD TEST3 TEST2 TEST1 4.7µF 10pF 10k 1% BIAS BDRV VOUT 24.9k 1% 24.9k 1% TMON TEMP MONITOR CURRENT IMON 40µA AT 25°C 60µA AT 150°C 150C DISABLE DISABLE PWM INPUT 0.1µF 1µF PVCC 5V VIN – + BIAS M2 M1 TMON Q1 SNSP2 470pF 220pF CONNECT TO SNSP1 SNS– DCR SENSE NETWORK 0.18µH 1µF > 0.85V = ON INTERNAL 5V REGULATOR PWM LOGIC CONTOL, POWER MOSFET DRIVERS, POWER MOSFET TDRV OPTIMIZED DEAD TIME CONTROL + – Figure 1. Simplified LTM4636-1 Block Diagram 4.99k 0.5% SNSP1 AND SNSP2 CONNECTED AT PCB – SNSP1 VFB DIFF AMP SNS PWM CURRENT SENSE POWER CONTROL – + 10 + – TEST4 24.9k 1% SGND GND 46361 F01 CROWBAR OVP_SET OTP_SET VOUTS1+ VOUTS1– PWM TMON GMON TEMP– TEMP– SNSP2 2.2Ω 2.2µF VOUT SW VIN RUNP PVCC OPTIONAL 0.85V COUT VOUT 1.5V AT 40A TEMP+ 2200pF VIN 4.70V TO 15V CIN VIN ≤ 5.5V, TIE TO VIN AND PVCC TOGETHER, TIE RUNP TO GND. VIN > 5.5V OPERATE AS SHOWN 15k 22µF (VIN – 0.85V) (15K) 2.2Ω, 0805 + + R1 R1 = VIN UVLO EXAMPLE LTM4636-1 BLOCK DIAGRAM 46361fa LTM4636-1 DECOUPLING REQUIREMENTS TA = 25°C. Use Figure 1 configuration. SYMBOL PARAMETER CONDITIONS MIN CIN External Input Capacitor Requirement (VIN = 4.70V to 16V, VOUT = 1.5V) IOUT = 40A, 6 × 22µF Ceramic X7R Capacitors (See Table 4) 100 COUT External Output Capacitor Requirement (VIN = 4.70V to 16V, VOUT = 1.5V) IOUT = 40A (See Table 4) TYP MAX UNITS µF 1000 µF OPERATION Power Module Description The LTM4636-1 is a high efficiency regulator that can provide a 40A output with few external input and output capacitors. This module provides precisely regulated output voltages programmable via external resistors from 0.6V DC to 3.3V DC over a 4.70V to 15V input range. The Typical Application schematic with protection is shown in Figure 20. The LTM4636-1 has an integrated constant-frequency current mode regulator, power MOSFETs, 0.18µH inductor, protection circuitry, 5V regulator and other supporting discrete components. The switching frequency range is from 250kHz to 770kHz, and the typical operating frequency is 400kHz. For switching noise-sensitive applications, it can be externally synchronized from 250kHz to 800kHz, subject to minimum on-time limitations and limiting the inductor ripple current to less than 40% of maximum output current. A single resistor is used to program the frequency. See the Applications Information section. With current mode control and internal feedback loop compensation, the LTM4636-1 module has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. An option has been provided for external loop compensation. LTpowerCAD™ can be used to optimize the external compensation option. See the Applications Information section. Current mode control provides cycle-by-cycle fast current limit in an overcurrent condition. An internal overvoltage monitor feedback pin referred will attempt to protect the output voltage in the event of an overvoltage >10%. The top MOSFET is turned off and the bottom MOSFET is turned on until the output is cleared. Pulling the RUNC pin below 1.1V forces the regulator controller into a shutdown state. The TRACK/SS pin is used for programming the output voltage ramp and voltage tracking during start-up. See the Applications Information section. Optional internal overvoltage protection and overtemperature functions can be used to protect from power MOSFET failures, input and output overvoltage and overtemperature conditions. These two features can be used to trip off and retry an input circuit breaker in the event of either/or both an overvoltage and overtemperature fault. The OVP_TRIP, OVER_TEMP, TMON, OVP_SET, CROWBAR and OTP_SET pins are all used to support these two features. These features can be implemented along with an input circuit breaker to protect expensive systems boards, processors and FPGA devices from damage. See the Applications Information section. The LTM4636-1 is internally compensated to be stable over all operating conditions. Table 5 provides a guideline for input and output capacitances for several operating conditions. LTpowerCAD is available for transient and stability analysis. This tool can be used to optimize the regulators loop response. A remote sense amplifier is provided for accurately sensing output voltages at the load point. Multiphase operation can be easily employed with the internal clock source or a synchronization clock applied to the MODE/PLLIN input using an external clock source, and connecting the CLKOUT pins. See the Applications Information section. Review Figure 4. High efficiency at light loads can be accomplished with selectable Burst Mode operation using the MODE_PLLIN pin. These light load features will accommodate battery operation. Efficiency graphs are provided for light load operation in the Typical Performance Characteristics section. 46361fa For more information www.linear.com/LTM4636-1 11 LTM4636-1 OPERATION A TEMP+ and TEMP– pins are provided to allow the internal device temperature to be monitored using an onboard diode connected NPN transistor. High efficiency at light loads can be accomplished with selectable Burst Mode operation using the MODE_PLLIN pin. These light load features will accommodate battery operation. Efficiency graphs are provided for light load operation in the Typical Performance Characteristics section. APPLICATIONS INFORMATION The typical LTM4636-1 application circuit is shown in Figure 20. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 5 for specific external capacitor requirements for particular applications. For parallel operation of N LTM4636-1s, the following equation can be used to solve for RFB: VIN to VOUT Step-Down Ratios Or use VOUTS1 on one channel and connect all feedback pins together utilizing a single feedback resistor. There are restrictions in the VIN to VOUT step-down ratio that can be achieved for a given input voltage. The maximum duty cycle is 94% typical at 500kHz operation. The VIN to VOUT minimum dropout is a function of load current and operation at very low input voltage and high duty cycle applications. At very low duty cycles the minimum 100ns on-time must be maintained. See the PLL, Frequency Adjustment and Synchronization section and temperature derating curves. Output Voltage Programming The PWM controller has an internal 0.6V ±1% reference voltage. As shown in the Block Diagram, a 4.99k internal feedback resistor connects the VOUTS1 and VFB pins together. When the remote sensing is used, then VOUTS1+ and VOUTS1– are connected to the remote VOUT and GND points. If no remote sense the VOUTS1+ connects to VOUT. The output voltage will default to 0.6V with no feedback resistor. Adding a resistor RFB from VFB to ground programs the output voltage: VOUT 0.6V • 4.99k R FB R FB R FB 4.99k / N VOUT –1 0.6V Tie the VFB pins together for each parallel output. The COMP pins must be tied together also. See the Typical Applications section examples. Input Capacitors The LTM4636-1 module should be connected to a low AC-impedance DC source. Additional input capacitors are needed for the RMS input ripple current rating. The ICIN(RMS) equation which follows can be used to calculate the input capacitor requirement. Typically 22µF X7R ceramics are a good choice with RMS ripple current ratings of ~4A each. A 47µF to 100µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this bulk capacitor is not needed. For a buck converter, the switching duty cycle can be estimated as: D VOUT V IN Table 1. VFB Resistor Table vs Various Output Voltages VOUT (V) RFB (k) 12 0.6 1.0 1.2 1.5 1.8 2.5 3.3 Open 7.5 4.99 3.24 2.49 1.58 1.1 46361fa For more information www.linear.com/LTM4636-1 LTM4636-1 APPLICATIONS INFORMATION Without considering the inductor ripple current, for each output the RMS current of the input capacitor can be estimated as: I CIN(RMS) IOUT(MAX) % • D • (1– D) where % is the estimated efficiency of the power module. The bulk capacitor can be a switcher-rated aluminum electrolytic capacitor or a Polymer capacitor. Output Capacitors The LTM4636-1 is designed for low output voltage ripple noise. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, low ESR Polymer capacitor or ceramic capacitors. The typical output capacitance range is from 400µF to 1000µF. Additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. Table 5 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 15A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 5 matrix, and LTpowerCAD is available for stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. LTpowerCAD can be used to calculate the output ripple reduction as the number of implemented phases increases by N times. External loop compensation can be used for transient response optimization. Burst Mode Operation The LTM4636-1 is capable of Burst Mode operation in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. To enable Burst Mode operation, simply float the MODE_PLLIN pin. During Burst Mode operation, the peak current of the inductor is set to approximately 30% of the maximum peak current value in normal operation even though the voltage at the COMPA pin indicates a lower value. The voltage at the COMPA pin drops when the inductor’s average current is greater than the load requirement. As the COMPA voltage drops below 0.5V, the burst comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current. The load current is now being supplied from the output capacitors. When the output voltage drops, causing COMPA to rise, the internal sleep line goes low, and the LTM4636-1 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Pulse-Skipping Mode Operation In applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the LTM4636-1 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE_PLLIN pin to INTVCC enables pulse-skipping operation. With pulse-skipping mode at light load, the internal current comparator may remain tripped for several cycles, thus skipping operation cycles. This mode has lower ripple than Burst Mode operation and maintains a higher frequency operation than Burst Mode operation. Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE_PLLIN pin to ground. In this mode, inductor current is allowed to reverse during low output loads, the COMPA voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4636-1’s output voltage is in regulation. 46361fa For more information www.linear.com/LTM4636-1 13 LTM4636-1 APPLICATIONS INFORMATION Multiphase Operation For outputs that demand more than 40A of load current, multiple LTM4636-1 devices can be paralleled to provide more output current without increasing input and output ripple voltage. The MODE_PLLIN pin allows the LTM4636-1 to be synchronized to an external clock and the internal phase-locked loop allows the LTM4636-1 to lock onto input clock phase as well. The FREQ resistor is selected for normal frequency, then the incoming clock can synchronize the device over the specified range. A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used. See Application Note 77. The LTM4636-1 device is an inherently current mode controlled device, so parallel modules will have good current sharing. This will balance the thermals in the design. 0.60 0.55 0.50 Tie the COMPA to COMPB and then tie the COMPA pins together, tie VFB pins of each LTM4636-1 together to share the current evenly. Figure 21 shows a schematic of the parallel design. For external compensation and parallel operation only tie COMP A pins together with external compensation. Input RMS Ripple Current Cancellation Application Note 77 provides a detailed explanation of multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved phases (see Figure 2). PLL, Frequency Adjustment and Synchronization The LTM4636-1 switching frequency is set by a resistor (RFREQ) from the FREQ pin to signal ground. A 20µA current (IFREQ) flowing out of the FREQ pin through RFREQ develops a voltage on the FREQ pin. RFREQ can be calculated as: RFREQ FREQV 20µA 1 PHASE 2 PHASE 3 PHASE 4 PHASE 6 PHASE RMS INPUT RIPPLE CURRENT DC LOAD CURRENT 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 DUTY CYCLE (VOUT/VIN) 46361 F02 Figure 2. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six µModule Regulators (Phases) 14 46361fa For more information www.linear.com/LTM4636-1 LTM4636-1 APPLICATIONS INFORMATION The relationship of FREQV voltage to switching frequency is shown in Figure 3. For low output voltages from 0.6V to 1.2V, 350kHz operation is an optimal frequency for the best power conversion efficiency while maintaining the inductor current to about 45% of maximum load current. For output voltages from 1.5V to 1.8V, 500kHz is optimal. For output voltages from 2.5V to 3.3V, 700kHz is optimal. See efficiency graphs for optimal frequency set point. Limit the 2.5V and 3.3V outputs to 35A. The LTM4636-1 can be synchronized from 200kHz to 1200kHz with an input clock that has a high level above 2V and a low level below 1.2V. See the Typical Applications section for synchronization examples. The LTM4636-1 minimum on-time is limited to approximately 100ns. The on-time can be calculated as: 1 FREQ • V OUT V IN Output Voltage Tracking Output voltage tracking can be programmed externally using the TRACK/SS pin. The output can be tracked up and down with another regulator. The master regulator’s output is divided down with an external resistor divider that is the same as the slave regulator’s feedback divider to implement coincident tracking. The LTM4636-1 uses 1300 1100 FREQUENCY (kHz) t ON(MIN) The LTM4636-1's CLKOUT pin phase difference from VOUT can be programmed by applying a voltage to the PHMODE pin. This voltage can be programmed using the 5.5V INTVCC pin. Most of the phase selections can be programmed by either grounding, floating, or tying this pin to INTVCC. The 60 degree phase shift will require 3/4 INTVCC and can be programmed with a voltage divider from the INTVCC pin. See Figure 4 for phase programming and the 2 to 6 phase connections. See Figure 21 for example design. 900 700 500 300 100 0.4 0.6 0.8 1.0 1.2 VFREQ (V) 1.4 1.6 1.8 46361 F03 Figure 3. FREQ Voltage to Switching Frequency 46361fa For more information www.linear.com/LTM4636-1 15 LTM4636-1 APPLICATIONS INFORMATION an accurate 4.99k resistor internally for the top feedback resistor. Figure 5 shows an example of coincident tracking. VOUT(SLAVE) 1 4.99k R TA more than 0.6V. RTA in Figure 5 will be equal to RFB for coincident tracking. The TRACK/SS pin of the master can be controlled by an external ramp or the soft-start function of that regulator can be used to develop that master ramp. The LTM4636-1 can be used as a master by setting the ramp rate on its track pin using a soft-start capacitor. A 1.25µA current source is used to charge the soft-start capacitor. The following equation can be used: • V TRACK VTRACK is the track ramp applied to the slave’s track pin. VTRACK has a control range of 0V to 0.6V, or the internal reference voltage. When the master’s output is divided down with the same resistor values used to set the slave’s output, then the slave will coincident track with the master until it reaches its final value. The master will continue to its final value from the slave’s regulation point (see Figure 6). Voltage tracking is disabled when VTRACK is PHASE SELECTION VOUT PHASE 0 0 0 0 0 TWO PHASE 0 PHASE CLKOUT PHMODE PHASE (V) 90 0 90 1/4 INTVCC FLOAT 120 3/4 INTVCC 60 INTVCC 180 t SOFT-START MODE_PLLIN CLKOUT C SS 1.25µA 180 PHASE MODE_PLLIN CLKOUT LTM4636-1 PHMODE VOUT INTVCC 0.6V • LTM4636-1 PHMODE VOUT FLOAT THREE PHASE 0 PHASE 120 PHASE 240 PHASE MODE_PLLIN CLKOUT LTM4636-1 PHMODE VOUT MODE_PLLIN CLKOUT LTM4636-1 PHMODE VOUT MODE_PLLIN CLKOUT LTM4636-1 PHMODE VOUT FOUR PHASE 0 PHASE 90 PHASE 180 PHASE 270 PHASE MODE_PLLIN CLKOUT MODE_PLLIN CLKOUT MODE_PLLIN CLKOUT MODE_PLLIN CLKOUT LTM4636-1 PHMODE VOUT LTM4636-1 PHMODE VOUT LTM4636-1 PHMODE VOUT LTM4636-1 PHMODE VOUT INTVCC R2 10k 3/4 INTV CC R1 30.1k 3/4 INTVCC 0 PHASE SIX PHASE 60 PHASE 120 PHASE MODE_PLLIN CLKOUT MODE_PLLIN CLKOUT MODE_PLLIN CLKOUT LTM4636-1 PHMODE VOUT LTM4636-1 PHMODE VOUT 3/4 INTVCC 3/4 INTVCC LTM4636-1 PHMODE VOUT 180 PHASE 240 PHASE 300 PHASE MODE_PLLIN CLKOUT LTM4636-1 PHMODE VOUT MODE_PLLIN CLKOUT LTM4636-1 PHMODE VOUT MODE_PLLIN CLKOUT LTM4636-1 VOUT PHMODE 3/4 INTVCC 3/4 INTVCC 46361 F04 Figure 4. Phase Selection Examples 16 46361fa For more information www.linear.com/LTM4636-1 LTM4636-1 APPLICATIONS INFORMATION 4.7V TO 15V + 5V PVCC1 INTVCC1 100µF 25V 22µF 16V ×5 5V PVCC1 CSS 0.1µF 15k 0.1µF INTVCC1 COMPA COMPB TRACK/SS VIN INTVCC 22µF PVCC VOLTAGE OUT TEMP MONITOR TMON SW RUNC RUNP HIZREG 1.5V AT 40A VOUT LTM4636-1 VOUTS1+ + FREQ 40.2k 2200pF 2.2Ω, 0805 + 470µF 6.3V + – VOUTS1 VFB 470µF 6.3V 470µF 6.3V 100µF ×4 6.3V RFB 3.24k TEMP+ TEMP– SNSP1 SNSP2 SGND PGND OPTIONAL TEMP MONITOR FOR TELEMETRY READBACK ICs 5V PVCC2 INTVCC2 1.5V 22µF 16V ×5 5V PVCC2 15k 0.1µF R7B 4.99k R7A 4.99k INTVCC2 COMPA COMPB TRACK/SS VIN INTVCC 22µF PVCC VOLTAGE OUT TEMP MONITOR TMON SW RUNC RUNP HIZREG 1.2V AT 40A VOUT LTM4636-1 VOUTS1+ 2200pF 2.2Ω, 0805 + FREQ + 470µF + 6.3V – VOUTS1 VFB TEMP+ TEMP– SNSP1 SNSP2 SGND PGND 470µF 6.3V 470µF 6.3V 100µF ×4 6.3V RFB1 4.99k OPTIONAL TEMP MONITOR FOR TELEMETRY READBACK ICs 46361 F05 PINS NOT USED IN THIS CIRCUIT: CLKOUT, GMON, MODE/PLLIN, PGOOD, OTP_SET, CROWBAR, OVP_TRIP, OVP_SET, BIAS, OVER_TEMP, PHMODE, PWM, TEST1, TEST2, TEST3 Figure 5. Dual Outputs (1.5V and 1.2V) with Tracking MASTER OUTPUT OUTPUT VOLTAGE SLAVE OUTPUT TIME 46361 F06 Figure 6. Output Voltage Coincident Tracking Characteristics 46361fa For more information www.linear.com/LTM4636-1 17 LTM4636-1 APPLICATIONS INFORMATION Ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the master’s TRACK/SS pin. As mentioned above, the TRACK/SS pin has a control range from 0V to 0.6V. The master’s TRACK/SS pin slew rate is directly equal to the master’s output slew rate in volts/time. The equation: MR SR • 4.99k R TB where MR is the master’s output slew rate and SR is the slave’s output slew rate in volts/time. When coincident tracking is desired, then MR and SR are equal, thus RTB is equal to 60.4k. RTA is derived from equation: R TA 0.6V V FB V FB V TRACK – 4.99k R FB1 R TB Temperature Monitoring Measuring the absolute temperature of a diode is possible due to the relationship between current, voltage and temperature described by the classic diode equation: ID IS • e In ratiometric tracking, a different slew rate maybe desired for the slave regulator. RTB can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach its final value before the master output. For example, MR = 1.5V/ms, and SR = 1.2V/ms. Then RTB = 6.19k. Solve for RTA to equal 4.22k. For applications that do not require tracking or sequencing, simply tie the TRACK/SS pin to INTVCC to let RUN control the turn on/off. When the RUN pin is below its threshold or the VIN undervoltage lockout, then TRACK/SS is pulled low. Default Overcurrent and Overvoltage Protection The LTM4636-1 has overcurrent protection (OCP) in a short circuit. The internal current comparator threshold folds back during a short to reduce the output current. An overvoltage condition (OVP) above 10% of the regulated VD • VT or VD where VFB is the feedback voltage reference of the regulator, and VTRACK is 0.6V. Since RTB is equal to the 4.99k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then RTA is equal to RFB with VFB = VTRACK. Therefore RTB = 4.99k, and RTA = 4.99k in Figure 5. 18 output voltage will force the top MOSFET off and the bottom MOSFET on until the condition is cleared. Foldback current limiting is disabled during soft-start or tracking start-up. I • VT •In D IS where ID is the diode current, VD is the diode voltage, is the ideality factor (typically close to 1.0) and IS (saturation current) is a process dependent parameter. VT can be broken out to: VT k•T q where T is the diode junction temperature in Kelvin, q is the electron charge and k is Boltzmann’s constant. VT is approximately 26mV at room temperature (298K) and scales linearly with Kelvin temperature. It is this linear temperature relationship that makes diodes suitable temperature sensors. The IS term in the previous equation is the extrapolated current through a diode junction when the diode has zero volts across the terminals. The IS term varies from process to process, varies with temperature, and by definition must always be less than ID. Combining all of the constants into one term: KD •k q where KD = 8.62−5, and knowing ln(ID/IS) is always positive because ID is always greater than IS, leaves us with the equation that: I VD T KELVIN • K D •In D IS 46361fa For more information www.linear.com/LTM4636-1 LTM4636-1 APPLICATIONS INFORMATION where VD appears to increase with temperature. It is common knowledge that a silicon diode biased with a current source has an approximate –2mV/°C temperature relationship (Figure 7), which is at odds with the equation. In fact, the IS term increases with temperature, reducing the ln(ID/IS) absolute value yielding an approximate –2mV/°C composite diode voltage slope. 0.7 DIODE VOLTAGE (V) T(KELVIN) ∆VD K'D ( CELSIUS) T(KELVIN) – 273.15 where 300°K = 27°C means that is we take the difference in voltage across the diode measured at two currents with a ratio of 10, the resulting voltage is 198μV per Kelvin of the junction with a zero intercept at 0 Kelvin. 0.8 The diode connected NPN transistor at the TEMP pin can be used to monitor the internal temperature of the LTM4636-1. 0.6 0.5 0.4 0.3 –50 Solving for temperature: –25 50 25 0 75 TEMPERATURE (°C) 100 VIN VOUT IOUT AIR FLOW 12 1 40 200 LFM 125 46361 F07 Figure 7. Diode Voltage VD vs Temperature T(°C) To obtain a linear voltage proportional to temperature we cancel the IS variable in the natural logarithm term to remove the IS dependency from the equation 1. This is accomplished by measuring the diode voltage at two currents I1, and I2, where I1 = 10 • I2) and subtracting we get: ∆VD T(KELVIN) • K D •IN I1 IS – T(KELVIN) • K D •IN I2 IS Combining like terms, then simplifying the natural log terms yields: (8a) VIN VOUT IOUT AIR FLOW 12 3.3 35 200 LFM ∆VD = T(KELVIN) • KD • lN(10) and redefining constant K'D K D •IN(10) 198µV K yields ∆VD = K'D • T(KELVIN) (8b) Figure 8. The Two Images Show the LTM4636-1 Operating at 1V at 40A and 3.3V at 35A from a 12V Input. Both Images Reflect Only a 40°C to 45°C Rise Above Ambient at Full Load Current with 200LPM 46361fa For more information www.linear.com/LTM4636-1 19 LTM4636-1 APPLICATIONS INFORMATION Enhanced Overvoltage OVP and Overtemperature Protection OTP The LTM4636-1 has two enhanced protection features that can be used to detect overtemperature and overvoltage. The BIAS pin is supplied to power the protection circuitry off of an auxiliary supervisory supply separate from the high power circuit breaker path. This is required to properly bias the protection circuitry with the proper headroom at power up, and circuit breaker retry. This separate bias supply needs to supply 1mA per module, and 6mA per module during an overvoltage and overtemperature event. If the CROWBAR signal is used then an instantaneous current will be need to drive the crow bar mosfets. This is current is ~ 50mA. The bias voltage can be used to program the OTP and OVP set points. The TMON pin voltage varies from 1.0V at 25°C up to 1.45V at 150°C. The TMON pin can be compared to a programmable set point utilizing the 24.9k resistor to ground on the OTP_SET pin. See the block diagram. By adding an external resistor from this pin to the BIAS pin, an OTP trip point can be set below the 150°C (1.45V) level as an overtemperature detection, and the OVER_TEMP opencollector pin will pull low to provide a system alert, or can be used to trip off power. This feature can be ignored by floating the OVER_TEMP and OTP_SET pins. The equation: R OTP 24.9k • OTP _ SET BIAS OTP _ SET 1; 1.0V(25 C) 3.52mV/°C • 105 C For 130°C, OTP_SET = 1.37V Where BIAS is the voltage applied to BIAS pin, Ex: 5V. OTP_SET is the voltage equivalent to temperature on the TMON pin. For example, BIAS = 5V, and the overtemperature trip point is set to 130°C. TMON has a range of 440mV from 25°C to 150°C, therefore the TMON pin moves 3.52mV/°C above 25°C. 130°C minus 25°C = 105°C rise. The ROTP resistor calculates out to a close 1% value of 66.5k. 20 The BIAS supply can be between 4V to 5.5V, the OTP_SET trip point depends on the BIAS supply voltage to be accurate, otherwise a more accurate reference can be derived from the BIAS supply to be utilized to program the set point. See application schematics. The LTM4636-1 controller has overvoltage protection feedback voltage referred that trips at ~7.5% above VOUT. This feature will try to correct an overvoltage transient issue, but does not protect for a shorted input power source in the event of a top power switch short while the bottom switch is on trying to protect the load. The input source has a direct path to ground in this condition. Neither will this feature protect an overvoltage issue caused by an open feedback path. The enhanced overvoltage protection consists of a fast comparator that compares VOUT to a programmed value set at the OVP_SET pin. An OVP_TRIP point can be set using the BIAS supply and an external resistor (ROVP) with the internal 24.9k resistor. The equation: R OVP 24.9k • BIAS OVP _ TRIP –1 where OVP_TRIP is the maximum overvoltage level set point. The OVP_TRIP open-collector output pulls low and can be used to trip off a circuit breaker or alert the system of an OVP fault. The CROWBAR output drive can be used to drive an external N-channel power MOSFET to clamp the output voltage and discharge the inductor stored energy. Depending on the power design, the OVP trip point and the output capacitance, the CROWBAR clamp may not be needed. Testing will need to be performed to characterize the behavior of the clamping with and without the crowbar. Proper crowbar power MOSFET SOA (safe operating area) selection will be required to make sure the MOSFET can handle the discharge current. A small surface mount resistor can be placed in series from VOUT to the drain of the CROWBAR FET to limit the CROWBAR but still clamp the output. To disable the function, float the OVP_SET, OVP_TRIP and CROWBAR pins. The BIAS supply can be between 4.0V to 5.5V, while the OVP_TRIP point depends on the BIAS supply voltage accuracy. Otherwise an accurate reference can be derived from the BIAS supply. 46361fa For more information www.linear.com/LTM4636-1 LTM4636-1 APPLICATIONS INFORMATION RUNP and RUNC Enable The RUNP pin is used to enable the 5V PVCC supply that powers the power driver stage and enables the power stage ~1ms later. The RUNC pin is used to enable the control section that drives the power stage. The RUNP needs to be enabled first, and then RUNC. RUNP has a 0.85V threshold and can be connected to the input voltage and RUNC has a 1.35V threshold and a 10k resistor to ground. See the Block Diagram for details. A 0.1µF capacitor from the RUNC pin to ground is used to set the delay for RUNC enable. If the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond wire inductance. First the SW pin can be monitored with a wide bandwidth scope with a high frequency scope probe. The ring frequency can be measured for its value. The impedance Z can be calculated: Z(L) = 2πfL, INTVCC and PVCC Regulators The LTM4636-1 has an internal low dropout regulator from VIN called INTVCC. This regulator output has a 4.7μF ceramic capacitor internal. This regulator powers the control section. The PVCC 5V regulator supplies power to the power MOSFET driver stage. An additional 50mA can be used from this 5V PVCC supply for other needs. The input supply source resistance needs to be very low in order to minimize IR drops when operating from a 5V input source. Depending on the output voltage and current, the input supply can source large current,and PVCC 5V regulator needs a minimum 4.7V supply. Additional input capacitance maybe needed for 5V inputs to limit the input droop. Stability Compensation The LTM4636-1 has already been internally compensated when COMPB is tied to COMPA for all output voltages. Table 5 is provided for most application requirements. For specific optimized requirements, disconnect COMPB from COMPA, and use LTpowerCAD to perform specific control loop optimization. Then select the desired external compensation and output capacitance for the desired optimized response. SW Pins The SW pins are generally for testing purposes by monitoring these pins. These pins can also be used to dampen out switch node ringing caused by LC parasitic in the switched current paths. Usually a series R-C combination is used called a snubber circuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor. where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. Calculated by: Z(C) = 1/(2πfC). These values are a good place to start with. Modification to these components should be made to attenuate the ringing with the least amount of power loss. A recommended value of 2.2Ω in series with 2200pF to ground should work for most applications. See Figure 19 for layout guidelines. The 2.2Ω resistor should be an 0805 size. Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board. The motivation for providing these thermal coefficients in found in JESD51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are, in and of themselves, not relevant to providing guidance of thermal performance; instead, the derating 46361fa For more information www.linear.com/LTM4636-1 21 LTM4636-1 APPLICATIONS INFORMATION curves provided in this data sheet can be used in a manner that yields insight and guidance pertaining to one’s application usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section gives four thermal coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below: 1. 2. 3 package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of JCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 4 JA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a 95mm × 76mm PCB with four layers. JCbottom, the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. JCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the JB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule package and into the board, and is really the sum of the JCbottom and the thermal resistance of the bottom of the part through the solder joints and a portion of the board. The board temperature is measured a specified distance from the package. A graphical representation of the aforementioned thermal resistances is given in Figure 9; blue resistances are contained within the µModule regulator, whereas green resistances are external to the µModule package. As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a µModule regulator. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through the bottom of the µModule package—as the standard defines for JCtop and JCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS JUNCTION-TO-CASE (TOP) RESISTANCE CASE (TOP)-TO-AMBIENT RESISTANCE JUNCTION-TO-BOARD RESISTANCE JUNCTION JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD (BOTTOM) RESISTANCE RESISTANCE At BOARD-TO-AMBIENT RESISTANCE 46361 F09 µMODULE DEVICE Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients 22 46361fa For more information www.linear.com/LTM4636-1 LTM4636-1 APPLICATIONS INFORMATION Within the LTM4636-1, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the LTM4636-1 and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a softwaredefined JEDEC environment consistent with JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4636-1 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves shown in this data sheet. The power loss curves in Figure 10 to Figure 12 can be used in coordination with the load current derating curves in Figure 13 to Figure 18 for calculating an approximate JA thermal resistance for the LTM4636-1 with various airflow conditions. The power loss curves are taken at room temperature and can be increased with a multiplicative factor according to the junction temperature, which is ~1.4 for 120°C. The derating curves are plotted with the output current starting at 40A and the ambient temperature increased. The output voltages are 1V, 2.5V and 3.3V. These are chosen to include the lower, middle and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at ~125°C maximum while lowering output current or power with increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. The monitored junction temperature of 125°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example, in Figure 14 the load current is derated to ~30A at ~94°C with no air flow and the power loss for the 12V to 1.0V at 30A output is about 4.2W. The 4.2W loss is calculated with the ~3W room temperature loss from the 12V to 1.0V power loss curve at 30A, and the 1.4 multiplying factor at 125°C junction. If the 94°C ambient temperature is subtracted from the 125°C junction temperature, then the difference of 31°C divided by 4.2W equals a 7.4°C/W JA thermal resistance. Table 2 specifies a 7.2°C/W value which is very close. Tables 2, 3, and 4 provide equivalent thermal resistances for 1V, 1.5V and 3.3V outputs with and without airflow and heat sinking. The derived thermal resistances in Tables 2 thru 4 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss curves are provided in Figure 10 through Figure 12. The printed circuit board is a 1.6mm thick six layer board with two ounce copper for all layers and one ounce copper for the two inner layers. The PCB dimensions are 95mm × 76mm. Safety Considerations The LTM4636-1 does not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. The fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top MOSFET fault. If the internal top MOSFET fails, then turning it off will not resolve the overvoltage, thus the internal bottom MOSFET will turn on indefinitely trying to protect the load. Under this fault condition, the For more information www.linear.com/LTM4636-1 46361fa 23 LTM4636-1 APPLICATIONS INFORMATION 6 5 6 4 3 5 1 1 0 5 10 15 20 25 30 OUTPUT CURRENT (A) 35 0 40 5 3 2 1 0 5 10 15 20 25 30 OUTPUT CURRENT (A) 35 0 40 45 40 40 35 35 35 0 0 30 25 20 15 10 0LFM 200LFM 400LFM 5 LOAD CURRENT (A) 45 40 15 0 120 0 46361 F13 20 15 0 120 40 40 40 35 35 35 15 10 0 0 25 20 15 60 20 40 80 100 AMBIENT TEMPERATURE (°C) 120 Figure 16. 12VIN, 1.5VOUT Derate Curve 0 0 120 30 25 20 15 10 0LFM 200LFM 400LFM 5 46361 F16 24 30 10 0LFM 200LFM 400LFM 5 LOAD CURRENT (A) 45 LOAD CURRENT (A) 45 20 60 20 40 80 100 AMBIENT TEMPERATURE (°C) Figure 15. 5VIN, 1.5VOUT Derate Curve 45 25 0 46361 F15 Figure 14. 12VIN, 1VOUT Derate Curve 30 0LFM 200LFM 400LFM 46361 F14 Figure 13. 5VIN, 1VOUT Derate Curve 40 25 5 60 20 40 80 100 AMBIENT TEMPERATURE (°C) 35 30 10 0LFM 200LFM 400LFM 5 60 20 40 80 100 AMBIENT TEMPERATURE (°C) 10 15 20 25 30 OUTPUT CURRENT (A) Figure 12. 12V Input Power Loss Curves 45 20 5 46361 F12 Figure 11. 8V Input Power Loss Curves 25 0 46361 F11 LOAD CURRENT (A) LOAD CURRENT (A) 3 Figure 10. 5V Input Power Loss Curves 10 LOAD CURRENT (A) 4 2 46361 F10 30 3.3VOUT, 750kHz 2.5VOUT, 650kHz 1.8VOUT, 600kHz 1.5VOUT, 550kHz 1VOUT, 350kHz 6 4 2 0 7 3.3VOUT, 700kHz 2.5VOUT, 600kHz 1.8VOUT, 500kHz 1.5VOUT, 450kHz 1.2VOUT, 400kHz 1VOUT, 350kHz 7 WATTS (W) 7 WATTS (W) 8 3.3VOUT, 500kHz 2.5VOUT, 500kHz 1.8VOUT, 450kHz 1.5VOUT, 425kHz 1.2VOUT, 300kHz 1VOUT, 300kHz WATTS (W) 8 0LFM 200LFM 400LFM 5 60 20 40 80 100 AMBIENT TEMPERATURE (°C) 120 46361 F17 Figure 17. 5VIN, 3.3VOUT Derate Curve 0 0 60 20 40 80 100 AMBIENT TEMPERATURE (°C) 120 46361 F18 Figure 18. 12VIN, 3.3VOUT Derate Curve 46361fa For more information www.linear.com/LTM4636-1 LTM4636-1 APPLICATIONS INFORMATION Table 2. 1V Output DERATING CURVE VIN POWER LOSS CURVE AIRFLOW (LFM) JA (°C/W) Figures 13, 14 5V, 12V Figure 10, 12 0 7.2 Figures 13, 14 5V, 12V Figure 10, 12 200 5.4 Figures 13, 14 5V, 12V Figure 10, 12 400 4.8 Table 3. 1.5V Output DERATING CURVE VIN POWER LOSS CURVE AIRFLOW (LFM) JA (°C/W) Figures 15, 16 5V, 12V Figure 10, 12 0 7.4 Figures 15, 16 5V, 12V Figure 10, 12 200 5.0 Figures 15, 16 5V, 12V Figure 10, 12 400 4.5 DERATING CURVE VIN POWER LOSS CURVE AIRFLOW (LFM) JA (°C/W) Figures 17, 18 12V Figure 10, 12 0 7.4 Figures 17, 18 12V Figure 10, 12 200 5.0 Figures 17, 18 12V Figure 10, 12 400 4.4 Table 4. 3.3V Table 5. LTM4636-1 Capacitor Matrix, All Below Parameters are Typical and are Dependent on Board Layout Taiyo Yuden 22µF, 25V C3216X7S0J226M Panasonic SP 470µF 2.5V EEFGX0E471R Murata 22µF, 25V GRM31CR61C226KE15L Panasonic POSCAP 470µF 2R5 2R5TPD470M5 Murata 100µF, 6.3V GRM32ER60J107M Panasonic POSCAP 470µF 6.3V 6TPD470M5 AVX 100µF, 6.3V 18126D107MAT Taiyo Yuden 220µF, 4V Murata 220µF, 4V Sanyo 20SEP100M 100µF 20V 46361fa For more information www.linear.com/LTM4636-1 25 LTM4636-1 APPLICATIONS INFORMATION VOUT CIN CIN COUT1 (CERAMIC) AND (V) (CERAMIC) (BULK) COUT2 (CERAMIC AND BULK) 0.9 22µF × 5 100µF 100µF × 8, 470µF × 3 0.9 22µF × 5 100µF 220µF × 6, 470µF × 2 0.9 22µF × 5 100µF 220µF × 10, 470µF 1 22µF × 5 100µF 100µF × 4, 470µF × 3 1 22µF × 5 100µF 100µF × 6, 470µF × 2 1 22µF × 5 100µF 100µF × 8, 470µF × 2 1.2 22µF × 5 100µF 100µF × 4, 470µF × 3 1.2 22µF × 5 100µF 100µF × 6, 470µF × 2 1.2 22µF × 5 100µF 220µF × 4, 470µF 1.5 22µF × 5 100µF 100µF × 4, 470µF × 3 1.5 22µF × 5 100µF 100µF × 4, 470µF × 2 1.5 22µF × 5 100µF 100µF × 3, 470µF 1.8 22µF × 5 100µF 100µF × 3, 470µF 1.8 22µF × 5 100µF 100µF, 470µF 1.8 22µF × 5 100µF 220µF × 2, 470µF 2.5 22µF × 5 100µF 100µF × 2, 470µF CFF* (pf) 22 68 None None None None None None None None None None None None None None CCOMP (pf) 100 100 220 100 100 150 100 100 100 100 100 100 220 220 220 220 VIN DROOP (V) (mV) 5,12 38 5,12 40 5,12 40 5,12 40 5,12 50 5,12 55 5,12 45 5,12 45 5,12 50 5,12 60 5,12 56 5,12 75 5,12 90 5,12 95 5,12 90 5,12 120 2.5 22µF × 5 100µF 100µF × 6, 470µF 22 220 5,12 87 3.3 22µF × 5 100µF 100µF × 4 220 220 5,12 130 3.3 22µF × 5 100µF 100µF, 470µF None 220 5,12 140 PEAK-TO-PEAK LOAD DEVIATION RECOVERY STEP RFB FREQ (mV) TIME (µs) (A/µs) (kΩ) (kHz) 76 40 15 10 350 80 30 15 10 350 80 30 15 10 350 80 30 15 7.5 350 100 30 15 7.5 350 105 30 15 7.5 350 90 35 15 4.99 350 90 35 15 4.99 400 104 30 15 4.99 400 120 35 15 3.24 425 110 35 15 3.24 425 150 25 15 3.24 425 180 25 15 2.49 500 197 24 15 2.49 500 180 20 15 2.49 500 220 30 15 1.58 650 (12V) 500 (5V) 174 40 15 1.58 650 (12V) 500 (5V) 260 25 15 1.1 750 (12V) 500 (5V) 280 30 15 1.1 750 (12V) 500 (5V) * CFF is a capacitor from VOUT to VFB. Table 6. Enhanced External Compensation, Lower Voltage Transition During Transient. Careful Power Integrity Layout Required LOAD VOUT CIN CIN COUT1 (CERAMIC) AND CFF CCOMP VIN DROOP PEAK-TO-PEAK RECOVERY STEP RFB (V) (CERAMIC) (BULK)† COUT2 (CERAMIC AND BULK) (pf) (pf) (V) (mV) DEVIATION (mV) TIME (µs) (A/µs) (kΩ) 0.9 22µF × 5 100µF 220µF × 10, 470µF 47 100 5, 12 25 50 26 15 10 1 22µF × 5 100µF 220µF × 10, 470µF 47 100 5, 12 28 55 25 15 7.5 1.2 22µF × 5 100µF 220µF × 10, 470µF 47 100 5, 12 33 66 30 15 4.99 † Bulk capacitance is optional if V has very low input impedance IN 26 FREQ RCOMP (kHz) (k) 350 15 350 15 350 15 CCOMP (pF) 1000 1000 1000 46361fa For more information www.linear.com/LTM4636-1 LTM4636-1 APPLICATIONS INFORMATION input voltage will source very large currents to ground through the failed internal top MOSFET and enabled internal bottom MOSFET. This can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. A fuse or circuit breaker can be used as a secondary fault protector in this situation. The LTM4636-1 has the enhanced over temperature protection discussed earlier and schematic applications will be shown at the end of the data sheet. • Place a dedicated power ground layer underneath the unit. Layout Checklist/Example • Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to GND underneath the unit. • To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. • Do not put vias directly on the pad, unless they are capped or plated over. • Place test points on signal pins for testing. The high integration of the LTM4636-1 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. • For parallel modules, tie the COMP and VFB pins together. Use an internal layer to closely connect these pins together. • Use large PCB copper areas for high current paths, including VIN, GND and VOUT. It helps to minimize the PCB conduction loss and thermal stress. • Add RSNUB (2.2Ω) and CSNUB (2200pF) to dampen switch ringing. Figure 19 gives a good example of the recommended layout. • Place high frequency ceramic input and output capacitors next to the VIN, GND and VOUT pins to minimize high frequency noise. VOUT 1 VOUT 2 3 4 5 6 7 8 9 10 11 12 VOUT A B COUT3 E F RFREQ G TEMP SENSE H GND J GND COUT4 PVCC CAP RFB D CTK/SS COUT2 CRUN COUT1 RRUNC C RSNUB 0805 K L M CSNUB 0603 CIN2 CIN4 CIN1 CIN3 VIN GND GND 46361 F19 Figure 19. Recommended PCB Layout 46361fa For more information www.linear.com/LTM4636-1 27 28 0.01µF 1000pF PG 10k PG UV VDD GND TIMER INTVCC IMON SOURCE LTC4218-12 SENSE+ SENSE– GATE 10Ω 1k M2 Si7880DP 5V + 0.1µF 100µF 25V For more information www.linear.com/LTM4636-1 0.1µF BIAS 66.5k 34.8k VIN = 12V VOUT = 1V IOUT = 40A SHORT = VIN TO VOUT 100ms/DIV VIN TO VOUT SHORT (ZOOM IN) VIN to VOUT Short OPTIONAL TEMP MONITOR 0.01µF 20k TRIP CSS 0.1µF INTVCC 15k PVCC 100pF BIAS LTM4636-1 INTVCC VFB VOUTS1– VOUTS1+ VOUT SW CROWBAR OVP_SET PVCC 46361 F20c VIN AFTER HOT SWAP CIRCUIT BREAKER 10V/DIV SWITCH 10V/DIV CROWBAR GATE 5V/DIV VOUT 1V/DIV 46361 F20a ROVP 86.6k 22µF + 470µF 6.3V 470µF 6.3V M1: SUD50N03-07 M2: Si7880ADP + 470µF 6.3V M1 100µF 6.3V ×4 2200pF VIN = 12V VOUT = 1V IOUT = 40A SHORT = VIN TO VOUT 100ms/DIV VIN to VOUT Short (Zoom In) 46361 F20d PINS NOT USED IN CIRCUIT LTM4636: CLKOUT, GMON, PGOOD, PHMODE, PWM, TEST1, TEST2, TEST3, TMON RFB2 7.5k + 100k 1V AT 40A 2.2Ω, 0805 0.01µF OPTIONAL CROWBAR OVP TRIP SET TO 1.1V 5V PVCC TEMP+ TEMP– SNSP1 SNSP2 SGND PGND OTP_SET MODE/PLLIN FREQ OVER_TEMP OVP_TRIP HIZREG RUNP RUNC COMPA VIN COMPB TRACK/SS INTVCC Figure 20. 10.8V to 14V, 1V at 40A Design with Protection VIN AFTER HOT SWAP CIRCUIT BREAKER 10V/DIV VIN AFTER HOT SWAP CIRCUIT BREAKER 10V/DIV 46361 F20b SWITCH 10V/DIV SWITCH NODE 10V/DIV 100ms/DIV CROWBAR GATE 5V/DIV CROWBAR GATE 5V/DIV VIN = 12V VOUT = 1V IOUT = 40A OVP SETPOINT = 1.1V RETRY EVERY 100ms VOUT 1V/DIV VOUT 1V/DIV Overvoltage Retry with VOUT at 1.1V 22µF 16V ×5 OVERTEMPERATURE AND OVERVOLTAGE FAULT SIGNAL 0.1µF APPLIED POWER TRIP SIGNALS PULLS UV PIN LOW AND RETRIES 100ms LATER AFTER OVP OR OTP EVENT. VIN PULL UV PIN BELOW 0.62V TO CLEAR FAULT 23.7k HOUSEKEEPING SUPPLY RSENSE TRIP = 15mV 0.002Ω PINS NOT USED IN CIRCUIT LTC4218-12: CL, FB, FLT, ISET, OV TRIP UV PIN VIN 10.8V TO 14V HOT SWAP CIRCUIT BREAKER FRONT END LTM4636-1 TYPICAL APPLICATIONS 46361fa LTM4636-1 TYPICAL APPLICATIONS VIN ≤ 5.5V, TIE VIN AND PVCC TOGETHER, TIE RUNP TO GND. VIN > 5.5V, THEN OPERATE AS SHOWN INTVCC1 4.75V TO 15V 22µF 16V ×4 RUNC RUNP INTVCC1 INTVCC1 100µF 25V 34.8k CLK VOLTAGE OUT TEMP MONITOR TMON COMPA COMPB TRACK/SS COMP TRACK/SS 22µF PVCC VIN INTVCC 100pF + 5V PVCC1 2.2Ω, 0805 SW RUNC RUNP HIZREG PHMODE FREQ MODE/PLLIN CLKOUT U1 LTM4636-1 VOUT + VFB OPTIONAL TEMP MONITOR FOR TELEMETRY READBACK ICs COMP TRACK/SS CSS 0.22µF RUNC 0.47µF COMPA COMPB TRACK/SS VIN INTVCC RUNP INTV CC2 RUNC RUNP HIZREG 1V 80A 22µF PVCC VOLTAGE OUT TEMP MONITOR TMON 2.2Ω, 0805 SW SGND U2 LTM4636-1 34.8k SGND OPTIONAL TEMP MONITOR FOR TELEMETRY READBACK ICs VOUTS1– MODE/PLLIN 2200pF VOUT VOUTS1+ + FREQ CLK 100µF 6.3V ×4 5V PVCC2 INTVCC2 7.5k 470µF 6.3V SGND 4.75V TO 15V 5V, PVCC2 + VFB TEMP+ TEMP– SNSP1 SNSP2 SGND PGND 22µF 16V ×4 470µF 6.3V VOUTS1– SGND 2200pF VFB TEMP+ TEMP– SNSP1 SNSP2 SGND PGND 470µF 6.3V + 470µF 6.3V 100µF 6.3V ×4 VFB RFB2 7.5k 46361 F21 SGND PINS NOT USED IN CIRCUIT LTM4636-1 U1: GMON, PGOOD, PWM, TEST1, TEST2, TEST3, VOSNS1+, CROWBAR, OTP_SET, OVP_SET, BIAS, OVP_TRIP, OVER_TEMP PINS NOT USED IN CIRCUIT LTM4636-1 U2: GMON, PGOOD, PHMODE, PWM, TEST1, TEST2, TEST3, CROWBAR, OTP_SET, OVP_SET, BIAS, OVP_TRIP, OVER_TEMP Figure 21. 2-Phase 1V, 80A Regulator Design 46361fa For more information www.linear.com/LTM4636-1 29 12V 30 ON UV SCL ALERT BGGND SCL BGGND For more information www.linear.com/LTM4636-1 10nF CSS 1nF SOURCE FB 0.1µF 10k 12V 3.57k 28.7k 12V CTIMER 10nF GPIO GND INTVCC ADR0 TIMER LTC4215GN SENSE– GATE 10Ω 10k 100µF 25V SGND 34.8k CLK RUNC RUNP HIZREG RUNC RUNP INTVCC1 0.47µF 22µF 16V ×3 SGND CLK1 RUNC RUNP INTVCC3 TRIP COMP TRACK/SS 34.8k 100pF OPTIONAL TEMP MONITOR FOR TELEMETRY READBACK ICs 22µF 16V ×3 INTVCC2 BIAS 5V VFB VOUTS1– VOUT SW TMON CROWBAR 5V PVCC2 U3 LTM4636-1 BIAS 5V PVCC3 VOUTS1– VOUT SW TMON OTP_SET PVCC SGND 5V SGND VFB TEMP+ TEMP– SNSP1 SNSP2 SGND PGND FREQ MODE/PLLIN RUNC RUNP HIZREG OVER_TEMP VIN INTVCC COMPA COMPB TRACK/SS INTVCC3 TEMP+ TEMP– SNSP1 SNSP2 SGND PGND VFB VOUTS1– VOUT VOUTS1+ SW TMON OTP_SET PVCC SGND U2 LTM4636-1 VIN INTVCC COMPA COMP COMPB TRACK/SS TRACK/SS CSS 0.22µF SGND RUNC RUNC RUNP RUNP INTVCC2 HIZREG OVER_TEMP TRIP FREQ CLK MODE/PLLIN 34.8k CLKOUT CLK1 SGND 4.99k OPTIONAL TEMP MONITOR FOR TELEMETRY READBACK ICs 12V – 5V PVCC1 BIAS PVCC OVP_SET OTP_SET U1 LTM4636-1 INTVCC 5V TEMP TEMP SNSP1 SNSP2 SGND PGND + FREQ MODE/PLLIN CLKOUT OVP_TRIP OVER_TEMP COMPA COMPB TRACK/SS VIN TRIP COMP TRACK/SS OPTIONAL TEMP MONITOR FOR TELEMETRY READBACK ICs + 22µF 16V ×3 INTVCC1 Figure 22. 3-Phase 0.9V at 120A with Overtemperature and Overvoltage Protection PINS NOT USED IN CIRCUIT LTM4636-1 U3: GMON, PGOOD, PHMODE, PWM, TEST1, TEST2, TEST3, VOUTS1, CLKOUT, OVP_SET, OVP_TRIP PINS NOT USED IN CIRCUIT LTM4636-1 U2: GMON, PGOOD, PHMODE, PWM, TEST1, TEST2, TEST3, OVP_SET, OVP_TRIP PINS NOT USED IN CIRCUIT LTM4636-1 U1: GMON, PGOOD, PHMODE, PWM, TEST1, TEST2, TEST3, VOUTS1 SS ALERT SCL 4.53k VDD SDA CF 0.01µF 34.6k TRIP KELVIN SENSE RS M1 OPTIONAL CIRCUIT 0.0015Ω Si7880ADP BREAKER FRONT END SDA ALERT SDA SYSTEM SEATPIN SEATPIN D1 P6KE16A 12V 12V CONNECTOR HOUSEKEEPING SUPERVISORY SUPPLY 22µF + 470µF 6.3V VOUTS1– + 46361 F22 VFB + 470µF 6.3V 5V 66.5k 470µF 6.3V 0.01µF 66.5k 470µF 6.3V 5V 470µF 6.3V + 2200pF VOUTS1– 2.2Ω, 0805 VOLTAGE OUT TEMP MONITOR 22µF RFB3 10k + 2200pF 0.9V AT 120A 2.2Ω, 0805 VFB 470µF 6.3V 2200pF VOUTS1– 66.5k VOLTAGE OUT TEMP MONITOR VFB + 2.2Ω, 0805 5V 100µF 100µF 6.3V ×3 100µF 6.3V ×3 M2 100µF 6.3V ×3 100k OPTIONAL CROWBAR 22µF VOLTAGE OUT TEMP MONITOR 102k 0.1Ω 1210 LTM4636-1 TYPICAL APPLICATIONS 46361fa LTM4636-1 TYPICAL APPLICATIONS 46361 F23 Figure 23. DC2448A Demo Board 95 90 EFFICIENCY (%) 85 80 75 70 65 60 0 10 20 30 40 50 60 70 80 90 100 110 120 LOAD CURRENT (A) 46361 F25 46361 F24 Figure 24. Thermal Plot, 12V to 0.9V at 120A, 400LFM Air Flow Figure 25. Efficiency, 12V to 0.9V at 120A VIN to VOUT Short VOUT 40mV DROOP VOUT 1V/DIV CROWBAR GATE 5V/DIV SWITCH 10V/DIV 30A/µs STEP 46361 F26 INTERNAL COMPENSATION COUT = 6× 470µF 6V TPD POS CAP, 12 × 100µf CERAMIC FURTHER OPTIMIZATION CAN BE UTILIZED WITH EXTERNAL COMP Figure 26. 12V to 0.9V 30A/µs Load Step VIN AFTER HOT SWAP CIRCUIT BREAKER 10V/DIV 100ms/DIV 46361 F27 Figure 27. 12V to 0.9V Overvoltage Trip 46361fa For more information www.linear.com/LTM4636-1 31 LTM4636-1 TYPICAL APPLICATIONS 5V IN SHDN 0.47µF RSENSE TRIP = 15mV, 30A KELVIN SENSE 0.001Ω 9V TO 14V INPUT SMBJ16A GRN LED 5VBIAS OUT LT1761-5 BYP GND INTVCC2 22µF 16V 10µF 0.001Ω GRN LED 10Ω SENSE– 10k VDD UV 1000pF 7.5k ON OFF 9.53k 107k SOURCE + LTC4218 PG OV IMON ISET PGOOD GND 22µF 16V INPUT CURRENT MONITOR 0.01µF 0.1µF 5V PVCC1 COMP CSS 0.47µF RUNC RUNP 0.47µF INTVCC1 PINS NOT USED IN CIRCUIT U1: PGOOD, TEST1, TEST2, TEST3, TEST4, GMON, OVP_TEMP, OVP_SET, CROWBAR SGND OVER_TEMP OVP_TRIP SW PHMODE FREQ MODE/PLLIN CLKOUT VOUT – VOUTS1 VFB 34.8k COMPA COMPB TK/SS VIN INTVCC 100k 2.2Ω, 0805 0.1Ω 1210 VOUT GND_SNS + VFB 470µF 470µF 6.3V + 6.3V 100µF 6.3V ×3 SW CLK1 VOUTS1– VFB TEMP+ TEMP– SNSP1 SNSP2 SGND PGND 0.9V AT 160A + 470µF 470µF 6.3V + 6.3V 100µF 6.3V ×3 VFB RFB 10k GND_SNS 5V PVCC3 BIAS COMPA COMPB TK/SS 22µF PVCC 66.5k OTP_SET TMON RUNC RUNP HIZREG PWM TRIP OVER_TEMP 34.8k CLK2 CLK3 PHMODE FREQ MODE/PLLIN CLKOUT U3 LTM4636 VOLTAGE OUT TEMP MONITOR PWM3 TP 2.2Ω, 0805 2200pF SW VOUT VOUTS1– VFB TEMP+ TEMP– SNSP1 SNSP2 SGND PGND OPTIONAL TEMP MONITOR FOR TELEMETRY READBACK ICs GND_SNS VFB + 470µF 470µF 6.3V + 6.3V 100µF 6.3V ×3 5V 9V TO 14V 5V PVCC4 INTVCC4 22µF 16V VIN INTVCC BIAS 22µF PVCC COMPA COMPB TK/SS OTP_SET RUNC RUNP HIZREG PWM TMON U4 LTM4636 OVER_TEMP SW VOUTS1– 34.8k CLK3 PHMODE FREQ MODE/PLLIN 66.5k VOLTAGE OUT TEMP MONITOR PWM4 TP 2.2Ω, 0805 TRIP PINS NOT USED IN CIRCUIT U4: PGOOD, TEST1, TEST2, TEST3, TEST4, VOUTS1, GMON, OVP_TEMP, OVP_SET, CROWBAR, CLKOUT 2200pF 2.2Ω, 0805 5V VIN INTVCC RUNC RUNP INTVCC4 PWM1 TP PWM U1 LTM4636 HIZREG VOUT COMP TK/SS VOLTAGE OUT TEMP MONITOR TMON RUNC RUNP VOUTS1+ RUNC RUNP INTVCC3 66.5k OTP_SET PHMODE FREQ MODE/PLLIN CLKOUT 100pF TK/SS 22µF 16V 0.01µF 2200pF 22µF OVER_TEMP COMP 22µF 16V PWM2 TP PVCC TRIP 22µF 16V PINS NOT USED IN CIRCUIT U3: PGOOD, TEST1, TEST2, TEST3, TEST4, VOUTS1, GMON, OVP_TEMP, OVP_SET, CROWBAR VOLTAGE OUT TEMP MONITOR 5V PVCC1 BIAS INTVCC3 22µF 16V M1 5V 9V TO 14V 22µF 16V PWM U2 LTM4636 OPTIONAL TEMP MONITOR FOR TELEMETRY READBACK ICs M1: 5UD50N03-07 66.5k (130°C) TEMP+ TEMP– SNSP1 SNSP2 SGND PGND 4.99k 20k 22µF 100k TMON RUNC RUNP HIZREG INTVCC1 22µF 16V PVCC OVP_SET OTP_SET CROWBAR OPTIONAL TEMP MONITOR FOR TELEMETRY READBACK ICs 22µF 16V TIMER INTVCC 34.8k CLK1 CLK2 5V PVCC2 BIAS COMPA COMPB TK/SS 9V TO 14V 20k FLT AUX_UV1 TRIP FB SENSE TRIP 150µF 35V PINS NOT USED IN CIRCUIT U2: PGOOD, TEST1, TEST2, TEST3, TEST4, VOUTS1, GMON GATE 0.01µF 10k + RUNC RUNP INTVCC2 10k 1k 100k VIN INTVCC M2 PSMN2R0-30YLE 10k RED LED 22µF 16V COMP TK/SS 10nF RED LED 22µF 16V 2200pF VOUT VFB GND_SNS VFB + 470µF 470µF 6.3V + 6.3V 100µF 6.3V ×3 TEMP+ TEMP– SNSP1 SNSP2 SGND PGND OPTIONAL TEMP MONITOR FOR TELEMETRY READBACK ICs 46361 F28 Figure 28. 12V to 0.9V, A1/60A with Circuit Breaker Front End and Overtemperature and Overvoltage Protection 32 46361fa For more information www.linear.com/LTM4636-1 LTM4636-1 TYPICAL APPLICATIONS 46361 F29 Figure 29. DC2448A Demo Board VIN to VOUT Short VOUT 1V/DIV CROWBAR GATE 5V/DIV SWITCH 10V/DIV VIN AFTER HOT SWAP CIRCUIT BREAKER 10V/DIV 100ms/DIV 46361 F30 Figure 30. Thermal Plot, 12V to 0.9V at 160A, 400LFM Air Flow 46361 F31 Figure 31. 12V to 0.9V Overvoltage Trip 95 90 VOUT 31mV DROOP EFFICIENCY (%) 85 80 75 70 30A/µs STEP 65 60 46361 F34 0 20 40 60 80 100 120 140 160 LOAD CURRENT (A) INTERNAL COMPENSATION COUT = 8X 470µF 6V TPD POS CAP, 16 × 100µF CERAMIC FURTHER OPTIMIZATION CAN BE UTILIZED WITH EXTERNAL COMP 46361 F32 Figure 32. Efficiency, 12V to 0.9V at 160A Figure 33. 12V to 0.9V 30A/µs Load Step 46361fa For more information www.linear.com/LTM4636-1 33 LTM4636-1 PACKAGE DESCRIPTION PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY. Pin Assignment Table (Arranged by Pin Number) PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 VOUT B1 VOUT C1 VOUT D1 VOUT E1 PGOOD F1 SNSP2 A2 VOUT B2 VOUT C2 VOUT D2 VOUT E2 RUNC F2 SNSP1 A3 VOUT B3 VOUT C3 VOUT D3 VOUTS1– E3 TRACK/SS F3 HIZREG A4 VOUT B4 VOUT C4 VOUT D4 VOUTS1+ E4 VFB F4 SGND A5 VOUT B5 VOUT C5 VOUT D5 COMPB E5 COMPA F5 TEST2 A6 VOUT B6 VOUT C6 VOUT D6 GND E6 GND F6 INTVCC A7 VOUT B7 VOUT C7 VOUT D7 GND E7 GND F7 GND A8 VOUT B8 VOUT C8 VOUT D8 GND E8 GND F8 GND A9 VOUT B9 VOUT C9 VOUT D9 GND E9 GND F9 PVCC A10 VOUT B10 VOUT C10 VOUT D10 OVER_TEMP E10 OVP_TRIP F10 GND A11 VOUT B11 VOUT C11 VOUT D11 VOUT E11 CROWBAR F11 OTP_SET A12 VOUT B12 VOUT C12 VOUT D12 VOUT E12 OVP_SET F12 GND PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 GND J1 GND K1 GND L1 GND M1 GND G2 GND H2 TEST3 J2 GND K2 GND L2 GND M2 GND G3 CLKOUT H3 MODE/PLLIN J3 GND K3 GND L3 GND M3 GND G4 SGND H4 TEST1 J4 VIN K4 VIN L4 VIN M4 VIN G5 FREQ H5 VIN J5 VIN K5 VIN L5 VIN M5 VIN G6 GND H6 VIN J6 VIN K6 VIN L6 VIN M6 VIN G7 PHMODE H7 PWM J7 VIN K7 VIN L7 VIN M7 VIN G8 RUNP H8 TMON J8 GND K8 VIN L8 VIN M8 VIN G9 BIAS H9 GMON J9 GND K9 GND L9 GND M9 GND G10 GND H10 GND J10 GND K10 GND L10 GND M10 GND G11 TEMP– H11 GND J11 GND K11 SW L11 SW M11 GND G12 TEMP+ H12 GND J12 GND K12 GND L12 GND M12 GND 34 46361fa For more information www.linear.com/LTM4636-1 LTM4636-1 PACKAGE DESCRIPTION TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 A VOUT VOUT VOUT B VOUT C VOUTS1– VOUTS1+ COMPB VOUT VOUT OVER_TEMP D VFB COMPA HIZREG SGND TEST2 INTVCC CLKOUT SGND FREQ GND PGOOD RUNC TRACK/SS SNSP2 SNSP1 GND OVP_TRIP CROWBAR OVP_SET E OTP_SET PVCC GND F GND PHMODE RUNP BIAS PWM TMON GMON TEMP– TEMP+ G GND TEST3 MODE/PLLIN TEST1 H VIN GND J GND GND VIN VIN GND SW K SW L GND GND VIN VIN GND M PACKAGE PHOTO 46361fa For more information www.linear.com/LTM4636-1 35 aaa Z 0.630 ±0.025 Ø 144x 3.1750 (2.4) (2.4) SUGGESTED PCB LAYOUT TOP VIEW 1.9050 PACKAGE TOP VIEW E 0.6350 0.0000 0.6350 (3.0) 1.9050 4 5.7150 (10.0) 3.1750 PIN “A1” CORNER (3.0) (11.20) 5.7150 Y For more information www.linear.com/LTM4636-1 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850 X D aaa Z NOM 7.07 0.60 2.41 0.75 0.63 16.00 16.00 1.27 13.97 13.97 0.41 2.00 4.06 0.46 2.05 4.21 0.15 0.10 0.20 0.30 0.15 A2 SUBSTRATE THK MOLD CAP HT INDUCTOR HT BALL DIMENSION PAD DIMENSION BALL HT NOTES DETAIL B PACKAGE SIDE VIEW EPOXY/SOLDER MAX 7.42 0.70 2.51 0.90 0.66 DIMENSIONS H1 TOTAL NUMBER OF BALLS: 144 0.36 1.95 3.76 MIN 6.57 0.50 2.31 0.60 0.60 Z SUBSTRATE ddd M Z X Y eee M Z DETAIL A SYMBOL A A1 A2 b b1 D E e F G H1 H2 H3 aaa bbb ccc ddd eee b1 DETAIL B H2 MOLD CAP Øb (144 PLACES) H3 ccc Z A1 A (Reference LTC DWG # 05-08-1937 Rev D) 144-Lead (16mm × 16mm × 7.07mm) Package (Reference LTCBGA DWG # 05-08-1937 Rev D) // bbb Z 36 6.9850 BGA Package 144-Lead (16mm × 16mm × 7.16mm) Z e b 11 10 9 7 G 6 e 5 PACKAGE BOTTOM VIEW 8 4 3 2 1 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 4 7 TRAY PIN 1 BEVEL ! PACKAGE IN TRAY LOADING ORIENTATION µModule M L K J H G F E D C B A 7 SEE NOTES PIN 1 BGA 144 1016 REV D PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY 6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu OR Sn Pb EUTECTIC 5. PRIMARY DATUM -Z- IS SEATING PLANE BALL DESIGNATION PER JEP95 3 2. ALL DIMENSIONS ARE IN MILLIMETERS. DRAWING NOT TO SCALE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 COMPONENT PIN “A1” 3 SEE NOTES F b 12 DETAIL A LTM4636-1 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTM4636-1#packaging for the most recent package drawings. 46361fa 4.4450 4.4450 6.9850 LTM4636-1 REVISION HISTORY REV DATE DESCRIPTION A 12/17 Changed Turn-On-Time TYP from 50ms to 750µs PAGE NUMBER 3 46361fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more www.linear.com/LTM4636-1 tion that the interconnection of itsinformation circuits as described herein will not infringe on existing patent rights. 37 LTM4636-1 TYPICAL APPLICATION 5V to 2.5V at 30A Design INTVCC 5V + 22µF 16V 100µF 25V 22µF 16V 22µF 16V 22µF 16V 22µF 16V COMPA COMPB TK/SS 15k CSS 0.1µF VIN INTVCC TMON INTVCC PINS NOT USED IN CIRCUIT LTM4636-1: CLKOUT, GMON, PGOOD, PHMODE, PWM, SW, TEST1, TEST2, TEST3, CROWBAR, BIAS, OVP_SET, OTP_SET, OVER_TEMP, OVP_TRIP VOLTAGE OUT TEMP MONITOR 2.5V AT 35A VOUT SGND 0.1µF 22µF PVCC VOUTS1+ RUNC RUNP HIZREG LTM4636-1 + 470µF 4V + – 47k SGND VOUTS1 VFB FREQ MODE/PLLIN TEMP+ TEMP– SNSP1 SNSP2 SGND PGND OPTIONAL TEMP MONITOR FOR TELEMETRY READBACK ICs 100µF ×3 6.3V 470µF 4V 47pF RFB 1.58k 46361 TA02 SGND DESIGN RESOURCES SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design: • Selector Guides • Demo Boards and Gerber Files • Free Simulation Tools µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. Manufacturing: • Quick Start Guide • PCB Design, Assembly and Manufacturing Guidelines • Package and Board Level Reliability 2. Search using the Quick Power Search parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTM4609 Buck-Boost DC/DC µModule Family All Pin Compatible; Up to 5A; Up to 36VIN, 34VOUT 15mm × 15mm × 2.82mm LTM4612 Ultralow Noise High VOUT DC/DC µModule Regulator 5A, 5V ≤ VIN ≤ 36V, 3.3V ≤ VOUT ≤ 15V, 15mm × 15mm × 2.82mm Package LTM4627 15A DC/DC µModule Regulator 4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5V, LGA and BGA Packages LTM4620 Dual 13A, Single 26A DC/DC µModule Regulator Up to 100A with Four in Parallel, 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 2.5V LTM4636 LTM4636-1 without Overvoltage/Overtemperature Protection 4.75V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 3.3V, 16mm × 16mm × 7.12mm BGA 38 46361fa LT 1217 REV A • PRINTED IN USA For more information www.linear.com/LTM4636-1 www.linear.com/LTM4636-1 LINEAR TECHNOLOGY CORPORATION 2017