ATA5279/ATA5279C
Antenna Driver for Multiple Antennas
DATASHEET
Features
● Six connections for series-resonant LF coil antennas
● Drives up to 1A peak current on the first three channels and up to 700mA peak on
the second three, largely independent of the battery voltage
● On-off-keyed data modulation with up to 5.7Kbit/s (manchester coded)
● Sinusoidal-like output signal for superior EMC behavior
● 20 selectable steps for current regulation for field strength measurement (RSSI)
● Output driver stages are protected against electrical and thermal overload
● Very low power-down current consumption
● SPI interface for easy microcontroller bus connection
● LF data buffer to minimize microcontroller’s CPU load during a data transmission
● Small outline package: QFN48, 7mm × 7mm
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1.
Description
The Atmel® ATA5279 is an LF coil driver IC intended for passive entry/-go (PEG) systems. It can drive up to six lowfrequency-antennas (i.e., coils) to provide a wake-up and initialization channel to the key fob.
Figure 1-1. Block Diagram
VS
VCC
OSCI
Oscillator
Internal Supply
POR, BG, UV/OV
OSCO
PGND
VDS
Boost
Controller
HP 1-3
SPI
LF Data Buffer
A3P
Sine Wave
Generator
LP 1-3
A6P
MISO
Return Line
Driver
VIF
IRQ
BCNT
A4P
A5P
MOSI
NRES
A1P
A2P
DC
DC
S_CS
S_CLK
VL
Control Logic
Communication
Protocol Handling
Driver Stage
Control
A1N
A2N
A3N
Integrator
A4N
A5N
MACT
A6N
VSHF
Sample
and Hold
Zero Cross
Detector
Reference
AGND
2
ATA5279/ATA5279C [DATASHEET]
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RGND
CINT
VSHS
Pin Configuration
VL3
PGND3
VL2
PGND2
VL1
PGND1
VDS3
IRQ
NRES
S_CLK
S_CS
MOSI
Figure 2-1. Pinning QFN48
A6N1
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
8
29
9
28
27
10
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
Atmel
ATA5279
Table 2-1.
MISO
AGND3
A6P
A3P
A5P
AGND2
A2P
A4P
AGND1
VDS2
A1P
A1N2
VSHF2
A2N1
A2N2
VDS1
A4N1
A4N2
A1N1
VS
RGND
CINT
VCC
VSHS
VIF
OSCI
OSCO
MACT
BCNT
VSHF1
A6N2
A3N1
A3N2
A5N1
A5N2
2.
Pin Description
Pin
Symbol
Heat Slug
PGND
Function
Pin Group
Backside ground connection
-
1
VS
Battery supply pin
-
2
RGND
Reference ground
-
3
CINT
Integration capacitor connection
-
4
VCC
Analog 5V stabilization capacitor connection
-
5
VSHS
Shunt resistor voltage sense input
-
6
VIF
Digital supply voltage input
-
7
OSCI
Oscillator input pin
CSP
8
OSCO
Oscillator output pin
CSP
9
MACT
Modulator active indicator output pin
DO
10
BCNT
LF-bit counter output pin
DO
11
VSHF1
Shunt resistor driving pin 1
RLO
12
A6N1
Coil 6 negative connection line pin 1
LRL
13
A6N2
Coil 6 negative connection line pin 2
LRL
14
A3N1
Coil 3 negative connection line pin 1
HRL
15
A3N2
Coil 3 negative connection line pin 2
HRL
16
A5N1
Coil 5 negative connection line pin 1
LRL
17
A5N2
Coil 5 negative connection line pin 2
LRL
18
VSHF2
Shunt resistor driving pin 2
RLO
19
A2N1
Coil 2 negative connection line pin 1
HRL
20
A2N2
Coil 2 negative connection line pin 2
HRL
21
VDS1
Driver supply pin 1
DS
22
A4N1
Coil 4 negative connection line pin 1
LRL
23
A4N2
Coil 4 negative connection line pin 2
LRL
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Table 2-1.
4
Pin Description (Continued)
Pin
Symbol
Function
Pin Group
24
A1N1
Coil 1 negative connection line pin 1
HRL
25
A1N2
Coil 1 negative connection line pin 2
HRL
26
A1P
Coil 1 positive connection line pin
HDL
27
VDS2
Driver supply pin 2
DS
28
AGND1
Driver ground pin 1
-
29
A4P
Coil 4 positive connection line pin
LDL
30
A2P
Coil 2 positive connection line pin
HDL
31
AGND2
Driver ground pin 2
-
32
A5P
Coil 5 positive connection line pin
LDL
33
A3P
Coil 3 positive connection line pin
HDL
34
A6P
Coil 6 positive connection line pin
LDL
35
AGND3
Driver ground pin 3
-
36
MISO
Master-In-Slave-Out SPI output pin
DO
37
MOSI
Master-Out-Slave-In SPI input pin
DI
38
S_CS
SPI chip select pin
DI
39
S_CLK
SPI clock input pin
DI
40
NRES
Chip reset input pin
DI
Interrupt request output pin
DO
Driver supply pin 3
DS
Boost converter low-side switch output 1
-
Boost converter low-side switch input 1
BLS
Boost converter low-side switch output 2
-
Boost converter low-side switch input 2
BLS
Boost converter low-side switch output 3
-
Boost converter low-side switch input 3
BLS
41
IRQ
42
VDS3
43
PGND1
44
VL1
45
PGND2
46
VL2
47
PGND3
48
VL3
ATA5279/ATA5279C [DATASHEET]
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3.
Functional Description
3.1
Operation Modes
Atmel® ATA5279 features five operation modes. They are:
● Power-down mode (reset state)
●
●
●
●
Idle mode
Operating mode
Shutdown mode
Diagnosis mode
Power-down mode is active after supply voltages have been applied to the chip. No internal circuitry is active in this mode
and as such power consumption is minimal. If no operation of the chip is demanded, it should be kept in this state. To enter
power-down mode, a negative pulse on the NRES pin for at least tNRES,min is required.
After wake-up from power-down mode by a logic high signal at the S_CS pin, the chip is in idle mode. That is, the oscillator
is running and the control logic waits for commands coming from the serial interface. Furthermore, the selected output driver
stage is ready for operation (the voltage on the corresponding output pin AxP is approximately half the battery supply
voltage). The current consumption of the chip is now mainly defined by the cross current through the active driver stage
(please refer also to Section 3.2 “Coil Driver Stage” on page 6).
When processing coil driving commands, the chip is in operation mode. From the interface point of view, there is no
difference from the idle mode; however, current consumption is now higher as the output driver stages are operating and,
depending on the selected output current, the DC-DC converter is also operating.
If a connection failure (short circuit on any of the coil connection lines) is detected, the ATA5279 enters the shutdown mode
to protect itself from damage. In this mode, the interface operates in idle mode but with all power stages shutdown and no LF
transmission command processing. This mode should be exited using the Reset Fault Status command (see below),
however, it can also be exited by resetting the chip.
In diagnosis mode, the output driver stages are also disabled. In their place, high-ohmic current sources are activated that
can be programmed via the serial interface in order to check the coil connection lines for failures. This mode can be exited by
an appropriate SPI command or by resetting the chip.
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3.2
Coil Driver Stage
The driver stage for each coil consists of two N-channel DMOS transistors. The low-side transistor is in Darlington
configuration to maintain a source-follower characteristic.
Figure 3-1. Principle Driver Stage Setup
VDS
IHSDiag
IHS
Diag Enable
Nmirr
VSin_pre
AxP
Ax_State
Pmirr1
Pmirr2
Npwr
Diag Enable
Internal nodes
ILS
ILS
ILSDiag
GND
In the graphic above, the names of internal pins have a grey shaded background, and the hatched area is not part of the
driver stage itself but only used in diagnostic mode (please refer to the Diagnosis Block description for further information on
this topic).
The driver stages are supplied by the three VDS pins, which are tied together inside the chip.
A quiescence current regulation ensures low cross current while in idle state. The output transistors are monitored for current
and temperature to protect them from damage caused by irregular load conditions or too high ambient temperatures.
The driving stage is optimized for signal quality to ensure low harmonic distortions.
Two groups of driver stages are integrated: the first group is intended for high-current coils, whereas the second group
drives low-current coils. Note that there are certain coil impedance ranges for each driver group. If the connected load
exceeds this range, proper current regulation and/or data modulation is not guaranteed.
While in idle mode and especially during a transmission, the driver stages of the five inactive (i.e., not selected) coils are
switched to high-side outputs, i.e., the positive coil connection lines are tied to the VDS potential. The same applies to the
return line inputs AxN. These measures ensure minimum parasitic currents in the disabled coils while the selected coil is
operating.
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3.2.1
Driver Stage
The return line stage is built by an open drain NMOS equipped with a free wheel diode. In parallel to the diode there is a pullup resistance to terminate the inactive antenna coils.
Figure 3-2. Principle Return Line Stage
VDS
IHSDiag
100kΩ
Diag Enable
AxN
AxN_State
VSHF
Diag Enable
ILSDiag
GND
Similar to the driver stage the components within the grey area describe the functionality in diagnosis mode.
Table 3-1.
States of Driver Outputs within Operation Modes
Mode
Operation/
Transmission Mode
Output Entering by SPI cmd
Shutdown Mode
Fault has detected
Idle Mode
Entering by S_CS
AxP
Selected driver active
others are on High
Level (VDS)
Selected driver stays
on VDS/2 ready for
All high impedance
Operation
Others are on High
Level
AxN
Selected driver stays
on low level
Others are on High
Level
Selected driver stays
on low level
All high impedance
Others are on High
Level
Power Down/Reset
Entering by NRES or
POC
Diagnosis Mode
Entering by SPI
High impedance
High impedance
(Diagnosis current
sources
programmable)
High impedance
High impedance
(Diagnosis current
sources
programmable)
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3.3
Sine Wave Generator
The sinusoidal coil-driving signal is internally generated. Its amplitude is dependant on the measured coil current, and the
frequency is derived from the oscillator stage. In conjunction with the output driver stages, the generated signal is optimized
for low harmonic distortions.
The peak-to-peak amplitude of the sinusoidal signal is directly defined by the voltage on the external integration capacitor
connected to the CINT pin. This voltage, with an offset subtracted, is internally used to generate a low-voltage sine wave
signal, which is in turn amplified and level-shifted up to the desired output level.
The output signal itself has a DC offset close to the half of the supply voltage, and the maximum possible amplitude has
about 3V distance to each of the supplies. Figure 3-3 illustrates this.
Figure 3-3. Maximum Possible Coil Driving Signal for a Given Supply Voltage VDS
VDS
VOUT,max
0.5 x VDS
VOUT,min
GND
In application, the output coil current is the fixed valued (selectable via SPI). Hence, the required output voltage is calculated
as follows:
V Out,p = I Coil,p × ( Z Coil + R DSon,HRS/LRS + R Shunt )
Here, ZCoil is the complex impedance of the coil, RDSon,HRS/LRS is the on-resistance of the appropriate return line current
selector (see also Section 8. “Functional Parameters” on page 29) and RShunt is the resistance of the externally applied
current sense shunt resistor (typ. 1Ω, see also Section 4. “Application” on page 26).
3.4
Boost Converter
The coil driver stage can be supplied by a DC-DC converter in boost configuration. Together with an externally applied
choke, freewheeling diode and capacitor, the battery voltage can be brought up to the required value, which is dependant on
the coil's impedance and the selected current. The converter is only enabled during an active transmission. The peak current
through the low-side switch IVL and the output voltage VVDS are measured to shut down the converter operation in case one
of the values exceeds its upper limit.
Note:
There is no dedicated temperature monitoring for the boost converter low-side switch. For further details,
please refer to Section 4.1 “Application Hints” on page 27.
The switching frequency is, like the coil driving signal, derived from the oscillator stage and 125kHz in value when using an
8MHz input clock. The least possible time the boost converter takes to generate the maximum possible output voltage from
the minimum possible input voltage is dependant on several parameters. The values of the external components (choke
inductance, charge capacitance and CINT integration capacitance) greatly effects this time.
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3.5
Coil Current Sensing (Zero Cross, Sample and Hold, Integrator)
The coil current flows through an external shunt resistor, causing a current-dependant voltage, which is fed into the IC via
the VSHS pin. By monitoring the zero crossing events of this signal, the phase of the coil current is known and hence the
positive peak value can be sampled. The VSHS voltage is sampled at T/4 after the zero cross event.
The peak coil current is then subtracted from an internal reference voltage that is dependant on the selected coil current,
which results in the regulation difference.
An amplifier stage converts this difference into a current, which is then fed into an externally applied integration capacitor
connected to the CINT pin. The resulting voltage on this capacitor directly influences the amplitude of the sine wave signal. It
also determines the supply voltage generated by the boost converter, if the necessary coil supply voltage exceeds the actual
supply voltage level. Note that during an active transmission, this voltage is internally limited to VCINT,max.
Note that in idle mode, the voltage on the integration capacitor is kept at a value that corresponds to the battery supply
voltage. This ensures that the boost converter, if needed, always performs a soft start from the battery voltage level on.
The desired current can be selected via the SPI. A total of 20 predefined steps are available, divided into the following
sections:
● The lower four steps (50mA to 200mA) are intended for the low-current coils only
●
●
The next ten steps (250mA to 700mA) are intended for both types of coils
The upper six steps (750mA to 1A) are intended only for the high-current coils
The IC allows the use of a current step not intended for a particular driver group; however, in this case, full functionality,
especially a stabilized coil current, cannot be guaranteed. See also the Control Logic block description for an overview over
the commands.
3.6
Diagnosis
The diagnosis stage monitors both the positive (AxP) and negative (AxN) connection lines of the six coils. If one of these
lines is shorted to battery supply or to ground, the following measures are taken for protection and diagnostic reasons:
● All coil driver stages are shut down, i.e., put into high impedance state
●
●
●
The shunt resistor is disconnected from the coil return lines
The reason for the fault shutdown is stored in the fault register
An interrupt request is triggered (see also control logic block)
In addition to short circuits, a disconnected coil (i.e., open load) or an excessive junction temperature can also lead to such a
fault shutdown.
Note that this type of diagnosis is carried out continuously during normal operation of the IC to protect both the IC and the
peripherals from damage.
It must be avoided to design the system's load profile in such a way that the protection features of the chip are triggered
under normal operating conditions. Consecutive triggering of the overtemperature shutdown may lead to a reduced lifetime.
In the event of such a fault shutdown, the IC can be brought back to operation by resetting its fault register with the
appropriate SPI command (please refer also to the Section 3.9.2 “General Command Description” on page 20 later in this
document). As a result, transmission on non- faulty coils is still possible even if there is a failure of one coil.
Beyond this, the diagnosis of all connected coil lines is a very useful tool for maintenance reasons. The Atmel® ATA5279 has
implemented test structures that can be activated and read out via SPI commands, so that the microcontroller can be
programmed to detect most of the possible faults, for example, shorts between different coil connection lines and multiple
shorts in one pair of lines.
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3.6.1
Functional Description of Diagnosis Mode
In this diagnosis mode, the coil-line drivers themselves are switched to high impedance. Hence, only the test structure at
every coil connection (both at the positive outputs AxP of the drivers and at the negative outputs AxN) is present and can
directly test the status of the line. Figure 3-4 illustrates this:
Figure 3-4. Base Structure of the Diagnosis Module of One Output Channel
VDS
VDS
S_HxP
c0 = '1'
S_HxN
c1 = '1'
AxP
c0 bit
AxN
c1 bit
S_LxN
c1 = '0'
S_LxP
c0 = '0'
AGND
AGND
Latch
Driver x select
c0, 1 bits
The structure above can be found in each of the six channels of the Atmel® ATA5279. As soon as the diagnosis mode is
engaged, all channels are operated in this way. On the channel that is actually selected, the setting of the switches can be
changed with the Set Coil Current command and the status of the two connection lines can be checked with the Get Driver
Setup command.
The two switches in the P line driver are controlled with one bit. That means, either the high-side (S_HxP) or the low-side
(S_LxP) switch is closed. The same is true for the N line driver (S_HxN, S_LxN). The controlling bits c0 and c1 are taken from
the coil current selection register (see Section 3.9.2 “General Command Description” on page 20 in this document).
Note that the setting of the switches is latched. That means, if the setting on the switches of the selected driver is changed,
the setting on the five other channels remains unchanged.
By a combination of test structures, many different faults, even between the coils, can be detected.
As described in the principle schematic of a driver stage above, a test structure consists of two switchable current sources
(one to VDS and one to GND) and a comparator that converts the voltage level on the line into a digital signal. An internal
comparator monitors the output level of the AxP and AxN stage referring to a threshold level of ½ VDS. The switches for the
current sources can only be controlled in diagnosis mode, with the corresponding coil being selected (see also Driver
Command description). Note that one switch is always closed, either the high-side or the low-side switch of one test
structure. These structures are independent, i.e., they can be set up for each line individually and at the same time.
The status of the connection lines of the selected coil can be read out with a SPI command.
Note:
10
To leave the Diagnosis Mode a “Reset Fault Status” command need to be sent at the end.
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In the following example, there is a short circuit between the positive coil connections of coil 1 and 2.
Figure 3-5. Example 1, Using the Diagnosis Mode
VDS
S_H1P
S_H2P
A1P
RShort
A2P
S_L1P
S_L2P
Status_1
Status_2
GND
Taking the circuit situation shown above, the test run starts with both S_L1P and S_L2P switches closed (default state when
entering the diagnosis mode for the first time). The read-back of the line state result in both times 0, which is not unexpected.
However, the result does not change when either altering the channel 1 or the channel 2 switch setting. That can be caused
both by the failure shown above and by short-circuits of both lines to ground. The final diagnosis can be identified by
changing both channels to the high-side switches (S_H1P and S_H2P). In this case, the two status lines both return 1s –
which eliminates the possibility of two short-circuits to ground.
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Table 3-2 summarizes this test sequence.
Table 3-2.
Sequence for Example 1, Using the Diagnosis Mode
Step
Command
I/O
Coding
1
Select Driver
I
00101001 – 29h
Selects driver 1 with Diagnosis Mode enabled
2
Get Driver Setup
I
O
01101000 – 68h
00000001 – 01h
Reads back active driver info:
Channel 1 active, both lines return a 0
3
Select Driver
I
00101010 – 2Ah
Selects driver 2 with Diagnosis Mode enabled
4
Get Driver Setup
I
O
01101000 – 68h
00000010 – 02h
Reads back active driver info:
Channel 2 active, both lines return a 0
5
Set Coil Current
I
10100001 – A1h
6
- no command -
7
Get Driver Setup
I
O
01101000 – 68h
00000010 – 02h
Reads back active driver info:
Channel 2 active, but both lines return a 0
8
Select Driver
I
00101001 – 29h
Selects driver 1 with Diagnosis Mode enabled
9
Set Coil Current
I
10100001 – A1h
Closes test switches S_H1P and S_L1N (Note: S_L1P
and S_H1N are then open)
10
- no command -
11
Get Driver Setup
I
O
01101000 – 68h
00001001 – 09h
Reads back active driver info:
Channel 1 active and A1P returns a 1
12
Select Driver
I
00101010 – 2Ah
Selects driver 2 with Diagnosis Mode enabled
13
Set Coil Current
I
10100000 – A0h
14
- no command -
15
Get Driver Setup
Note:
Actions/Remarks
Closes test switches S_H2P and S_L2N
Note:
S_L2P and S_H2N are then open
Wait for the test structures to stabilize in the new setting,
see below
Wait for the test structures to stabilize in the new setting,
see below
Closes test switches S_L2P and S_L2N
Note:
S_H2P and S_H2N are then open
Wait for the test structures to stabilize in the new setting,
see below
I
01101000 – 68h
Reads back active driver info:
O
00000010 – 02h
Channel 2 active and A2P returns a 1
Steps 6, 10 and 14 are wait states, as the test structures need some time to stabilize in their new setting. This
depends mainly on the externally applied capacitors on the AxP and the AxN pins.
The suggested waiting time is calculated as follows:
V S × ( C e + C ant )
t diag,wait = ---------------------------------------300 µA
The sequence above is an example of how the failure illustrated in Figure 3-5 on page 11 could be detected. Depending on
the grade of detection detail that is required, a matrix for the test sequence should be set up to find the most effective way of
programming and testing. For more details on the commands, please refer also to Section 3.9.2 “General Command
Description” on page 20.
The second example circuit has two faults in the circuitry.
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Figure 3-6. Example 2, Using the Diagnosis Mode
VDS
RShort1
S_H4P
S_H4N
A4P
A4N
S_L4P
S_L4N
RShort2
Status_4
Status_4N
GND
If channel four is activated in normal operation, a fault shutdown will occur. The reason for this shutdown (i.e., the entry in the
fault register) could either be an overload on the A4P line (here a short circuit to VS) or a short-circuit on the A4N line to VS.
In any case, the IC protects itself and the external components from damage; however, the fact that there is more than one
failure in the wiring cannot be discovered.
In diagnosis mode, by testing the A4P line with S_H4P and S_L4P, the short circuit to VS could be found first. The same
result would be found when testing the return line switch 4 accordingly, so the presence of more than one fault on coil 4 is
determined. The precise fault cannot be found though. The diagnosis result would be the same both for the above shown
circuit and for the A4N line being directly shorted to VS (without the failure in the coil module, here RShunt2) and for the
combination of the two.
Table 3-3.
Sequence for Example 2, Using the Diagnosis Mode
Step
Command
I/O
Coding
Actions / Remarks
1
Select Driver
I
00101101 – 2Dh
Selects driver 4 with Diagnosis Mode enabled
2
Get Driver Setup
I
O
01101000 – 68h
00011101 – 15h
Reads back active driver info:
Channel 4 active, A4N returns a 1
3
Set Coil Current
I
10100010 – A2h
Closes test switches S_L4P and S_H4N
Note:
S_H4P and S_L4N are open then
Wait for the test structures to stabilize in the new
setting, see first example
4
- no command -
5
Get Driver Setup
I
O
01101000 – 68h
00011101 – 1Dh
6
Set Coil Current
I
10100000 – A0h
7
- no command -
8
Get Driver Setup
Reads back active driver info:
Channel 4 active, both lines return a 1
Closes test switches S_L4P and S_L4N
Note:
S_H4P and S_H4N are open then
Wait for the test structures to stabilize in the new
setting, see first example
I
O
01101000 – 68h
00010101 – 15h
Reads back active driver info:
Channel 4 active and A4N returns a 1
Again, this is only an example of how the diagnosis system can be used. Generally, a more systematic approach is
suggested in order to efficiently test all connection lines used.
Note:
To exit the diagnosis mode correctly, two SPI commands have to be sent: the first is the Select Driver command with the DM bit set to 0 and the second is a Reset Fault Status command. See also SPI Command
Description.
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3.7
SPI
The SPI is used to select the required coil and its current, to provide LF data to the IC, to select and start an LF transmission,
and to read out status information. It is equipped with a chip select input to enable or disable communication. When disabled,
the data output of the IC is in high impedance mode, so other devices may communicate on the same bus.
If the device is woken up from power-down mode (S_CS=1) a wait time of > 200µs has to be considered before sending a
SPI command. This time is needed to start up the internal supply voltage and settling the resonator frequency.
The interface is configured as a slave device, always requiring a master (e.g., a microcontroller) for operation. The maximum
input clock frequency is 1/4 of the system clock present at the OSCI pin, resulting, for example, in a maximum signal speed
of 2 Mbit/s when using a typical 8MHz input clock. The SPI features four different operation modes, which only differ in the
relationship between the clock signal (S_CLK) and the data I/Os.
Both the SPI itself and the corresponding I/O lines are supplied by the application-provided logic supply voltage connected to
the VIF pin. This ensures that the controller (master) and the IC (slave) operate with the same voltage levels.
In total, four modes of operations are possible, each differing in clock polarity and phase.
Figure 3-8 and Figure 3-9 illustrate this.
Figure 3-7. SPI Operation in POL = 1 and PHA = 1 Mode (Default Mode after Reset)
Sample
S_CS
Setup
S_CLK
MISO
Z
X
MOSI
X
X
Z
LSB
1
2
3
4
5
6
MSB
X
Figure 3-8. SPI Operation in POL = 0 and PHA = 0 Mode
Sample
S_CS
Setup
S_CLK
14
MISO
Z
MOSI
X
LSB
1
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2
3
4
5
6
MSB
X
Z
X
X
Figure 3-9. SPI Operation in POL = 1 and PHA = 0 Mode
Sample
S_CS
Setup
S_CLK
MISO
Z
MOSI
X
LSB
1
2
3
4
5
6
MSB
X
Z
X
X
Figure 3-10. SPI Operation in POL = 0 and PHA = 1 Mode
Sample
S_CS
Setup
S_CLK
MISO
Z
X
MOSI
X
X
Z
LSB
1
2
3
4
5
6
MSB
X
The configuration mode can be selected with the appropriate SPI command (see Section 3.9.2 “General Command
Description” on page 20). Note that after power-up or a reset, the IC is always in its default configuration (POL = 1, PHA = 1),
which must be used to alter the configuration. At the end of the SPI configuration-changing command, the new configuration
is activated with the falling edge of the S_CS signal.
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3.7.1
Timing
Figure 3-11 illustrates the timing parameters of the SPI communication.
Figure 3-11. Timing Parameters of the SPI Communication
tIo
tCS,set
tCShold
tSPIoff
thi
S_CS
S_CLK
MISO
Z
MOSI
X
LSB
1
tSPI
tsetup
Note:
Table 3-4.
C
o
n
t
r
tout,valid
MSB
X
X
X
tMISOoff
tMISOon
thold
The diagram above is using POL = 0 and PHA = 0 as a setup for the SPI. The values are also valid for the
other three configurations. The limits for the timing values shown above can be found in Section 8. “Functional
Parameters” on page 29.
States of Control I/Os
Name Pin # Direction
S
P
I
6
X
Operation/
Transmission Mode
Entering by SPI cmd
Shutdown Mode
Fault has detected
Idle Mode
Entering by S_CS
Power Down/Reset
Entering by NRES or
POC
S_CS
38
Input
Weak-pull-down
Weak-pull-down
Weak-pull-down
Weak-pull-down
S_CLK
39
Input
High impedance
High impedance
High impedance
High impedance
MOSI
37
Input
High impedance
High impedance
High impedance
High impedance
MISO
36
Push-pull Tristate (S_CS = low)
Tristate (S_CS = low)
Tristate (S_CS = low)
Tristate (S_CS = low)
output Low/High (S_CS = high) Low/High (S_CS = high) Low/high (S_CS = high) Low/high (S_CS = high)
VIF
6
Input
Supply current
Supply current
Supply current
Supply current
NRES
40
Input
Weak-pull-up
Weak-pull-up
Weak-pull-up
Weak-pull-up
IRQ
41
Push-pull
output
Low/high(1)
Low/high(1)
Low/high(1)
High
BCNT
10
Push-pull
output
Low/high(1)
Low
Low
Low
Low
Low
MACT
Push-pull
High
Low
output
State dependant on modulation, chip state or SPI data
9
Note:
1.
16
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3.8
Command Buffer
This buffer is a First-In-First-Out (FIFO)-type buffer, located between the SPI and the modulator stage. The microcontroller
can write coil-driving related commands and data with full SPI speed to keep the CPU and bus load low.
3.8.1
Structure
The buffer can store up to 128bits, organized in 16 words, each eight bit in size. Hence, each data word from the SPI that
contains a control command for the driver stages (i.e., select a certain driver, select a certain current, transmit LF-data bits
and transmit a constant wave) is stored in a buffer word. Figure 3-12 outlines this.
Figure 3-12. Structure of 128-bit FIFO Command Buffer
Data
Selector
8
General Command
Processing
8
Write Pointer
0
7
0
1
7
0
2
7
3
7
4
7
5
7
6
7
7
7
8
7
9
7
10
7
11
7
12
7
13
7
14
7
15
7
128 bit FIFO Buffer
8
From SPI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read Pointer
Modulator Stage
8
The read pointer indicates the next word to be processed by the Modulator Stage, whereas the write pointer indicates the
next free location for data from the SPI. These pointers are controlled by the internal logic to enable the first-in-first-out
functionality.
3.8.2
Usage
After wake-up from power down or failure shut down, the buffer is reset and ready to receive commands and LF data. Any LF
command and data is fed into the buffer via the SPI. The buffer can be filled even during an active data modulation, i.e.,
when some LF data and/or commands remain in the buffer while waiting to be processed. This increases the independency
of the coil driver from the microcontroller. An interrupt request (IRQ) is triggered when the fill state of the buffer drops below
6 data bytes or if too many words are sent and a FIFO overflow occurs.
Seamless data processing is an important feature of the command buffer. LF data intended for the same coil and the same
current step can be distributed to several commands without the risk of having unwanted gaps in the LF telegram. This
allows protocols to have any length and is usable both with the Send LF-data and the Send Carrier command. Refer also to
the Section 3.9.1 “Modulator Stage” on page 18 for further details.
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3.9
Control Logic
The internal control logic handles all information coming from the SPI and controls the power stages. Diagnostic information
is also collected and evaluated here.
3.9.1
Modulator Stage
The modulator stage controls the coil drivers. It gets all necessary information from the command buffer. That is:
● Which coil to drive
●
●
●
●
Which current to maintain in this coil/which diagnosis switch to close (in diagnosis mode)
Which baud rate to use for LF data transmission
What kind of transmission (i.e., data or carrier)
LF data itself (respectively the on-time when a carrier is to be transmitted)
When a modulator operation is started by an SPI command, the data in the buffer is processed in the order it arrives via SPI,
command by command. The time for this data processing depends on the command itself and, if LF transmissions are
involved, the amount and length of the data bits.
Table 3-5 lists the timings for the driver-related commands.
Table 3-5.
Execution Durations of Driver-related Commands
Command
LF Period Counts Comment
Select Driver
64
During the first 32 periods, the actual driver is stopped in order to decay any
oscillation in the coil. Then the switching itself is performed and another 32
periods waiting time is started in order to wait for the new driver to reach its
operation point
Select Coil Curr.
4
The switching time of internal references takes less than 4LF periods. Note
that there will always be an interruption in a telegram if the coil current is
changed between two transmission commands
Send LF Data
N × 2 × {32 / 22}
The duration of this command depends on the selected data rate (3.9Kbit/s,
i.e. 32 periods/LF bit, or 5.7Kbit/s, i.e., 22 periods/LF bit) and the amount of
nibbles N (2LF data bits) to be transmitted
Send LF Carrier
T × (32 / 22)
The duration of this command depends on the selected data rate (see also
above) and the carrier duration T
Note:
Table 3-5 lists the duration of command execution for the different commands and not the decoding or processing time. This is done simultaneous, so that two commands can be executed seamlessly.
LF data is transmitted on-off-keyed (OOK). “1” enables the field, whereas “0” disables it. Note that the field generation
strongly depends on the bandwidth (the Q factor) of the coil. If it is too narrow, the receiver might not be able to decode the
data correctly. Figure 3-13 shows the signal path from the modulator stage to the receiver.
Figure 3-13. Example for OOK-data Modulation with Atmel ATA5279
Modulator Data
off
1
0
Transmitter Coil Current
1
1
1
Current
Envelope
Receiver Detection Thresholds
Receiver Data
18
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off
1
0
1
1
0
1
Coils with high Q values need more periods to reach the desired field strength and hence appropriate detection level
thresholds in the receiver. So the Q factor must be adapted in order to ensure proper data communication. For example, the
thresholds here are chosen at 70% of the required output current for a 0 to 1 and at 30% for a 1 to 0 detection.
The IC supports two data rates: standard, which is 3.9Kbit/s (or 32LF periods), and high speed, rated with 5.7Kbit/s (or 22LF
periods). Note that this refers to the encoded (net) data rate. The minimum length of an active field (e.g., the time for the first
1 in Figure 3-13), is 16LF periods in standard and 11LF periods in high speed mode (i.e., gross data rate).
Another aspect of the LF data transmission is that current regulation can only be done roughly, as the measurement must be
interrupted over and over again. At a 0 to 1 transition, the current measurement will not start until the 5th period, and there
will not be any measurement during a 0-transmission. The regulation precision that is achieved during carrier transmission is
not valid here.
As described in Section 3.8 “Command Buffer” on page 17, data is processed seamlessly to avoid gaps in longer LF
telegrams. The following example illustrates this feature.
Assume that following data words have been written into the command buffer via the SPI:
1. Send 2LF bits (SPI data 00h 05h)
2.
Send carrier with a length of 24 data bits (SPI data 98h)
In this example, the output signal of the modulator resembles the illustration below.
Figure 3-14. Example of Data Transmission of Two Consecutive Commands
First Command
Second Command
Modulator Data
BCNT Signal
2 x tdata
24 x tdata
26 x tdata
The value for tdata depends on the speed setting of the modulator (32LF periods in standard and 22 periods in high speed
mode, with one period being 8µs when operating with 125kHz output frequency and therefore 8MHz system clock).
The least amount of data that can be processed by the modulator stage is four LF bits or two (e.g. Manchester-encoded)
data bits. The first command in the upper example is a minimum-length LF data command.
To ensure the traceability of the LF protocol, two pins are provided, which indicate an active data transmission (MACT) and
the change of an LF bit (BCNT). Figure 3-13 illustrates the function of these two signals:
Figure 3-15. LF Transmission Tracing Signals
Modulator Data
Transmitter Coil Current
off
1
0
1
1
0
1
1
off
Current Envelope
MACT Signal
BCNT Signal
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The MACT signal can be used to start a timer whereas BCNT can be used as input signal to a counter. Note that for carrier
transmissions, only the MACT signal is active. There are not any pulses on the BCNT line.
3.9.2
General Command Description
The following commands are directly processed by the control logic, i.e., they are not fed into the data buffer:
Table 3-6.
Bit Definitions of the General SPI Commands
MSB
6
5
4
3
2
1
LSB
Get status info
LSB
Command
Output Word (MISO Data)
MSB
Input Word (MOSI Data)
6
5
4
3
2
1
0
1
1
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R
F
BO
BU
T
S
Op
X
0
1
1
0
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
C4
C3
C2
C1
C0
DG
D1
D0
0
1
1
1
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DG
D1
D0
T
F03
F02
F01
F00
Reset fault status
0
1
0
0
0
0
0
0
X
X
X
X
X
X
X
X
Set SPI config
0
1
0
0
1
0
PO
PH
X
X
X
X
X
X
X
X
Halt operation
0
1
0
1
0
0
0
0
X
X
X
X
X
X
X
X
Get driver setup
Get fault info
Refer to Section 3.7 “SPI” on page 14 for bit direction definitions.
● Get Status Info:
This command delivers the general IC status information back to the microcontroller (via the SPI bus). One part of the
return word is the interrupt request source. If such a request is active (i.e., the IRQ line is high), the source for it is
coded here.
●
Possible sources include the diagnosis block to indicate a driver stage fault (bit F), a general reset (either triggered
externally by the NRES pin or internally by the power-on reset structure, bit R), an overtemperature of the chip (bit T),
or the FIFO buffer indicating that the fill state has dropped to 6 data bytes or below (bit BU), or the fill state exceeds
the upper limit of 16 bytes (bit BO). The IRQ signal is reset with this command. Additionally, the operability flag of the
IC (bit Op) is returned in the word. Note that only if no fault is stored in the fault register and all operation voltages are
present and valid, the operability is given (indicated by a 1 in the Op bit). Otherwise, Atmel® ATA5279 will not process
any driver-related command. Finally, the LF speed mode bit returned here indicates the current speed state of the
modulator stage (bit S, 0 for normal speed, 1 for high speed).
bit R:
Chip reset - either triggered externally by the NRES pin or internally by the
power on reset structure
bit F:
Indicator for a driver stage fault
bit BO: The FIFO buffer fill state exceeds the upper limit of 16 bytes
bit BU: The FIFO buffer fill state drops to 6 data bytes or below
bit T:
Chip overtemperature indicator
bit S:
LF modulator speed mode indicator
bit Op LF driver stage operability indicator
The IRQ flag is set if one or more of the listed status bits are set. From these the S-bit and Op-bit are excluded. The
IRQ flag can be reset by sending “Get Status Info” command.
●
20
Get Driver Setup:
This command returns the actual setup of the driver stage, i.e., the selected coil, encoded in the bits DG,D1..0, and the
selected current, which can be found in the bits C4..0 (see also “Select Driver” and “Set Coil Current” command
description below for details on bit coding). This command is also used in diagnosis mode to fetch the state of the coil
connection lines.
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●
Get Fault Info:
This command returns the content of the driver stage fault register back to the microcontroller via the SPI bus. The
register contains both the code for the detected fault and the number of the driver stage that was active when the fault
occurred. Refer also to the Section 3.9.4 “Status Monitor” on page 24 for further details.
●
Reset Fault Status:
This command clears the content of the driver stage fault register and sets the operability bit in the general state
register if all supply voltages are present and valid. This command is necessary to resume normal operation following
the occurrence and subsequent removal of a fault. Please note that prior to this command, the active channel should
be switched to a line that is not faulty. Otherwise, the internal logic might get corrupted and must then be reset with a
negative pulse on the NRES line.
Note that this command is also required to bring the Atmel ATA5279 back into operation mode once the diagnosis
mode was active and was then cleared by a Select Driver command.
●
Set SPI Config:
This command changes the two configuration bits PO(L) and PH(A). These bits are responsible for the serial data
processing of the SPI.
Default: PO = 1, PH = 1
●
Halt Operation:
As this command is processed immediately, it is not written to the FIFO buffer even if it is a driver-related command.
The effect of this command is that the content of the FIFO buffer is cleared, hence no new LF data is available, and if
any driver is active it will be stopped. Note that such stops are only carried out at the end of an LF period (i.e., when
the sinusoidal output signal reaches half of the supply voltage).
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3.9.3
Driver-related Command Description
Following commands are processed via the LF data buffer:
Table 3-7.
Bit Definitions of the Driver-Related SPI Commands
6
5
4
3
2
1
6
5
4
3
2
1
LSB
Select driver
0
0
1
BR
DM
DG
D1
D0
X
X
X
X
X
X
X
X
Select coil current
1
0
1
C4
C3
C2
C1
C0
X
X
X
X
X
X
X
X
0
0
0
0
N3
N2
N1
N0
X
X
X
X
X
X
X
X
L7
L6
L5
L4
L3
L2
L1
L0
0
0
0
0
N3
N2
N1
N0
..
..
..
..
..
..
..
..
L7
L6
L5
L4
L3
L2
L1
L0
1
0
0
T4
T3
T2
T1
T0
X
X
X
X
X
X
X
X
Send LF data
Send LF carrier
LSB
Command
MSB
Output Word
MSB
Input Word
●
Select Driver:
This command selects the coil that is to be driven or tested next. The BR-bit indicates the modulation speed (0 for
3.9Kbit/s, i.e., 32LF periods and 1 for 5.7Kbit/s, i.e., 22LF periods).
●
The DG,1..0 bits indicate the channel number to be activated. DG selects the driver group (0 for high-current driver 1..3,
1 for low-current driver 4..6) and D1..0 the required driver in the group (01 for driver 1 / 4, 11 for driver 3 / 6). For
connection line diagnosis, the diagnosis mode can be enabled by setting the DM-bit to 1.
bit BR:
bit DM:
Notes:
LF modulator speed (0 for 3.9Kbit/s, i.e., 32LF periods and 1 for 5.7Kbit/s,
i.e., 22 LF periods, referred to Manchester coding)
Diagnosis mode selector (0: Normal LF operation mode, 1: Coil connection
diagnosis mode)
1.
If set, all coil connections are switched to this mode. Normal operation is not possible. (i.e., LF transmission).
The same works for the opposite way: once a Select Driver command is received with the DM-bit at 0, all connection lines are switched back to normal operation mode.
2.
For a proper operation after a diagnosis run, a Reset Fault Status command also needs to be sent.
bits DG,1..0:
bit DG:
Active channel indicator
Driver group selector (0 for high-current driver 1..3, 1 for low-current driver
4..6)
bits D1..0:
Driver selector, i.e. 01 is driver 1 (DG = 0) / 4 (DG = 1), 11 is driver 3
(DG = 0) / 6 (DG = 1).
Default: DG,1..0 = [001], DM = 0, BR = 0 --> Channel 1, diagnosis mode off and normal LF speed selected.
●
Select Coil Current
This command defines the current to be established for the next LF transmissions.
bits C4..0:
bits C1..C0:
Contain the step number in the range of 0 to 19 (00hex to 13hex)
Are used in diagnosis mode, to control the test switches of the activated
connection line
whereas …
bit C0:
The low/high-side switch of the AxP line
bit C1:
The low/high-side switch of the AxN line)
Default: C4..0 = [00000] --> 50 mA coil current selected.
22
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●
Send LF Data:
This command must be used to start an LF data telegram on the selected coil. The bits N3..0 contain the amount of
nibbles to be transferred into the LF data buffer of the Atmel® ATA5279. This amount has to be coded as follows:
N3..0 = (nNibbles – 1)
Hence, a maximum of 16 nibbles or eight words and a minimum of one nibble can be written into the buffer using one
command.
Note also that this command uses one more word of space in the buffer, as the header word is also stored. So for
example, if the LF telegram consists of four words, the required space in the LF data buffer is five words (four words
of pure data and one word for the command header).
It is important that the amount of nibbles passed in the header word matches the number of words transferred
afterwards to the IC, as no data consistency checking can be carried out here. If an odd number of nibbles is to be
transferred, the data word on the SPI has to be completed with dummy data in the upper nibble, as the SPI always
requires complete data words on the bus. The FIFO buffer is also only filled with complete words.
For an example, if seven nibbles of LF data (i.e., 14 LF Manchester data bits) are to be sent by the Atmel ATA5279 via
the LF channel, the Send LF Data command consists of five words, the header word (here 06h) and four LF data
words, whereas the last word contains only four bits (the four least significant) of the LF data.
For an additional example, see Figure 3-16, which illustrates how LF transmission data is processed in ATA5279.
Figure 3-16. LF Data Processing
SPi Data String (hex)
02h
35h
04h
SPi Data String (bin)
0000 0010
0 0 1 1 0 1 01
0 1 00
LF Telegram
MACT Signal
BCNT Signal
●
Send LF Carrier:
This command should be used when a carrier shall be transmitted on the LF channel via the selected coil. The current
will be regulated by ATA5279 to the value selected with the last Select Coil Current command (resp. the default value
of 50mA). See also Section 3.5 “Coil Current Sensing (Zero Cross, Sample and Hold, Integrator)” on page 9 for
further details.
The duration of this carrier can be defined by the T4..0 bits. Note that the time unit here is one LF data bit, i.e., 32LF
periods in normal- and 22LF periods in high-speed mode. That leads to a maximum definable carrier time per
command of 31 × 0.256ms = 7.936ms when using an 8MHz system clock.
However, when the T4..0-value is set to 0, an endless carrier transmission with the actually selected current on the
actually active coil is started. This can be used for long-term measurements or for energy-coupling purposes. Be
aware that long-term transmissions can produce a huge amount of heat in the driver, dependant on the selected coil
current and the properties of the coil itself. It is therefore strongly recommended to use this feature only with a
maximum current settings of 100mA; otherwise, the chip temperature might reach excessive values.
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23
3.9.4
Status Monitor
The status monitor holds all information from the diagnosis stage. In case of an existing fault, all power stages are disabled.
As soon as a fault is stored, an interrupt request (IRQ) to the microcontroller is generated. This signal is persistent until the
status info is polled by the microcontroller. The entry in the fault register can only be cleared by the Reset Fault command or
a global reset.
There are two different status registers:
● A general IC status register (requestable by the Get Status Info command)
●
A coil-driver related fault register (requestable by the Get Fault Info command)
The fault register is encoded as follows:
Table 3-8.
Fault Assignment between Driver Stages and the Fault Registers
MSB
Fault Register
DG
LSB
D1
D0
T
F03
F02
F01
F00
The meaning of the bits is described below:
● DG, D1..0: The driver group and number that was active when the fault occurred. Only a selected driver can be affected
by external faults. Therefore, it is sufficient to store the type of failure and the corresponding driver number. Refer to
Section 3.9.3 “Driver-related Command Description” on page 22 for further details on the coding of these bits.
●
T: A temperature shutdown has occurred. Note that there is not necessarily a link between the driver number and this
fault, as all sensor signals of the chip are OR’ed together. However, in general, it can be assumed that the last active
driver also caused the overtemperature condition.
●
F03: This bit indicates a missing return line signal during modulation. That means that the current detection unit was
not able to find a sinusoidal signal on the VSHS pin although the LF coil was driven. The reason for this can either be
an open load condition or a short-circuit on the AxN pin towards ground.
●
F02: This bit indicates an excessive positive voltage on the VSHS pin. In normal applications, this is only the case if
there is a high current flowing through the shunt resistor. The typical reason for this is a short-circuit on the AxN line
towards battery. Another possible reason could be a shorted LF coil.
●
F01: This bit indicates an excessive current through the high-side transistor that drives the AxP line. The most typical
reason for this is a short-circuit towards ground.
●
F00: This bit indicates an excessive current through the low-side transistor that drives the AxP line. The most typical
reason for this is a short-circuit towards battery.
Note:
24
To make sure a repeated detection of an existing fault, the related channel need to be changed before a “Reset
Fault Status” command is executed.
ATA5279/ATA5279C [DATASHEET]
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3.10
Oscillator
This block provides the clock signals internally needed for control logic, the LF driver stage, and the boost converter. The
oscillator requires an external clock source, which can either be an active signal from a microcontroller for example, or a
passive oscillation device like a crystal or a ceramic resonator. As the LF carrier frequency is directly derived from this clock,
the (resonance) frequency of the clock source must be chosen to match the desired LF frequency. Possible values range
from 6.4MHz to 9.6MHz, where 8MHz is the typical value resulting in an LF frequency of 125kHz.
Note that during start-up (i.e., as long as no stable oscillation can be detected), the driving current for the crystal is increased
to shorten the start-up delay. Furthermore, the IC is only functional if the oscillator is working properly. That means, during
start-up after a power-down phase, no communication and no operation of the IC is possible until the oscillator reaches its
operation point.
If an external clock source such as a microcontroller is to be used, the logic-level clock signal must be applied at the OSCI
pin, and the OSCO pin must be left open. Note that the chip protection features, need a clock signal present at the OSCI pin;
without this, the chip is not fully protected. Therefore, if the chip is in any mode but in power-down (reset), a clock signal is
needed.
The oscillator block is, like the control logic and the SPI, supplied by the application-provided logic supply voltage connected
to the pin VIF.
3.11
Internal Supply
The internal power supply stage provides all internally needed BIAS currents and reference voltages. An integrated onetime-programming (OTP) structure is used to adjust internal settings. This ensures parameter stability over the production
process.
The internal supply block performs monitoring functions to reset or shut down the IC in case of supply shortages or during
power-up. A power-management minimizes current consumption during power-down mode of the IC.
Another part of this block is the internal 5V voltage regulator. It is supplied by the VS pin, i.e., the battery supply connection.
This voltage is used for all internal analog functions and driving processes. It is active as long as the IC is not in power-down
mode. To increase stability and quality of this supply line, it is externally available (pin VCC) for connection to a ceramic
capacitor for filtering and buffering. Note that no loads must be connected to this pin.
As with the oscillator, this supply voltage must settle in its operation point prior to any operation. The control logic checks the
status of this voltage and inhibits operation until it reaches the required level. Furthermore, the driver supply voltage present
on the VDSx pins is also monitored. If the level falls below VVDS,min, the operability flag of the chip is cleared (bit Op in the
Status Register) and driver-related commands cannot be processed. Once the voltage level is valid again, the Op bit is set
again, and operability is restored.
ATA5279/ATA5279C [DATASHEET]
9125P–RKE–05/14
25
4.
Application
Find below a typical application schematic for the Atmel® ATA5279.
Figure 4-1. Application Schematic for the Atmel ATA5279
VBATT
D1
D2
L2
L1
+
+
C1
C3
C6
C2
C4
VS
VCC
VL
PGND
VDS
PCB
OSCI
Q1
Oscillator
OSCO
Internal Supply
POR, BG, UV/OV
car
A1P
Boost
Controller
HP 1-3
DC
Ant1
A2P
Ant2
A3P
DC
Ant3
μC voltage supply line (VDD)
μC connection
Ce1 Ce2 Ce3
S_CS
S_CLK
SPI
MOSI
LF Data Buffer
A4P
Sine Wave
Generator
LP 1-3
Ant4
A5P
Ant5
A6P
MISO
Ant6
Ce4 Ce5 Ce6
C7
A1N
VIF
Return Line
Driver
NRES
Control Logic
Communication
Protocol Handling
IRQ
BCNT
A2N
A3N
Driver Stage
Control
A4N
Integrator
A5N
MACT
A6N
Ce7 Ce8 Ce9 Ce10 Ce11 Ce12
VSHF
Sample
and Hold
Zero Cross
Detector
Reference
GND
RGND
CINT
CINT
Notes:
26
VSHS
R1
1.
A negative current on pin MISO that causes the voltage to drop below –0.6V with respect to ground might lead
to a chip reset, comparable to a logic low on the NRES pin.
2.
For applications with > 6 antennas please refer to the application note “Atmel ATA5279 Antenna Driver
Extension”.
3.
R1 ≥ 1Ω for proper operation.
4.
No pull-up resistance (by means of resistor or microcontroller pull-up) allowed.
5.
Ce < 4nF (recommended 1nF)
ATA5279/ATA5279C [DATASHEET]
9125P–RKE–05/14
Table 4-1.
4.1
Bill of Materials (BOM) for Typical Application Circuit
Part
Value
R1
1Ω
Description
C1
220µF/50V
Supply line input filter and stabilizing cap
C2
100nF cer.
Supply line input filter cap
C3
10µF/50V cer.
C4
100nF cer.
Boost converter filter cap (+ESD clamp)
C6
100nF cer.
Internal 5V supply line stabilizing cap
CINT
10nF cer.
Integration cap for current regulation loop
Filter cap for VIF supply
Shunt resistor, ±1% tolerance
Boost converter storage cap, low ESR
C7
100nF cer.
Ce1..12
1nF cer.
Add. ESD buffer, necessity
D1
50V/2A
Schottky diode
D2
50V/2A
Schottky diode
L1
68µH/2.5A
Supply line input filter choke
L2
82µH/2.5A
Boost converter charging choke
Q1
8MHz
Crystal or resonator
Application Hints
Important application aspects, in terms of circuitry, selection of components and thermal considerations are provided by
application notes listed below:
● ATAN0003_ATA5279_Application_Hints
●
LF Antenna Driver ATA5279C Thermal Considerations and PCB Design Suggestions
ATA5279/ATA5279C [DATASHEET]
9125P–RKE–05/14
27
5.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Voltage range on pin VS
Voltage range on pins VDSx, VLx
Voltage range on pins AxP
Symbol
Min.
Max.
Unit
VVS
–0.3
40
V
VVDS,max
–0.3
46
V
VAxP,max
–0.3
VVDS + 0.3
V
Voltage range on pins VSHFx, VSHS
VVSHF,max
–3
VVCC + 0.3
V
Voltage range on pins AxNx
VAxNx,max
VVSHF – 0.3
46
V
Voltage range on pins VCC, VIF
VDIGSUP,max
–0.3
+5.5
V
Voltage on pins RGND, PGNDx
VGND,max
–0.3
+0.3
V
VIO,max
–0.3
VVIF + 0.3
V
VCINT,max
–0.3
VVCC + 0.3
V
VESD
2
Voltage range on pins NRES, S_CS, S_CLK, MOSI,
OSCI, MACT, BCNT, IRQ, MISO, OSCO
Voltage range on pin CINT
ESD Voltage Ratings
- HBM (MIL-STD-883F, M. 3015.7)
Count of peaks over lifetime:
Number of events
Peak junction temperature
Note:
All voltages refer to the AGND pins.
6.
kV
Tj.max
500,000 at
200
Thermal Resistance
Parameters
Thermal resistance junction to case
Symbol
Value
Unit
RthJC
10
K/W
(1)
Thermal resistance junction to ambient
RthJA
35
Note:
1. Value that can be achieved when providing sufficient thermal vias and heat dissipation area
7.
°C
K/W
Temperature Range
Parameters
Junction operating temperature range
(1)(2)
Symbol
Min.
Max.
Unit
Tj
–40
+145
°C
Storage temperature range
Tstg
–40
+150
°C
Note:
1. Triggering the overtemperature switch off mode as described in parameter 6.5 in Section 8. “Functional Parameters” on
page 29 is not recommended for standard application. Note: The permanent use of overtemperature switch off will
reduce the life time of the IC.
2.
28
For more details in terms of thermal considerations please refer to the application note “Thermal Considerations and
PCB Design Hints”.
ATA5279/ATA5279C [DATASHEET]
9125P–RKE–05/14
8.
Functional Parameters
All parameters valid for 7.0V ≤ VS ≤ 16.5V and –40°C ≤ Ta ≤ 105°C unless otherwise noted.
No.
1
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Power Supply
1.1
VS-pin power-down
mode supply current
VVS ≤ 14V
1
IVSpd
5.5
10
µA
A
1.2
VS-pin idle mode
supply current
VVS = 16.5V
1
IVS,idle
3.5
5
mA
A
1.3
Internal VCC voltage
- idle
- load
7V ≤ VS ≤ 28V
IVCC = 0
IVCC = 5mA
4
VVCC,0
VVCC,1
4.8
5.05
5.3
V
A
1.4
VS voltage clamp
VS = 28V
VS = 40V
1
IVS,C28
IVS,C40
50
1.5
180
3
400
4.5
µA
mA
A
1.5
VCC power-on reset
threshold
4
VPORVCC
4.1
4.8
V
A
1.6
VDS operation
threshold
VS = 16.5V
DS
VVDS,min
5.1
6
V
A
1.7
Battery supply range
for normal operation
Idle mode
1
VVS
7
16.5
V
D
1.8
VDS power-down
mode supply current
VVDS = 28V
DS
IVDS,0
0
1.4
µA
A
1.9
VDS fault-shutdown
mode supply current
VVDS = 16.5V
DS
IVDS,FS
0.85
2.45
mA
A
1.10
Battery supply range
for Jump start
operation
Idle mode
1
VVS
7
26.5
V
D
1.11
VCC power-up time
4
tVCC
200
µs
D
1.12
Minimum VS voltage
level for VCC
operation
1
VVS,min
6
V
D
2
5.15
0.12
Boost Converter
2.1
Overvoltage shutdown level
DS
VVDSmax
40
42
44
V
A
2.2
Switch overcurrent
shutdown level
BLS
IVLmax
2.9
3.2
4
A
A
2.3
Switch on-state
resistance
BLS
RDSon,VL
0.5
Ω
A
2.4
Max duty cycle (ton / T)
BLS
DBoost
0.875
-
A
2.5
Switch leakage
current
VVL = 38V
BLS
IVL,leak
500
nA
A
2.6
Switch fall time
IVL = 200mA
BLS
tVL,f
50
200
ns
A
2.7
Switch rise time
IVL = 200mA
BLS
tVL,r
50
200
ns
A
IVL = 500mA
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
In this column, pin group names are given. Please refer to Section 2. “Pin Configuration” on page 3 in this document for
more details.
2.
Operation of coils with higher impedance than the given value is possible but functional limitations might occur (inability
to reach to configured coil current). Coils with lower impedance should not be used as they might be detected as faulty.
ATA5279/ATA5279C [DATASHEET]
9125P–RKE–05/14
29
8.
Functional Parameters (Continued)
All parameters valid for 7.0V ≤ VS ≤ 16.5V and –40°C ≤ Ta ≤ 105°C unless otherwise noted.
No.
3
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
CSP
fOSC
6.4
8
9.6
MHz
D
Oscillator
3.1
External clock source
frequency range
3.2
Driver output sink
resistance during
startup
IOSCO = 100µA
CSP
ROSC,L1
0.9
2.2
kΩ
A
3.3
Driver output sink
resistance during
operation
IOSCO = 100µA
CSP
ROSC,L1
1.8
4.4
kΩ
A
3.4
Driver output source
resistance during
startup
IOSCO = –100µA
CSP
ROSC,L1
0.9
2.2
kΩ
A
3.5
Driver output source
resistance during
operation
IOSCO = –100µA
CSP
ROSC,L1
1.8
4.4
kΩ
A
3.6
Feedback resistance
VOSCI, OSCO = 5V
CSP
RFB,OSC
220
360
kΩ
A
3.7
Clock input low-tohigh detection
threshold
CSP
VLH,OSC
0.45 × VIF
0.55 × VIF
3.8
Power-down input
pull-down resistance
7
ROSCI,0
3
6
3.9
Driver
transconductance in
start-up condition
8
gm
600
4
VOSCI = 5V
VVIF = 5V
A
kΩ
A
nA/mV
D
High-current Driver Stage (A1P, A2P, A3P)
4.1
Sourcing current limit
(RMS)
Idle mode, DC
ramping
HDL
IHP,HSCL
–1.7
–0.88
A
B
4.2
Sinking current limit
(RMS)
Idle mode, DC
ramping
HDL
IHP,LSCL
1.1
2
A
B
4.3
Signal difference
VAxP,pp = 30V
carrier to harmonics 2, Icoil,p = 200mA
fOSCI = 8MHZ
3, 4, 5
HDL
DSig
–34
dB
A
4.4
Load imped. range
(amount of complex
impedance)(2)
Icoil,pp = 2App
HDL
HRL
ZCoil,HP
2
12
Ω
D
4.5
Min. output voltage
IAxP = 200mA
Tj ≅ 30°C
HDL
VOHP,min
2.5
4.3
V
A
4.6
Max. output voltage
IAxP = –200mA
Tj ≅ 30°C
HDL
VOHP,max
VDS – 4.5
VDS – 2.5
V
A
4.7
Idle mode cross
current
VVDS = 16.5V
DS
IAxPH,CC
35
68
mA
A
50
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
30
1.
In this column, pin group names are given. Please refer to Section 2. “Pin Configuration” on page 3 in this document for
more details.
2.
Operation of coils with higher impedance than the given value is possible but functional limitations might occur (inability
to reach to configured coil current). Coils with lower impedance should not be used as they might be detected as faulty.
ATA5279/ATA5279C [DATASHEET]
9125P–RKE–05/14
8.
Functional Parameters (Continued)
All parameters valid for 7.0V ≤ VS ≤ 16.5V and –40°C ≤ Ta ≤ 105°C unless otherwise noted.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
4.8
Idle mode output
voltage
VVDS = 20V
IAxP = 0
IAxP = ±200mA
Tj ≅ 30°C
HDL
VAxPH,dile
4.9
Inactive pull-up
impedance
VVDS = 20V
IAxP = –100µA
Tj ≅ 30°C
HDL
4.10
Diagnosis mode pullup current
4.11
Diagnosis mode pulldown current
5
Typ.
Max.
Unit
Type*
9
11
V
A
RAxPH,PU
11.5
27
kΩ
B
VVDS = 16.5V
VAxP = 0V
IPU,Diag
–150
–100
µA
A
VVDS = 16.5V
VAxP = 16.5V
IPD,Diag
170
260
µA
A
Low Current Driver Stage (A4P, A5P, A6P)
5.1
Sourcing current limit
(RMS)
Idle mode, DC
ramping
LDL
ILP,HSCL
–1.2
–0.55
A
B
5.2
Sinking current limit
(RMS)
Idle mode, DC
ramping
LDL
ILP,LSCL
0.9
1.7
A
B
5.3
Signal difference
VAxP,pp = 30V
carrier to harmonics 2, Icoil,p = 200mA
fOSCI = 8MHZ
3, 4, 5
LDL
DSig
–34
dB
A
5.4
Load imped. range
(amount of complex
impedance)(2)
LDL
LRL
ZCoil,LP
10
25
Ω
D
5.5
Min. output voltage
IAxP = 200mA
Tj ≅ 30°C
LDL
VOLP,min
2.5
4.3
V
A
5.6
Max. output voltage
IAxP = –200mA
Tj ≅ 30°C
LDL
VOLP,max
VDS – 4.5
VDS – 2.5
V
A
5.7
Idle mode cross
current
VVDS = 16.5V
DS
IAxPL,CC
28
53
mA
A
5.8
Idle mode output
voltage
VVDS = 20V
IAxP = 0
IAxP = ±200mA
Tj ≅ 30°C
HDL
VAxPL,dile
9
11
V
A
5.9
Inactive pull-up
impedance
VVDS = 20V
IAxP = –100µA
Tj ≅ 30°C
HDL
RAxPL,PU
11.5
27
kΩ
B
5.10
Diagnosis mode pullup current
VVDS = 16.5V
VAxP = 0V
HDL
LDL
IPU,Diag
–150
–100
µA
A
5.11
Diagnosis mode pulldown current
VVDS = 16.5V
VAxP = 16.5V
HDL
LDL
IPD,Diag
170
260
µA
A
40
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
In this column, pin group names are given. Please refer to Section 2. “Pin Configuration” on page 3 in this document for
more details.
2.
Operation of coils with higher impedance than the given value is possible but functional limitations might occur (inability
to reach to configured coil current). Coils with lower impedance should not be used as they might be detected as faulty.
ATA5279/ATA5279C [DATASHEET]
9125P–RKE–05/14
31
8.
Functional Parameters (Continued)
All parameters valid for 7.0V ≤ VS ≤ 16.5V and –40°C ≤ Ta ≤ 105°C unless otherwise noted.
No.
6
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1.05
1.2
Ω
Ω
A
Coil Return Line and Diagnosis Stage (A1N … A6N)
6.1
Return line switch on- IHPS = 0.3A
state resistance
ILPS = 0.22A
HRL
LRL
RDS,onHPS
RDS,onLPS
6.2
Return line switch
RShunt = 1Ω
overcurrent shutdown Ch. 1-3 selected
threshold
Ch. 4-6 selected
RLO
IShunt,max
1.25
0.875
1.75
1.225
A
A
A
6.3
Diagnosis mode pullup current
VVDS = 16.5V
VAxP/N = 0V
HRL
LRL
IPU,Diag
–150
–100
µA
A
6.4
Diagnosis mode pulldown current
VVDS = 16.5V
VAxP/N = 16.5V
HRL
LRL
IPD,Diag
170
260
µA
A
Diagnoses mode
threshold voltage
VVDS = 16.5V
VAxP/N = 16.5V
6.4.1
6.5
Overtemperature
shutdown threshold
6.6
Open load and short
circuit detection AxN
to GND
6.7
Short circuit detection
AxP or AxN to Vbatt
7
0.45 x VDS
0.80 x VDS
D
TOTsdwn
145
170
°C
B
HRL
LRL
tOLdet
115
215
µs
A
HRL
LRL
tOLdet
100
µs
B
5
VZC
–10
+10
mV
A
5
tZCdel
150
290
ns
A
Zero Crossing Detector
7.1
Pos. slope detection
threshold
7.2
Polarity detection
delay
9
Integrator Stage
9.1
IPU_Diag active 0.38 x VDS
IPD_Diag active 0.62 x VDS
Voltage jump from
VVSHS – 20mV to
VVSHS + 20mV
Input offset voltage
5
Vofs,Integ
–2.5
+2.5
mV
B
3
IINT,POS
–20
–8
µA
A
9.2
Positive output
linearity
VVSHS = 1.1Vpp
Current step 20
selected
9.3
Negative output
linearity
VVSHS = 0.9Vpp
Current step 20
selected
3
IINT,NEG
8
20
µA
A
9.6
Upper output voltage
limit
ICINT = 30µA
VSHS = 100mVp
Current step 20
selected
3
VCINT,max
3.15
3.45
V
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
32
1.
In this column, pin group names are given. Please refer to Section 2. “Pin Configuration” on page 3 in this document for
more details.
2.
Operation of coils with higher impedance than the given value is possible but functional limitations might occur (inability
to reach to configured coil current). Coils with lower impedance should not be used as they might be detected as faulty.
ATA5279/ATA5279C [DATASHEET]
9125P–RKE–05/14
8.
Functional Parameters (Continued)
All parameters valid for 7.0V ≤ VS ≤ 16.5V and –40°C ≤ Ta ≤ 105°C unless otherwise noted.
No.
Parameters
10
References
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
49.5
54.5
mV
A
10.1
Current step 1 level
-
VREF,S1
10.2
Current step 2 level
-
VREF,S2
97
105
mV
A
10.3
Current step 3 level
-
VREF,S3
145
157
mV
A
10.4
Current step 4 level
-
VREF,S4
192
208
mV
A
10.5
Current step 5 level
-
VREF,S5
245
255
mV
A
10.6
Current step 6 level
-
VREF,S6
294
306
mV
A
10.7
Current step 7 level
-
VREF,S7
343
357
mV
A
10.8
Current step 8 level
-
VREF,S8
392
408
mV
A
10.9
Current step 9 level
-
VREF,S9
441
459
mV
A
10.10 Current step 10 level
-
VREF,S10
490
510
mV
A
10.11 Current step 11 level
-
VREF,S11
539
561
mV
A
10.12 Current step 12 level
-
VREF,S12
588
612
mV
A
10.13 Current step 13 level
-
VREF,S13
637
663
mV
A
10.14 Current step 14 level
-
VREF,S14
686
714
mV
A
10.15 Current step 15 level
-
VREF,S15
735
765
mV
A
10.16 Current step 16 level
-
VREF,S16
784
816
mV
A
10.17 Current step 17 level
-
VREF,S17
833
867
mV
A
10.18 Current step 18 level
-
VREF,S18
882
918
mV
A
10.19 Current step 19 level
-
VREF,S19
931
969
mV
A
10.20 Current step 20 level
-
VREF,S20
980
1020
mV
A
IsupVIF
0.6
1.9
3
mA
A
2
5
µA
A
11
Digital Interface (SPI, Control Logic)
11.1
Supply current in
operation mode
VVIF ≤ 5.5V
6
11.2
Supply current in
power-down mode
VVIF = 5.0V
6
11.3
SPI clock period
Chip in operation
39
TSPI
4 × 1/fOSCI
s
D
11.4
SPI clock low-phase
timing
Chip in operation
39
tLo,min
2 × 1/fOSCI
s
D
11.5
SPI clock high-phase
timing
Chip in operation
39
thi,min
2 × 1/fOSCI
s
D
11.6
SPI output enabling
time
Chip in operation
tMISOon,max
100
ns
D
11.7
SPI output disabling
time
Chip in operation
tMISOoff,max
100
ns
D
11.8
Minimum SPI disable
time
Chip in operation
tSPIoff,min
s
D
4 × 1/fOSCI
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
In this column, pin group names are given. Please refer to Section 2. “Pin Configuration” on page 3 in this document for
more details.
2.
Operation of coils with higher impedance than the given value is possible but functional limitations might occur (inability
to reach to configured coil current). Coils with lower impedance should not be used as they might be detected as faulty.
ATA5279/ATA5279C [DATASHEET]
9125P–RKE–05/14
33
8.
Functional Parameters (Continued)
All parameters valid for 7.0V ≤ VS ≤ 16.5V and –40°C ≤ Ta ≤ 105°C unless otherwise noted.
No.
Parameters
11.9
Minimum chip select
setup time
Minimum chip select
11.10
hold time
Test Conditions
Pin
Symbol
Chip in operation
tCSset,min
Chip in parallel mode
Min.
Typ.
Max.
Unit
2 × 1/fOSCI
Type*
D
s
D
200µs
Chip in operation
tCShold,min
2 × 1/fOSCI
s
D
11.11
Minimum data input
setup time
Chip in operation
tsetup,min
100
ns
D
11.12
Minimum data input
hold time
Chip in operation
thold,min
100
ns
D
11.13
Output source
capability
VVIF = 5V
ISource = –1mA
DO
Vdig,H
4.75
V
A
VVIF = 5 V
Isink = 1mA
DO
Vdig,L
0.25
V
A
37
38
39
40
37
38
39
40
Iin,L
–0.2
–0.2
–0.2
–60
0
12
0
0
0
0
0
–20
0.2
40
0.2
0.2
µA
A
11.14 Output sink capability
Vin = 0V
VVIF = 5.5V
11.15 Input current
Vin = 5.5V
VVIF = 5.5V
Iin,H
11.16
Input high level
threshold
VVIF = 3.1V
DI
VLH
0.48
0.64
VVIF
A
11.17
Input low level
threshold
VVIF = 3.1V
DI
VHL
0.32
0.48
VVIF
A
11.18
External reset input
timing
tNRES,min
100
ns
D
11.19
Tristate output
leakage current
nA
A
VMISO = 2.5V
IL,max
500
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
34
1.
In this column, pin group names are given. Please refer to Section 2. “Pin Configuration” on page 3 in this document for
more details.
2.
Operation of coils with higher impedance than the given value is possible but functional limitations might occur (inability
to reach to configured coil current). Coils with lower impedance should not be used as they might be detected as faulty.
ATA5279/ATA5279C [DATASHEET]
9125P–RKE–05/14
Ordering Information
Extended Type Number
ATA5279C-WGQW
Remarks
Taped and reeled, MOQ 4000
Package Information
Top View
D
48
1
E
PIN 1 ID
technical drawings
according to DIN
specifications
12
Dimensions in mm
A1
Two Step Singulation process
A
Side View
Partially Plated Surface
Bottom View
D2
13
24
25
12
COMMON DIMENSIONS
E2
(Unit of Measure = mm)
1
A
36
48
37
e
A (10:1)
Symbol
MIN
NOM
MAX
A
0.8
0.85
0.9
A1
A3
0
0.16
0.035
0.21
0.05
0.26
D
6.9
7
7.1
D2
5.5
5.6
5.7
E
6.9
7
7.1
E2
5.5
5.6
5.7
L
0.35
0.4
0.45
b
0.2
0.25
0.3
e
NOTE
0.5
L
10.
Package
VQFN48, 7mm × 7mm
A3
9.
b
10/18/13
TITLE
Package Drawing Contact:
[email protected]
Package: VQFN_7x7_48L
Exposed pad 5.6x5.6
GPC
DRAWING NO.
REV.
6.543-5130.03-4
1
ATA5279/ATA5279C [DATASHEET]
9125P–RKE–05/14
35
11.
Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
9125P-RKE-05/14
9125O-RKE-07/13
History
• Section 9 “Ordering Information” on page 35 updated
• Section 10 “Package Information” on page 35 updated
• Section 9 “Ordering Information” on page 35 updated
• Section 3.7 “SPI” on page 14 updated
9125N-RKE-01/13
• Section 3.8.2 “Usage” on page 17 updated
• Section 7 “Temperature Range” on page 28 updated
• Section 8 “Functional Parameters” number 11.9 on page 34 updated
• Section 3.2.1 “Return Line Driver Stages” on page 7 added
9125M-RKE-12/12
• Section 3.6.1 “Functional Description of Diagnosis Mode” on page 10 updated
• Section 4.1 “Application Hints” on page 27 updated
9125L-RKE-03/11
• ATA5279C on page 1 added
9125K-RKE-11/10
• Section 9 “Ordering Information” on page 38 changed
9125J-RKE-11/10
• Section 8 “Functional Parameters” numbers 4.9, 5.9, 6.6 and 6.7 on pages 33 to 35 changed
• Figure 1-1 “Block Diagram” on page 1 changed
• Table 2-1 “Pin Description” on page 3 changed
• Order of Figures 3-6 to 3-9 on pages 14 to 15 changed
9125I-RKE-09/10
• Figure 4-1 “Application Schematic for ATA5279” on page 27 changed
• Table 4-1 “Bill of Materials (BOM) for Typical Application Circuit” on page 28 changed
• Section 7 “Operating Range” on page 31 changed
• Section 8 “Functional Parameters” numbers 1.11 and 1.12 on page 32 added
• Section 8 “Functional Parameters” numbers 11.1 to 11.12 on page 36 changed
9125H-RKE-05/10
• Datasheet ATA5279P renamed in datasheet ATA5279
• Ordering number for small taped & reeled unit introduced as following: ATA5279P-PLPW
• Features item 3 “On-off-keyed Data Modulation .. ” on page 1 changed
• Table 3-1 “States of Driver Outputs within Operation Modes” on page 6 added
• Table 3-4 “States of Control I/Os” on page 16 added
• Note 2 “For applications with 6 antennas .. ” on page 27 added
9125G-RKE-01/10
• Note “Application Note - LF Antenna Driver ATA5279P ... ” on page 30 added
• Section 5 “Absolute Maximum Ratings” part “Count of peaks over lifetime .. ” on page 31 changed
• Section 7 “Operating Range” Note 2 “Triggering the overtemperature .. ” and Note 3 “For more
details in terms ... ” on page 31 changed
• Data rate from 4.0Kbit/s to 3.9Kbit/s on pages 18, 19 and 23 changed
36
ATA5279/ATA5279C [DATASHEET]
9125P–RKE–05/14
XXXXXX
Atmel Corporation
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© 2014 Atmel Corporation. / Rev.: Rev.: 9125P–RKE–05/14
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