ON MTV16N50E Power field effect transistor Datasheet

MTV16N50E
Advance Information
TMOS E−FET.™
Power Field Effect
Transistor
D3PAK for Surface Mount
N−Channel Enhancement−Mode Silicon
Gate
This high voltage MOSFET uses an advanced termination scheme to
provide enhanced voltage−blocking capability without degrading
performance over time. In addition, this advanced TMOS E−FET is
designed to withstand high energy in the avalanche and commutation
modes. The new energy efficient design also offers a drain−to−source
diode with a fast recovery time. Designed for high speed switching
applications in power supplies, converters, PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
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TMOS POWER FET
16 AMPERES, 500 VOLTS
RDS(on) = 0.40 W
D3PAK Surface Mount
CASE 433−01
Style 2
N−Channel
®
D
G
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
500
Vdc
Drain−to−Gate Voltage (RGS = 1.0 MΩ)
VDGR
500
Vdc
Gate−to−Source Voltage — Continuous
VGS
±20
Vdc
ID
ID
16
9.0
60
Adc
PD
180
1.4
2.0
Watts
W/°C
Watts
TJ, Tstg
−55 to 150
°C
Rating
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 μs)
IDM
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Apk
Single Pulse Drain−to−Source Avalanche Energy — Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc, Peak IL = 16 Apk, L = 6.7 mH, RG = 25 Ω )
EAS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
RθJC
RθJA
RθJA
0.7
62.5
35
°C/W
TL
260
°C
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
mJ
860
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 1
1
Publication Order Number:
MTV16N50E/D
MTV16N50E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
500
—
—
520
—
—
—
—
—
—
250
1000
—
—
100
2.0
—
3.2
7.0
4.0
—
mV/°C
—
0.32
0.40
Ohm
—
—
—
—
6.7
5.6
gFS
5.0
—
—
mhos
Ciss
—
3200
4480
pF
Coss
—
400
560
Crss
—
320
448
td(on)
—
28
60
tr
—
80
160
td(off)
—
80
160
tf
—
60
120
QT
—
65
—
Q1
—
17
—
Q2
—
47
—
Q3
—
34
—
—
—
1.0
0.9
1.6
—
trr
—
390
—
ta
—
245
—
tb
—
145
—
QRR
—
5.35
—
—
5.0
—
—
13
—
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 μAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0)
IGSS
Vdc
mV/°C
μAdc
nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 μAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 8.0 Adc)
RDS(on)
Drain−to−Source On−Voltage
(VGS = 10 Vdc, ID = 16 Adc)
(VGS = 10 Vdc, ID = 8.0 Adc, TJ = 125°C)
VDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 8.0 Adc)
Vdc
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 250 Vdc, ID = 16 Adc,
VGS = 10 Vdc,
RG = 4.7 Ω)
Fall Time
Gate Charge
(See Figure 8)
(VDS = 400 Vdc, ID = 16 Adc,
VGS = 10 Vdc)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 16 Adc, VGS = 0 Vdc)
(IS = 16 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = 16 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/μs)
Reverse Recovery Stored Charge
VSD
Vdc
ns
μC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
LD
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
(1) Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
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2
nH
nH
MTV16N50E
TYPICAL ELECTRICAL CHARACTERISTICS
16
14
12
10
8
5V
6
4
2
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0
16
14
12
10
8
1
2
3
4
5
6
7
8
4
9
0
10
TJ = −55°C
0
3
4
5
6
7
8
9
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.6
0.5
0.4
25°C
0.3
0.2
− 55°C
0.1
0.0
5
10
15
20
25
ID, DRAIN CURRENT (AMPS)
30
35
0.4
TJ = 25°C
0.35
VGS = 10 V
0.3
15 V
0.25
0.2
0.15
0
Figure 3. On−Resistance versus Drain Current
and Temperature
25
10
15
20
ID, DRAIN CURRENT (AMPS)
5
30
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
100000
2.5
VGS = 0 V
VGS = 10 V
ID = 8 A
TJ = 125°C
10000
I DSS , LEAKAGE (nA)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 100°C
2.0
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS = 10 V
0
25°C
2
0.8
0.7
100°C
6
4V
0
VDS ≥ 10 V
18
6V
9V
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
I D , DRAIN CURRENT (AMPS)
18
20
7V
VGS = 10 V
TJ = 25°C
I D , DRAIN CURRENT (AMPS)
20
1.5
100°C
1000
1.0
0.5
0
−50
−25
0
25
50
100
75
TJ, JUNCTION TEMPERATURE (°C)
125
25°C
100
10
150
Figure 5. On−Resistance Variation with
Temperature
0
100
200
300
400
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
5
MTV16N50E
POWER MOSFET SWITCHING
The capacitance (Ciss) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to
the on−state when calculating td(off).
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves
would maintain a value of unity regardless of the switching
speed. The circuit used to obtain the data is constructed to
minimize common inductance in the drain and gate circuit
loops and is believed readily achievable with board
mounted components. Most power electronic loads are
inductive; the data in the figure is taken with a resistive load,
which approximates an optimally snubbed inductive load.
Power MOSFETs may be safely operated into an inductive
load; however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate
of average input current (I G(AV) ) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation
for voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
7000
VDS = 0 V
TJ = 25°C
VGS = 0 V
Crss
C, CAPACITANCE (pF)
5000
4000
TJ = 25°C
Ciss
6000
C, CAPACITANCE (pF)
10000
VGS = 0 V
Ciss
3000
2000
Ciss
1000
Coss
100
Crss
Coss
1000
0
−10
Crss
−5
0
VGS
5
10
10
15
20
25
0
10
100
10
VDS
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7a. Low Voltage Capacitance Variation
Figure 7b. High Voltage Capacitance Variation
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4
15
500
QT
9
300
Q2
1000
td(off)
td(on)
200
6
TJ = 25°C
ID = 16 A
3
Q3
0
TJ = 25°C
ID = 16 A
VDD = 250 V
VGS = 10 V
400
VGS
Q1
10000
t, TIME (ns)
12
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
MTV16N50E
0
10
20
40
50
60
70
80
90
tr
100
VDS
30
100
0
100
tf
10
1
10
100
Qg, TOTAL GATE CHARGE (nC)
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
10
14
TJ = 25°C
VGS = 0 V
I S , SOURCE CURRENT (AMPS)
12
10
8
6
4
2
0
0
0.2
0.6
0.4
0.8
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with
an increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as
shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the
procedures discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I DM ) nor rated voltage (V DSS ) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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MTV16N50E
SAFE OPERATING AREA
900
VGS = 20 V
SINGLE PULSE
TC = 25°C
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
100
10
100 μs
1 ms
10 ms
1
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
700
600
500
400
300
200
100
0
25
1000
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
50
75
100
125
15
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
1
ID = 16 A
800
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
P(pk)
0.01
SINGLE PULSE
t1
t2
DUTY CYCLE, D = t1/t2
0.001
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RθJC(t)
1.0E+00
1.0E+01
MTV16N50E
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.165
4.191
0.118
3.0
0.100
2.54
0.063
1.6
0.190
4.826
0.243
6.172
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
almost double the power dissipation with this method, one
will be giving up area on the printed circuit board which can
defeat the purpose of using surface mount technology. For
example, a graph of RθJA versus drain pad area is shown in
Figure 15.
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, RθJA, the thermal resistance
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data
sheet, PD can be calculated as follows:
RθJA , THERMAL RESISTANCE, JUNCTION
TO AMBIENT (°C/W)
PD =
100
TJ(max) − TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device. For a D3PAK
device, PD is calculated as follows.
Board Material = 0.0625″
G−10/FR−4, 2 oz Copper
1.75 Watts
80
TA = 25°C
60
3.0 Watts
40
5.0 Watts
20
0
PD = 150°C − 25°C = 2.0 Watts
62.5°C/W
2
4
6
A, AREA (SQUARE INCHES)
8
10
Figure 15. Thermal Resistance versus Drain Pad
Area for the D3PAK Package (Typical)
The 62.5°C/W for the D3PAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.0 Watts. There are
other alternatives to achieving higher power dissipation from
the surface mount packages. One is to increase the area of
the drain pad. By increasing the area of the drain pad, the
power dissipation can be increased. Although one can
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad™. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
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MTV16N50E
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC−59, SC−70/SOT−323, SOD−123, SOT−23, SOT−143,
SOT−223, SO−8, SO−14, SO−16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
and D2PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 16 shows a
typical stencil for the DPAK and D2PAK packages. The
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇÇ
ÇÇÇÇÇÇ ÇÇ
ÇÇÇ
ÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇÇÇÇ
SOLDER PASTE
OPENINGS
STENCIL
Figure 16. Typical Stencil for DPAK and
D2PAK Packages
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* Due to shadowing and the inability to set the wave height
to incorporate other surface mount components, the D2PAK
is not recommended for wave soldering.
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MTV16N50E
TYPICAL SOLDER HEATING PROFILE
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density board.
The Vitronics SMD310 convection/infrared reflow soldering
system was used to generate this profile. The type of solder
used was 62/36/2 Tin Lead Silver with a melting point
between 177 −189°C. When this type of furnace is used for
solder reflow work, the circuit boards and solder joints tend
to heat first. The components on the board are then heated
by conduction. The circuit board, because it has a large
surface area, absorbs the thermal energy more efficiently,
then distributes this energy to the components. Because of
this effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a
figure for belt speed. Taken together, these control settings
make up a heating “profile” for that particular circuit board.
On machines controlled by a computer, the computer
remembers these profiles from one operating session to the
next. Figure 17 shows a typical heating profile for use when
soldering a surface mount device to a printed circuit board.
This profile will vary among soldering systems but it is a good
starting point. Factors that can affect the profile include the
type of soldering system in use, density and types of
components on the board, type of solder used, and the type
of board or substrate material being used. This profile shows
temperature versus time. The line on the graph shows the
STEP 1
PREHEAT
ZONE 1
RAMP"
200°C
STEP 2
STEP 3
VENT
HEATING
SOAK" ZONES 2 & 5
RAMP"
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 4
STEP 5
HEATING
HEATING
ZONES 3 & 6 ZONES 4 & 7
SOAK"
SPIKE"
STEP 6
VENT
205° TO 219°C
PEAK AT
SOLDER JOINT
170°C
160°C
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
50°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 17. Typical Solder Heating Profile
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STEP 7
COOLING
MTV16N50E
PACKAGE DIMENSIONS
CASE 433−01
ISSUE B
−T−
B
S
SEATING
PLANE
C
4
R
E
Q
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
W
Y
V
N
1
P
2
K
3
F
U
L
A
2 PL
J
D 2 PL
G
0.13 (0.005)
X
H
M
T
DIM
A
B
C
D
E
F
G
H
J
K
L
N
P
Q
R
S
U
V
W
X
Y
INCHES
MIN
MAX
0.588
0.592
0.623
0.627
0.196
0.200
0.048
0.052
0.058
0.062
0.078
0.082
0.430 BSC
0.105
0.110
0.018
0.022
0.150
0.160
0.058
0.062
0.353
0.357
0.078
0.082
0.053
0.057
0.623
0.627
0.313
0.317
0.028
0.032
0.050
−−−
0.054
0.058
0.050
0.060
0.104
0.108
STYLE 2:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
14.94
15.04
15.82
15.93
4.98
5.08
1.22
1.32
1.47
1.57
1.98
2.08
1.092 BSC
2.67
2.79
0.46
0.56
3.81
4.06
1.47
1.57
8.97
9.07
1.98
2.08
1.35
1.45
15.82
15.93
7.95
8.05
0.71
0.81
1.27
−−−
1.37
1.47
1.27
1.52
2.64
2.74
GATE
DRAIN
SOURCE
DRAIN
E−FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
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MTV16N50E/D