ON CS3524AGDWR16 Voltage mode pwm control circuit Datasheet

CS3524A
Voltage Mode
PWM Control Circuit with
200 mA Output Drivers
The CS3524A PWM control circuit retains the same versatile
architecture of the industry standard CS3524 (SG3524) while adding
substantial improvements.
The CS3524 is pin−compatible with “non−A” versions, and in most
applications can be directly interchanged. The CS3524A, however,
eliminates many of the design restrictions which had previously
required additional external circuitry.
The CS3524A includes a precision 5.0 V reference trimmed to ±1%
accuracy (eliminating the need for potentiometer adjustments), an
error amplifier with an output voltage swing extending to 5.0 V, and a
current sense amplifier useful in either the ground or power supply
output lines. The uncommitted 60 V, 200 mA NPN output pair greatly
enhances the output drive capability.
The CS3524A features an undervoltage lockout circuit which
disables all internal circuitry (except the reference) until the input
voltage has risen to 8.0 V. This holds standby current low until
turn−on, and greatly simplifies the design of low power, off−line
supplies. The turn−on circuit has approximately 600 mV of hysteresis
for jitter free activation.
Other improvements include a PWM latch that insures freedom
from multiple pulsing within a period, even in noisy environments;
logic to eliminate double pulsing on a single output, a 200 ns external
shutdown capability, and automatic thermal protection from excessive
chip temperature. The oscillator circuit is usable to 500 kHz and is
easier to synchronize with an external clock pulse.
Features
Precision Reference Internally Trimmed to ±1%
Current Limit
Undervoltage Lockout
Start−Up Supply Current < 4.0 mA
Output to 200 mA
60 V Output Capability
Wide Common−Mode Input Range for Error and Current Limit
Amplifiers
• PWM Latch Insures Single Pulse per Period
• Double Pulse Suppression
• 200 ns Shutdown
• Guaranteed Frequency
• Thermal Shutdown
•
•
•
•
•
•
•
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 4
1
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MARKING
DIAGRAMS
16
16
CS3524A
AWLYYWW
1
DIP−16
N SUFFIX
CASE 648
1
16
16
CS3524A
1
SO−16L
DW SUFFIX
CASE 751G
A
WL, L
YY, Y
WW, W
AWLYYWW
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
EA−
1
VREF
EA+
VIN
SYNC
EB
VOUTB
VOUTA
ISENSE+
ISENSE−
RT
EA
CT
GND
SHUTDOWN
COMP
ORDERING INFORMATION
Device
Package
Shipping
CS3524AGN16
DIP−16
25 Units/Rail
CS3524AGDW16
SO−16L
46 Units/Rail
CS3524AGDWR16
SO−16L 1000 Tape & Reel
Publication Order Number:
CS3524A/D
CS3524A
5 V Reference
Regulator
VIN
UV
Sense
SYNC
RT
Power to
Internal
Circuitry
CLOCK
OSC
VREF
VOUTA
Flip
T Flop
EA
CT
RAMP
COMP
VIN
EA−
+
COMP
−
S
S
200 mV
ISENSE+
ISENSE−
VOUTB
PWM
Latch
EB
−
EA
+
EA+
R
1 kΩ
VIN
SHUTDOWN
10 kΩ
GND
CL
Figure 1. Block Diagram
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
Unit
Supply Voltage (VIN)
40
V
Collector Supply Voltage (VCC)
60
V
Output Current (Each Output)
200
mA
Reference Output Current
50
mA
Oscillator Charging Current
5.0
mA
Power Dissipation at TA = 25°C
1000
mW
Power Dissipation at TJ = +25°C
Derate for Case Temperature above +25°C
2000
16
mW
mW/°C
−65 to +150
°C
260 peak
230 peak
°C
°C
Storage Temperature Range
Lead Temperature Soldering
Wave Solder (through hole styles only) Note 1
Reflow (SMD styles only) Note 2
1. 10 seconds max.
2. 60 seconds max above 183°C
*The maximum package power dissipation must be observed.
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2
CS3524A
ELECTRICAL CHARACTERISTICS (0°C ≤ TA ≤ +70°C, VIN = VCC = 20 V; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
8.0
−
40
V
5.5
7.5
8.5
V
Turn−On Characteristics
Input Voltage
Operating Range after Turn−On
Turn−On Threshold
−
Turn−On Current
VIN Turn−On − 100 mV
−
2.5
4.0
mA
Operating Current
VIN = 8.0 to 40 V
−
5.0
10
mA
−
0.6
−
V
4.9
5.0
5.2
V
Turn−On Hysteresis (Note 3)
−
Reference Section
Output Voltage
TA = 25°C
Line Regulation
VIN = 10 to 40 V
−
10
30
mV
Load Regulation
IL = 0 to 20 mA
−
20
50
mA
Temperature Stability (Note 3)
Over Operating Range
−
20
50
mV
Short Circuit Current
VREF = 0, TA = 25°C
−
80
100
mA
Output Noise Voltage (Note 3)
10 Hz ≤ f ≤ 10 kHz, TA = 25°C
−
40
−
μVRMS
Long Term Stability (Note 3)
TA = 125°C, 1000 Hrs.
−
20
50
mV
Oscillator Section
RT = 2700 W, CT = 0.01 mF; unless otherwise specified
Initial Accuracy
TA = 25°C
39
43
47
kHz
Temperature Stability (Note 3)
Over Operating Temperature Range
−
1.0
2.0
%
Minimum Frequency
RT = 150 kΩ, CT = 0.1 μF
−
−
120
Hz
Maximum Frequency
RT = 2.0 kΩ, CT = 470 pF
500
−
−
kHz
Output Amplitude (Note 3)
TA = 25°C
−
3.5
−
V
Output Pulse Width (Note 3)
TA = 25°C
−
0.5
−
μs
Ramp Peak
−
3.3
3.5
3.7
V
Ramp Valley
−
0.7
0.9
1.0
V
Error Amplifier Section
VCM = 2.5 V; unless otherwise specified
Input Offset Voltage
−
−
2.0
10
mV
Input Bias Current
−
−
1.0
10
μA
Input Offset Current
−
−
0.5
1.0
μA
Common Mode Rejection Ratio
VCM = 1.5 to 5.5 V
60
75
−
dB
Power Supply Rejection Ratio
VIN = 10 to 40 V
50
60
−
dB
Output Swing
Minimum Total Range
0.5
−
5.0
V
Open Loop Voltage Gain
ΔVOUT = 1.0 to 4.0 V, RL ≥ 10 MΩ
60
80
−
dB
Gain−Bandwidth (Note 3)
TA = 25°C, AV = 0 dB
−
3.0
−
MHz
Current Limit Amplifier
VSENSE = VO; unless otherwise specified
Input Offset Voltage
TA = 25°C, EA Set for Max. Output
180
200
220
mV
Input Offset Voltage
Over Operating Temperature Range
170
−
230
mV
−
−1.0
−10
μA
Input Bias Current
−
Common Mode Rejection Ratio
VSENSE = 0 to 15 V
50
60
−
dB
Power Supply Rejection Ratio
VIN = 10 to 40 V
50
60
−
dB
3. These parameters are guaranteed by design but not 100% tested in production.
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3
CS3524A
ELECTRICAL CHARACTERISTICS (continued) (0°C ≤ TA ≤ +70°C, VIN = VCC = 20 V; unless otherwise specified.)
Characteristic
Test Conditions
Current Limit Amplifier (continued)
Min
Typ
Max
Unit
VSENSE = VO; unless otherwise specified
Output Swing
Minimum Total Range
0.5
−
5.0
V
Open Loop Voltage Gain
ΔVOUT = 1.0 to 4.0 V, RL ≥ 10 MΩ
70
80
−
dB
Delay Time (Note 4)
ΔVIN = 300 mV
−
300
−
ns
Collector Emitter Voltage
IC = 100 μA
60
80
−
V
Collector Leakage Current
VCE = 50 V
−
0.1
20
μA
Saturation
IC = 20 mA
IC = 200 mA
−
−
0.2
1.0
0.4
2.2
V
V
Emitter Output Voltage
IE = 50 mA
17
18
−
V
Rise Time (Note 4)
TA = 25°C, R = 2.0 kΩ
−
200
−
ns
Fall Time (Note 4)
TA = 25°C, R = 2.0 kΩ
−
100
−
ns
Comparator Delay (Note 4)
TA = 25°C, VCOMP to VOUT
−
300
−
ns
Shutdown Delay (Note 4)
TA = 25°C, VSHUT to VOUT
−
200
−
ns
Shutdown Threshold
TA = 25°C, RC = 2.0 kΩ
0.5
0.7
1.0
V
−
165
−
°C
Output Section (Each Output)
Thermal Shutdown (Note 4)
−
4. These parameters are guaranteed by design but not 100% tested in production.
TYPICAL PERFORMANCE CHARACTERISTICS
50
RF = ∞
VIN = 20 V
TA = 25°C
RF = 1 M Ω
60
Duty−Cycle (One Output) − %
Open Voltage Gain (dB)
80
RF = 300 kΩ
RF = 100 kΩ
40
20
0
RF = 30 kΩ
RF is impedance to ground.
Values below 30 kΩ will
begin to limit the maximum
duty−cycle.
100
1k
10 k
100 k
40
30
CT = 10 μF
20
CT = 1 μF
10
0
1M
VIN = 20 V
RT = 2700 Ω
TA = 25°C
0
1
2
3
4
Input Voltage VIN
Frequency (Hz)
Figure 2. Error Amplifier Voltage Gain vs.
Frequency Over RF
Figure 3. Duty Cycle vs. Input Voltage
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4
5
CS3524A
10
8
7
TA = 25°C
6
TA = 125°C
Output (V)
20
TA = −55°C
5
4
3
2
Note: Outputs off. RT = ∞
1
0
Output at
VOA or VOB
15
10
5
VIN = 20 V
RL = 2 kΩ
TA = 25°C
0
Input (V)
Quiescent Current (mA)
9
10
0
20
30
5
4
3
2
1
0
Input at VOB
Note: Minimum input pulse width to latch is 200 ns.
0
50
40
Figure 4. Quiescent Supply Current vs. Supply
Voltage Over Temperature
1M
10
5.0
Output Dead Time (μs)
Oscillator Frequency (Hz)
2
100 k
3
4
10 k
5
1. CT = 1.0 nF
1 k 2. CT = 3.0 nF
3. CT = 10 nF
4. CT = 30 nF
5. CT = 100 nF
100
1
2
10
50
20
2.0
1.0
0.5
0.1
1
100
Note: Dead time = osc output
pulse width plus output delay
2
5
0
1
Output (V)
Input (V)
Output (V)
Input (V)
VIN = 20 V, TA = 25°C
EA+ = VREF
ISENSE− = GND
0
2
100
VIN = 20 V
RL = 2.0 kΩ
TA = 25°C
15
10
5
Output at
VOA or VOB
0
0.1
50
20
Overdrive
5%
10%
20%
50%
Input at ISENSE+
20
Figure 7. Output Dead Time vs. Timing Capacitor
Value
Output at COMP
0.2
10
Timing Capacitor, CT (nF)
Timing Resistor, RT (kΩ)
Figure 6. Oscillator Frequency vs. Timing
Components Resistor Over Timing Capacitance
6
5
4
3
2
1
0
3
VIN = 20 V
RT = 2700 Ω
TA = 25°C
0.2
f [ 1.15
RTCT
5
2
Figure 5. Shutdown Delay from PWM Comparator
VIN = 20 V
TA = 25°C
1
1
Delay Time (μs)
Supply Voltage VIN (V)
3
1.0
Input at
Shutdown
0.5
0
Note: Minimum input pulse
width to latch is 200 ns.
4
0
Delay Time (μs)
1
2
3
Delay Time (μs)
Figure 8. Current Limit Amplifier Delay
Figure 9. Turn−Off Delay from Shutdown
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5
CS3524A
5
VCE Sat (V)
4
3
TA = 125°C
2
TA = 25°C
TA = −55°C
1
0
0
50
100
200
150
250
Output Collector Current (mA)
Figure 10. Output Saturation Voltage vs. Output
Current Over Temperature
VCC
2 kΩ
1W
IS
VIN
VOUTB
EA
GND
ISENSE−
COMP
EA−
EA+
CT
RT
ISENSE+
CS3524A
SHUTDOWN
VOUTA
SYNC
VREF
2 kΩ
1W
EB
100 kΩ 100 kΩ
SHUTDOWN
2 kΩ
0.1
RT
CT
10 kΩ
0.1
2 kΩ
10 kΩ
1 kΩ
Figure 11. Open Loop Test Circuit
2. The effect of the shutdown cannot be seen at the
compensation terminal, but must be observed at the
outputs.
Note: The CS3524A should be able to be tested in any
3524 test circuit with two possible exceptions:
1. The higher gain−bandwidth of the current limit
amplifier in the CS3524A may cause oscillations in
an uncompensated 3524 test circuit.
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6
CS3524A
PACKAGE DIMENSIONS
DIP−16
N SUFFIX
CASE 648−08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
−T−
H
SEATING
PLANE
K
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SO−16L
DW SUFFIX
CASE 751G−03
ISSUE B
A
D
9
1
8
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
h X 45 _
E
M
0.25
16X
M
14X
e
T A
S
B
DIM
A
A1
B
C
D
E
e
H
h
L
q
S
L
A
0.25
B
B
A1
8X
H
B
M
16
q
SEATING
PLANE
C
T
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
10.15
10.45
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
PACKAGE THERMAL DATA
Parameter
DIP−16
SO−16L
Unit
RΘJC
Typical
42
23
°C/W
RΘJA
Typical
80
105
°C/W
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7
CS3524A
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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CS3524A/D