MCNIX MX29LV640BTXBC-12G 64m-bit [8m x 8/4m x 16] single voltage 3v only flash memory Datasheet

MX29LV640BT/BB
FEATURES
64M-BIT [8M x 8/4M x 16] SINGLE VOLTAGE 3V ONLY
FLASH MEMORY
GENERAL FEATURES
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• 8,388,608 x 8 / 4,194,304 x 16 switchable
• Sector structure
- 8KB (4KW) x 8 and 64KB(32KW) x 127
• Sector Protection/Chip Unprotect
- Provides sector group protect function to prevent
program or erase operation in the protected sector
group
- Provides chip unprotect function to allow code
changes
- Provides temporary sector group unprotect function
for code changes in previously protected sector groups
• Secured Silicon Sector
- Provides a 128-word area for code or data that can
be permanently protected.
- Once this sector is protected, it is prohibited to program or erase within the sector again.
• Latch-up protected to 250mA from -1V to Vcc + 1V
• Low Vcc write inhibit is equal to or less than 1.5V
• Compatible with JEDEC standard
- Pin-out and software compatible to single power supply Flash
SOFTWARE FEATURES
• Support Common Flash Interface (CFI)
- Flash device parameters stored on the device and
provide the host system to access.
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from
or program data to another sector which is not being
erased
• Status Reply
- Data# polling & Toggle bits provide detection of program and erase operation completion
HARDWARE FEATURES
• Ready/Busy (RY/BY#) Output
- Provides a hardware method of detecting program
and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal
state machine to read mode
• WP#/ACC input
- Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect
status
- ACC (high voltage) accelerates programming time
for higher throughput during system
PERFORMANCE
• High Performance
- Fast access time: 90/120ns
- Fast program time: 11us/word, 45s/chip (typical)
- Fast erase time: 0.9s/sector, 45s/chip (typical)
• Low Power Consumption
- Low active read current: 9mA (typical) at 5MHz
- Low standby current: 0.2uA (typ.)
• Minimum 100,000 erase/program cycle
• 10 years data retention
PACKAGE
• 48-pin TSOP
• 63-Ball CSP
• All Pb-free devices are RoHS Compliant
GENERAL DESCRIPTION
The MX29LV640BT/BB is a 64-mega bit Flash memory
organized as 8M bytes of 8 bits or 4M words of 16 bits.
MXIC's Flash memories offer the most cost-effective and
reliable read/write non-volatile random access memory.
The MX29LV640BT/BB is packaged in 48-pin TSOP and
63-ball CSP. It is designed to be reprogrammed and
erased in system or in standard EPROM programmers.
The standard MX29LV640BT/BB offers access time as
fast as 90ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29LV640BT/BB has separate chip enable
(CE#) and output enable (OE#) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
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1
MX29LV640BT/BB
AUTOMATIC SECTOR ERASE
MX29LV640BT/BB uses a command register to manage
this functionality.
The MX29LV640BT/BB is sector(s) erasable using
MXIC's Auto Sector Erase algorithm. Sector erase modes
allow sectors of the array to be erased in one erase cycle.
The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are controlled internally within the device.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and program
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and programming operations produces reliable
cycling. The MX29LV640BT/BB uses a 2.7V to 3.6V
VCC supply to perform the High Reliability Erase and
auto Program/Erase algorithms.
AUTOMATIC ERASE ALGORITHM
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the
status of the programming operation.
AUTOMATIC PROGRAMMING
The MX29LV640BT/BB is byte/word programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify
the data programmed. The typical chip programming time
at room temperature of the MX29LV640BT/BB is less
than 50 seconds.
Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE# .
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX29LV640BT/BB
electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection.
MXIC's Automatic Programming algorithm require the user
to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times
the programming pulse width, provides the program verification, and counts the number of sequences. A status
bit similar to DATA# polling and a status bit toggling between consecutive read cycles, provide feedback to the
user as to the status of the programming operation.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command register to respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 50 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 115 seconds. The Automatic Erase algorithm
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internally within the device.
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REV. 1.2, SEP. 07, 2005
2
MX29LV640BT/BB
PIN CONFIGURATION
48 TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX29LV640BT/BB
63 Ball CSP (Top View, Ball Down)
12.0 mm
8
NC
NC
7
NC
NC
A13
A12
A14
A15
A16
BYTE#
Q15/
A-1
GND
6
A9
A8
A10
A11
Q7
Q14
Q13
Q6
5
WE#
RESET#
A21
A19
Q5
Q12
VCC
Q4
4
RY/
BY#
WP#/
ACC
A18
A20
Q2
Q10
Q11
Q3
3
A7
A17
A6
A5
Q0
Q8
Q9
Q1
A3
A4
A2
A1
A0
CE#
OE#
GND
NC*
NC*
NC*
NC*
11.0 mm
2
NC*
1
NC*
NC*
A
B
C
D
E
F
G
H
J
K
NC*
NC*
NC*
NC*
L
M
* Ball are shorted together via the substrate but not connected to the die.
P/N:PM1076
REV. 1.2, SEP. 07, 2005
3
MX29LV640BT/BB
LOGIC SYMBOL
PIN DESCRIPTION
SYMBOL
PIN NAME
A0~A21
Address Input
Q0~Q14
Data Inputs/Outputs
Q15/A-1
Q15(Word Mode)/LSB addr(Byte Mode)
CE#
Chip Enable Input
WE#
Write Enable Input
OE#
Output Enable Input
RESET#
Hardware Reset Pin, Active Low
22
A0-A21
CE#
OE#
WP#/ACC Hardware Write Protect/Programming
Acceleration Input
RY/BY#
WE#
Read/Busy Output
BYTE#
Selects 8 bit or 16 bit mode
VCC
+3.0V single power supply
GND
Device Ground
NC
Pin Not Connected Internally
16 or 8
Q0-Q15
(A-1)
RY/BY#
RESET#
WP#/ACC
BYTE#
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REV. 1.2, SEP. 07, 2005
4
MX29LV640BT/BB
BLOCK DIAGRAM
CE#
OE#
WE#
WP#/ACC
BYTE#
RESET#
WRITE
CONTROL
LOGIC
STATE
HIGH VOLTAGE
MACHINE
(WSM)
LATCH
BUFFER
STATE
FLASH
REGISTER
ARRAY
ARRAY
Y-DECODER
AND
X-DECODER
ADDRESS
A0-A21
PROGRAM/ERASE
INPUT
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15
I/O BUFFER
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REV. 1.2, SEP. 07, 2005
5
MX29LV640BT/BB
MX29LV640BT SECTOR GROUP ARCHITECTURE
Sector
Group
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
10
10
10
10
Sector Sector Address
A21-A12
SA0
0000000xxx
SA1
0000001xxx
SA2
0000010xxx
SA3
0000011xxx
SA4
0000100xxx
SA5
0000101xxx
SA6
0000110xxx
SA7
0000111xxx
SA8
0001000xxx
SA9
0001001xxx
SA10
0001010xxx
SA11
0001011xxx
SA12
0001100xxx
SA13
0001101xxx
SA14
0001110xxx
SA15
0001111xxx
SA16
0010000xxx
SA17
0010001xxx
SA18
0010010xxx
SA19
0010011xxx
SA20
0010100xxx
SA21
0010101xxx
SA22
0010110xxx
SA23
0010111xxx
SA24
0011000xxx
SA25
0011001xxx
SA26
0011010xxx
SA27
0011011xxx
SA28
0011100xxx
SA29
0011101xxx
SA30
0011110xxx
SA31
0011111xxx
SA32
0100000xxx
SA33
0100001xxx
SA34
0100010xxx
SA35
0100011xxx
SA36
0100100xxx
SA37
0100101xxx
SA38
0100110xxx
SA39
0100111xxx
Sector Size
(Kbytes/Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
P/N:PM1076
(x8)
Address Range
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
(x16)
Address Range
000000h-07FFFh
008000h-0FFFFh
010000h-17FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
REV. 1.2, SEP. 07, 2005
6
MX29LV640BT/BB
Sector
Group
11
11
11
11
12
12
12
12
13
13
13
13
14
14
14
14
15
15
15
15
16
16
16
16
17
17
17
17
18
18
18
18
19
19
19
19
20
20
20
20
Sector Sector Address
A21-A12
SA40
0101000xxx
SA41
0101001xxx
SA42
0101010xxx
SA43
0101011xxx
SA44
0101100xxx
SA45
0101101xxx
SA46
0101110xxx
SA47
0101111xxx
SA48
0110000xxx
SA49
0110001xxx
SA50
0110010xxx
SA51
0110011xxx
SA52
0110100xxx
SA53
0110101xxx
SA54
0110110xxx
SA55
0110111xxx
SA56
0111000xxx
SA57
0111001xxx
SA58
0111010xxx
SA59
0111011xxx
SA60
0111100xxx
SA61
0111101xxx
SA62
0111110xxx
SA63
0111111xxx
SA64
1000000xxx
SA65
1000001xxx
SA66
1000010xxx
SA67
1000011xxx
SA68
1000100xxx
SA69
1000101xxx
SA70
1000110xxx
SA71
1000111xxx
SA72
1001000xxx
SA73
1001001xxx
SA74
1001010xxx
SA75
1001011xxx
SA76
1001100xxx
SA77
1001101xxx
SA78
1001110xxx
SA79
1001111xxx
Sector Size
(Kbytes/Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
P/N:PM1076
(x8)
Address Range
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
400000h-40FFFFh
410000h-41FFFFh
420000h-42FFFFh
430000h-43FFFFh
440000h-44FFFFh
450000h-45FFFFh
460000h-46FFFFh
470000h-47FFFFh
480000h-48FFFFh
490000h-49FFFFh
4A0000h-4AFFFFh
4B0000h-4BFFFFh
4C0000h-4CFFFFh
4D0000h-4DFFFFh
4E0000h-4EFFFFh
4F0000h-4FFFFFh
(x16)
Address Range
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-147FFFh
168000h-14FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1FFFFFh
200000h-207FFFh
208000h-20FFFFh
210000h-217FFFh
218000h-21FFFFh
220000h-227FFFh
228000h-22FFFFh
230000h-237FFFh
238000h-23FFFFh
240000h-247FFFh
248000h-24FFFFh
250000h-257FFFh
258000h-25FFFFh
260000h-247FFFh
268000h-24FFFFh
270000h-277FFFh
278000h-27FFFFh
REV. 1.2, SEP. 07, 2005
7
MX29LV640BT/BB
Sector
Group
21
21
21
21
22
22
22
22
23
23
23
23
24
24
24
24
25
25
25
25
26
26
26
26
27
27
27
27
28
28
28
28
29
29
29
29
30
30
30
30
Sector Sector Address
A21-A12
SA80
1010000xxx
SA81
1010001xxx
SA82
1010010xxx
SA83
1010011xxx
SA84
1010100xxx
SA85
1010101xxx
SA86
1010110xxx
SA87
1010111xxx
SA88
1011000xxx
SA89
1011001xxx
SA90
1011010xxx
SA91
1011011xxx
SA92
1011100xxx
SA93
1011101xxx
SA94
1011110xxx
SA95
1011111xxx
SA96
1100000xxx
SA97
1100001xxx
SA98
1100010xxx
SA99
1100011xxx
SA100 1100100xxx
SA101 1100101xxx
SA102 1100110xxx
SA103 1100111xxx
SA104 1101000xxx
SA105 1101001xxx
SA106 1101010xxx
SA107 1101011xxx
SA108 1101100xxx
SA109 1101101xxx
SA110 1101110xxx
SA111 1101111xxx
SA112 1110000xxx
SA113 1110001xxx
SA114 1110010xxx
SA115 1110011xxx
SA116 1110100xxx
SA117 1110101xxx
SA118 1110110xxx
SA119 1110111xxx
Sector Size
(Kbytes/Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
P/N:PM1076
(x8)
Address Range
500000h-50FFFFh
510000h-51FFFFh
520000h-52FFFFh
530000h-53FFFFh
540000h-54FFFFh
550000h-55FFFFh
560000h-56FFFFh
570000h-57FFFFh
580000h-58FFFFh
590000h-59FFFFh
5A0000h-5AFFFFh
5B0000h-5BFFFFh
5C0000h-5CFFFFh
5D0000h-5DFFFFh
5E0000h-5EFFFFh
5F0000h-5FFFFFh
600000h-60FFFFh
610000h-61FFFFh
620000h-62FFFFh
630000h-63FFFFh
640000h-64FFFFh
650000h-65FFFFh
660000h-66FFFFh
670000h-67FFFFh
680000h-68FFFFh
690000h-69FFFFh
6A0000h-6AFFFFh
6B0000h-6BFFFFh
6C0000h-6CFFFFh
6D0000h-6DFFFFh
6E0000h-6EFFFFh
6F0000h-6FFFFFh
700000h-70FFFFh
710000h-71FFFFh
720000h-72FFFFh
730000h-73FFFFh
740000h-74FFFFh
750000h-75FFFFh
760000h-76FFFFh
770000h-77FFFFh
(x16)
Address Range
280000h-287FFFh
288000h-28FFFFh
290000h-297FFFh
298000h-29FFFFh
2A0000h-2A7FFFh
2A8000h-2AFFFFh
2B0000h-2B7FFFh
2B8000h-2BFFFFh
2C0000h-2C7FFFh
2C8000h-2CFFFFh
2D0000h-2D7FFFh
2D8000h-2DFFFFh
2E0000h-2E7FFFh
2E8000h-2EFFFFh
2F0000h-2F7FFFh
2F8000h-2FFFFFh
300000h-307FFFh
308000h-30FFFFh
310000h-317FFFh
318000h-31FFFFh
320000h-327FFFh
328000h-32FFFFh
330000h-337FFFh
338000h-33FFFFh
340000h-347FFFh
348000h-34FFFFh
350000h-357FFFh
358000h-35FFFFh
360000h-347FFFh
368000h-34FFFFh
370000h-377FFFh
378000h-37FFFFh
380000h-387FFFh
388000h-38FFFFh
390000h-397FFFh
398000h-39FFFFh
3A0000h-3A7FFFh
3A8000h-3AFFFFh
3B0000h-3B7FFFh
3B8000h-3BFFFFh
REV. 1.2, SEP. 07, 2005
8
MX29LV640BT/BB
Sector
Group
31
31
31
31
32
32
32
33
34
35
36
37
38
39
40
Sector Sector Address
A21-A12
SA120 1111000xxx
SA121 1111001xxx
SA122 1111010xxx
SA123 1111011xxx
SA124 1111100xxx
SA125 1111101xxx
SA126 1111110xxx
SA127 1111111000
SA128 1111111001
SA129 1111111010
SA130 1111111011
SA131 1111111100
SA132 1111111101
SA133 1111111110
SA134 1111111111
Sector Size
(Kbytes/Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
(x8)
Address Range
780000h-78FFFFh
790000h-79FFFFh
7A0000h-7AFFFFh
7B0000h-7BFFFFh
7C0000h-7CFFFFh
7D0000h-7DFFFFh
7E0000h-7EFFFFh
7F0000h-7F1FFFh
7F2000h-7F3FFFh
7F4000h-7F5FFFh
7F6000h-7F7FFFh
7F8000h-7F9FFFh
7FA000h-7FBFFFh
7FC000h-7FDFFFh
7FE000h-7FFFFFh
(x16)
Address Range
3C0000h-3C7FFFh
3C8000h-3CFFFFh
3D0000h-3D7FFFh
3D8000h-3DFFFFh
3E0000h-3E7FFFh
3E8000h-3EFFFFh
3F0000h-3F7FFFh
3F8000h-3FFFFFh
3F9000h-3F9FFFh
3FA000h-3FAFFFh
3FB000h-3FBFFFh
3FC000h-3FCFFFh
3FD000h-3FDFFFh
3FE000h-3FEFFFh
3FF000h-3FFFFFh
Note:The address range is A21:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH)
Top Boot Security Sector Addresses
Sector Address
A21~A12
1111111111
Sector Size
(bytes/words)
256/128
(x8)
Address Range
7FFF00h-7FFFFFh
P/N:PM1076
(x16)
Address Range
3FFF70h-3FFFFFh
REV. 1.2, SEP. 07, 2005
9
MX29LV640BT/BB
MX29LV640BB SECTOR GROUP ARCHITECTURE
Sector
Group
1
2
3
4
5
6
7
8
9
9
9
10
10
10
10
11
11
11
11
12
12
12
12
13
13
13
13
14
14
14
14
15
15
15
15
16
16
16
16
Sector Sector Address
A21-A12
SA0
0000000000
SA1
0000000001
SA2
0000000010
SA3
0000000011
SA4
0000000100
SA5
0000000101
SA6
0000000110
SA7
0000000111
SA8
0000001xxx
SA9
0000010xxx
SA10
0000011xxx
SA11
0000100xxx
SA12
0000101xxx
SA13
0000110xxx
SA14
0000111xxx
SA15
0001000xxx
SA16
0001001xxx
SA17
0001010xxx
SA18
0001011xxx
SA19
0001100xxx
SA20
0001101xxx
SA21
0001110xxx
SA22
0001111xxx
SA23
0010000xxx
SA24
0010001xxx
SA25
0010010xxx
SA26
0010011xxx
SA27
0010100xxx
SA28
0010101xxx
SA29
0010110xxx
SA30
0010111xxx
SA31
0011000xxx
SA32
0011001xxx
SA33
0011010xxx
SA34
0011011xxx
SA35
0011100xxx
SA36
0011101xxx
SA37
0011110xxx
SA38
0011111xxx
Sector Size
(Kbytes/Kwords)
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
P/N:PM1076
(x8)
Address Range
000000h-001FFFh
002000h-003FFFh
004000h-005FFFh
006000h-007FFFh
008000h-009FFFh
00A000h-00BFFFh
00C000h-00DFFFh
00E000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
(x16)
Address Range
000000h-000FFFh
001000h-001FFFh
002000h-002FFFh
003000h-003FFFh
004000h-004FFFh
005000h-005FFFh
006000h-006FFFh
007000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
REV. 1.2, SEP. 07, 2005
10
MX29LV640BT/BB
Sector
Group
17
17
17
17
18
18
18
18
19
19
19
19
20
20
20
20
21
21
21
21
22
22
22
22
23
23
23
23
24
24
24
24
25
25
25
25
26
26
26
26
Sector Sector Address
A21-A12
SA39
0100000xxx
SA40
0100001xxx
SA41
0100010xxx
SA42
0100011xxx
SA43
0100100xxx
SA44
0100101xxx
SA45
0100110xxx
SA46
0100111xxx
SA47
0101000xxx
SA48
0101001xxx
SA49
0101010xxx
SA50
0101011xxx
SA51
0101100xxx
SA52
0101101xxx
SA53
0101110xxx
SA54
0101111xxx
SA55
0110000xxx
SA56
0110001xxx
SA57
0110010xxx
SA58
0110011xxx
SA59
0110100xxx
SA60
0110101xxx
SA61
0110110xxx
SA62
0110111xxx
SA63
0111000xxx
SA64
0111001xxx
SA65
0111010xxx
SA66
0111011xxx
SA67
0111100xxx
SA68
0111101xxx
SA69
0111110xxx
SA70
0111111xxx
SA71
1000000xxx
SA72
1000001xxx
SA73
1000010xxx
SA74
1000011xxx
SA75
1000100xxx
SA76
1000101xxx
SA77
1000110xxx
SA78
1000111xxx
Sector Size
(Kbytes/Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
P/N:PM1076
(x8)
Address Range
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
400000h-40FFFFh
410000h-41FFFFh
420000h-42FFFFh
430000h-43FFFFh
440000h-44FFFFh
450000h-45FFFFh
460000h-46FFFFh
470000h-47FFFFh
(x16)
Address Range
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1FFFFFh
200000h-207FFFh
208000h-20FFFFh
210000h-217FFFh
218000h-21FFFFh
220000h-227FFFh
228000h-22FFFFh
230000h-237FFFh
238000h-23FFFFh
REV. 1.2, SEP. 07, 2005
11
MX29LV640BT/BB
Sector
Group
27
27
27
27
28
28
28
28
29
29
29
29
30
30
30
30
31
31
31
31
32
32
32
32
33
33
33
33
34
34
34
34
35
35
35
35
36
36
36
36
Sector Sector Address
A21-A12
SA79
1001000xxx
SA80
1001001xxx
SA81
1001010xxx
SA82
1001011xxx
SA83
1001100xxx
SA84
1001101xxx
SA85
1001110xxx
SA86
1001111xxx
SA87
1010000xxx
SA88
1010001xxx
SA89
1010010xxx
SA90
1010011xxx
SA91
1010100xxx
SA92
1010101xxx
SA93
1010110xxx
SA94
1010111xxx
SA95
1011000xxx
SA96
1011001xxx
SA97
1011010xxx
SA98
1011011xxx
SA99
1011100xxx
SA100 1011101xxx
SA101 1011110xxx
SA102 1011111xxx
SA103 1100000xxx
SA104 1100001xxx
SA105 1100010xxx
SA106 1100011xxx
SA107 1100100xxx
SA108 1100101xxx
SA109 1100110xxx
SA110 1100111xxx
SA111 1101000xxx
SA112 1101001xxx
SA113 1101010xxx
SA114 1101011xxx
SA115 1101100xxx
SA116 1101101xxx
SA117 1101110xxx
SA118 1101111xxx
Sector Size
(Kbytes/Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
P/N:PM1076
(x8)
Address Range
480000h-48FFFFh
490000h-49FFFFh
4A0000h-4AFFFFh
4B0000h-4BFFFFh
4C0000h-4CFFFFh
4D0000h-4DFFFFh
4E0000h-4EFFFFh
4F0000h-4FFFFFh
500000h-50FFFFh
510000h-51FFFFh
520000h-52FFFFh
530000h-53FFFFh
540000h-54FFFFh
550000h-55FFFFh
560000h-56FFFFh
570000h-57FFFFh
580000h-58FFFFh
590000h-59FFFFh
5A0000h-5AFFFFh
5B0000h-5BFFFFh
5C0000h-5CFFFFh
5D0000h-5DFFFFh
5E0000h-5EFFFFh
5F0000h-5FFFFFh
600000h-60FFFFh
610000h-61FFFFh
620000h-62FFFFh
630000h-63FFFFh
640000h-64FFFFh
650000h-65FFFFh
660000h-66FFFFh
670000h-67FFFFh
680000h-68FFFFh
690000h-69FFFFh
6A0000h-6AFFFFh
6B0000h-6BFFFFh
6C0000h-6CFFFFh
6D0000h-6DFFFFh
6E0000h-6EFFFFh
6F0000h-6FFFFFh
(x16)
Address Range
240000h-247FFFh
248000h-24FFFFh
250000h-257FFFh
258000h-25FFFFh
260000h-267FFFh
268000h-26FFFFh
270000h-277FFFh
278000h-27FFFFh
280000h-287FFFh
288000h-28FFFFh
290000h-297FFFh
298000h-29FFFFh
2A0000h-2A7FFFh
2A8000h-2AFFFFh
2B0000h-2B7FFFh
2B8000h-2BFFFFh
2C0000h-2C7FFFh
2C8000h-2CFFFFh
2D0000h-2D7FFFh
2D8000h-2DFFFFh
2E0000h-2E7FFFh
2E8000h-2EFFFFh
2F0000h-2F7FFFh
2F8000h-2FFFFFh
300000h-307FFFh
308000h-30FFFFh
310000h-317FFFh
318000h-31FFFFh
320000h-327FFFh
328000h-32FFFFh
330000h-337FFFh
338000h-33FFFFh
340000h-347FFFh
348000h-34FFFFh
350000h-357FFFh
358000h-35FFFFh
360000h-367FFFh
368000h-36FFFFh
370000h-377FFFh
378000h-37FFFFh
REV. 1.2, SEP. 07, 2005
12
MX29LV640BT/BB
Sector
Group
37
37
37
37
38
38
38
38
39
39
39
39
40
40
40
40
Sector Sector Address
A21-A12
SA119 1110000xxx
SA120 1110001xxx
SA121 1110010xxx
SA122 1110011xxx
SA123 1110100xxx
SA124 1110101xxx
SA125 1110110xxx
SA126 1110111xxx
SA127 1111000xxx
SA128 1111001xxx
SA129 1111010xxx
SA130 1111011xxx
SA131 1111100xxx
SA132 1111101xxx
SA133 1111110xxx
SA134 1111111xxx
Sector Size
(Kbytes/Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
(x8)
Address Range
700000h-70FFFFh
710000h-71FFFFh
720000h-72FFFFh
730000h-73FFFFh
740000h-74FFFFh
750000h-75FFFFh
760000h-76FFFFh
770000h-77FFFFh
780000h-78FFFFh
790000h-79FFFFh
7A0000h-7AFFFFh
7B0000h-7BFFFFh
7C0000h-7CFFFFh
7D0000h-7DFFFFh
7E0000h-7EFFFFh
7F0000h-7FFFFFh
(x16)
Address Range
380000h-387FFFh
388000h-38FFFFh
390000h-397FFFh
398000h-39FFFFh
3A0000h-3A7FFFh
3A8000h-3AFFFFh
3B0000h-3B7FFFh
3B8000h-3BFFFFh
3C0000h-3C7FFFh
3C8000h-3CFFFFh
3D0000h-3D7FFFh
3D8000h-3DFFFFh
3E0000h-3E7FFFh
3E8000h-3EFFFFh
3F0000h-3F7FFFh
3F8000h-3FFFFFh
Note:The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH)
Bottom Boot Security Sector Addresses
Sector Address
A21~A12
0000000000
Sector Size
(bytes/words)
256/128
(x8)
Address Range
000000h-0000FFh
P/N:PM1076
(x16)
Address Range
000000-00007Fh
REV. 1.2, SEP. 07, 2005
13
MX29LV640BT/BB
Table 1. BUS OPERATION (1)
Q8~Q15
Operation
CE# OE# WE#
RE-
WP#
ACC
Address
Q0~Q7 BYTE#
SET#
Read
L
L
H
H
L/H
X
AIN
DOUT
BYTE#
=VIH
=VIL
DOUT
Q8-Q14=
High Z
Q15=A-1
Write (Program/Erase)
L
H
L
H
(Note 2)
X
AIN
(Note 3) (Note 3) Q8-Q14=
High Z
Q15=A-1
Accelerated Program
L
H
L
H
(Note 2)
VHH
AIN
(Note 3) (Note 3) Q8-Q14=
High Z
Q15=A-1
Standby
VCC±
X
X
0.3V
VCC±
H
H
X
High-Z
High-Z
High-Z
0.3V
Output Disable
L
H
H
H
L/H
X
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
L/H
X
X
High-Z
High-Z
High-Z
Sector Group Protect
L
H
L
VID
L/H
X
X
X
X
X
(Note 2)
Chip unprotect
A6=L,A1=H,A0=L
L
H
L
VID
(Note 2)
X
(Note 2)
Temporary Sector
Sector Addresses, (Note 3)
Sector Addresses, (Note 3)
A6=H, A1=H, A0=L
X
X
X
VID
(Note 2)
X
AIN
(Note 3) (Note 3)
High-Z
Group Unprotect
Legend:
L=Logic LOW=VIL, H=Logic High=VIH, VID=12.0±0.5V, X=Don't Care, AIN=Address IN, DIN=Data IN, DOUT=Data OUT
Notes:
1. The sector group protect and chip unprotect functions may also be implemented via programming equipment. See
the "Sector Group Protection and Chip Unprotect" section.
2. If WP#=VIL, the two outermost boot sectors remain protected. If WP#=VIH, the two outermost boot sector
protection depends on whether they were last protected or unprotect using the method described in "Sector/ Sector
Block Protection and Unprotect".
3. DIN or DOUT as required by command sequence, Data# polling or sector protect algorithm (see Figure 14).
P/N:PM1076
REV. 1.2, SEP. 07, 2005
14
MX29LV640BT/BB
Table 2. AUTOSELECT CODES (High Voltage Method)
Operation
Read
CE# OE# WE# A0
A1
A5
A6
A8
to
to
A2
A7
A9
A14 A15
to
to
A10 A21
Manufactures Code
L
L
H
L
L
X
X
X
VID
X
X
XXC2H
Device Code
L
L
H
H
L
X
X
X
VID
X
X
22C9H (word)
Silicon (Top Boot Block)
ID
Q0~Q15
Device Code
XXC9H (byte)
L
L
H
H
L
X
X
X
VID
X
X
(Bottom Boot Block)
Sector Protect Verify
XXCBH (byte)
L
L
H
X
H
X
X
X
VID
X
SA
Secured Silicon Sector
Indicator Bit (Q7)
22CBH (word)
Code(1)
xx88h
L
L
H
H
H
X
L
X
VID
X
X
(factory locked)
xx08h
(non-factory locked)
Notes:
1.code=xx00h means unprotected, or code=xx01h means protected, SA=Sector Address, X=Don't care.
P/N:PM1076
REV. 1.2, SEP. 07, 2005
15
MX29LV640BT/BB
REQUIREMENTS FOR READING ARRAY
DATA
ACCELERATED PROGRAM OPERATION
The device offers accelerated program operations through
the ACC function. This is one of two functions provided
by the WP#/ACC pin. This function is primarily intended
to allow faster manufacturing throughput at the factory.
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should remain at VIH.
If the system asserts VHH on this pin, the device automatically enters the aforementioned accelerated program
mode, temporarily unprotects any protected sectors, and
uses the higher voltage on the pin to reduce the time
required for program operations. Removing VHH from the
WP#/ACC pin must not be at VHH for operations other
than accelerated programming, or device damage may
result.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid address on
the device address inputs produce valid data on the device data outputs. The device remains enabled for read
access until the command register contents are altered.
STANDBY MODE
MX29LV640BT/BB can be set into Standby mode with
two different approaches. One is using both CE# and
RESET# pins and the other one is using RESET# pin
only.
WRITE COMMANDS/COMMAND SEQUENCES
To program data to the device or erase sectors of memory
, the system must drive WE# and CE# to VIL, and OE#
to VIH.
When using both pins of CE# and RESET#, a CMOS
Standby mode is achieved with both pins held at Vcc ±
0.3V. Under this condition, the current consumed is less
than 0.2uA (typ.). If both of the CE# and RESET# are
held at VIH, but not within the range of VCC ± 0.3V, the
device will still be in the standby mode, but the standby
current will be larger. During Auto Algorithm operation,
Vcc active current (Icc2) is required even CE# = "H"
until the operation is completed. The device can be read
with standard access time (tCE) from either of these
standby modes.
An erase operation can erase one sector, multiple sectors , or the entire device. Table indicates the address
space that each sector occupies. A "sector address"
consists of the address bits required to uniquely select a
sector. The "Writing specific address and data commands
or sequences into the command register initiates device
operations. Table 1 defines the valid register command
sequences. Writing incorrect address and data values or
writing them in the improper sequence resets the device
to reading array data. Section has details on erasing a
sector or the entire chip, or suspending/resuming the erase
operation.
When using only RESET#, a CMOS standby mode is
achieved with RESET# input held at Vss ± 0.3V, Under
this condition the current is consumed less than 1uA
(typ.). Once the RESET# pin is taken high, the device is
back to active without recovery delay.
After the system writes the Automatic Select command
sequence, the device enters the Automatic Select mode.
The system can then read Automatic Select codes from
the internal register (which is separate from the memory
array) on Q7-Q0. Standard read cycle timings apply in
this mode. Refer to the Automatic Select Mode and Automatic Select Command Sequence section for more
information.
In the standby mode the outputs are in the high impedance state, independent of the OE# input.
MX29LV640BT/BB is capable to provide the Automatic
Standby Mode to restrain power consumption during readout of data. This mode can be used effectively with an
application requested low power consumption such as
handy terminals.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC
Characteristics" section contains timing specification
table and timing diagrams for write operations.
To active this mode, MX29LV640BT/BB automatically
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If RESET# is asserted during a program or erase
operation, the RY/BY# pin remains a "0" (busy) until the
internal reset operation is complete, which requires a time
of tREADY. The system can thus monitor RY/BY# to
determine whether the reset operation is complete. If
RESET# is asserted when a program or erase operation
is completed within a time of tREADY. The system can
read data tRH after the RESET# pin returns to VIH.
switch themselves to low power mode when
MX29LV640BT/BB addresses remain stable during access time of tACC+30ns. It is not necessary to control
CE#, WE#, and OE# on the mode. Under the mode, the
current consumed is typically 0.2uA (CMOS level).
AUTOMATIC SLEEP MODE
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 3 for the timing diagram.
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this
mode when address remain stable for tACC+30ns. The
automatic sleep mode is independent of the CE#, WE#,
and OE# control signals. Standard address access timings provide new data when addresses are changed. While
in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table
represents the automatic sleep mode current specification.
SECTOR GROUP PROTECT OPERATION
The MX29LV640BT/BB features hardware sector group
protection. This feature will disable both program and
erase operations for these sector group protected. In this
device, a sector group consists of four adjacent sectors
which are protected or unprotected at the same time. To
activate this mode, the programming equipment must force
VID on address pin A9 and control pin OE#, (suggest
VID = 12V) A6 = VIL and CE# = VIL. (see Table 2) Programming of the protection circuitry begins on the falling
edge of the WE# pulse and is terminated on the rising
edge. Please refer to sector group protect algorithm and
waveform.
OUTPUT DISABLE
With the OE# input at a logic high level (VIH), output
from the devices are disabled. This will cause the output
pins to be in a high impedance state.
MX29LV640BT/BB also provides another method. Which
requires VID on the RESET# only. This method can be
implemented either in-system or via programming equipment. This method uses standard microprocessor bus
cycle timing.
RESET# OPERATION
The RESET# pin provides a hardware method of resetting
the device to reading array data. When the RESET# pin
is driven low for at least a period of tRP, the device
immediately terminates any operation in progress,
tristates all output pins, and ignores all read/write
commands for the duration of the RESET# pulse. The
device also resets the internal state machine to reading
array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another
command sequence, to ensure data integrity
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
( with CE# and OE# at VIL and WE# at VIH). When
A1=1, it will produce a logical "1" code at device output
Q0 for a protected sector. Otherwise the device will produce 00H for the unprotected sector. In this mode, the
addresses, except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer
and device codes. (Read Silicon ID)
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at VSS±0.3V, the device draws
CMOS standby current (ICC4). If RESET# is held at VIL
but not within VSS±0.3V, the standby current will be
greater.
It is also possible to determine if the group is protected
in the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.
The RESET# pin may be tied to system reset circuitry.
A system reset would that also reset the Flash memory,
enabling the system to read the boot-up firmware from
the Flash memory.
CHIP UNPROTECT OPERATION
The MX29LV640BT/BB also features the chip unprotect
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unconnected; inconsistent behavior of the device may
result.
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in the
code. It is recommended to protect all sectors before activating chip unprotect mode.
TEMPORARY SECTOR GROUP UNPROTECT
OPERATION
To activate this mode, the programming equipment must
force VID on control pin OE# and address pin A9. The
CE# pins must be set at VIL. Pins A6 must be set to
VIH. (see Table 2) Refer to chip unprotect algorithm and
waveform for the chip unprotect algorithm. The unprotect
mechanism begins on the falling edge of the WE# pulse
and is terminated on the rising edge.
This feature allows temporary unprotect of previously
protected sector to change data in-system. The Temporary Sector Unprotect mode is activated by setting the
RESET# pin to VID(11.5V-12.5V). During this mode, formerly protected sectors can be programmed or erased
as unprotect sector. Once VID is remove from the RESET# pin, all the previously protected sectors are protected again.
MX29LV640BT/BB also provides another method. Which
requires VID on the RESET# only. This method can be
implemented either in-system or via programming equipment. This method uses standard microprocessor bus
cycle timing.
SILICON ID READ OPERATION
It is also possible to determine if the chip is unprotect in
the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs (Q0-Q7) for an unprotect sector. It is
noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the
device resides in the target system. PROM programmers typically access signature codes by raising A9 to
a high voltage. However, multiplexing high voltage onto
address lines is not generally desired system design practice.
WRITE PROTECT (WP#)
MX29LV640BT/BB provides hardware method to access
the silicon ID read operation. Which method requires VID
on A9 pin, VIL on CE#, OE#, A6, and A1 pins. Which
apply VIL on A0 pin, the device will output MXIC's manufacture code of C2H. Which apply VIH on A0 pin, the
device will output MX29LV640BT/BB device code of C9H/
CBH.
The write protect function provides a hardware method
to protect boot sectors without using VID.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two "outermost" 8 Kbyte boot sectors independently of whether
those sectors were protected or unprotect using the
method described in Sector/Sector Group Protection and
Chip Unprotect". The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses
in a bottom-boot-configured device, or the two sectors
containing the highest addresses in a top-boot-configured device.
VERIFY SECTOR GROUP PROTECT STATUS
OPERATION
MX29LV640BT/BB provides hardware method for sector
group protect status verify. Which method requires VID
on A9 pin, VIH on WE# and A1 pins, VIL on CE#, OE#,
A6, and A0 pins, and sector address on A16 to A21 pins.
Which the identified sector is protected, the device will
output 01H. Which the identified sector is not protect,
the device will output 00H.
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the two outermost 8K Byte boot
sectors were last set to be protected or unprotect. That
is, sector protection or unprotection for these two sectors
depends on whether they were last protected or unprotect
using the method described in "Sector/Sector Group Protection and Chip Unprotect".
DATA PROTECTION
Note that the WP#/ACC pin must not be left floating or
The MX29LV640BT/BB is designed to offer protection
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against accidental erasure or programming caused by
spurious system level signals that may exist during power
transition. During power up the device automatically resets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific command sequences. The device also
incorporates several features to prevent inadvertent write
cycles resulting from VCC power-up and power-down transition or system noise.
is removed from the device. On power-up, or following a
hardware reset, the device reverts to sending command
to sector SA0.
LOW VCC WRITE INHIBIT
When VCC is less than VLKO the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional write
when VCC is greater than VLKO.
SECURED SILICON SECTOR
The MX29LV640BT/BB features a OTP memory region
where the system may access through a command sequence to create a permanent part identification as so
called Electronic Serial Number (ESN) in the device.
Once this region is programmed, any further modification on the region is impossible. The secured silicon sector
is a 128 words in length, and uses a Secured Silicon
Sector Indicator Bit (Q7) to indicate whether or not the
Secured Silicon Sector is locked when shipped from the
factory. This bit is permanently set at the factory and
cannot be changed, which prevent duplication of a factory locked part. This ensures the security of the ESN
once the product is shipped to the field.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns (typical) on CE# or WE#
will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE# = VIL,
CE# = VIH or WE# = VIH. To initiate a write cycle CE#
and WE# must be a logical zero while OE# is a logical
one.
The MX29LV640BT/BB offers the device with Secured
Silicon Sector either factory locked or customer lockable. The factory-locked version is always protected
when shipped from the factory , and has the Secured
Silicon Sector Indicator Bit permanently set to a "1".
The customer-lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to
utilize that sector in any form they prefer. The customerlockable version has the secured sector Indicator Bit
permanently set to a "0". Therefore, the Secured Silicon
Sector Indicator Bit prevents customer, lockable device
from being used to replace devices that are factory locked.
POWER-UP SEQUENCE
The MX29LV640BT/BB powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of the predefined command
sequences.
POWER-UP WRITE INHIBIT
The system access the Secured Silicon Sector through
a command sequence (refer to "Enter Secured Silicon/
Exit Secured Silicon Sector command Sequence). After
the system has written the Enter Secured Silicon Sector
command sequence, it may read the Secured Silicon
Sector by using the address normally occupied by the
last sector SA134 (for MX29LV640BT) or first sector SA0
(for MX29LV640BB). Once entry the Secured Silicon
Sector the operation of boot sectors is disabled but the
operation of main sectors is as normally. This mode of
operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power
If WE#=CE#=VIL and OE#=VIH during power up, the
device does not accept commands on the rising edge of
WE#. The internal state machine is automatically reset
to the read mode on power-up.
POWER SUPPLY DE COUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected between its VCC and GND.
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FACTORY LOCKED:Secured Silicon Sector
Programmed and Protected At the Factory
In device with an ESN, the Secured Silicon Sector is
protected when the device is shipped from the factory.
The Secured Silicon Sector cannot be modified in any
way. A factory locked device has an 8-word random ESN
at address 3FFF70h-3FFF77h (for MX29LV640BT) or
000000h-000007h (for MX29LV640BB).
CUSTOMER LOCKABLE:Secured Silicon
Sector NOT Programmed or Protected At the
Factory
As an alternative to the factory-locked version, the device
may be ordered such that the customer may program
and protect the 128-word Secured Silicon Sector.
Programming and protecting the Secured Silicon Sector
must be used with caution since, once protected, there
is no procedure available for unprotected the Secured
Silicon Sector area and none of the bits in the Secured
Silicon Sector memory space can be modified in any
way.
The Secured Silicon Sector area can be protected using
one of the following procedures:
Write the three-cycle Enter Secured Silicon Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 14, except
that RESET# may be at either VIH or VID. This allows insystem protection of the Secured Silicon Sector without
raising any device pin to a high voltage. Note that method
is only applicable to the Secured Silicon Sector.
Write the three-cycle Enter Secured Silicon Sector Region
command sequence, and then alternate method of sector
protection described in the :Sector Group Protection and
Unprotect" section.
Once the Secured Silicon Sector is programmed, locked
and verified, the system must write the Exit Secured
Silicon Sector Region command sequence to return to
reading and writing the remainder of the array.
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MX29LV640BT/BB
Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress. Either of the two
reset command sequences will reset the device (when
applicable).
SOFTWARE COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them
in the improper sequence will reset the device to the
read mode. Table 3 defines the valid register command
sequences. Note that the Erase Suspend (B0H) and
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data are latched on
rising edge of WE# or CE#, whichever happens first.
TABLE 3. MX29LV640BT/BB COMMAND DEFINITIONS
First Bus
Command
Bus
Cycle
Second Bus Third Bus
Cycle
Fourth Bus
Cycle
Cycle
Cycles Addr Data Addr Data Addr Data Addr
Fifth Bus
Cycle
Data
Sixth Bus
Cycle
Addr Data Addr Data
Read (Note 5)
1
RA
RD
Reset (Note 6)
1
XXX
F0
Word
4
555
AA
2AA
55
555
90
X00
C2H
Byte
4
AAA
AA
555
55
AAA
90
X00
C2H
Word
4
555
AA
2AA
55
555
90
X01
DDI
Byte
4
AAA
AA
555
55
AAA
90
X02
Secured Sector Fact-
Word
4
555
AA
2AA
55
555
90
X03
see
ory Protect (Note 9)
Byte
4
AAA
AA
555
55
AAA
90
X06
note 9
Sector Group Protect
Word
4
555
AA
2AA
55
555
90
(SA)X02 xx00/
Verify (Note 8)
Byte
4
AAA
AA
555
55
AAA
90
(SA)X04 xx01
Enter Secured Silicon
Word
3
555
AA
2AA
55
555
88
Sector
Byte
3
AAA
AA
555
55
AAA
88
Exit Secured Silicon
Word
4
555
AA
2AA
55
555
90
XXX
00
Sector
Byte
4
AAA
AA
555
55
AAA
90
XXX
00
Program
Word
4
555
AA
2AA
55
555
A0
PA
PD
Byte
4
AAA
AA
555
55
AAA
A0
PA
PD
Word
6
555
AA
2AA
55
555
80
555
AA
2AA 55
555
Byte
6
AAA
AA
555
55
AAA
80
AAA
AA
555
AAA 10
Word
6
555
AA
2AA
55
555
80
555
AA
2AA 55
SA
30
Byte
6
AAA
AA
555
55
AAA
80
AAA
AA
555
SA
30
Word
1
55
98
Byte
1
AA
98
Erase Suspend (Note 10)
1
BA
B0
Erase Resume (Note 11)
1
BA
30
Automatic Select (Note 7)
Manufacturer ID
Device ID
Chip Erase
Sector Erase
CFI Query (Note 12)
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MX29LV640BT/BB
Legend:
X=Don't care
RA=Address of the memory location to be read.
RD=Data read from location RA during read operation.
PA=Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# or
CE# pulse, whichever happen later.
DDI=Data of device identifier
C2H for manufacture code
C9/CBH (Top/Bottom) for device code
PD=Data to be programmed at location PA. Data is
latched on the rising edge of WE# or CE# pulse.
SA=Address of the sector to be erase or verified (in
autoselect mode).
Address bits A21-A12 uniquely select any sector.
Notes:
1. See Table 1 for descriptions of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or automatic select data, all bus cycles are write operation.
4. Address bits are don't care for unlock and command cycles, except when PA or SA is required.
5. No unlock or command cycles required when device is in read mode.
6. The Reset command is required to return to the read mode when the device is in the automatic select mode or if
Q5 goes high.
7. The fourth cycle of the automatic select command sequence is a read cycle.
8. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. In the third
cycle of the command sequence, address bit A21=0 to verify sectors 0~63, A21=1 to verify sectors 64~134 for
Top Boot device.
9. The data is 88h for factory locked and 08h for not factory locked.
10.The system may read and program functions in non-erasing sectors, or enter the automatic select mode, when in
the erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.
11.The Erase Resume command is valid only during the Erase Suspend mode.
12.Command is valid when device is ready to read array data or when device is in automatic select mode.
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array data (also applies during Erase Suspend).
READING ARRAY DATA
The device is automatically set to reading array data
after device power-up. No commands are required to retrieve data. The device is also ready to read array data
after completing an Automatic Program or Automatic
Erase algorithm.
SILICON ID READ COMMAND SEQUENCE
The SILICON ID READ command sequence allows the
host system to access the manufacturer and devices
codes, and determine whether or not a sector is protected. Table 3 shows the address and data requirements.
This method is an alternative to that shown in Table 1,
which is intended for PROM programmers and requires
VID on address bit A9.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See Erase Suspend/Erase
Resume Commands for more information on this mode.
The system must issue the reset command to re-enable the device for reading array data if Q5 goes high, or
while in the automatic select mode. See the "Reset Command" section, next.
The SILICON ID READ command sequence is initiated
by writing two unlock cycles, followed by the SILICON
ID READ command. The device then enters the SILICON ID READ mode, and the system may read at any
address any number of times, without initiating another
command sequence. A read cycle at address XX00h
retrieves the manufacturer code. A read cycle at address
XX01h returns the device code. A read cycle containing
a sector address (SA) and the address 02h returns 01h if
that sector is protected, or 00h if it is unprotected. Refer
to Table for valid sector addresses.
RESET COMMAND
Writing the reset command to the device resets the device to reading array data. Address bits are don't care for
this command.
The system must write the reset command to exit the
automatic select mode and return to reading array data.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores
reset commands until the operation is complete.
BYTE/WORD PROGRAM COMMAND SEQUENCE
The reset command may be written between the sequence cycles in a program command sequence before
programming begins. This resets the device to reading
array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the
device ignores reset commands until the operation is
complete.
The command sequence requires four bus cycles, and
is initiated by writing two unlock write cycles, followed
by the program set-up command. The program address
and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required
to provide further controls or timings. The device automatically generates the program pulses and verifies the
programmed cell margin. Table 3 shows the address and
data requirements for the byte program command sequence.
The reset command may be written between the sequence cycles in an SILICON ID READ command sequence. Once in the SILICON ID READ mode, the reset
command must be written to return to reading array data
(also applies to SILICON ID READ during Erase Suspend).
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses
are no longer latched. The system can determine the
status of the program operation by using Q7, Q6, or RY/
BY#. See "Write Operation Status" for information on
these status bits.
If Q5 goes high during a program or erase operation,
writing the reset command returns the device to reading
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hard-
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ware reset immediately terminates the programming
operation. The Byte/Word Program command sequence
should be reinitiated once the device has reset to reading array data, to ensure data integrity.
tion Status" for information on these status bits. When
the Automatic Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
"0" back to a "1". Attempting to do so may halt the operation and set Q5 to "1" ,” or cause the Data# Polling
algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still
"0". Only erase operations can convert a "0" to a "1".
Figure 5 illustrates the algorithm for the erase operation.
See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to Figure 4 for timing
diagrams.
SECTOR ERASE COMMANDS
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H, or
the sector erase command 30H.
The Automatic Sector Erase does not require the device
to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic
Sector Erase command. Upon executing the Automatic
Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data
pattern. The system is not required to provide any control or timing during these operations.
The MX29LV640BT/BB contains a Silicon-ID-Read operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the
read silicon ID command sequence into the command
register. Following the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of 22C9H/22CBH for MX29LV640BT/BB.
When the sector(s) is automatically verified to contain an
all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when
the data on Q7 is "1" and the data on Q6 stops toggling
for two consecutive read cycles, at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.
SETUP AUTOMATIC CHIP/SECTOR ERASE
When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector erase
is a six-bus cycle operation. There are two "unlock" write
cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector
address is latched on the falling edge of WE# or CE#,
whichever happens later , while the command (data) is
latched on the rising edge of WE# or CE#, whichever
happens first. Sector addresses selected are loaded
into internal register on the sixth falling edge of WE# or
CE#, whichever happens later. Each successive sector
load cycle started by the falling edge of WE# or CE#,
whichever happens later must begin within 50us from
the rising edge of the preceding WE# or CE#, whichever
happens first. Otherwise, the loading period ends and
internal auto sector erase cycle starts. (Monitor Q3 to
determine if the sector erase timer window is still open,
see section Q3, Sector Erase Timer.) Any command other
AUTOMATIC CHIP/SECTOR ERASE COMMAND
The device does not require the system to preprogram
prior to erase. The Automatic Erase algorithm automatically pre-program and verifies the entire memory for an
all zero data pattern prior to electrical erase. The system
is not required to provide any controls or timings during
these operations. Table 3 shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Automatic
Erase algorithm are ignored. Note that a hardware reset
during the chip erase operation immediately terminates
the operation. The Chip Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
The system can determine the status of the erase operation by using Q7, Q6, Q2, or RY/BY#. See "Write Opera-
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The single cycle Query command is valid only when the
device is in the Read mode, including Erase Suspend,
Standby mode, and Read ID mode; however, it is ignored
otherwise.
than Sector Erase(30H) or Erase Suspend(B0H) during
the time-out period resets the device to read mode.
ERASE SUSPEND
The Reset command exits from the CFI mode to the Read
mode, or Erase Suspend mode, or read ID mode. The
command is valid only when the device is in the CFI
mode.
This command only has meaning while the state machine is executing Automatic Sector Erase operation, and
therefore will only be responded during Automatic Sector
Erase operation. When the Erase Suspend command is
issued during the sector erase operation, the device requires a maximum 20us to suspend the sector erase
operation. However, When the Erase Suspend command
is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends
the erase operation. After this command has been executed, the command register will initiate erase suspend
mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to respond to the
Erase Resume, program data to, or read data from any
sector not selected for erasure.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend program operation is complete, the system can once again
read array data within non-suspended blocks.
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions. Another Erase Suspend command can
be written after the chip has resumed erasing.
QUERY COMMAND AND COMMON FLASH
INTERFACE (CFI) MODE
MX29LV640BT/BB is capable of operating in the CFI
mode. This mode all the host system to determine the
manufacturer of the device such as operating parameters
and configuration. Two commands are required in CFI
mode. Query command of CFI mode is placed first, then
the Reset command exits CFI mode. These are described
in Table 3.
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Table 4-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description
Query-unique ASCII string "QRY"
Primary vendor command set and control interface ID code
Address for primary algorithm extended query table
Alternate vendor command set and control interface ID code (none)
Address for secondary algorithm extended query table (none)
Address h Address h
(x16)
(x8)
10
20
11
22
12
24
13
26
14
28
15
2A
16
2C
17
2E
18
30
19
32
1A
34
Data h
Address h Address h
(x16)
(x8)
1B
36
1C
38
1D
3A
1E
3C
1F
3E
20
40
21
42
22
44
23
46
24
48
25
4A
26
4C
Data h
Address h Address h
(x16)
(x8)
27
4E
28
50
29
52
2A
54
2B
56
Data h
0051
0052
0059
0002
0000
0040
0000
0000
0000
0000
0000
Table 4-2. CFI Mode: System Interface Data Values
Description
VCC supply, minimum (2.7V)
VCC supply, maximum (3.6V)
VPP supply, minimum (none)
VPP supply, maximum (none)
Typical timeout for single word/byte write (2N us)
Typical timeout for maximum size buffer write (2N us)
Typical timeout for individual block erase (2N ms)
Typical timeout for full chip erase (2N ms)
Maximum timeout for single word/byte write times (2N X Typ)
Maximum timeout for maximum size buffer write times (2N X Typ)
Maximum timeout for individual block erase times (2N X Typ)
Maximum timeout for full chip erase times (not supported)
0027
0036
0000
0000
0004
0000
000A
0000
0005
0000
0004
0000
Table 4-3. CFI Mode: Device Geometry Data Values
Description
Device size (2n bytes)
Flash device interface code (02=asynchronous x8/x16)
Maximum number of bytes in multi-byte write (not supported)
P/N:PM1076
0017
0002
0000
0000
0000
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MX29LV640BT/BB
Number of erase block regions
Erase block region 1 information
[2E,2D] = # of blocks in region -1
[30, 2F] = size in multiples of 256-bytes
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
2C
2D
2E
2F
30
31h
32h
33h
34h
35h
36h
37h
38h
58
5A
5C
5E
60
62
64
66
68
6A
6C
6E
70
0002
0007
0000
0020
0000
007Eh
0000h
0000h
0001h
0000h
0000h
0000h
0000h
39h
3Ah
3Bh
3Ch
72
74
76
78
0000h
0000h
0000h
0000h
Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Description
Query-unique ASCII string "PRI"
Major version number, ASCII
Minor version number, ASCII
Address sensitive unlock (0=required, 1= not required)
Erase suspend (2= to read and write)
Sector protect (N= # of sectors/group)
Temporary sector unprotect (1=supported)
Sector protect/unprotect scheme
Simultaneous R/W operation (0=not supported)
Burst mode type (0=not supported)
Page mode type (0=not supported)
ACC (Acceleration) Supply Minimum
00h=Not Supported, D7-D4: Volt, D3-D0:100mV
ACC (Acceleration) Supply Maximum
00h=Not Supported, D7-D4: Volt, D3-D0:100mV
Top/Bottom Boot Sector Flag
02h=Bottom Boot Device, 03h=Top Boot Device
P/N:PM1076
Address h Address h
(x16)
(x8)
40
80
41
82
42
84
43
86
44
88
45
8A
46
8C
47
8E
48
90
49
92
4A
94
4B
96
4C
98
4Dh
9A
Data h
0050
0052
0049
0031
0031
0000
0002
0004
0001
0004
0000
0000
0000
00B5
4Eh
9C
00C5
4Fh
9E
0002h/
0003h
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MX29LV640BT/BB
WRITE OPERATION STATUS
The device provides several bits to determine the status
of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/BY#.
Table 5 and the following subsections describe the functions of these bits. Q7, RY/BY#, and Q6 each offer a
method for determining whether a program or erase operation is complete or in progress. These three bits are
discussed first.
Table 5. Write Operation Status
Status
Byte/Word Program in Auto Program Algorithm
Auto Erase Algorithm
Erase Suspend Read
(Erase Suspended Sector)
Q7
Note1
Q6
Q5
Note2
Q3
Q2
RY/BY#
Q7
Toggle
0
N/A
No
Toggle
0
0
Toggle
0
1
Toggle
0
1
No
Toggle
0
N/A Toggle
1
In Progress
Erase Suspended Mode
Erase Suspend Read
Data
(Non-Erase Suspended Sector)
Erase Suspend Program
Byte/Word Program in Auto Program Algorithm
Exceeded
Time Limits Auto Erase Algorithm
Erase Suspend Program
Data
Data Data Data
1
Q7
Toggle
0
N/A
N/A
0
Q7
Toggle
1
N/A
No
Toggle
0
0
Toggle
1
1
Toggle
0
Q7
Toggle
1
N/A
N/A
0
Notes:
1. Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.
2. Performing successive read operations from any address will cause Q6 to toggle.
3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the
Q2 bit.
However, successive reads from the erase-suspended sector will cause Q2 to toggle.
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28
MX29LV640BT/BB
happens first pulse in the command sequence (prior to
the program or erase operation), and during the sector
time-out.
Q7: Data# Polling
The Data# Polling bit, Q7, indicates to the host system
whether an Automatic Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data#
Polling is valid after the rising edge of the final WE# pulse
in the program or erase command sequence.
During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6
to toggle. The system may use either OE# or CE# to
control the read cycles. When the operation is complete,
Q6 stops toggling.
During the Automatic Program algorithm, the device outputs on Q7 the complement of the datum programmed
to Q7. This Q7 status also applies to programming during Erase Suspend. When the Automatic Program algorithm is complete, the device outputs the datum programmed to Q7. The system must provide the program
address to read valid status information on Q7. If a program address falls within a protected sector, Data# Polling on Q7 is active for approximately 1 us, then the device returns to reading array data.
After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles for
100us and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase suspended.
When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When
the device enters the Erase Suspend mode, Q6 stops
toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-suspended.
Alternatively, the system can use Q7.
During the Automatic Erase algorithm, Data# Polling produces a "0" on Q7. When the Automatic Erase algorithm
is complete, or if the device enters the Erase Suspend
mode, Data# Polling produces a "1" on Q7. This is analogous to the complement/true datum output described for
the Automatic Program algorithm: the erase function
changes all the bits in a sector to "1" prior to this, the
device outputs the "complement,” or "0".” The system
must provide an address within any of the sectors selected for erasure to read valid status information on Q7.
If a program address falls within a protected sector, Q6
toggles for approximately 2us after the program command sequence is written, then returns to reading array
data.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on
Q7 is active for approximately 100 us, then the device
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algorithm is complete.
Table 5 shows the outputs for Toggle Bit I on Q6.
When the system detects Q7 has changed from the
complement to true data, it can read valid data at Q7-Q0
on the following read cycles. This is because Q7 may
change asynchronously with Q0-Q6 while Output Enable
(OE#) is asserted low.
Q2:Toggle Bit II
Q6:Toggle BIT I
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively erasing (that is,
the Automatic Erase algorithm is in process), or whether
that sector is erase-suspended. Toggle Bit II is valid
after the rising edge of the final WE# or CE#, whichever
happens first pulse in the command sequence.
Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE# or CE#, whichever
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE# or CE# to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com-
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MX29LV640BT/BB
If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it
may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence. This
allows the system to continue to use the other active
sectors in the device.
parison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits
are required for sectors and mode information. Refer to
Table 5 to compare outputs for Q2 and Q6.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read cycle.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or combination of sectors are bad.
If this time-out condition occurs during the byte/word programming operation, it specifies that the entire sector
containing that byte is bad and this sector may not be
reused, (other sectors are still functional and can be reused).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase operation. If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never
reads a valid data on Q7 bit and Q6 never stops toggling.
Once the Device has exceeded timing limits, the Q5 bit
will indicate a "1". Please note that this is not a device
failure condition since the device was incorrectly used.
The Q5 failure condition may appear if the system tries
to program a to a "1" location that is previously programmed to "0". Only an erase operation can change a
"0" back to a "1".” Under this condition, the device halts
the operation, and when the operation has exceeded the
timing limits, Q5 produces a "1".
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively,
it may choose to perform other system tasks. In this
case, the system must start at the beginning of the algorithm when it returns to determine the status of the
operation.
Q3:Sector Erase Timer
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data# Polling
and Toggle Bit are valid after the initial sector erase command sequence.
Q5:Program/Erase Timing
Q5 will indicate if the program or erase time has exceeded
the specified limits (internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
indicates that the program or erase cycle was not successfully completed. Data# Polling and Toggle Bit are
the only operating functions of the device under this condition.
If Data# Polling or the Toggle Bit indicates the device
has been written with a valid erase command, Q3 may
be used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data# Polling or
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30
MX29LV640BT/BB
Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command
has been accepted, the system software should check
the status of Q3 prior to and following each subsequent
sector erase command. If Q3 were high on the second
status check, the command may not have been accepted.
If the time between additional erase commands from the
system can be less than 50us, the system need not to
monitor Q3.
RY/BY#:READY/BUSY OUTPUT
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in progress
or complete. The RY/BY# status is valid after the rising
edge of the final WE# pulse in the command sequence.
Since RY/BY# is an open-drain output, several RY/BY#
pins can be tied together in parallel with a pull-up resistor
to VCC .
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device
is ready to read array data (including during the Erase
Suspend mode), or is in the standby mode.
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MX29LV640BT/BB
ABSOLUTE MAXIMUM RATINGS
OPERATING RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
A9, OE#, ACC, and
RESET# (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Commercial (C) Devices
Ambient Temperature (TA ). . . . . . . . . . . . 0° C to +70° C
Industrial (I) Devices
Ambient Temperature (TA ). . . . . . . . . . -40° C to +85° C
VCC Supply Voltages
VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V.
During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20ns.
2. Minimum DC input voltage on pins A9, OE#, and
RESET# is -0.5 V. During voltage transitions, A9, OE#,
and RESET# may overshoot VSS to -2.0 V for periods of up to 20ns. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20ns.
3. No more than one output may be shorted to ground at
a time. Duration of the short circuit should not be
greater than one second.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect
device reliability.
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MX29LV640BT/BB
DC CHARACTERISTICS
TA=-40°° C to 85°° C, VCC=2.7V~3.6V
Parameter Description
Test Conditions
I LI
VIN = VSS to VCC ,
Input Load Current (Note 1)
Min.
Typ.
Max.
Unit
±1.0
uA
35
uA
±1.0
uA
VCC = VCC max
I LIT
A9 Input Leakage Current
VCC=VCC max; A9 = 12.5V
I LO
Output Leakage Current
VOUT = VSS to VCC ,
VCC= VCC max
ICC1 VCC Active Read Current
(Notes 2,3)
ICC2 VCC Active Write Current
CE#= VIL,
5 MHz
9
16
mA
OE# = VIH
1 MHz
2
4
mA
CE#= V IL , OE# = V IH
26
30
mA
CE#,RESET#=VCC±0.3V
0.2
15
uA
0.2
15
uA
0.2
15
uA
(Notes 2,4,6)
ICC3 VCC Standby Current
(Note 2)
ICC4 VCC Reset Current
(Note 2)
ICC5 Automatic Sleep Mode
(Note 2,5)
WP#=VIH
RESET#=VSS±0.3V
WP#=VIH
VIL = V SS ± 0.3 V,
VIH = VCC ± 0.3 V,
WP#=VIH
IACC ACC Accelerated Program
Current
CE#=VIL,
ACC pin
5
10
mA
OE#=VIH
VCC pin
15
30
mA
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
0.7xVcc
Vcc+0.3
V
VHH
Voltage for ACC Program
VCC = 3.0 V ± 10%
11.5
12.5
V
VCC = 3.0 V ± 10%
11.5
12.5
V
0.45
V
Acceleration
VID
Voltage for Autoselect and
Temporary Sector Unprotect
VOL
Output Low Voltage
IOL= 4.0mA,VCC=VCC min
VOH1 Output High Voltage
IOH=-2.0mA,VCC=VCC min 0.85VCC
V
VOH2
IOH=-100uA,VCC=VCC min
VCC-0.4
V
1.5
V
VLKO Low VCC Lock-Out Voltage
(Note 4)
Notes:
1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0uA.
2. Maximum ICC specifications are tested with VCC = VCC max.
3. The ICC current listed is typically is less than 2 mA/MHz, with OE# at VIH. Typical specifications are for VCC =
3.0V.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30 ns. Typical sleep
mode current is 200 nA.
6. Not 100% tested.
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SWITCHING TEST CIRCUITS
TEST SPECIFICATIONS
Test Condition
90
120
Output Load
1 TTL gate
Output Load Capacitance, CL 30
100
(including jig capacitance)
Input Rise and Fall Times
5
Input Pulse Levels
0.0-3.0
Input timing measurement
1.5
reference levels
Output timing measurement
1.5
reference levels
2.7K ohm
DEVICE UNDER
TEST
3.3V
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
Unit
pF
ns
V
V
V
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don't Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State(High Z)
SWITCHING TEST WAVEFORMS
3.0V
1.5V
Measurement Level
1.5V
0.0V
INPUT
OUTPUT
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AC CHARACTERISTICS
Read-Only Operations
TA=-40°° C to 85°° C, VCC=2.7V~3.6V
Parameter
Speed Options
Std.
Description
Test Setup
90
120
Unit
tRC
Read Cycle Time (Note 1)
Min
90
120
ns
tACC
Address to Output Delay
CE#, OE#=VIL
Max
90
120
ns
tCE
Chip Enable to Output Delay
OE#=VIL
Max
90
120
ns
tOE
Output Enable to Output Delay
Max
35
50
ns
tDF
Chip Enable to Output High Z (Note 1)
Max
30
30
ns
tDF
Output Enable to Output High Z (Note 1)
Max
30
30
ns
tOH
Output Hold Time From Address, CE#
Min
0
ns
Read
Min
0
ns
Output Enable Hold Time
Toggle and
Min
10
ns
(Note 1)
Data# Polling
or OE#, whichever Occurs First
tOEH
Notes:
1. Not 100% tested.
2. See SWITCHING TEST CIRCUITS and TEST SPECIFICATIONS TABLE for test specifications.
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MX29LV640BT/BB
Figure 1. COMMAND WRITE OPERATION
VCC
Addresses
3V
VIH
ADD Valid
VIL
tAH
tAS
WE#
VIH
VIL
tWPH
tWP
tCWC
CE#
VIH
VIL
tCS
OE#
tCH
VIH
VIL
tDS
tDH
VIH
Data
DIN
VIL
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READ/RESET OPERATION
Figure 2. READ TIMING WAVEFORMS
tRC
VIH
ADD Valid
Addresses
VIL
tCE
VIH
CE#
tRH
VIL
tRH
VIH
WE#
VIL
OE#
VIH
VIL
Outputs
tDF
tOE
tOEH
VOH
tACC
HIGH Z
tOH
DATA Valid
HIGH Z
VOL
VIH
RESET#
VIL
RY/BY#
0V
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AC CHARACTERISTICS
Parameter
Description
Test Setup All Speed Options Unit
tREADY1
RESET# PIN Low (During Automatic Algorithms)
MAX
20
us
MAX
500
ns
to Read or Write (See Note)
tREADY2
RESET# PIN Low (NOT During Automatic Algorithms)
to Read or Write (See Note)
tRP1
RESET# Pulse Width (During Automatic Algorithms)
MIN
10
us
tRP2
RESET# Pulse Width (NOT During Automatic Algorithms)
MIN
500
ns
tRH
RESET# High Time Before Read (See Note)
MIN
50
ns
tRB
RY/BY# Recovery Time(to CE#, OE# go low)
MIN
0
ns
tRPD
RESET# Low to Standby Mode
MIN
20
us
Note:Not 100% tested
Figure 3. RESET# TIMING WAVEFORM
RY/BY#
CE#, OE#
tRH
RESET#
tRP2
tReady2
Reset Timing NOT during Automatic Algorithms
tReady1
RY/BY#
tRB
CE#, OE#
RESET#
tRP1
Reset Timing during Automatic Algorithms
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ERASE/PROGRAM OPERATION
Figure 4. AUTOMATIC CHIP/SECTOR ERASE TIMING WAVEFORM
Erase Command Sequence(last two cycle)
tWC
2AAh
Address
Read Status Data
tAS
VA
SA
555h for chip erase
VA
tAH
CE#
tCH
OE#
tWHWH2
tWP
WE#
tCS
tWPH
tDS
tDH
55h
Data
In
Progress Complete
30h
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
NOTES:
1.SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
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Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Data Poll
from system
YES
No
DATA = FFh ?
YES
Auto Erase Completed
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Figure 6. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
NO
Last Sector
to Erase ?
YES
Data Poll from System
NO
Data=FFh?
YES
Auto Sector Erase Completed
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MX29LV640BT/BB
Figure 7. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
NO
ERASE SUSPEND
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
Programming End
NO
YES
Write Data 30H
ERASE RESUME
Continue Erase
Another
Erase Suspend ?
NO
YES
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MX29LV640BT/BB
Figure 8. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART
START
Enter Secured Silicon Sector
Wait 1us
First Wait Cycle Data=60h
Second Wait Cycle Data=60h
A6=0, A1=1, A0=0
Wait 300us
No
Data = 01h ?
Yes
Device Failed
Write Reset Command
Secured Sector Protect Complete
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MX29LV640BT/BB
AC CHARACTERISTICS
Erase and Program Operations
TA=-40°° C to 85°° C, VCC=2.7V~3.6V
Parameter
Speed Options
Std.
Description
90
120
Unit
tWC
Write Cycle Time (Note 1)
Min
90
120
ns
tCWC
Command Write Cycle Time (Note 1)
Min
90
120
ns
tAS
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low during toggle bit polling
Min
15
ns
tAH
Address Hold Time
Min
tAHT
Address Hold Time From CE# or OE# high during toggle
Min
45
50
0
ns
ns
bit polling
tDS
Data Setup Time
Min
45
50
ns
tDH
Data Hold Time
Min
0
ns
tOEPH
Output Enable High during toggle bit polling
Min
20
ns
tGHWL
Read Recovery Time Before Write
Min
0
ns
(OE# High to WE# Low)
tGHEL
Read Recovery Time Before Write
Min
0
ns
tCS
CE# Setup Time
Min
0
ns
tCH
CE# Hold Time
Min
0
ns
tWP
Write Pulse Width
Min
tWPH
Write Pulse Width High
Min
30
ns
tWHWH1
Programming Operation
Byte
Typ
9
us
Word
Typ
11
us
35
50
ns
tWHWH2
Sector Erase Operation (Note 2)
Typ
1.6
sec
tVHH
VHH Rise and Fall Time (Note 1)
Min
250
ns
tVCS
VCC Setup Time (Note 1)
Min
50
us
tRB
Write Recovery Time from RY/BY#
Min
0
ns
tBUSY
Program/Erase Valid to RY/BY# Delay
Min
90
ns
Notes:
1. Not 100% tested.
2. See the "Erase And Programming Performance" section for more information.
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MX29LV640BT/BB
Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS
Program Command Sequence(last two cycle)
tWC
XXXh
Address
Read Status Data (last two cycle)
tAS
PA
PA
PA
tAH
CE#
tCH
OE#
tWP
WE#
tWHWH1
tCS
tWPH
tDS
tDH
A0h
Status
PD
DOUT
Data
tBUSY
tRB
RY/BY#
tVCS
VCC
NOTES:
1.PA=Program Address, PD=Program Data, DOUT is the true data the program address
Figure 10. ACCELERATED PROGRAM TIMING DIAGRAM
VHH
ACC
VIL or VIH
VIL or VIH
tVHH
tVHH
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MX29LV640BT/BB
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
Std.
Description
90
120
Unit
tWC
Write Cycle Time (Note 1)
Min
90
120
ns
tAS
Address Setup Time
Min
tAH
Address Hold Time
Min
45
50
ns
tDS
Data Setup Time
Min
45
50
ns
tDH
Data Hold Time
Min
0
ns
tGHEL
Read Recovery Time Before Write
Min
0
ns
0
ns
(OE# High to WE# Low)
tWS
WE# Setup Time
Min
0
ns
tWH
WE# Hold Time
Min
0
ns
tCP
CE# Pulse Width
Min
tCPH
CE# Pulse Width High
Min
30
ns
tWHWH1
Programming Operation
Byte
Typ
9
us
Word
Typ
11
us
Typ
1.6
sec
tWHWH2
Sector Erase Operation (Note 2)
45
50
ns
Notes:
1. Not 100% tested.
2. See the "Erase And Programming Performance" section for more information.
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MX29LV640BT/BB
Figure 11. CE# CONTROLLED PROGRAM TIMING WAVEFORM
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Address
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tCP
tWHWH1 or 2
CE#
tWS
tCPH
tDS
tBUSY
tDH
Q7
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
NOTES:
1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.
2.Figure indicates the last two bus cycles of the command sequence.
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MX29LV640BT/BB
Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Data Poll
from system
Increment
Address
No
Verify Word Ok ?
YES
No
Last Address ?
YES
Auto Program Completed
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MX29LV640BT/BB
SECTOR GROUP PROTECT/CHIP UNPROTECT
Figure 13. Sector Group Protect / Chip Unprotect Waveform (RESET# Control)
VID
VIH
RESET#
SA, A6
A1, A0
Valid*
Valid*
Sector Group Protect or Chip Unprotect
Data
60h
1us
60h
Valid*
Verify
40h
Status
Sector Group Protect:150us
Chip Unprotect:15ms
CE#
WE#
OE#
Note: For sector group protect A6=0, A1=1, A0=0. For chip unprotect A6=1, A1=1, A0=0
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MX29LV640BT/BB
Figure 14. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECT ALGORITHMS WITH
RESET#=VID
START
START
Protect all sectors:
The indicated portion of
the sector protect algorithm
must be performed
for all unprotected sectors
prior to issuing the first
sector unprotect address
PLSCNT=1
RESET#=VID
Wait 1us
PLSCNT=1
RESET#=VID
Wait 1us
Temporary Sector
Unprotect Mode
No
First Write
Cycle=60h?
First Write
Cycle=60h?
No
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector address
No
Sector Protect:
Write 60h to sector
address with
A6=0, A1=1, A0=0
All sectors
protected?
Yes
Set up first sector address
Wait 150us
Verify Sector Protect:
Write 40h to sector
address with
A6=0, A1=1, A0=0
Sector Unprotect:
Write 60h to sector
address with
A6=1, A1=1, A0=0
Reset
PLSCNT=1
Increment PLSCNT
Wait 15 ms
Read from
sector address
with
A6=0, A1=1, A0=0
Verify Sector Unprotect:
Write 40h to sector
address with
A6=1, A1=1, A0=0
No
Increment PLSCNT
No
PLSCNT=25?
Yes
Data=01h?
Read from
sector address
with
A6=1, A1=1, A0=0
Yes
No
Device failed
Protect another
No
sector?
Sector Protect
Algorithm
Reset
PLSCNT=1
Yes
PLSCNT=1000?
Data=00h?
No
Yes
Remove VID from RESET#
Yes
Device failed
Last sector
verified?
Write reset command
Chip Unprotect
Algorithm
Sector Protect complete
No
Yes
Remove VID from RESET#
Write reset command
Sector Unprotect complete
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MX29LV640BT/BB
AC CHARACTERISTICS
Parameter
Description
Test Setup
All Speed Options
Unit
tVLHT
Voltage transition time
Min.
4
us
tWPP1
Write pulse width for sector group protect
Min.
100
ns
tWPP2
Write pulse width for chip unprotect
Min.
100
ns
tOESP
OE# setup time to WE# active
Min.
4
us
Figure 15. SECTOR GROUP PROTECT TIMING WAVEFORM (A9, OE# Control)
A1
A6
12V
3V
A9
tVLHT
Verify
12V
3V
OE#
tVLHT
tVLHT
tWPP 1
WE#
tOESP
CE#
Data
01H
F0H
tOE
A21-A16
Sector Address
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Figure 16. SECTOR GROUP PROTECTION ALGORITHM (A9, OE# Control)
START
Set Up Sector Addr
PLSCNT=1
OE#=VID, A9=VID, CE#=VIL
A6=VIL
Activate WE# Pulse
Time Out 150us
Set WE#=VIH, CE#=OE#=VIL
A9 should remain VID
Read from Sector
Addr=SA, A1=1
No
PLSCNT=32?
.
No
Data=01H?
Yes
Device Failed
Protect Another
Sector?
Yes
Remove VID from A9
Write Reset Command
Sector Protection
Complete
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MX29LV640BT/BB
Figure 17. CHIP UNPROTECT TIMING WAVEFORM (A9, OE# Control)
A1
12V
3V
A9
tVLHT
A6
Verify
12V
3V
OE#
tVLHT
tVLHT
tWPP 2
WE#
tOESP
CE#
Data
00H
F0H
tOE
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MX29LV640BT/BB
Figure 18. CHIP UNPROTECT FLOWCHART (A9, OE# Control)
START
Protect All Sectors
PLSCNT=1
Set OE#=A9=VID
CE#=VIL, A6=1
Activate WE# Pulse
Time Out 15ms
Increment
PLSCNT
Set OE#=CE#=VIL
A9=VID, A1=1
Set Up First Sector Addr
Read Data from Device
No
Data=00H?
Increment
Sector Addr
Yes
No
All sectors have
No
PLSCNT=1000?
Yes
Device Failed
been verified?
Yes
Remove VID from A9
Write Reset Command
Chip Unprotect
Complete
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
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MX29LV640BT/BB
AC CHARACTERISTICS
Parameter
Description
Test
All Speed Options Unit
Setup
tVIDR
VID Rise and Fall Time (see Note)
Min
500
ns
tRSP
RESET# Setup Time for Temporary Sector Unprotect
Min
4
us
tRRB
RESET# Hold Time from RY/BY# High for Temporary
Min
4
us
Sector Group Unprotect
Figure 19. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORMS
12V
RESET#
0 or 3V
VIL or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
tRRB
RY/BY#
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MX29LV640BT/BB
Figure 20. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART
Start
RESET# = VID (Note 1)
Perform Erase or Program Operation
Operation Completed
RESET# = VIH
Temporary Sector Unprotect Completed(Note 2)
Note : 1. All protected sectors are temporary unprotected.
VID=11.5V~12.5V
2. All previously protected sectors are protected again.
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MX29LV640BT/BB
Figure 21. SILICON ID READ TIMING WAVEFORM
VCC
3V
VID
ADD
VIH
VIL
A9
ADD
VIH
A0
VIL
A1
VIH
tACC
tACC
VIL
VIH
ADD
VIL
CE#
VIH
VIL
WE#
VIH
tCE
VIL
OE#
VIH
tOE
VIL
tDF
tOH
tOH
VIH
DATA
Q0-Q15
DATA OUT
DATA OUT
VIL
22C9H for Top
00C2H
22CBH for Bottom
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MX29LV640BT/BB
WRITE OPERATION STATUS
Figure 22. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
tRC
Address
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
Q7
Status Data
Q0-Q6
Status Data
Complement
Status Data
True
True
Valid Data
Valid Data
High Z
High Z
tBUSY
RY/BY#
NOTES:
VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data raed cycle.
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MX29LV640BT/BB
Figure 23. DATA# POLLING ALGORITHM
Start
Read Q7~Q0
Add.=VA(1)
Yes
Q7 = Data ?
No
No
Q5 = 1 ?
Yes
Read Q7~Q0
Add.=VA
Yes
Q7 = Data ?
(2)
No
FAIL
Pass
Notes:
1.VA=valid address for programming.
2.Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.
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MX29LV640BT/BB
Figure 24. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
tRC
Address
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tDH
Q6/Q2
Valid Status
tOH
Valid Status
(first read)
Valid Status
Valid Data
(second read)
(stops toggling)
Valid Data
RY/BY#
NOTES:
VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.
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MX29LV640BT/BB
Figure 25. TOGGLE BIT ALGORITHM
START
Read Q7~Q0
Read Q7~Q0
(Note 1)
NO
Toggle Bit Q6
=Toggle?
YES
NO
Q5=1?
YES
Read Q7~Q0 Twice
(Note 1,2)
Toggle Bit Q6=
Toggle?
YES
Program/Erase Operation Not
Complete, Write Reset Command
Program/Erase Operation Complete
Note:
1. Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".
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Figure 26. Q6 versus Q2
Enter Embedded
Erasing
Erase
Suspend
Erase
WE#
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Resume
Erase
Suspend
Program
Erase Suspend
Read
Erase
Erase
Complete
Q6
Q2
NOTES:
The system can use OE or CE to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended
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MX29LV640BT/BB
ERASE AND PROGRAMMING PERFORMANCE (1)
LIMITS
PARAMETER
MIN.
TYP.(2)
MAX.
UNITS
Sector Erase Time
0.9
15
sec
Chip Erase Time
45
65
sec
Byte Programming Time
9
300
us
Word Programming Time
11
360
us
Accelerated Word/Byte Program Time
7
210
us
Chip Programming Time
Byte Mode
50
160
sec
Word Mode
45
140
sec
Erase/Program Cycles
Note:
100,000
Cycles
1. Not 100% Tested, Excludes external system level over head.
2. Typical program and erase times assume the following condition= 25° C,3.0V VCC.
Additionally, programming typicals assume checkerboard pattern.
LATCH-UP CHARACTERISTICS
MIN.
MAX.
Input Voltage with respect to GND on all pins except I/O pins
-1.0V
13.5V
Input Voltage with respect to GND on all I/O pins
-1.0V
Vcc + 1.0V
-100mA
+100mA
Current
Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time.
TSOP PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Set
TYP
MAX
UNIT
CIN
Input Capacitance
VIN=0
6
7.5
pF
COUT
Output Capacitance
VOUT=0
8.5
12
pF
CIN2
Control Pin Capacitance
VIN=0
7.5
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA=25° C, f=1.0MHz
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MX29LV640BT/BB
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO.
MX29LV640BTTC-90
ACCESS TIME
Ball Pitch/
(ns)
Ball size
90
PACKAGE
48 Pin TSOP
Remark
Commercial grade
(Normal Type)
MX29LV640BTTC-12
120
48 Pin TSOP
Commercial grade
(Normal Type)
MX29LV640BBTC-90
90
48 Pin TSOP
Commercial grade
(Normal Type)
MX29LV640BBTC-12
120
48 Pin TSOP
Commercial grade
(Normal Type)
MX29LV640BTTI-90
90
48 Pin TSOP
Industrial grade
(Normal Type)
MX29LV640BTTI-12
120
48 Pin TSOP
Industrial grade
(Normal Type)
MX29LV640BBTI-90
90
48 Pin TSOP
Industrial grade
(Normal Type)
MX29LV640BBTI-12
120
48 Pin TSOP
Industrial grade
(Normal Type)
MX29LV640BTTC-90G
MX29LV640BTTC-12G
MX29LV640BBTC-90G
MX29LV640BBTC-12G
MX29LV640BTTI-90G
MX29LV640BTTI-12G
MX29LV640BBTI-90G
MX29LV640BBTI-12G
90
120
90
120
90
120
90
120
P/N:PM1076
48 Pin TSOP
Commercial grade
(Normal Type)
PB-free
48 Pin TSOP
Commercial grade
(Normal Type)
PB-free
48 Pin TSOP
Commercial grade
(Normal Type)
PB-free
48 Pin TSOP
Commercial grade
(Normal Type)
PB-free
48 Pin TSOP
Industrial grade
(Normal Type)
PB-free
48 Pin TSOP
Industrial grade
(Normal Type)
PB-free
48 Pin TSOP
Industrial grade
(Normal Type)
PB-free
48 Pin TSOP
Industrial grade
(Normal Type)
PB-free
REV. 1.2, SEP. 07, 2005
64
MX29LV640BT/BB
PART NO.
ACCESS TIME
Ball Pitch/
PACKAGE
Remark
(ns)
Ball size
MX29LV640BTXBC-90
90
0.8mm/0.3mm
63 Ball CSP
Commercial grade
MX29LV640BTXBC-12
120
0.8mm/0.3mm
63 Ball CSP
Commercial grade
MX29LV640BBXBC-90
90
0.8mm/0.3mm
63 Ball CSP
Commercial grade
MX29LV640BBXBC-12
120
0.8mm/0.3mm
63 Ball CSP
Commercial grade
MX29LV640BTXBI-90
90
0.8mm/0.3mm
63 Ball CSP
Industrial grade
MX29LV640BTXBI-12
120
0.8mm/0.3mm
63 Ball CSP
Industrial grade
MX29LV640BBXBI-90
90
0.8mm/0.3mm
63 Ball CSP
Industrial grade
MX29LV640BBXBI-12
120
0.8mm/0.3mm
63 Ball CSP
Industrial grade
MX29LV640BTXBC-90G
90
0.8mm/0.3mm
63 Ball CSP
Commercial grade
Pb-free
MX29LV640BTXBC-12G
120
0.8mm/0.3mm
63 Ball CSP
Commercial grade
Pb-free
MX29LV640BBXBC-90G
90
0.8mm/0.3mm
63 Ball CSP
Commercial grade
Pb-free
MX29LV640BBXBC-12G
120
0.8mm/0.3mm
63 Ball CSP
Commercial grade
Pb-free
MX29LV640BTXBI-90G
90
0.8mm/0.3mm
63 Ball CSP
Industrial grade
Pb-free
MX29LV640BTXBI-12G
120
0.8mm/0.3mm
63 Ball CSP
Industrial grade
Pb-free
MX29LV640BBXBI-90G
90
0.8mm/0.3mm
63 Ball CSP
Industrial grade
Pb-free
MX29LV640BBXBI-12G
120
0.8mm/0.3mm
63 Ball CSP
Industrial grade
Pb-free
P/N:PM1076
REV. 1.2, SEP. 07, 2005
65
MX29LV640BT/BB
PACKAGE INFORMATION
P/N:PM1076
REV. 1.2, SEP. 07, 2005
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P/N:PM1076
REV. 1.2, SEP. 07, 2005
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REVISION HISTORY
Revision No.
1.0
1.1
1.2
Description
1. Removed "Preliminary"
1. Added "BYTE#" in Pin Description & Logic Symbol
1. Modified "RESET# TIMING WAVEFORM"
P/N:PM1076
Page
P1
P4
P38
Date
MAR/08/2005
MAR/22/2005
SEP/07/2005
REV. 1.2, SEP. 07, 2005
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MX29LV640BT/BB
MACRONIX INTERNATIONAL CO., LTD.
Headquarters:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
Europe Office :
TEL:+32-2-456-8020
FAX:+32-2-456-8021
Hong Kong Office :
TEL:+86-755-834-335-79
FAX:+86-755-834-380-78
Japan Office :
Kawasaki Office :
TEL:+81-44-246-9100
FAX:+81-44-246-9105
Osaka Office :
TEL:+81-6-4807-5460
FAX:+81-6-4807-5461
Singapore Office :
TEL:+65-6346-5505
FAX:+65-6348-8096
Taipei Office :
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-262-8887
FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.