AD ADUM5230 Isolated half-bridge driver with integrated high-side supply Datasheet

Isolated Half-Bridge Driver
with Integrated High-Side Supply
ADuM5230
FEATURES
GENERAL DESCRIPTION
Integrated, isolated high-side supply
150 mW of secondary side power
Isolated high-side and low-side outputs
100 mA output source current, 300 mA output sink current
High common-mode transient immunity: >25 kV/μs
High temperature operation: 105°C
Adjustable power level
Wide body 16-lead SOIC package
Safety and regulatory approvals (pending)
UL recognition: 2500 V rms for 1 minute per UL1577
The ADuM5230 1 is an isolated half-bridge gate driver that
employs Analog Devices, Inc., iCoupler® technology to provide
independent and isolated high-side and low-side outputs.
Combining CMOS and microtransformer technologies, this
isolation component contains an integrated dc-to-dc converter
providing an isolated high-side supply. This eliminates the cost,
space, and performance difficulties associated with external
supply configurations such as a bootstrap circuitry. This highside isolated supply powers not only the ADuM5230 high-side
output but also any external buffer circuitry used with the
ADuM5230.
APPLICATIONS
In comparison to gate drivers employing high voltage level
translation methodologies, the ADuM5230 offers the benefit
of true, galvanic isolation between the input and each output.
Each output can operate up to ±700 VP relative to the input,
thereby supporting low-side switching to negative voltages.
The differential voltage between the high-side and low-side
may be as high as 700 VP.
MOSFET/IGBT gate drive
Plasma display modules
Motor drives
Power supplies
Solar panel inverters
1
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; 7,075,329; other
pending patents.
GND1 1
16
VOA
15
VISO
VADJ 3
14
GNDISO
GND1 4
13
NC
ISOLATED
DC/DC
CONVERTER
VDD1 2
VIA 5
╓
╜
ENCODE
DECODE
╓
╜
12
NC
VIB 6
╓
╜
ENCODE
DECODE
╓
╜
11
GNDB
10
VDDB
9
VOB
VDD1 7
ADuM5230
GND1 8
NC = NO CONNECT
07080-001
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADuM5230
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Perfomance Characteristics ................................................8
Applications ....................................................................................... 1
Applications Information .............................................................. 10
General Description ......................................................................... 1
Theory of Operation .................................................................. 10
Functional Block Diagram .............................................................. 1
PC Board Layout ........................................................................ 10
Revision History ............................................................................... 2
Thermal Analysis ....................................................................... 10
Specifications..................................................................................... 3
Propagation Delay-Related Parameters ................................... 11
Electrical Characteristics ............................................................. 3
DC Correctness and Magnetic Field Immunity........................... 11
Package Characteristics ............................................................... 5
Power Consumption .................................................................. 12
Regulatory Information ............................................................... 5
Increasing and Decreasing Available Power............................... 12
Insulation and Safety-Related Specifications ............................ 5
Common-Mode Transient Immunity ..................................... 12
Recommended Operating Conditions ...................................... 5
Typical Application Usage ......................................................... 13
Absolute Maximum Ratings............................................................ 6
Insulation Lifetime ..................................................................... 13
ESD Caution .................................................................................. 6
Outline Dimensions ....................................................................... 15
Pin Configuration and Pin Function Descriptions ...................... 7
Ordering Guide .......................................................................... 15
REVISION HISTORY
4/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADuM5230
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 12.0 ≤ VDDB ≤ 18.0 V. All min/max specifications apply over the
entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 5.0 V, VDDB = 15 V.
Table 1.
Parameter
DC SPECIFICATIONS
Input Supply Current, Quiescent
Channel B Supply Current, Quiescent
Channel A Output Supply Voltage
At 100 kHz Switching Frequency
Maximum Channel A Output Supply Current
Input Supply Current
Channel B Supply Current
At 1000 kHz Switching Frequency
Maximum Channel A Output Supply Current
Input Supply Current
Channel B Supply Current
Input Currents
Logic High Input Voltage
Logic Low Input Voltage
Logic High Output Voltages
Logic Low Output Voltages
Undervoltage Lockout, VISO and VDDB Supply
Positive-Going Threshold
Negative-Going Threshold
Hysteresis
Undervoltage Lockout, VDD1 Supply
Positive-Going Threshold
Negative-Going Threshold
Hysteresis
Output Short-Circuit Pulsed Current, Sourcing 1
Output Short-Circuit Pulsed Current, Sinking1
SWITCHING SPECIFICATIONS
Minimum Pulse Width 2
Maximum Switching Frequency 3
Propagation Delay 4
Change vs. Temperature
Pulse Width Distortion, |tPLH − tPHL|
Channel-to-Channel Matching, Rising or Falling
Matching Edge Polarity 5
Channel-to-Channel Matching, Rising vs. Falling
Opposite Edge Polarity 6
Part-to-Part Matching, Rising or Falling Edges 7
Part-to-Part Matching, Rising vs. Falling Edges 8
Symbol
Min
Typ
IDD1(Q)
IDDB(Q)
VISO
12
IISO(max, 100)
IDD1
IDDB
10
IISO(max, 1000)
IDD1
IDDB
IIA, IIB
VATH, VBTH
VATL, VBTL
VOAH, VOBH
7.5
−10
0.7 × VDD1
15
+0.01
VISO – 0.1,
VDDB – 0.1
VOAL, VOBL
VDDBUV+
VDDBUV−
VDDBUVH
8.0
7.4
VDD1UV+
VDD1UV−
VDD1UVH
IOA, IOB
IOA, IOB
3.5
3.0
Max
Unit
Test Conditions
125
mA
IISO = 0 mA, dc signal inputs,
VADJ = open
1.6
18.5
mA
V
200
1.8
mA
mA
mA
CL = 200 pF
IISO = IISO(max, 100)
CL = 200 pF
CL = 200 pF
IISO = IISO(max, 1000)
CL = 200 pF
0 ≤ VIA, VIB ≤ 5.5 V
0.3 × VDD1
VISO, VDDB
mA
mA
mA
μA
V
V
V
IOA, IOB = −1 mA
0.1
V
IOA, IOB = 1 mA
10.1
9.0
V
V
V
4.2
3.9
V
V
V
mA
mA
100
CL = 200 pF
CL = 200 pF
200
7.5
+10
0.9
0.4
100
300
PW
PWD
tM2
8
8
ns
MHz
ns
ps/°C
ns
ns
tM1
10
ns
CL = 200 pF
55
63
ns
ns
CL = 200 pF
CL = 200 pF
1
tPHL, tPLH
100
100
Rev. 0 | Page 3 of 16
CL = 200 pF
CL = 200 pF
CL = 200 pF
ADuM5230
Parameter
Common-Mode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Symbol
|CMH|
Min
25
Typ
35
|CML|
25
35
Max
Unit
kV/μs
kV/μs
tR
25
ns
tF
10
ns
1
Test Conditions
VIx = VDD1, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
CL = 200 pF, IISO = 10 mA,
100 kHz switching frequency
CL = 200 pF, IISO = 10 mA,
100 kHz switching frequency
Short-circuit duration is less than 1 sec. Average output current must conform to the limit shown under the Absolute Maximum Ratings section.
The minimum pulse width is the shortest pulse width at which the specified timing parameters are guaranteed. Operation below the minimum pulse width is strongly
discouraged because in some instances pulse stretching to 1 μs may occur.
3
The maximum switching frequency is the maximum signal frequency at which the specified timing and power conversion parameters are guaranteed. Operation
above the maximum frequency is strongly discouraged.
4
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
In channel-to-channel matching, the rising or falling matching edge polarity is the magnitude of the propagation delay difference between two channels of the same
part when both inputs are either both rising or falling edges. The loads on each channel are equal.
6
In channel-to-channel matching, the rising vs. falling opposite edge polarity is the magnitude of the propagation delay difference between two channels of the same
part when one input is a rising edge and one input is a falling edge. The loads on each channel are equal.
7
In part-to-part matching, the rising or falling edges is the magnitude of the propagation delay difference between the same channels of two different parts when the
inputs are either both rising or falling edges. The supply voltages, temperatures, and loads of each part are equal.
8
In part-to-part matching, the rising vs. falling edges is the magnitude of the propagation delay difference between the same channels of two different parts when one
input is a rising edge and the other input is a falling edge. The supply voltages, temperatures, and loads of each part are equal.
2
Rev. 0 | Page 4 of 16
ADuM5230
PACKAGE CHARACTERISTICS
Table 2.
Parameter
Resistance (Input-to-Output) 1
Capacitance (Input-to-Output)1
Input Capacitance
IC Junction-to-Ambient Thermal Resistance
1
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1012
2.0
4.0
48
Max
Unit
Ω
pF
pF
°C/W
Test Conditions
f = 1 MHz
The device is considered a two-terminal device: Pin 1 to Pin 8 are shorted together, and Pin 9 to Pin 16 are shorted together.
REGULATORY INFORMATION
The ADuM5230 will be approved by the organization listed in Table 3.
Table 3.
UL 1 (pending)
Recognized under 1577 component recognition program, File E214100
1
In accordance with UL1577, each ADuM5230 is proof-tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
Minimum External Tracking (Creepage)
Unit
V rms
mm
L(I02)
3.5 min
mm
0.017 min
mm
Conditions
1 minute duration
Measured from input conductors to output conductors,
shortest distance through air
Measured from input conductors to output conductors,
shortest distance path along body
Distance through the insulation
>175
V
DIN IEC 112/VDE 0303 Part 1
CTI
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
600
RECOMMENDED OPERATING CONDITIONS
500
Table 5.
Parameter
Operating Temperature (TA)
Input Supply Voltage 1 (VDD1)
Channel B Supply Voltage1 (VDDB)
Input Signal Rise and Fall Times
Minimum VDD1 Power-On Slew Rate 2 (PSLEW)
400
300
200
1
100
0
–40
2
0
40
80
120
AMBIENT TEMPERATURE (°C)
160
200
Value
−40°C to +105°C
4.5 V to 5.5 V
12 V to 18.5 V
1 ms
400 V/ms
All voltages are relative to their respective ground.
The ADuM5230 power supply may fail to initialize properly if VDD1 is applied
too slowly.
07080-010
SAFE OPERATING VDD1 CURRENT (mA)
Minimum Internal Gap (Internal
Clearance)
Tracking Resistance (Comparative
Tracking Index)
Isolation Group
L(I01)
Value
2500
3.5 min
Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on
Case Temperature, per DIN EN 60747-5-2
Rev. 0 | Page 5 of 16
ADuM5230
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 6.
Parameter
Storage Temperature (TST)
Ambient Operating Temperature (TA)
Input Supply Voltage 1 (VDD1)
Channel B Supply Voltage1 (VDDB)
Input Voltage1 (VIA, VIB)
Output Voltage1 (VOA, VOB)
Input-Output Voltage 2
Output Differential Voltage 3
Output DC Current (IOA, IOB)
Common-Mode Transients 4
Rating
−55°C to +150°C
−40°C to +105°C
−0.5 V to +7.0 V
−0.5 V to +27 V
−0.5 V to VDDI + 0.5 V
−0.5 V to VISO + 0.5 V,
−0.5 V to VDDB + 0.5 V
−700 VPEAK to +700 VPEAK
700 VPEAK
−20 mA to +20 mA
−100 kV/μs to +100 kV/μs
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1
All voltages are relative to their respective ground.
Input-to-output voltage is defined as GNDISO − GND1 or GNDB − GND1.
Output differential voltage is defined as GNDISO − GNDB.
4
Refers to common-mode transients across any insulation barrier. Commonmode transients exceeding the Absolute Maximum Ratings may cause
latch-up or permanent damage.
2
3
Table 7. Maximum Continuous Working Voltage1
Parameter
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Basic Insulation
DC Voltage
Basic Insulation
1
Max
424
Unit
V peak
Constraint
50-year minimum lifetime
600
V peak
50-year minimum lifetime
600
V peak
50-year minimum lifetime
Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Rev. 0 | Page 6 of 16
ADuM5230
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
GND1 1
16 VOA
VDD1 2
15 VISO
VADJ 3
14 GNDISO
ADuM5230
GND1 4
TOP VIEW
(Not to Scale)
VIA 5
13 NC
12 NC
VIB 6
11 GNDB
10 VDDB
GND1 8
9
VOB
NC = NO CONNECT
07080-002
VDD1 7
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
GND1
VDD1
VADJ
GND1
VIA
VIB
VDD1
GND1
VOB
VDDB
GNDB
NC
NC
GNDISO
VISO
VOA
Description
Ground Reference for Input Logic Signals.
Input Supply Voltage, 4.5 V to 5.5 V.
Adjusts Internal DC-to-DC Converter Duty Cycle (Normally Left Unconnected).
Ground Reference for Input Logic Signals.
Logic Input A.
Logic Input B.
Input Supply Voltage, 4.5 V to 5.5 V.
Ground Reference for Input Logic Signals.
Output B Signal.
Output B Supply Voltage, 12 V to 18 V.
Ground Reference for Output B Signal.
No Connect.
No Connect.
Ground Reference for Output A Signal and Isolated Output Supply Voltage.
Isolated Output Supply Voltage.
Output A Signal.
Table 9. Truth Table (Positive Logic)
VIA
Input
High
High
Low
Low
X
VIB
Input
High
Low
High
Low
X
VDD1
State 1
Powered
Powered
Powered
Powered
UVLO
VISO State1
Powered
Powered
Powered
Powered
Unpowered
VDDB State1
Powered
Powered
Powered
Powered
X
VOA
Output
High
High
Low
Low
Low
VOB
Output
High
Low
High
Low
Low
X
X
Powered
UVLO
Unpowered
Low
Low
X
High
Powered
UVLO
Powered
Low
High
X
Low
Powered
UVLO
Powered
Low
Low
High
X
Powered
Powered
UVLO
High
Low
Low
X
Powered
Powered
UVLO
Low
Low
1
UVLO represents either a voltage below the UVLO threshold for that supply or absence of power.
Rev. 0 | Page 7 of 16
Notes
Output returns to input state within 1 μs of VDD1
power restoration.
Output returns to input state within 1 μs of VISO
and VDDB power restoration.
Output returns to input state within 1 μs of VISO
power restoration.
Output returns to input state within 1 μs of VISO
power restoration.
VOB output returns to input state within 1 μs of
VDDB power restoration.
VOB output returns to input state within 1 μs of
VDDB power restoration.
ADuM5230
TYPICAL PERFOMANCE CHARACTERISTICS
20
14.0
4.5V
5.0V
5.5V
19
VISO @ MAXIMUM LOAD (V)
18
17
16
VISO (V)
VISO @ 100kHz
VISO @ 1MHz
13.5
15
14
13
12
13.0
12.5
12.0
11.5
0
5
10
15
IISO LOAD CURRENT (mA)
20
11.0
–40
07080-011
10
Figure 4. Typical VISO Supply Voltage vs. IISO External Load Current
0
40
TEMPERATURE (°C)
80
120
07080-014
11
Figure 7. Typical VISO Output Voltage at Maximum Combined Load Over
Temperature
200
6
180
5
140
4
VDDB (mA)
120
100
80
20
0
5
10
15
IISO LOAD CURRENT (mA)
20
Figure 5. Typical VDD1 Supply Current vs. VISO External Load Current
0
200
400
600
FREQUENCY (kHz)
800
1000
0
20
15
10
4.5V
5.0V
5.5V
0
5
10
15
IISO LOAD CURRENT (mA)
20
–1.0
–1.5
–2.0
–2.5
–3.0
07080-013
5
–0.5
0
50
100
IOH (mA)
150
200
07080-016
(VOH – VDD) OUTPUT VOLTAGE DROP (V)
25
EFFICIENCY (%)
0
Figure 8. Typical Current Consumption for VOA or VOB Outputs, CL = 200 pF
30
0
18V
15V
12V
1
07080-015
4.5V
5.0V
5.5V
40
0
3
2
60
07080-012
IDD1 CURRENT (mA)
160
Figure 9. Typical VOH Drop vs. IOH (VDD1 = 5 V, VDDB, VISO = 12 V to 18 V)
Figure 6. Typical VISO Supply Efficiency vs. VISO External Load Current
Rev. 0 | Page 8 of 16
ADuM5230
2.0
40
VISO = 15V
VISO = 12V
1.5
OUTPUT CURRENT (mA)
VOL OUTPUT VOLTAGE (V)
35
1.0
0.5
30
25
20
15
10
0
100
200
IOL (mA)
300
400
0
07080-017
0
0
20
40
60
PWM DUTY FACTOR (%)
80
100
07080-020
5
Figure 13. Current Available at the Output vs. PWM Duty Factor for VDD1 = 5 V
Figure 10. Typical VOL vs. IOL (VDD1 = 5 V, VDDB, VISO = 12 V to 18 V)
70
1.0
0.9
ON DUTY FACTOR
0.8
66
64
TPLH @ 18V
TPHL @ 18V
TPLH @ 12V
TPHL @ 12V
60
–40
0
40
TEMPERATURE (°C)
80
120
POWER DISSIPATION (mW)
0.3
VDD1 = 5.0
0/10
1/9
2/8
3/7
4/6
5/5
6/4
UPPER/LOWER VADJ RESISTOR VALUES (kΩ)
7/3
Figure 14. Upper/Lower VADJ Voltage Divider Resistor Values to Determine
PWM Duty Factor for VDD1 = 5 V
1200
1000
800
600
VDD1 = 5.5V
VDD1 = 4.5V
1000
07080-019
200
10
100
LOAD IMPEDANCE (Ω)
0.4
0
1400
1
0.5
0.1
1600
0
0.6
0.2
Figure 11. Typical Propagation Delay vs. Temperature
400
0.7
07080-021
62
07080-018
PROPAGATION DELAY (ns)
68
Figure 12. Power Dissipation vs. Load Impedance for Fault Conditions
Rev. 0 | Page 9 of 16
ADuM5230
APPLICATIONS INFORMATION
The dc-to-dc converter section of the ADuM5230 works on
principles that are common to most modern power supply
designs. It is implemented as an open-loop PWM controller,
which sets the power level being transferred to the secondary.
VDD1 power is supplied to an oscillating circuit that switches
current into a chip-scale air core transformer. On the secondary
side, power is rectified to a dc voltage. The voltage is then
clamped to approximately 18 V and provided to the secondary
side VOA data channel and to the VISO pin for external use. The
output voltage is unregulated and varies with load.
The PWM duty cycle is set by internal bias elements, but can be
controlled externally through the VADJ pin with an external
resistor network. This feature allows the user to boost the
available power at the secondary, or reduce excess power if it is
not required for the application (see the Power Consumption
section).
Undervoltage lockouts are provided on the VDD1, VDDB, and VISO
supply lines to interlock the data channels from low supply
voltages.
PC BOARD LAYOUT
The ADuM5230 digital isolator with a 150 mW isoPower™
integrated dc-to-dc converter requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
required at the input and output supply pins (see Figure 15).
The power supply section of the ADuM5230 uses a very high
oscillator frequency to pass power efficiently through its chip
scale transformers. In addition, the normal operation of the
data section of the iCoupler® introduces switching transients on
the power supply pins. Bypass capacitors are required for
several operating frequencies. Noise suppression requires a low
inductance high frequency capacitor; ripple suppression and
proper regulation require a large value capacitor. These are most
conveniently connected between Pin 1 and Pin 2 for VDD1 and
between Pin 15 and Pin 14 for VISO. To suppress noise and
reduce ripple, a parallel combination of at least two capacitors is
required. The recommended capacitor values are 0.1 μF and
10 μF. It is strongly recommended that a very low inductance
ceramic or equivalent capacitor be used for the smaller value.
The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm.
Bypassing with noise suppression and stiffening capacitors is
recommended between Pin 1 and Pin 2, a bypass capacitor is
recommended between Pin 7 and Pin 8. Bypassing with noise
suppression and stiffening capacitors is recommended between
Pin 14 and Pin 15.
GND1
VOA
VDD1
VISO
VADJ
GND1
VIA
ADuM5230
TOP VIEW
(Not to Scale)
GNDISO
NC
NC
GNDB
VIB
VDD1
VDDB
GND1
VOB
NC = NO CONNECT
07080-022
THEORY OF OPERATION
Figure 15. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isolation
barrier is minimized. Furthermore, the board layout should be
designed such that any coupling that does occur equally affects
all pins on a given component side. Failure to ensure this may
cause voltage differentials between pins exceeding the absolute
maximum ratings specified in Table 6, leading to latch-up
and/or permanent damage.
The ADuM5230 is a power device that dissipates about 1 W of
power when fully loaded and run at maximum speed. Because it
is not possible to apply a heat sink to an isolation device, the device
primarily depends on heat dissipation into the PCB through the
GND pins. If the device is used at high ambient temperatures,
care should be taken to provide a thermal path from the GND
pins to the PCB ground plane. The board layout in Figure 15
shows enlarged pads for Pin 1 and Pin 8. Multiple vias should
be implemented from the pad to the ground plane. This significantly reduces the temperatures inside the chip. The dimensions
of the expanded pads are left to the discretion of the designer
and the available board space.
THERMAL ANALYSIS
The ADuM5230 part consists of several internal die attached to
three lead frames, each with a die attach paddle. For the purposes
of thermal analysis, the device is treated as a thermal unit with
the highest junction temperature reflected in the θJA parameter
shown in Table 2. The value of θJA is based on measurements
taken with the part mounted on a JEDEC standard four-layer
board with fine width traces and still air. Under normal operating
conditions, the ADuM5230 operates at full load across the full
temperature range without derating the output current.
However, following the recommendations in the PC Board
Layout section decreases the thermal resistance to the PCB,
allowing increased thermal margin in high ambient
temperatures.
Under output short-circuit conditions, as shown in Figure 12,
the package power dissipation is within safe operating limits;
however, if the load is in the 100 Ω range, power dissipation is
high enough to cause thermal damage when the ambient temperature is above 80°C. Care should be taken to avoid excessive
nonshort loads if the part is to be operated at high temperatures.
Rev. 0 | Page 10 of 16
ADuM5230
100
50%
tPHL
OUTPUT (VOx)
07080-023
tPLH
50%
Figure 16. Propagation Delay Parameters
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than 1 μs, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses of more than about 5 μs, the input
side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see Table 9)
by the watchdog timer circuit.
The limitation on the ADuM5230 magnetic field immunity is set
by the condition in which induced voltage in the transformer
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines the conditions under
which this may occur.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (= dβ / dt )∑ πrn 2 ; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
0.001
1k
100M
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
(and was of the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V, still well above the 0.5 V
sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM5230 transformers. Figure 18 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown, the ADuM5230 is extremely immune and
can be affected only by extremely large currents operated at
high frequency very close to the component. For the 1 MHz
example noted, the user would have to place a 0.5 kA current
5 mm away from the ADuM5230 to affect the operation of the
component.
1000
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
0.01
Given the geometry of the receiving coil in the ADuM5230 and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 17.
10k
1M
10M
100k
MAGNETIC FIELD FREQUENCY (Hz)
Figure 17. Maximum Allowable External Magnetic Flux Density
MAXIMUM ALLOWABLE CURRENT (kA)
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
0.1
0.01
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM5230 component.
1
07080-024
INPUT (VIx)
10
1k
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
07080-025
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output may differ from the propagation
delay to a logic high.
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
PROPAGATION DELAY-RELATED PARAMETERS
Figure 18. Maximum Allowable Current
for Various Current-to-ADuM5230 Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces may induce error
voltages sufficiently large enough to trigger the thresholds of
Rev. 0 | Page 11 of 16
ADuM5230
succeeding circuitry. Care should be taken in the layout of such
traces to avoid this possibility.
POWER CONSUMPTION
The power converter in the ADuM5230 provides 13 mA of
power to the secondary in its default configuration. Power is
provided to both the data channel, VOA, and the VISO pin for offchip use. Current consumption of VOA varies with frequency as
shown in Figure 8. The maximum available power for external
use decreases as the frequency of the data channel increases to
stay within the total available current.
INCREASING AND DECREASING AVAILABLE POWER
The VADJ pin is used to increase or decrease the available power
at the VISO pin. This allows the increase of the VISO voltage for a
given load or the increase of the maximum VISO load. Alternatively,
power can also be reduced when it is not required at the output,
lowering the quiescent current and saving power.
Power adjustment is accomplished by adding a voltage divider
between VADJ, VDD1 and GND as shown in Figure 25. Under
normal operation, the VADJ pin is left open, allowing the internal
bias network to set the duty factor of the internal PWM. If the
VADJ pin is connected via a resistor divider, a duty factor other
than the default can be chosen. The relationship between the
duty factor of the internal PWM and the available power under
load is shown in Figure 13. When the desired duty factor is
chosen, the values of the upper and lower divider resistors can
be chosen as shown in Figure 14, which assumes a 10 kΩ total
divider resistance.
COMMON-MODE TRANSIENT IMMUNITY
In general, common-mode transients consist of linear and
sinusoidal components. The linear component of a commonmode transient is given by
VCM, linear = (ΔV/Δt) t
where ΔV/Δt is the slope of the transient shown in Figure 19
and Figure 20.
The transient of the linear component is given by
dVCM/dt = ΔV/Δt
The ability of the ADuM5230 to operate correctly in the
presence of linear transients is characterized by the data in
Figure 22. The data is based on design simulation and is the
maximum linear transient magnitude that the ADuM5230 can
tolerate without an operational error. This data shows a higher
level of robustness than what is shown in Table 1 because the
transient immunity values obtained in Table 1 use measured
data and apply allowances for measurement error and margin.
15V
VDD1
5V
GND1
15V
VISO AND VDDB
15V
GNDISO AND GNDB
ΔV
VISO AND VDDB
Δt
ΔV
GNDISO AND GNDB
Δt
5V
15V
07080-006
VDD1
GND1
Figure 19. Common-Mode Transient Immunity Waveforms—Input to Output
15V
VISO/VDDB
15V
GNDB/GNDB
VISO/VDDB
15V
VISO/VDDB
VISO/VDDB
GNDISO/GNDB
Δt
ΔV
Δt
15V
15V
07080-007
GNDISO/GNDB
ΔV
15V
GNDB/GNDB
Figure 20. Common-Mode Transient Immunity Waveforms—Between Outputs
VISO/VDDB
ΔVDD
GNDISO/GNDB
GNDISO/GNDB
Figure 21. Transient Immunity Waveforms—Output Supplies
Rev. 0 | Page 12 of 16
07080-008
Δt
VISO/VDDB
ADuM5230
200
300
180
160
TRANSIENT IMMUNITY (kV/µs)
TRANSIENT IMMUNITY (kV/µs)
250
BEST-CASE PROCESS VARIATION
200
150
100
WORST-CASE PROCESS VARIATION
140
120
100
50
80
BEST-CASE PROCESS VARIATION
60
40
20
0
20
40
TEMPERATURE (°C)
60
80
100
07080-003
–20
0
The sinusoidal component (at a given frequency) is given by
500
750
1000
1250
FREQUENCY (MHz)
1500
where:
V0 is the magnitude of the sinusoidal.
f is the frequency of the sinusoidal.
The transient magnitude of the sinusoidal component is given by
dVCM/dt = 2πf V0
The ability of the ADuM5230 to operate correctly in the presence of sinusoidal transients is characterized by the data in
Figure 23 and Figure 24. The data is based on design simulation
and is the maximum sinusoidal transient magnitude (2πf V0)
that the ADuM5230 can tolerate without an operational error.
Values for immunity against sinusoidal transients are not
included in Table 1 because measurements to obtain such values
have not been possible.
2000
The ADuM5230 is intended for driving low gate capacitance
transistors (200 pF typically). Most high voltage applications
involve larger transistors than this. To accommodate these
applications, users can implement a buffer configuration with
the ADuM5230, as shown in Figure 25. In many cases, the
buffer configuration is the least expensive option and provides
the greatest amount of design flexibility. The precise buffer/high
voltage transistor combination can be selected to fit the needs of
the application.
+HV
VDD1
VADJ
VIA
RUPPER
VISO
VOA
GNDISO
ADuM5230
FLOATING VDDB
RLOWER
VDDB
VIB
GND1
160
VOB
GNDB
140
–HV
120
07080-009
180
Figure 25. Application Circuit
100
INSULATION LIFETIME
BEST-CASE PROCESS VARIATION
80
60
40
20
WORST-CASE PROCESS VARIATION
0
250
500
750
1000
1250
FREQUENCY (MHz)
1500
1750
2000
Figure 23. Transient Immunity (Sinusoidal Transients),
27°C Ambient Temperature
07080-004
0
1750
TYPICAL APPLICATION USAGE
VCM, sinusoidal = V0sin(2πft)
TRANSIENT IMMUNITY (kV/µs)
250
Figure 24. Transient Immunity (Sinusoidal Transients),
100°C Ambient Temperature
Figure 22. Transient Immunity (Linear Transients) vs. Temperature
200
0
07080-005
WORST-CASE PROCESS VARIATION
0
–40
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation depends on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog
Devices conducts an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM5230.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage. Table 7 summarizes the
peak voltages for 50 years of service life for a bipolar ac
operating condition and the maximum Analog Devices
Rev. 0 | Page 13 of 16
ADuM5230
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the maximum working voltage recommended by
Analog Devices.
In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher
working voltages while still achieving a 50-year service life.
The working voltages listed in Table 7 can be applied while
maintaining the 50-year minimum lifetime, provided the
voltage conforms to either the unipolar ac or dc voltage cases.
Any cross insulation voltage waveform that does not conform to
Figure 27 or Figure 28 should be treated as a bipolar ac waveform,
and its peak voltage should be limited to the 50-year lifetime
voltage value listed in Table 7. Note that the voltage presented in
Figure 27 is shown as sinusoidal for illustration purposes only.
It is meant to represent any voltage waveform varying between
0 V and some limiting value. The limiting value can be positive
or negative, but the voltage cannot cross 0 V.
Rev. 0 | Page 14 of 16
07080-026
0V
Figure 26. Bipolar AC Waveform
RATED PEAK VOLTAGE
07080-027
The insulation lifetime of the ADuM5230 depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 26, Figure 27, and Figure 28 illustrate these
different isolation voltage waveforms.
RATED PEAK VOLTAGE
0V
Figure 27. Unipolar AC Waveform
RATED PEAK VOLTAGE
07080-028
recommended working voltages. In many cases, the approved
working voltage is higher than the 50-year service life voltage.
Operation at these high working voltages can lead to shortened
insulation life in some cases.
0V
Figure 28. DC Waveform
ADuM5230
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
8
0.51 (0.0201)
0.31 (0.0122)
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
45°
8°
0°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013- AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
032707-B
1
Figure 29. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters (inches)
ORDERING GUIDE
Model
ADuM5230ARWZ 2
ADuM5230ARWZ-RL2
1
2
No. of
Channels
2
2
Output Peak
Current (A) 1
0.1/0.3
0.1/0.3
Output
Voltage (V)
15
15
Temperature Range
−40°C to +105°C
−40°C to +105°C
Sourcing/sinking.
Z = RoHS Compliant Part.
Rev. 0 | Page 15 of 16
Package Description
16-Lead SOIC_W
16-Lead SOIC_W, 13-inch Tape
and Reel Option (1,000 Units)
Package
Option
RW-16
RW-16
ADuM5230
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07080-0-4/08(0)
Rev. 0 | Page 16 of 16