LINER LTC3810 Low iq, 60v, high frequency synchronous step-down controller Datasheet

LTC7800
Low IQ, 60V, High
Frequency Synchronous
Step-Down Controller
DESCRIPTION
FEATURES
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Wide VIN Range: 4V to 60V (65V Abs Max)
Low Operating IQ: 50μA
Wide Output Voltage Range: 0.8V ≤ VOUT ≤ 24V
RSENSE or DCR Current Sensing
Phase-Lockable Frequency (320kHz to 2.25MHz)
Programmable Fixed Frequency (320kHz to
2.25MHz)
Selectable Continuous, Pulse-Skipping or Low Ripple
Burst Mode® Operation at Light Load
Selectable Current Limit
Very Low Dropout Operation: 98% Duty Cycle
Adjustable Output Voltage Soft-Start or Tracking
Power Good Output Voltage Monitor
Output Overvoltage Protection
Low Shutdown IQ: < 14μA
Internal LDO Powers Gate Drive from VIN or EXTVCC
No Current Foldback During Start-Up
Small 20-Pin 3mm × 4mm QFN Package
APPLICATIONS
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The LTC®7800 is a high performance step-down switching
regulator DC/DC controller that drives an all N-channel
synchronous power MOSFET stage. A constant frequency current mode architecture allows a phase-lockable
frequency of up to 2.25MHz.
The 50μA no-load quiescent current extends operating run
time in battery-powered systems. OPTI-LOOP® compensation allows the transient response to be optimized over
a wide range of output capacitance and ESR values. The
LTC7800 features a precision 0.8V reference and power
good output indicator. A wide 4V to 60V input supply
range encompasses a wide range of intermediate bus
voltages and battery chemistries. The output voltage of
the LTC7800 can be programmed between 0.8V to 24V.
The TRACK/SS pin ramps the output voltages during
start-up. Current foldback limits MOSFET heat dissipation
during short-circuit conditions. The PLLIN/MODE pin selects among Burst Mode operation, pulse-skipping mode,
or continuous conduction mode at light loads.
L, LT, LTC, LTM, OPTI-LOOP, Burst Mode, Linear Technology and the Linear logo are registered
trademarks of Analog Devices, Inc. All other trademarks are the property of their respective
owners. Patents, including 5481178, 5705919, 6611131, 6498466, 6580258, 7230497.
Automotive Always-On Systems
Battery Powered Digital Devices
Distributed DC Power Systems
TYPICAL APPLICATION
High Efficiency 3.3V 2.1MHz Step-Down Regulator
C I1
2.2µF
×3
C I2
56µF
INTVCC
VIN
Efficiency and Power Loss vs
Output Current
2.2µF
PGND
820pF
LTC7800
PGOOD
EXTVCC
100k
FREQ
2.49k
80pF
TG
BOOST
SW
ITH
TRACK/SS
SGND
0.1µF
0.33µH
VOUT
3.3V
COUT 10A
33µF
×2
4mΩ
BG
SENSE+
0.1µF
SENSE–
10
80
1
357k
VFB
115k
70
0.1
60
50
0.01
40
30
POWER LOSS (W)
INTVCC
100k
100
VIN = 12V
90 VOUT = 3.3V
EFFICIENCY (%)
VIN
4V TO
28V
0.001
20
10
0
0.0001
0.001
0.01
0.1
1
10
0.0001
OUTPUT CURRENT (A)
3874 TA01b
7800f
For more information www.linear.com/LTC7800
1
LTC7800
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
ORDER INFORMATION
VIN
ILIM
TRACK/SS
FREQ
TOP VIEW
20 19 18 17
16 PGND
PLLIN/MODE 1
15 EXTVCC
SGND 2
SGND 3
14 INTVCC
21
SGND
RUN 4
13 BG
12 BOOST
SENSE+ 6
11 SW
9 10
TG
8
PGOOD
7
ITH
SENSE– 5
VFB
Input Supply Voltage (VIN).......................... –0.3V to 65V
Topside Driver Voltage (BOOST)..................–0.3V to 71V
Switch Voltage (SW)...................................... –5V to 65V
(BOOST-SW)................................................. –0.3V to 6V
BG, TG................................................................ (Note 8)
RUN.............................................................. –0.3V to 8V
Maximum Current Sourced into Pin from
Source > 8V.......................................................100μA
SENSE+, SENSE– Voltages.......................... –0.3V to 28V
PLLIN/MODE, INTVCC Voltages.................... –0.3V to 6V
ILIM, FREQ Voltages............................... –0.3V to INTVCC
EXTVCC....................................................... –0.3V to 14V
ITH, VFB Voltages.......................................... –0.3V to 6V
PGOOD Voltage............................................. –0.3V to 6V
TRACK/SS Voltage........................................ –0.3V to 6V
Operating Junction Temperature Range (Notes 2, 3)
LTC7800E, LTC7800I.......................... –40°C to 125°C
LTC7800H........................................... –40°C to 150°C
Maximum Junction Temperature (Notes 2, 3)
LTC7800E, LTC7800I......................................... 125°C
LTC7800H.......................................................... 150°C
Storage Temperature Range................... –65°C to 150°C
UDC PACKAGE
20-LEAD (3mm × 4mm) PLASTIC QFN
TJMAX = 150°C, θJA = 52°C/W
EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB
http://www.linear.com/product/LTC7800#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC7800EUDC#PBF
LTC7800EUDC#TRPBF
LHBS
20-Lead (3mm × 4mm) Plastic QFN
–40°C to 125°C
LTC7800IUDC#PBF
LTC7800IUDC#TRPBF
LHBS
20-Lead (3mm × 4mm) Plastic QFN
–40°C to 125°C
LTC7800HUDC#PBF
LTC7800HUDC#TRPBF
LHBS
20-Lead (3mm × 4mm) Plastic QFN
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
7800f
2
For more information www.linear.com/LTC7800
LTC7800
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified
operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, EXTVCC = 0V unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VIN
Input Supply Operating Voltage Range
VFB
Regulated Feedback Voltage
MIN
TYP
4
(Note 4); ITH Voltage = 1.2V
–40°C to 85°C
LTC7800E, LTC7800I
LTC7800H
IFB
Feedback Current
(Note 4)
VREFLNREG
Reference Voltage Line Regulation
(Note 4); VIN = 4.5V to 60V
VLOADREG
Output Voltage Load Regulation
(Note 4)
Measured in Servo Loop;
∆ITH Voltage = 1.2V to 0.7V
(Note 4)
Measured in Servo Loop;
∆ITH Voltage = 1.2V to 2V
gm
Transconductance Amplifier gm
(Note 4); ITH = 1.2V; Sink/Source 5µA
IQ
Input DC Supply Current
(Note 5)
Pulse Skip or Forced Continuous Mode
l
l
0.792
0.788
0.786
0.800
0.800
0.800
MAX
UNITS
60
V
0.808
0.812
0.812
V
V
V
±5
±50
nA
0.002
0.02
%/V
l
0.01
0.1
%
l
–0.01
–0.1
%
2
mmho
VFB = 0.83V (No Load)
2
mA
Sleep Mode
VFB = 0.83V (No Load)
50
Shutdown
RUN = 0V
UVLO
Undervoltage Lockout
INTVCC Ramping Up
INTVCC Ramping Down
Measured at VFB Relative to Regulated VFB
l
l
75
µA
14
25
µA
3.6
3.92
3.80
4.2
4.0
V
V
7
10
VOVL
Feedback Overvoltage Protection
ISENSE+
SENSE+ Pin Current
ISENSE–
SENSE– Pins Current
VSENSE– < INTVCC – 0.5V
VSENSE– > INTVCC + 0.5V
DFMAX
Maximum Duty Factor
In Dropout; VFREQ = 0V
97
98
ITRACK/SS
Soft-Start Charge Current
VTRACK/SS = 0V
7
10
14
µA
VRUN On
RUN Pin On Threshold
VRUN Rising
l
1.15
1.21
1.27
V
VRUN Hyst
RUN Pin Hysteresis
VFB = 0.7V, VSENSE– = 3.3V, ILIM = 0V
VFB = 0.7V, VSENSE– = 3.3V, ILIM = INTVCC
VFB = 0.7V, VSENSE– = 3.3V, ILIM = FLOAT
l
l
l
VSENSE(MAX)
700
13
%
±1
µA
±2
µA
µA
%
50
Maximum Current Sense Threshold
22
43
64
30
50
75
mV
36
57
85
mV
mV
mV
Gate Driver
TG
Pull-Up On-Resistance
Pull-Down On-Resistance
2.5
1.5
Ω
Ω
BG
Pull-Up On-Resistance
Pull-Down On-Resistance
2.4
1.1
Ω
Ω
TG tr
TG tf
TG Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
16
ns
ns
BG tr
BG tf
BG Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
13
ns
ns
TG/BG t1D
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF
20
ns
BG/TG t1D
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF
20
ns
7800f
For more information www.linear.com/LTC7800
3
LTC7800
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified
operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, EXTVCC = 0V unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
tON(MIN)
Minimum TG On-Time
(Note 7)
MIN
TYP
MAX
45
UNITS
ns
INTVCC Linear Regulator
VINTVCCVIN
Internal VCC Voltage
6V < VIN < 60V, VEXTVCC = 0V
VLDOVIN
INTVCC Load Regulation
ICC = 0mA to 50mA, VEXTVCC = 0V
VINTVCCEXT
Internal VCC Voltage
6V < VEXTVCC < 13V
VLDOEXT
INTVCC Load Regulation
ICC = 0mA to 50mA,
VEXTVCC = 8.5V
VEXTVCC
EXTVCC Switchover Voltage
ICC = 0mA to 50mA,
EXTVCC Ramping Positive
VLDOHYS
EXTVCC Hysteresis
4.85
4.85
4.5
5.1
5.35
V
0.7
1.1
%
5.1
5.35
V
0.6
1.1
%
4.7
4.9
V
250
mV
Oscillator and Phase-Locked Loop
f25kΩ
Programmable Frequency
RFREQ = 25k;
PLLIN/MODE = DC Voltage
f65kΩ
Programmable Frequency
RFREQ = 65k;
PLLIN/MODE = DC Voltage
f100kΩ
Programmable Frequency
RFREQ =100k;
PLLIN/MODE = DC Voltage
fLOW
Low Fixed Frequency
fHIGH
0.27
0.32
0.36
1.18
MHz
MHz
1.75
2.1
2.4
MHz
VFREQ = 0V;
PLLIN/MODE = DC Voltage
0.79
0.94
1.08
MHz
High Fixed Frequency
VFREQ = INTVCC;
PLLIN/MODE = DC Voltage
1.2
1.44
1.7
MHz
fSYNC
Synchronizable Frequency
PLLIN/MODE = External Clock
l
0.32
2.25
MHz
PLLIN VIH
PLLIN/MODE Input High Level
PLLIN/MODE = External Clock
l
2.5
PLLIN VIL
PLLIN/MODE Input Low Level
PLLIN/MODE = External Clock
l
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
IPGOOD
PGOOD Leakage Current
VPGOOD = 5V
VPG
PGOOD Trip Level
VFB with Respect to Set Regulated Voltage
l
V
0.5
V
0.4
V
±1
µA
–7
%
PGOOD1 Output
0.2
VFB Ramping Negative
–13
Hysteresis
2.5
VFB Ramping Positive
Hysteresis
tPG
Delay for Reporting a Fault
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC7800 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC7800E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC7800I is guaranteed
over the –40°C to 125°C operating junction temperature range, the
LTC7800H is guaranteed over the –40°C to 150°C operating junction
–10
7
10
%
13
%
2.5
%
25
µs
temperature range. High junction temperatures degrade operating
lifetimes; operating lifetime is derated for junction temperatures greater
than 125°C. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance and
other environmental factors.
Note 3: The junction temperature (TJ, in °C) is calculated from the ambient
temperature (TA, in °C) and power dissipation (PD, in Watts) according to
the formula:
TJ = TA + (PD • θJA), where θJA is 52°C/W.
7800f
4
For more information www.linear.com/LTC7800
LTC7800
ELECTRICAL CHARACTERISTICS
Note 4: The LTC7800 is tested in a feedback loop that servos VITH to a
specified voltage and measures the resultant VFB. The specification at 85°C
is not tested in production and is assured by design, characterization and
correlation to production testing at other temperatures (125°C for the
LTC7800E/LTC7800I and 150°C for the LTC7800H.)
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥ 40% of IMAX (See Minimum On-Time
Considerations in the Applications Information section).
Note 8: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only, otherwise permanent damage may
occur.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss vs
Output Current
Efficiency vs Output Current
1
0.1
PULSE-SKIPPING
LOSS
50
0.01
40
FCM EFFICIENCY
30 BURST
20 LOSS
PULSE–SKIPPING
EFFICIENCY
0
0.0001
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
FIGURE 11 CIRCUIT
60
50
40
30
10
10
0.0001
Burst Mode OPERATION
VIN = 12V
0
0.0001
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
FIGURES 11, 12 CIRCUITS
7800 G01
Load Step
Burst Mode Operation
VOUT = 5V
90
VOUT = 3.3V
85
80
20
0.001
10
95
VOUT = 3.3V
70
EFFICIENCY (%)
60
80
EFFICIENCY (%)
FCM LOSS
70
Efficiency vs Input Voltage
100
VOUT = 5V
90
BURST EFFICIENCY
POWER LOSS (W)
EFFICIENCY (%)
VIN = 12V
90 VOUT = 3.3V
80
100
10
100
10
75
ILOAD = 5A
5
7800 G02
25
30
35
7800 G03
Load Step
Forced Continuous Mode
VOUT
100mV/DIV
ACCOUPLED
VOUT
100mV/DIV
ACCOUPLED
IL
5A/DIV
IL
5A/DIV
IL
5A/DIV
20µs/DIV
LOAD STEP = 500mA TO 5A
VIN = 12V
VOUT = 3.3V
FIGURE 11 CIRCUIT
20
FIGURES 11, 12 CIRCUITS
Load Step
Pulse-Skipping Mode
7800 G04
15
INPUT VOLTAGE (V)
VOUT
100mV/DIV
ACCOUPLED
20µs/DIV
LOAD STEP = 500mA TO 5A
VIN = 12V
VOUT = 3.3V
FIGURE 11 CIRCUIT
10
7800 G05
50µs/DIV
LOAD STEP = 500mA TO 5A
VIN = 12V
VOUT = 3.3V
FIGURE 11 CIRCUIT
7800 G06
7800f
For more information www.linear.com/LTC7800
5
LTC7800
TYPICAL PERFORMANCE CHARACTERISTICS
Inductor Current at Light Load
Shutdown Current vs Input
Voltage
Soft Start-Up
30
VOUT = 5V
1V/DIV
25
VOUT = 3.3V
1V/DIV
Burst Mode
OPERATION
2A/DIV
PULSE-SKIPPING
MODE
7800 G07
1µs/DIV
7800 G08
2ms/DIV
VIN = 12V
VOUT = 3.3V
ILOAD = 50mA
SHUTDOWN CURRENT (µA)
FORCED
CONTINUOUS
MODE
20
15
10
5
FIGURES 11, 12 CIRCUITS
0
5 10 15 20 25 30 35 40 45 50 55 60 65
INPUT VOLTAGE (V)
7800 G09
Total Input Supply Current vs
Input Voltage
FIGURE 13 CIRCUIT
200
300µA LOAD
150
100
NO LOAD
50
0
5.8
EXTVCC AND INTVCC VOLTAGE (V)
SUPPLY CURRENT (µA)
250
INTVCC Line Regulation
5.5
6.0
5.0
5.6
5.4
INTVCC
5.2
5.0
EXTVCC RISING
4.8
EXTVCC FALLING
4.6
4.5
4.0
3.5
4.4
4.2
4.0
–75 –50 –25
5 10 15 20 25 30 35 40 45 50 55 60
INPUT VOLTAGE (V)
INTVCC VOLTAGE (V)
300
EXTVCC Switchover and INTVCC
Voltages vs Temperature
7800 G10
3.0
0 25 50 75 100 125 150
TEMPERATURE (°C)
ILOAD = 10mA
0 5 10 15 20 25 30 35 40 45 50 55 60 65
INPUT VOLTAGE (V)
7800 G12
7800 G11
700
60
PULSE-SKIPPING MODE
Burst Mode
OPERATION
20
ILIM = GND
0
ILIM = INTVCC
ILIM = FLOAT
–20
0
0.2
0.4
0.6 0.8
VITH (V)
1.0
1.2
600
500
400
300
200
100
0
FORCED CONTINUOUS MODE
–40
MAXIMUM CURRENT SENSE VOLTAGE (mV)
800
5% DUTY CYCLE
40
Maximum Current Sense
Threshold vs Duty Cycle
SENSE– Pin Input Bias Current
SENSE– CURRENT (µA)
CURRENT SENSE THESHOLD (mV)
80
Maximum Current Sense Voltage
vs ITH Voltage
1.4
7800 G13
–100
0
5
10
15
25
20
VSENSE COMMON MODE VOLTAGE (V)
7800 G14
80
70
ILIM = FLOAT
60
ILIM = INTVCC
50
40
ILIM = GND
30
20
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
7800 G15
7800f
6
For more information www.linear.com/LTC7800
LTC7800
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current vs Temperature
80
ILIM = FLOAT
ILIM = INTVCC
50
40
30
ILIM = GND
20
10
65
60
55
50
45
40
100 200 300 400 500 600
FEEDBACK VOLTAGE (mV)
30
–75 –50 –25
700 800
RUN PIN VOLTAGE (V)
TRACK/SS CURRENT (µA)
9.0
1.25
RUN RISING
1.20
RUN FALLING
1.15
1.10
–75 –50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
100
0
–100
–75 –50 –25
99.5
2.05
FREQUENCY (MHz)
98.5
98.0
97.5
7800 G22
0 25 50 75 100 125 150
TEMPERATURE (°C)
96.0
300
740
1180
1620
2060
2500
FREQ = 100k
1.85
1.65
FREQ = INTVCC
1.45
1.25
1.05
96.5
0 25 50 75 100 125 150
TEMPERATURE (°C)
794
Oscillator Frequency
vs Temperature
97.0
VOUT < INTVCC – 0.5V
796
2.25
DFMAX (%)
SENSE– CURRENT (µA)
200
798
7800 G21
99.0
300
800
100.0
500
400
802
Maximum Duty Factor vs
Frequency
VOUT > INTVCC + 0.5V
100
804
7800 G20
SENSE– Pin Input Bias Current
vs Temperature
600
60
80
40
LOAD CURRENT (mA)
806
792
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
7800 G19
700
20
808
8.5
800
0
Regulated Feedback Voltage
vs Temperature
11.5
9.5
EXTVCC = 5V
4.50
7800 G18
1.30
12.0
8.0
–75 –50 –25
4.75
Shutdown (RUN) Threshold
vs Temperature
10.0
EXTVCC = 8.5V
7800 G17
TRACK/SS Pull-Up Current
vs Temperature
10.5
EXTVCC = 0V
5.00
4.00
0 25 50 75 100 125 150
TEMPERATURE (°C)
7800 G16
11.0
VIN = 12V
4.25
35
0
INTVCC vs Load Current
5.25
70
REGULATED FEEDBACK VOLTAGE (mV)
0
VIN = 12V
75
60
5.50
INTVCC VOLTAGE (V)
70
QUIESCENT CURRENT (µA)
MAXIMUM CURRENT SENSE VOLTAGE (mV)
Foldback Current Limit
80
0.85
–75 –50 –25
FREQ = GND
0
25
50
75 100 125 150
TEMPERATURE (°C)
FREQUENCY (kHz)
7800 G23
7800 G24
7800f
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7
LTC7800
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency vs Input
Voltage
FREQ = GND
943
INTVCC VOLTAGE (V)
OSCILLATOR FREQUENCY (kHz)
944
942
941
939
938
937
935
22
4.1
20
4.0
RISING
3.9
3.8
FALLING
3.7
936
5
15
25
35
45
INPUT VOLTAGE (V)
55
65
Shutdown Current vs Temperature
4.2
SHUTDOWN CURRENT (µA)
945
Undervoltage Lockout Threshold
vs Temperature
3.6
–75 –50 –25
VIN = 12V
18
16
14
12
10
0 25 50 75 100 125 150
TEMPERATURE (°C)
7800 G25
7800 G26
8
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
7800 G27
PIN FUNCTIONS
PLLIN/MODE (Pin 1): External Synchronization Input to
Phase Detector and Forced Continuous Mode Input. When
an external clock is applied to this pin, the phase-locked
loop will force the rising TG signal to be synchronized with
the rising edge of the external clock, and the regulator
operates in forced continuous mode. When not synchronizing to an external clock, this input determines how the
LTC7800 operates at light loads. Pulling this pin to ground
selects Burst Mode operation. An internal 100k resistor to
ground also invokes Burst Mode operation when the pin is
floated. Tying this pin to INTVCC forces continuous inductor
current operation. Tying this pin to a voltage greater than
1.2V and less than INTVCC –1.3V selects pulse-skipping
operation. This can be done by connecting a 100k resistor
from this pin to INTVCC.
SGND (Pins 2, 3, Exposed Pad Pin 21): Small-signal
ground, must be routed separately from high current
grounds to the common (–) terminals of the CIN capacitor.
Pins 2, 3, Exposed Pad Pin 21, must both be electrically
connected to small signal ground for proper operation.
The exposed pad must be soldered to PCB ground for
rated thermal performance.
RUN (Pin 4): Digital Run Control Input. Forcing this pin
below 1.16V shuts down the controller. Forcing this pin
below 0.7V shuts down the entire LTC7800, reducing
quiescent current to approximately 14µA.
SENSE– (Pin 5): The (–) Input to the Differential Current
Comparator. When greater than INTVCC – 0.5V, the SENSE–
pin supplies power to the current comparator.
SENSE+ (Pin 6): The (+) input to the differential current
comparator is normally connected to DCR sensing network or current sensing resistor. The ITH pin voltage and
controlled offsets between the SENSE– and SENSE+ pins
in conjunction with RSENSE set the current trip threshold.
VFB (Pin 7): Receives the remotely sensed feedback voltage from an external resistive divider across the output.
ITH (Pin 8): Error Amplifier Outputs and Switching Regulator Compensation Point. The current comparator trip point
increases with this control voltage.
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LTC7800
PIN FUNCTIONS
PGOOD (Pin 9): Open-Drain Logic Output. PGOOD is pulled
to ground when the voltage on the VFB pin is not within
10% of its set point.
PGND (Pin 16): Driver Power Ground. Connects to the
source of bottom (synchronous) N-channel MOSFET and
the (–) terminal of CIN.
TG (Pin 10): High Current Gate Drives for Top N-channel
MOSFET. This is the output of floating driver with a voltage swing equal to INTVCC superimposed on the switch
node voltage SW.
VIN (Pin 17): Main Supply Pin. A bypass capacitor should
be tied between this pin and the SGND pins.
SW (Pin 11): Switch Node Connection to Inductor.
BOOST (Pin 12): Bootstrapped Supply to the Topside
Floating Driver. A capacitor is connected between the
BOOST and SW pin and a Schottky diode is tied between
the BOOST and INTVCC pins. Voltage swing at the BOOST
pin is from INTVCC to (VIN + INTVCC).
BG (Pin 13): High Current Gate Drive for Bottom (Synchronous) N-channel MOSFET. Voltage swing at this pin
is from ground to INTVCC.
INTVCC (Pin 14): Output of the Internal Linear Low Dropout
Regulator. The driver and control circuits are powered from
this voltage source. Must be decoupled to PGND with a
minimum of 2.2µF ceramic or other low ESR capacitor. Do
not use the INTVCC pin for any other purpose.
EXTVCC (Pin 15): External Power Input to an Internal LDO
Connected to INTVCC. This LDO supplies INTVCC power,
bypassing the internal LDO powered from VIN whenever
EXTVCC is higher than 4.7V. See EXTVCC Connection in the
Applications Information section. Do not float or exceed
14V on this pin.
ILIM (Pin 18): Current Comparator Sense Voltage Range
Inputs. Tying this pin to SGND, FLOAT or INTVCC sets the
maximum current sense threshold to one of three different
levels for the comparator.
TRACK/SS (Pin 19): External Tracking and Soft-Start Input.
The LTC7800 regulates the VFB voltage to the smaller of
0.8V or the voltage on the TRACK/SS pin. An internal 10μA
pull-up current source is connected to this pin. A capacitor
to ground at this pin sets the ramp time to final regulated
output voltage. Alternatively, a resistor divider on another
voltage supply connected to this pin allows the LTC7800
output to track another supply during start-up.
FREQ (Pin 20): The frequency control pin for the internal
VCO. Connecting the pin to GND forces the VCO to a fixed
low frequency of 0.94MHz. Connecting the pin to INTVCC
forces the VCO to a fixed high frequency of 1.44MHz.
Other frequencies between 320kHz and 2.25MHz can be
programmed by using a resistor between FREQ and GND.
An internal 20µA pull-up current develops the voltage to
be used by the VCO to control the frequency.
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9
LTC7800
FUNCTIONAL DIAGRAM
VIN
INTVCC
PGOOD
0.88V
VFB
DROP
OUT
DET
+
–
+
0.72V
S
Q
R
Q
D
BOT
SWITCH
LOGIC BOT
INTVCC
BG
VOUT
–
0.425V
+
SLEEP
–
ICMP
PFD
+
–
–+
+–
IR
–
SENSE+
+
2.7V
0.65V
100k
SENSE–
SLOPE COMP
VFB
EA
OV
EXTVCC
–
5.1V
LDO
EN
LDO
EN
7µA
+
4.7V
11V
–
SHDN
RST
2(VFB)
0.80V
TRACK/SS
RB
RA
+
VIN
+
+
–
CURRENT
LIMIT
5.1V
RSENSE
L
2mV
SYNC
DET
ILIM
COUT
PGND
CLK2
CLK1
PLLIN/MODE
CIN
SW
TOP ON
20µA
VCO
CB
TG
TOP
SHDN
FREQ
DB
BOOST
0.88V
ITH
CC2
10µA
FOLDBACK
CC
RC
TRACK/SS
SHDN
CSS
7800 FD
SGND
INTVCC
RUN
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LTC7800
OPERATION
Main Control Loop
Shutdown and Start-Up (RUN, TRACK/SS Pins)
The LTC7800 uses a constant frequency, current mode
step-down architecture. During normal operation, the
external top MOSFET is turned on when the clock for
that channel sets the RS latch, and is turned off when the
main current comparator, ICMP, resets the RS latch. The
peak inductor current at which ICMP trips and resets the
latch is controlled by the voltage on the ITH pin, which is
the output of the error amplifier, EA. The error amplifier
compares the output voltage feedback signal at the VFB
pin (which is generated with an external resistor divider
connected across the output voltage, VOUT, to ground)
to the internal 0.800V reference voltage. When the load
current increases, it causes a slight decrease in VFB relative to the reference, which causes the EA to increase the
ITH voltage until the average inductor current matches
the new load current.
The LTC7800 can be shut down using the RUN pin. Pulling
this pin below 1.16V shuts down the main control loop.
Pulling the RUN pin below 0.7V disables the controller and
most internal circuits, including the INTVCC LDOs. In this
state, the LTC7800 draws only 14μA of quiescent current.
After the top MOSFET is turned off each cycle, the bottom
MOSFET is turned on until either the inductor current starts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is tied to a voltage less than 4.7V,
the VIN LDO (low dropout linear regulator) supplies 5.1V
from VIN to INTVCC. If EXTVCC is taken above 4.7V, the VIN
LDO is turned off and an EXTVCC LDO is turned on. Once
enabled, the EXTVCC LDO supplies 5.1V from EXTVCC to
INTVCC. Using the EXTVCC pin allows the INTVCC power
to be derived from a high efficiency external source such
as one of the LTC7800 switching regulator outputs.
The top MOSFET driver is biased from the floating bootstrap
capacitor, CB, which normally recharges during each cycle
through an external diode when the top MOSFET turns
off. If the input voltage, VIN, decreases to a voltage close
to VOUT, the loop may enter dropout and attempt to turn
on the top MOSFET continuously. The dropout detector
detects this and forces the top MOSFET off for a short
time every tenth cycle to allow CB to recharge resulting
in about 98% duty cycle at 1MHz operation.
Releasing the RUN pin allows a small internal current to
pull up the pin to enable the controller. The RUN pin has
a 7μA pull-up which is designed to be large enough so
that the RUN pin can be safely floated (to always enable
the controller) without worry of condensation or other
small board leakage pulling the pin down. This is ideal
for always-on applications where the controller is enabled
continuously and never shut down.
The RUN pin may be externally pulled up or driven directly
by logic. When driving the RUN pin with a low impedance
source, do not exceed the absolute maximum rating of
8V. The RUN pin has an internal 11V voltage clamp that
allows the RUN pin to be connected through a resistor to a
higher voltage (for example, VIN), so long as the maximum
current into the RUN pin does not exceed 100μA.
The RUN pin can also be implemented as a UVLO by
connecting it to the output of an external resistor divider
network off VIN (see Applications Information section).
The start-up of the controller’s output voltage VOUT is
controlled by the voltage on the TRACK/SS pin. When the
voltage on the TRACK/SS pin is less than the 0.8V internal
reference, the LTC7800 regulates the VFB voltage to the
TRACK/SS pin voltage instead of the 0.8V reference. This
allows the TRACK/SS pin to be used to program a soft-start
by connecting an external capacitor from the TRACK/SS
pin to SGND. An internal 10μA pull-up current charges
this capacitor creating a voltage ramp on the TRACK/
SS pin. As the TRACK/SS voltage rises linearly from 0V
to 0.8V (and beyond up to 5V), the output voltage VOUT
rises smoothly from zero to its final value. Alternatively
the TRACK/SS pin can be used to cause the start-up of
VOUT to track that of another supply. Typically, this requires
connecting to the TRACK/SS pin an external resistor
divider from the other supply to ground (see Applications
Information section).
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11
LTC7800
OPERATION
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Forced Continuous Mode)
(PLLIN/MODE Pin)
The LTC7800 can be enabled to enter high efficiency Burst
Mode operation, constant frequency pulse-skipping mode,
or forced continuous conduction mode at low load currents. To select Burst Mode operation, tie the PLLIN/MODE
pin to SGND. To select forced continuous operation, tie
the PLLIN/MODE pin to INTVCC. To select pulse-skipping
mode, tie the PLLIN/MODE pin to a DC voltage greater
than 1.2V and less than INTVCC – 1.3V.
When the controller is enabled for Burst Mode operation, the minimum peak current in the inductor is set to
approximately 25% of the maximum sense voltage even
though the voltage on the ITH pin indicates a lower value.
If the average inductor current is higher than the load current, the error amplifier, EA, will decrease the voltage on
the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off. The ITH pin is
then disconnected from the output of the EA and parked
at 0.450V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC7800 draws
to only 50μA. In sleep mode, the load current is supplied
by the output capacitor. As the output voltage decreases,
the EA’s output begins to rise. When the output voltage
drops enough, the ITH pin is reconnected to the output
of the EA, the sleep signal goes low, and the controller
resumes normal operation by turning on the top external
MOSFET on the next cycle of the internal oscillator.
When the controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator, IR, turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus, the
controller operates in discontinuous operation.
In forced continuous operation or clocked by an external
clock source to use the phase-locked loop (see Frequency
Selection and Phase-Locked Loop section), the inductor
current is allowed to reverse at light loads or under large
transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in normal
operation. In this mode, the efficiency at light loads is
lower than in Burst Mode operation. However, continuous
operation has the advantage of lower output voltage ripple
and less interference to audio circuitry. In forced continuous mode, the output ripple is independent of load current.
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC7800 operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads, the
current comparator, ICMP, may remain tripped for several
cycles and force the external top MOSFET to stay off for
the same number of cycles (i.e., skipping pulses). The
inductor current is not allowed to reverse (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. It provides higher low current efficiency than
forced continuous mode, but not nearly as high as Burst
Mode operation.
Frequency Selection and Phase-Locked Loop (FREQ
and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC7800 can be selected
using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied
to INTVCC or programmed through an external resistor.
Tying FREQ to SGND selects 0.94MHz while tying FREQ
to INTVCC selects 1.44MHz. Placing a resistor between
FREQ and SGND allows the frequency to be programmed
between 320kHz and 2.25MHz, as shown in Figure 8.
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LTC7800
OPERATION
A phase-locked loop (PLL) is available on the LTC7800
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC7800’s phase detector adjusts the voltage (through
an internal lowpass filter) of the VCO input to align the
turn-on of the controller’s external top MOSFET to the
rising edge of the synchronizing signal.
The VCO input voltage is prebiased to the operating frequency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the phase-locked loop is from
approximately 300kHz to 2.3MHz, with a guarantee to be
between 320kHz and 2.25MHz. In other words, the
LTC7800’s PLL is guaranteed to lock to an external clock
source whose frequency is between 320kHz and 2.25MHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.1V (falling). The LTC7800 is
guaranteed to synchronize to an external clock that swings
up to at least 2.5V and down to 0.5V or less.
Output Overvoltage Protection
An overvoltage comparator guards against transient overshoots as well as other more serious conditions that may
overvoltage the output. When the VFB pin rises by more
than 10% above its regulation point of 0.800V, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Power Good Pin
The PGOOD pin is connected to an open drain of an internal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when the VFB pin voltage is not within
±10% of the 0.8V reference voltage. The PGOOD pin is also
pulled low when the RUN pin is low (shut down). When
the VFB pin voltage is within the ±10% requirement, the
MOSFET is turned off and the pin is allowed to be pulled
up by an external resistor to a source no greater than 6V.
Foldback Current
When the output voltage falls to less than 70% of its
nominal level, foldback current limiting is activated, progressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
interval (as long as the VFB voltage is keeping up with the
TRACK/SS voltage).
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13
LTC7800
APPLICATIONS INFORMATION
The Typical Application on the first page is a basic LTC7800
application circuit. LTC7800 can be configured to use
either DCR (inductor resistance) sensing or low value
resistor sensing. The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
RSENSE (if RSENSE is used) and inductor value. Next, the
power MOSFETs and Schottky diodes are selected. Finally,
input and output capacitors are selected.
Filter components mutual to the sense lines should be
placed close to the LTC7800, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing current elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If inductor DCR
sensing is used (Figure 2b), sense resistor R1 should be
placed close to the switching node, to prevent noise from
coupling into sensitive small-signal nodes.
TO SENSE FILTER,
NEXT TO THE CONTROLLER
7800 F01
COUT
INDUCTOR OR RSENSE
Current Limit Programming
Figure 1. Sense Lines Placement with Inductor or Sense Resistor
The ILIM pin is a tri-level logic input which sets the maximum
current limit of the controller. When ILIM is grounded, the
maximum current limit threshold voltage of the current
comparator is programmed to be 30mV. When ILIM is
floated, the maximum current limit threshold is 75mV.
When ILIM is tied to INTVCC, the maximum current limit
threshold is set to 50mV.
VIN
INTVCC
BOOST
TG
The SENSE+ and SENSE– pins are the inputs to the current comparators. The common mode voltage range on
these pins is 0V to 28V (abs max), enabling the LTC7800
to regulate output voltages up to a nominal 24V (allowing
margin for tolerances and transients).
The SENSE+ pin is high impedance over the full common
mode range, drawing at most ±1μA. This high impedance
allows the current comparators to be used in inductor
DCR sensing.
The impedance of the SENSE– pin changes depending on
the common mode voltage. When SENSE– is less than
INTVCC – 0.5V, a small current of less than 1μA flows out
of the pin. When SENSE– is above INTVCC + 0.5V, a higher
current (~700μA) flows into the pin. Between INTVCC –
0.5V and INTVCC + 0.5V, the current transitions from the
smaller current to the higher current.
RSENSE
SW
LTC7800
VOUT
BG
SENSE+
SENSE+ and SENSE– Pins
VIN
SENSE–
R1*
C1* PLACE CAPACITOR NEAR
SENSE PINS
SGND
7800 F02a
*R1 AND C1 ARE OPTIONAL
(2a) Using a Resistor to Sense Current
VIN
INTVCC
VIN
BOOST
INDUCTOR
TG
L
SW
LTC7800
BG
DCR
VOUT
R1
SENSE+
C1*
R2
SENSE–
SGND
*PLACE C1 NEAR
SENSE PINS
(R1||R2) • C1 =
L
DCR
RSENSE(EQ) = DCR
R2
R1 + R2
7800 F02b
(2b) Using the Inductor DCR to Sense Current
Figure 2. Current Sensing Methods
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LTC7800
APPLICATIONS INFORMATION
Low Value Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. RSENSE is chosen based on the required
output current.
The current comparator has a maximum threshold
VSENSE(MAX) determined by the ILIM setting. The current
comparator threshold voltage sets the peak of the inductor current, yielding a maximum average output current,
IMAX, equal to the peak value less half the peak-to-peak
ripple current, ΔIL. To calculate the sense resistor value,
use the equation:
RSENSE =
VSENSE(MAX)
IMAX +
ΔIL
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for the Maximum Current Sense Threshold
(VSENSE(MAX)) in the Electrical Characteristics table (30mV,
50mV or 75mV, depending on the state of the ILIM pin).
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to
the internal compensation required to meet stability criterion for buck regulators operating at greater than 50%
duty factor. A curve is provided in the Typical Performance
Characteristics section to estimate this reduction in peak
inductor current depending upon the operating duty factor.
Inductor DCR Sensing
For applications requiring the highest possible efficiency
at high load currents, the LTC7800 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC resistance of the copper wire, which can be
less than 1mΩ for today’s low value, high current inductors.
In a high current application requiring such an inductor,
power loss through a sense resistor would cost several
points of efficiency compared to inductor DCR sensing.
If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor
value is:
RSENSE(EQUIV) =
VSENSE(MAX)
IMAX +
ΔIL
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for the Maximum Current Sense Threshold
(VSENSE(MAX)) in the Electrical Characteristics table (30mV,
50mV or 75mV, depending on the state of the ILIM pin).
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
0.4%/°C. A conservative value for TL(MAX) is 100°C.
To scale the maximum inductor DCR to the desired resistor
value (RD), use the divider ratio:
RD =
RSENSE(EQUIV)
DCRMAX at TL(MAX)
C1 is usually selected to be in the range of 0.1μF to 0.47μF.
This forces R1 || R2 to around 2k, reducing error that might
have been caused by the SENSE+ pin’s ±1μA current.
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15
LTC7800
APPLICATIONS INFORMATION
The equivalent resistance R1 || R2 is scaled to the temperature inductance and maximum DCR:
R1|| R2 =
L
(DCR at 20°C) • C1
ΔIL =
The resistor values are:
R1=
R1|| R2
R1• RD
; R2 =
RD
1– RD
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
PLOSS R1=
The inductor value has a direct effect on ripple current. The
inductor ripple current, ΔIL, decreases with higher inductance or higher frequency and increases with higher VIN:
( VIN(MAX) – VOUT ) • VOUT
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
to the extra switching losses incurred through R1. However,
DCR sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
Inductor Value Calculation
The operating frequency and inductor selection are interrelated n that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET switching and gate charge losses. In addition to
this basic trade-off, the effect of inductor value on ripple
current and low current operation must also be considered.
 V 
1
VOUT 1– OUT 
( f) (L)  VIN 
Accepting larger values of ΔIL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ΔIL = 0.3(IMAX). The maximum
ΔIL occurs at the maximum input voltage.
The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ΔIL) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on inductance
value selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
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LTC7800
APPLICATIONS INFORMATION
Power MOSFET and Schottky Diode (Optional)
Selection
Two external power MOSFETs must be selected for the
LTC7800 controller: one N-channel MOSFET for the top
(main) switch, and one N-channel MOSFET for the bottom
(synchronous) switch.
The peak-to-peak drive levels are set by the INTVCC voltage.
This voltage is typically 5.1V during start-up (see EXTVCC
Pin Connection). Consequently, logic-level threshold
MOSFETs must be used in most applications. Pay close
attention to the BVDSS specification for the MOSFETs as well.
Selection criteria for the power MOSFETs include the onresistance, RDS(ON), Miller capacitance, CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge
curve usually provided on the MOSFET manufacturers’
datasheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle =
VOUT
VIN
Synchronous Switch Duty Cycle =
VIN − VOUT
VIN
The MOSFET power dissipations at maximum output
current are given by:
PMAIN =
PSYNC =
VOUT
2
(IMAX ) (1+ δ)RDS(ON) +
VIN

2 I
( VIN )  MAX  (RDR ) (CMILLER ) •
 2 


1
1
+

( f)
 VINTVCC – VPLATEAU VPLATEAU 
VIN – VOUT
2
(IMAX ) (1+ δ)RDS(ON)
VIN
where δ is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTHMIN is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1+ δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
A Schottky diode can be inserted in parallel with the bottom MOSFET to conduct during the dead-time between
the conduction of the two power MOSFETs. This prevents
the body diode of the bottom MOSFET from turning on,
storing charge during the dead-time and requiring a
reverse recovery period that could cost as much as 3%
in efficiency at high VIN. A 1A to 3A Schottky is generally
a good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
CIN and COUT Selection
The selection of CIN is usually based off the worst-case RMS
input current. The highest (VOUT)(IOUT) product needs to
be used in the formula shown in Equation 1 to determine
the maximum RMS capacitor current requirement.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
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LTC7800
APPLICATIONS INFORMATION
maximum RMS current must be used. The maximum RMS
capacitor current is given by:
CIN Required IRMS ≈
1/2
IMAX 
VOUT ) ( VIN – VOUT ) (1)
(

VIN
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC7800, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
A small (0.1μF to 1μF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC7800, is also
suggested. A small (≤10Ω) resistor placed between CIN
(C1) and the VIN pin provides further isolation.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (ΔVOUT) is approximated by:


1
ΔVOUT ≈ ΔIL ESR +

8 • f • COUT 

where f is the operating frequency, COUT is the output
capacitance and ΔIL is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage.
To improve the frequency response, a feedforward capacitor, CFF, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
VOUT
RB
LTC7800
RA
7800 F03
Figure 3. Setting Output Voltage
RUN Pin
The LTC7800 is enabled using the RUN pin. It has a rising
threshold of 1.21V with 50mV of hysteresis. Pulling the
RUN pin below 1.16V shuts down the main control loop.
Pulling it below 0.7V disables the controller and most
internal circuits, including the INTVCC LDOs. In this state,
the LTC7800 draws only 14μA of quiescent current.
Releasing the RUN pin allows a small 7μA internal current
to pull up the pin to enable the controller. The RUN pin may
be externally pulled up or driven directly by logic. When
driving the RUN pin with a low impedance source, do not
exceed the absolute maximum rating of 8V. The RUN pin
has an internal 11V voltage clamp that allows the RUN pin
to be connected through a resistor to a higher voltage (for
example, VIN), so long as the maximum current into the
RUN pin does not exceed 100μA.
The RUN pin can be implemented as a UVLO by connecting it to the output of an external resistor divider network
off VIN, as shown in Figure 4.
VIN
LTC7800
Setting Output Voltage
The LTC7800 output voltage is set by an external feedback
resistor divider carefully placed across the output, as shown
in Figure 3. The regulated output voltage is determined by:
CFF
VFB
RB
RUN
RA
7800 F04
Figure 4. Using the RUN Pin as a UVLO
 R 
VOUT = 0.8V 1+ B 
 RA 
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The rising and falling UVLO thresholds are calculated using
the RUN pin threshold:
 R 
VUVLO(RISING) = 1.21V 1+ B  – 7µA • RB
 RA 
 R 
VUVLO(FALLING) = 1.16V 1+ B  – 7µA • RB
 RA 
The resistor values should be carefully chosen such that
the absolute maximum ratings of the RUN pin do not get
violated over the entire VIN voltage range.
pin of the slave supply (VOUT), as shown in Figure 7.
During start-up VOUT will track VX according to the ratio
set by the resistor divider:
VX
RA
R
+ RTRACKB
=
• TRACKA
VOUT RTRACKA
RA + RB
For coincident tracking (VOUT = VX during start-up):
RA = RTRACKA
RB = RTRACKB
VX(MASTER)
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground, as shown in Figure 5.
An internal 10μA current source charges the capacitor,
providing a linear ramping voltage at the TRACK/SS pin.
The LTC7800 will regulate the VFB pin (and hence VOUT)
according to the voltage on the TRACK/SS pin, allowing
VOUT to rise smoothly from 0V to its final regulated value.
The total soft-start time will be approximately:
t SS = CSS •
VOUT(SLAVE)
7800 F06a
TIME
(6a) Coincident Tracking
VX(MASTER)
OUTPUT VOLTAGE
The start-up of VOUT is controlled by the voltage on the
TRACK/SS pin. When the voltage on the TRACK/SS pin
is less than the internal 0.8V reference, the LTC7800
regulates the VFB pin voltage to the voltage on the TRACK/
SS pin instead of 0.8V. The TRACK/SS pin can be used to
program an external soft-start function or to allow VOUT
to track another supply during start-up.
OUTPUT VOLTAGE
Tracking and Soft-Start (TRACK/SS Pin)
VOUT(SLAVE)
0.8V
10µA
7800 F06b
TIME
(6b) Ratiometric Tracking
LTC7800
TRACK/SS
Figure 6. Two Different Modes of Output Voltage Tracking
CSS
Vx VOUT
SGND
RB
7800 F05
Figure 5. Using the TRACK/SS Pin to Program Soft-Start
Alternatively, the TRACK/SS pin can be used to track
another supply during start-up, as shown qualitatively in
Figures 6a and 6b. To do this, a resistor divider should be
connected from the master supply (VX) to the TRACK/SS
LTC7800
VFB
RA
RTRACKB
TRACK/SS
RTRACKA
7800 F07
Figure 7. Using the TRACK/SS Pin for Tracking
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LTC7800
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INTVCC Regulators
The LTC7800 features two separate internal P-channel
low dropout linear regulators (LDO) that supply power
at the INTVCC pin from either the VIN supply pin or the
EXTVCC pin depending on the connection of the EXTVCC
pin. INTVCC powers the gate drivers and much of the
LTC7800’s internal circuitry. The VIN LDO and the EXTVCC
LDO regulate INTVCC to 5.1V. Each of these can supply a
peak current of at least 50mA and must be bypassed to
ground with a minimum of 2.2μF ceramic capacitor. No
matter what type of bulk capacitor is used, an additional
1μF ceramic capacitor placed directly adjacent to the INTVCC
and PGND pins is highly recommended. Good bypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers.
High input voltage applications in which large MOSFETs are
being driven at high frequencies may cause the maximum
junction temperature rating for the LTC7800 to be exceeded.
The INTVCC current, which is dominated by the gate charge
current, may be supplied by either the VIN LDO or the
EXTVCC LDO. When the voltage on the EXTVCC pin is less
than 4.7V, the VIN LDO is enabled. Power dissipation for the
IC in this case is highest and is equal to VIN • IINTVCC. The
gate charge current is dependent on operating frequency
as discussed in the Efficiency Considerations section. The
junction temperature can be estimated by using the equations given in Note 3 of the Electrical Characteristics. For
example, the LTC7800 INTVCC current is limited to less
than 26mA from a 40V supply when not using the EXTVCC
supply at a 70°C ambient temperature:
TJ = 70°C + (26mA)(40V)(52°C/W) = 124°C
To prevent the maximum junction temperature from being exceeded, the input supply current must be checked
while operating in forced continuous mode (PLLIN/MODE
= INTVCC) at maximum VIN.
When the voltage applied to EXTVCC rises above 4.7V, the
VIN LDO is turned off and the EXTVCC LDO is enabled. The
EXTVCC LDO remains on as long as the voltage applied to
EXTVCC remains above 4.5V. The EXTVCC LDO attempts
to regulate the INTVCC voltage to 5.1V, so while EXTVCC
is less than 5.1V, the LDO is in dropout and the INTVCC
voltage is approximately equal to EXTVCC. When EXTVCC
is greater than 5.1V, up to an absolute maximum of 14V,
INTVCC is regulated to 5.1V.
Using the EXTVCC LDO allows the MOSFET driver and
control power to be derived from the LTC7800’s switching output (4.7V ≤ VOUT ≤ 14V) during normal operation
and from the VIN LDO when the output is out of regulation
(e.g., start-up, short-circuit). If more current is required
through the EXTVCC LDO than is specified, an external
Schottky diode can be added between the EXTVCC and
INTVCC pins. In this case, do not apply more than 6V to
the EXTVCC pin and make sure that EXTVCC ≤ VIN.
Significant efficiency and thermal gains can be realized
by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
For 5V to 14V regulator outputs, this means connecting
the EXTVCC pin directly to VOUT. Tying the EXTVCC pin to
an 8.5V supply reduces the junction temperature in the
previous example from 125°C to:
TJ = 70°C + (26mA)(8.5V)(52°C/W) = 81°C
However, for 3.3V and other low voltage outputs, additional
circuitry is required to derive INTVCC power from the output.
The following list summarizes the three possible connections for EXTVCC:
1. EXTVCC Grounded. This will cause INTVCC to be powered
from the internal 5.1V regulator resulting in an efficiency
penalty of up to 10% at high input voltages.
2. EXTVCC Connected Directly to VOUT. This is the normal
connection for a 5V to 14V regulator and provides the
highest efficiency.
3. EXTVCC Connected to an External Supply. If an external
supply is available in the 5V to 14V range, it may be
used to power EXTVCC providing it is compatible with
the MOSFET gate drive requirements. Ensure that
EXTVCC < VIN.
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Topside MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor, CB, connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFET. Capacitor CB in the Functional Diagram is charged
though external diode DB from INTVCC when the SW pin
is low. When the topside MOSFET is to be turned on, the
driver places the CB voltage across the gate-source of
the MOSFET. This enhances the top MOSFET switch and
turns it on. The switch node voltage, SW, rises to VIN and
the BOOST pin follows. With the topside MOSFET on, the
boost voltage is above the input supply: VBOOST = VIN +
VINTVCC. The value of the boost capacitor, CB, needs to be
100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external
Schottky diode must be greater than VIN(MAX).
Fault Conditions: Current Limit and Current Foldback
The LTC7800 includes current foldback to help limit
load current when the output is shorted to ground. If
the output voltage falls below 70% of its nominal output
level, then the maximum sense voltage is progressively
lowered from 100% to 45% of its maximum selected
value. Under short-circuit conditions with very low duty
cycles, the LTC7800 will begin cycle skipping in order to
limit the short-circuit current. In this situation the bottom
MOSFET will be dissipating most of the power but less
than in normal operation. The short-circuit ripple current
is determined by the minimum on-time, tON(MIN), of the
LTC7800 (≈45ns), the input voltage and inductor value:
V 
ΔIL(SC) = tON(MIN)  IN 
 L 
The resulting average short-circuit current is:
1
ISC = 45% • ILIM(MAX) – ΔIL(SC)
2
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes huge
currents to flow, that blow the fuse to protect against a
shorted top MOSFET if the short occurs while the controller is operating.
A comparator monitors the output for overvoltage conditions. The comparator detects faults greater than 10%
above the nominal output voltage. When this condition
is sensed, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously for
as long as the overvoltage condition persists; if VOUT returns
to a safe level, normal operation automatically resumes.
A shorted top MOSFET will result in a high current condition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
Frequency Synchronization and Selection
The LTC7800 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter,
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the top MOSFET to be locked to the rising edge
of an external clock signal applied to the PLLIN/MODE pin.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the VCO input. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down the
VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP, holds the voltage at the VCO input.
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Note that the LTC7800 can only be synchronized to an
external clock whose frequency is within range of the
LTC7800’s internal VCO, which is guaranteed to be between
320kHz and 2.25MHz. Typically, the external clock (on the
PLLIN/MODE pin) input high threshold is 1.6V, while the
input low threshold is 1.1V. The LTC7800 is guaranteed
to synchronize to an external clock that swings up to at
least 2.5V and down to 0.5V or less.
Rapid phase locking can be achieved by using the FREQ pin
to set a free-running frequency near the desired synchronization frequency. The VCO’s input voltage is prebiased
at a frequency corresponding to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
the frequency slightly to achieve phase lock and synchronization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
2000
FREQ PIN
PLLIN/MODE PIN
FREQUENCY
0V
DC Voltage
0.94MHz
INTVCC
DC Voltage
1.44MHz
Resistor
DC Voltage
320kHz to 2.25MHz
Any of the Above
External Clock
Phase Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC7800 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
VOUT
VIN ( f )
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
1750
FREQUENCY (kHz)
Table 2
tON(MIN) <
2250
1500
1250
1000
750
500
250
Table 2 summarizes the different states in which the FREQ
pin can be used.
25
35
45
55
65
75
85
95
105
FREQ PIN RESISTOR (kΩ)
7800 F08
Figure 8. Relationship Between Oscillator Frequency and
Resistor Value at the FREQ Pin
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied to
INTVCC or programmed through an external resistor. Tying
FREQ to SGND selects 0.94MHz while tying FREQ to INTVCC
selects 1.44MHz. Placing a resistor between FREQ and
SGND allows the frequency to be programmed between
320kHz and 2.25MHz, as shown in Figure 8.
The minimum on-time for the LTC7800 is approximately
45ns. However, as the peak sense voltage decreases the
minimum on-time gradually increases up to about 70ns.
This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle
drops below the minimum on-time limit in this situation,
a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
7800f
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It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC7800 circuits: 1) IC VIN current, 2) INTVCC regulator current, 3) I2R losses, 4) topside MOSFET
transition losses.
1. The VIN current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver and control currents. VIN current typically results
in a small (<0.1%) loss.
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
from INTVCC to ground. The resulting dQ/dt is a current
out of INTVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG
= f(QT + QB), where QT and QB are the gate charges of
the topside and bottom side MOSFETs.
Supplying INTVCC from an output-derived source power
through EXTVCC will scale the VIN current required for
the driver and control circuits by a factor of (Duty Cycle)/
(Efficiency). For example, in a 20V to 5V application,
10mA of INTVCC current results in approximately 2.5mA
of VIN current. This reduces the midcurrent loss from
10% or more (if the driver was powered directly from
VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor and input and output capacitor ESR. In continuous
mode the average output current flows through L and
RSENSE, but is chopped between the topside MOSFET
and the synchronous MOSFET. If the two MOSFETs have
approximately the same RDS(ON), then the resistance
of one MOSFET can simply be summed with the resistances of L, RSENSE and ESR to obtain I2R losses. For
example, if each RDS(ON) = 30mΩ, RL = 50mΩ, RSENSE
= 10mΩ and RESR = 40mΩ (sum of both input and
output capacitance losses), then the total resistance
is 130mΩ. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
a 5V output, or a 4% to 20% loss for a 3.3V output.
Efficiency varies as the inverse square of VOUT for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) • VIN2 • IO(MAX) • CRSS • f
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5%
to 10% efficiency degradation in portable systems. It
is very important to include these system level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
CIN has adequate charge storage and very low ESR at
the switching frequency. A 25W supply will typically
require a minimum of 20μF to 40μF of capacitance
having a maximum of 20mΩ to 50mΩ of ESR. Other
losses including body diode conduction losses during
dead-time and inductor core losses generally account
for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
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LTC7800
APPLICATIONS INFORMATION
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ΔILOAD (ESR), where ESR is the effective
series resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot
or ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The availability of the ITH pin not only
allows optimization of control loop behavior, but it also
provides a DC coupled and AC filtered closed-loop response
test point. The DC step, rise time and settling at this test
point truly reflects the closed-loop response. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in Figure 9 circuit will provide
an adequate starting point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
to optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1μs to
10μs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Placing a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal
generator is a practical way to produce a realistic load step
condition. The initial output voltage step resulting from
the step change in output current may not be within the
bandwidth of the feedback loop, so this signal cannot be
used to determine phase margin. This is why it is better
to look at the ITH pin signal which is in the feedback loop
and is the filtered and compensated control loop response.
The gain of the loop will be increased by increasing RC
and the bandwidth of the loop will be increased by de-
creasing CC. If RC is increased by the same factor that
CC is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10μF capacitor would
require a 250μs rise time, limiting the charging current
to about 200mA.
Design Example
As a design example, assume VIN = 12V (nominal),
VIN = 22V (max), VOUT = 3.3V, IMAX = 5A, VSENSE(MAX)
= 75mV and f = 1MHz. The inductance value
is chosen first based on a 30% ripple current
assumption. The highest value of ripple current occurs
at the maximum input voltage. Tie the FREQ pin with a
54.9k resistor to GND, generating approximately 1MHz
operation. The inductor ripple current can be calculated
from the following equation:
ΔIL =

VOUT 
V
1– OUT 
( f) (L)  VIN(NOM) 
A 1.5μH inductor will produce 32% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 5.8A. Increasing the ripple
current will also help ensure that the minimum on-time
of 45ns is not violated. The minimum on-time occurs at
maximum VIN:
tON(MIN) =
VOUT
VIN(MAX) ( f)
=
3.3V
= 150ns
22V (1MHz )
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The equivalent RSENSE resistor value can be calculated by
using the minimum value for the maximum current sense
threshold (64mV):
RSENSE ≤
64mV
≈ 0.01Ω
5.8A
The power dissipation on the topside MOSFET can be
easily estimated. Choosing an Infineon BSZ097N04LSG
MOSFET results in: RDS(ON) = 11.4mΩ, CMILLER = 16pF.
At maximum input voltage with T(estimated) = 50°C:
PSYNC =
3.3V
2
(5A ) 1+ (0.005) (50°C – 25°C)
22V
2 5A
(11.4mΩ) + (22V ) (2.5Ω) (16pF ) •
2

1
1 
 5V – 1.5V + 1.5V (1MHz ) = 94mW
(22V – 3.3V )
22V
= 273mW
2
(5A ) (1.125) (11.4mΩ)
A short-circuit to ground will result in a folded back current of:
ISC =
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC.
Check the following in your layout:
Choosing 1% resistors: RA = 25k and RB = 78.7k yields
an output voltage of 3.32V.
PMAIN =
PC Board Layout Checklist
34mV 1  45ns (22V ) 
– 
 = 3.07A
0.01Ω 2  1.5µH 
with a typical value of RDS(ON) and δ = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
2
PSYNC,SC = (3.07A ) (1.125) (11.4mΩ)
= 121mW
CIN is chosen for an RMS current rating of at least 3A at
temperature. COUT is chosen with an ESR of 0.02Ω for
low output ripple. The output ripple in continuous mode
will be highest at the maximum input voltage. The output
voltage ripple due to ESR is approximately:
1. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CINTVCC must return to the combined COUT (–) terminals. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
2. Does the LTC7800 VFB pin’s resistive divider connect to
the (+) terminal of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
3. Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE+ and SENSE– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
4. Is the INTVCC decoupling capacitor connected close
to the IC, between the INTVCC and the power ground
pins? This capacitor carries the MOSFET drivers’ current peaks. An additional 1μF ceramic capacitor placed
immediately next to the INTVCC and PGND pins can help
improve noise performance substantially.
5. Keep the SW, TG, and BOOST nodes away from sensitive small-signal nodes. All of these nodes have very
large and fast moving signals and therefore should be
kept on the output side of the LTC7800 and occupy
minimum PC trace area.
VORIPPLE = RESR(∆IL) = 0.02Ω(1.60A) = 32mVP-P
7800f
For more information www.linear.com/LTC7800
25
LTC7800
APPLICATIONS INFORMATION
6. Use a modified star ground technique: a low impedance,
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
with tie-ins for the bottom of the INTVCC decoupling
capacitor, the bottom of the voltage feedback resistive
divider and the SGND pin of the IC.
PC Board Layout Debugging
It is helpful to use a DC-50MHz current probe to monitor
the current in the inductor while testing the circuit. Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator and probe the actual
output voltage as well. Check for proper performance over
the operating voltage and current range expected in the
application. The frequency of operation should be maintained over the input voltage range down to dropout and
until the output load drops below the low current operation threshold—typically 25% of the maximum designed
current level in Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required.
Reduce VIN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the un-
dervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
7800f
26
For more information www.linear.com/LTC7800
LTC7800
APPLICATIONS INFORMATION
LTC7800
TRACK/SS
ILIM
VIN
VIN
PGND
CIN
GND
+
FREQ
PLLIN/MODE
EXTVCC
SGND
INTVCC
1µF
CERAMIC
CINTVCC
COUT
+
SGND
BG
RUN
SENSE–
C1*
M1
BOOST
SENSE+
M2
SW
R1*
VFB
TG
ITH
PGOOD
L1
ROUT
PGOOD
D1*
RSENSE
VOUT
VPULL-UP
7800 F09
*R1, C1 AND D1 ARE OPTIONAL
Figure 9. Recommended Printed Circuit Layout Diagram
SW
VIN
RIN
CIN
D1
L1
RSENSE
VOUT
COUT
RL1
7800 F10
BOLD LINES INDICATE HIGH SWITCHING
CURRENT. KEEP LINES TO A MINIMUM LENGTH.
Figure 10. Branch Current Waveforms
7800f
For more information www.linear.com/LTC7800
27
LTC7800
APPLICATIONS INFORMATION
VIN
4V TO
28V*
C INA
2.2µF
×3
C INB
56µF
LTC7800
VIN
PLLIN/MODE
INTVCC
RUN
100k
INTVCC
100k
820pF
ILIM
D1
PGOOD
TG
EXTVCC
BOOST
FREQ
2.49k
82pF
2.2µF
PGND
MTOP
0.1µF
L1
0.33µH
SW
ITH
SENSE+
TRACK/SS
SENSE–
SGND
VOUT
3.3V
C OUT 10A*
33µF
×2
MBOT
BG
0.1µF
R SENSE
4mΩ
R FLT
10Ω
10pF
357k
1nF
VFB
SGND
115k
MTOP: INFINEON BSZ0506NS
MBOT: INFINEON BSZ0503NSI
L1: COILCRAFT XAL5030-331ME
CINA: TDK C4532X7R2A225M
CINB : SUN ELECT 63HVH56M
COUT : TDK C4532X7R1C336M
D1: CENTRAL SEMI CMDSH-4E
7800 F11
*OUTPUT CURRENT CAPABILITY AT HIGH INPUT VOLTAGES
MAY BE LIMITED BY THE THERMAL CHARACTERISTICS OF
THE OVERALL SYSTEM AND PRINTED CIRCUIT BOARD DESIGN.
Figure 11. High Efficiency 3.3V 2.1MHz Step-Down Regulator
VIN
5.5V TO
38V*
C INA
2.2µF
×3
C INB
56µF
VIN
LTC7800
PLLIN/MODE
RUN
INTVCC
100k
820pF
100k
VOUT
82pF
PGOOD
EXTVCC
ITH
0.1µF
TRACK/SS
SGND
SGND
2.2µF
PGND
ILIM
FREQ
4.99k
INTVCC
D1
TG
0.1µF
MTOP
L1
0.3µH
BOOST
SW
SENSE–
VOUT
5.0V
C OUT 10A*
47µF
×2
MBOT
BG
SENSE+
R SENSE
4mΩ
R FLT
20Ω
1nF
604k
10pF
VFB
115k
MTOP/MBOT: INFINEON BSZ097N04LS
L1: WURTH 744355230
CINA: TDK C4532X7R2A225M
*OUTPUT CURRENT CAPABILITY AT HIGH INPUT VOLTAGES
CINB : SUN ELECT 63HVH56M
MAY BE LIMITED BY THE THERMAL CHARACTERISTICS OF
COUT : TDK C4532X5R1A476M
D1: CENTRAL SEMI CMDSH-4E
THE OVERALL SYSTEM AND PRINTED CIRCUIT BOARD DESIGN.
7800 F12
Figure 12. High Efficiency 5V 2.1MHz Step-Down Regulator
7800f
28
For more information www.linear.com/LTC7800
LTC7800
APPLICATIONS INFORMATION
VIN
4V TO
58V
C INA
2.2µF
×3
C INB
56µF
LTC7800
VIN
PLLIN/MODE
RUN
100k
INTV CC
2.2nF
ILIM
D1
PGOOD
FREQ
3.92k
100pF
2.2µF
PGND
EXTV CC
25.5k
INTV CC
TG
MTOP
0.1µF
L1
1.3µH
BOOST
SW
ITH
TRACK/SS
SGND
COUT
100µF
×2
MBOT
BG
0.1µF
R SENSE
3mΩ
VOUT
3.3V
15A
R FLT
100Ω
SENSE+
280k
1nF
SENSE–
10pF
VFB
SGND
90.9k
MTOP, MBOT: INFINEON BSC100N06LS3
L1: WURTH 7443551130
CINA: TDK C4532X7R2A225M
CINB : SUN ELECT 63HVH56M
C OUT : TDK C4532X5R0J107M
D1: CENTRAL SEMI CMDD6001
7800 F13
Figure 13. High Efficiency 3.3V 320kHz Step-Down Regulator
C IN
4.7µF
×4
LTC7800
VIN
INTVCC
RUN
PLLIN/MODE
100k
INTVCC
VOUT
30.1k
4.7nF
ILIM
22pF
PGOOD
100
95
D1
D3
10Ω
0.1µF
90
EXTVCC
L1
1.2µH
BOOST
VOUT
5V
COUT 20A*
47µF
×3
SW
ITH
MBOT
BG
0.1µF
TRACK/SS
SENSE+
SGND
SENSE–
SGND
MTOP: EPC EPC2001
MBOT: EPC EPC2021
L1: COILCRAFT SER2010 122ML
CIN : TDK C4532X7R2A475M
COUT : TDK C4532X5R1A476M
D1: STM BAT41K
D2: DIODES DFLS2100
D3: BOURNS CD0603-Z5V1
Efficiency vs Output Current
MTOP
TG
FREQ
3.32k
2.2µF
PGND
D2
R FLT
6.49k
0.1µF
EFFICIENCY (%)
VIN
30V TO
60V*
85
80
75
70
65
60
VIN = 48V
VOUT = 5V
FCM MODE OPERATION
55
50
107k
0
2
1nF
4
6 8 10 12 14 16 18 20
OUTPUT CURRENT (A)
7800 F14b
VFB
20k
*OUTPUT CURRENT CAPABILITY AT HIGH INPUT VOLTAGES
MAY BE LIMITED BY THE THERMAL CHARACTERISTICS OF
THE OVERALL SYSTEM AND PRINTED CIRCUIT BOARD DESIGN.
7800 F14a
Figure 14. High Efficiency 5V 450kHz Step-Down Regulator Using GaN FETs
7800f
For more information www.linear.com/LTC7800
29
LTC7800
APPLICATIONS INFORMATION
VIN
18V TO
60V*
+
C INA
4.7µF
×2
C INB
47µF
LTC7800
VIN
INTV CC
RUN
PLLIN/MODE
100k
INTV CC
2.2µF
PGND
ILIM
Efficiency vs Output Current
MTOP
100
TG
PGOOD
D1
EXTV CC
10Ω
95
D3
3.3nF
13.7k
100pF
FREQ
0.1µF
L1
6.8µH
BOOST
SW
ITH
4mΩ
MBOT
BG
0.1µF
TRACK/SS
SENSE+
SGND
SENSE–
VFB
SGND
COUTA
22µF
×3
D2
R FLT
10Ω
1nF
+
VOUT
12V
10A*
COUTB
220µF
EFFICIENCY (%)
90
VOUT
25.5k
85
80
75
70
65
60
VIN = 48V
VOUT = 12V
FCM MODE OPERATION
55
499k
50
0
35.7k
MTOP/MBOT: GaN SYSTEMS GS61008P
L1: COILCRAFT XAL1510-682
CINA : TDK C3225X7S2A475M200AB
CINB : SUNCON 80CE47LX
COUTA : TDK C3225X7R1C226M
COUTB: KEMET T521X227M016ATE035
D1: CENTRAL SEMI CMDD6001
D2: DIODES DFLS1100
D3: BOURNS CD0603-Z5V1
1
2
3 4 5 6 7 8
OUTPUT CURRENT (A)
9
10
7800 F14b
7800 F15a
*OUTPUT CURRENT CAPABILITY AT HIGH INPUT VOLTAGES
MAY BE LIMITED BY THE THERMAL CHARACTERISTICS OF
THE OVERALL SYSTEM AND PRINTED CIRCUIT BOARD DESIGN.
Figure 15. High Efficiency 12V 320kHz Step-Down Regulator Using GaN FETs
7800f
30
For more information www.linear.com/LTC7800
LTC7800
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC7800#packaging/ for the most recent package drawings.
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
0.70 ±0.05
3.50 ±0.05
2.10 ±0.05
1.50 REF
2.65 ±0.05
1.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
2.50 REF
3.10 ±0.05
4.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 ±0.10
0.75 ±0.05
1.50 REF
19
R = 0.05 TYP
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
20
0.40 ±0.10
1
PIN 1
TOP MARK
(NOTE 6)
4.00 ±0.10
2
2.65 ±0.10
2.50 REF
1.65 ±0.10
(UDC20) QFN 1106 REV Ø
0.200 REF
0.00 – 0.05
R = 0.115
TYP
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
7800f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC7800
31
LTC7800
TYPICAL APPLICATION
VIN
12.5V TO
28V*
C INA
2.2µF
×3
C INB
56µF
VIN
LTC7800
PLLIN/MODE
RUN
INTV CC
100k
0.47nF
100k
VOUT
D1
PGOOD
TG
EXTV CC
BOOST
TRACK/SS
SGND
SGND
0.1µF
MTOP
L1
0.47µH
SW
ITH
0.1µF
2.2µF
PGND
ILIM
FREQ
2k
82pF
INTV CC
BG
SENSE+
SENSE–
R SENSE
4mΩ
VOUT
12V
COUT 10A*
10µF
×2
MBOT
R FLT
20Ω
2nF
487k
10pF
VFB
34.8k
MTOP: INFINEON BSZ0506NS
MBOT: INFINEON BSZ0506NS
L1: WURTH 744314047
CINA: TDK C4532X7R2A225M
CINB : SUN ELECT 63HVH56M
COUT : TDK C4532X7R1E106M
D1: CENTRAL SEMI CMDSH-4E
7800 F16
*OUTPUT CURRENT CAPABILITY AT HIGH INPUT VOLTAGES
MAY BE LIMITED BY THE THERMAL CHARACTERISTICS OF
THE OVERALL SYSTEM AND PRINTED CIRCUIT BOARD DESIGN.
Figure 16. High Efficiency 12V 2.1MHz Step-Down Regulator
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3891
60V, Low IQ, Synchronous Step-Down DC/DC Controller
with 99% Duty Cycle
4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V, IQ = 50µA PLL Fixed Frequency
50kHz to 900kHz, Pin Compatible with LTC7800
LTC3895
150V Low IQ, Synchronous Step-Down DC/DC Controller
4V ≤ VIN ≤ 140V, 150VP-P, 0.8V ≤ VOUT ≤ 24V, IQ = 50µA PLL Fixed
Frequency 50kHz to 900kHz
LTC3810
100V Synchronous Step-Down DC/DC Controller
Constant On-time Valley Current Mode 6.2V ≤ VIN ≤ 100V, 0.8V ≤
VOUT ≤ 0.93VIN, SSOP-28
LTC3864
60V, Low IQ, High Voltage DC/DC Controller with 100%
Duty Cycle
Fixed Frequency 50kHz to 850kHz, 3.5V≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤
VIN , IQ = 40µA, MSOP-12E, 3mm × 4mm DFN-12
LT3840
60V, Low IQ, Synchronous Step-Down Controller with
Integrated Buck-Boost Bias Voltage Regulator
2.5V≤ VIN ≤ 60V, 1.23V ≤ VOUT ≤ 60V, IQ = 75µA Synchronizable
Fixed Frequency 100kHz to 600kHz
LTC3892/LTC3892-1
60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 0.99VIN, PLL Fixed Frequency 50kHz
Controller with 99% Duty Cycle
to 900kHz, Adjustable 5V to 10V Gate Drive, IQ = 29µA
LTC3890/LTC3890-1/ 60V, Low IQ, Dual 2-Phase Synchronous Step-Down DC/DC PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT
≤ 24V, IQ = 50µA
LTC3890-2/LTC3890-3 Controller with 99% Duty Cycle
LTC7813
60V Low IQ, Synchronous Boost + Buck DC/DC Controller
4.5V (Down to 2.2V After Start-up) ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 60V,
Adjustable 5V to 10V Gate Drive, IQ = 33µA
LTC7801
150V Low IQ, Synchronous Step-Down DC/DC Controller
4V ≤ VIN ≤ 140V, 150V Abs Max, 0.8V ≤ VOUT ≤ 60V, IQ = 40µA, PLL
Fixed Frequency 320kHz to 2.25MHz
LTC7103
105V, 2.3A Low EMI Synchronous Step-Down Regulator
4.4V ≤ VIN ≤ 105V, 1V ≤ VOUT ≤ VIN, IQ = 2µA, Fixed Frequency
200kHz to 2MHz, 5mm × 6mm QFN
7800f
32
LT 0517 • PRINTED IN USA
For more information www.linear.com/LTC7800
www.linear.com/LTC7800
 LINEAR TECHNOLOGY CORPORATION 2017
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