Maxim MAX1160ACPI 10-bit, 20msps, ttl-output adc Datasheet

19-1189; Rev 0; 3/97
KIT
ATION
EVALU
E
L
B
AVAILA
10-Bit, 20Msps, TTL-Output ADC
Inputs and outputs are TTL compatible. An overrange
output is provided to indicate overflow conditions. Output
data format is straight binary. Power dissipation is low at
only 1W with +5V and -5.2V power-supply voltages. The
MAX1160 also accepts wide ±2V input voltages.
The MAX1160 is available in 28-pin DIP and SO packages in the commercial temperature range.
________________________Applications
Medical Imaging
Professional Video
Radar Receivers
Instrumentation
Digital Communications
________________Functional Diagram
ANALOG
INPUT
____________________________Features
♦ Monolithic 20Msps Converter
♦ On-Chip Track/Hold
♦ Bipolar, ±2V Analog Input
♦ 60dB SNR at 1MHz Input
♦ 5pF Input Capacitance
♦ TTL Outputs
______________Ordering Information
PART
TEMP. RANGE
MAX1160ACPI
0°C to +70°C
28 Wide Plastic DIP
PIN-PACKAGE
MAX1160BCPI
MAX1160ACWI
MAX1160BCWI
0°C to +70°C
0°C to +70°C
0°C to +70°C
28 Wide Plastic DIP
28 SO
28 SO
__________________Pin Configuration
TOP VIEW
TOP VIEW
4
COARSE
ADC
T/H
AMPLIFIER
BANK
SUCCESSIVE INTERPOLATION
STAGE i
SUCCESSIVE INTERPOLATION
STAGE i + 1
...
.
DECODING NETWORK
ANALOG
PRESCALER
10
DIGITAL
OUTPUT
DGND
1
28 DVCC
D0
2
27 VEE
D1
3
26 AGND
D2
4
25 VCC
D3
5
D4
6
23 VSB
D5
7
22 VRM
D6
8
21 VIN
D7
9
20 VST
D8
10
19 VFT
24 VFB
D9
11
18 VCC
D10
12
17 AGND
DGND
13
16 VEE
14
15 CLK
DVCC
SUCCESSIVE INTERPOLATION
STAGE N
MAX1160
DIP/SO
________________________________________________________________ Maxim Integrated Products
For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
1
MAX1160
_______________General Description
The MAX1160 10-bit, monolithic analog-to-digital converter (ADC) is capable of 20Msps minimum word
rates. An on-board track/hold ensures excellent dynamic performance without the need for external components. A 5pF input capacitance minimizes drive
requirement problems.
MAX1160
10-Bit, 20Msps, TTL-Output ADC
ABSOLUTE MAXIMUM RATINGS
VCC ..........................................................................................................6V
VEE .........................................................................................................-6V
Analog Input ......................................................VFB ≤ VIN ≤ VFT
VFT, VFB ...........................................................................3V, -3V
Reference-Ladder Current..................................................12mA
CLK Input...............................................................................VCC
Digital Outputs.....................................................30mA to -30mA
Continuous Power Dissipation (TA = +70°C)
Plastic DIP ......................................................................1.14W
SO .......................................................................................1W
Operating Temperature Range...............................0°C to +70°C
Junction Temperature .....................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec). ............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5.0V, VEE = -5.2V, DVCC = +5.0V, VIN = ±2.0V, VSB = -2.0V, VST = +2.0V, fCLK = 20MHz, 50% clock duty cycle,
TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
CONDITIONS
TEST
LEVEL
Resolution
MIN
MAX1160A
TYP
MAX
10
MIN
MAX1160B
TYP
MAX
10
UNITS
Bits
DC ACCURACY (± full scale, 250kHz sample rate, TA = +25°C)
Integral Nonlinearity
I
±1.0
±1.5
LSB
Differential Nonlinearity
I
±0.5
±0.75
LSB
Guaranteed
Guaranteed
No Missing Codes
ANALOG INPUT
Input Voltage Range
VI
±2.0
Input Bias Current
VIN = 0V
VI
30
Input Bias Current
TA = -55°C to +125°C
VI
Input Resistance
Input Resistance
TA = -55°C to +125°C
Input Capacitance
±2.0
60
30
75
V
60
75
µA
µA
VI
100
300
100
300
kΩ
VI
75
300
75
300
kΩ
V
5
5
pF
V
120
120
MHz
Positive Full-Scale Error
V
±2.0
±2.0
LSB
Negative Full-Scale Error
V
±2.0
±2.0
LSB
800
Ω
0.8
Ω/°C
Input Bandwidth
3dB small signal
REFERENCE INPUT
Reference-Ladder
Resistance
VI
Reference-Ladder
Tempco
V
500
800
500
0.8
TIMING CHARACTERISTICS
Maximum Conversion Rate
VI
Overvoltage Recovery Time
V
Pipeline Delay (Latency)
VI
20
20
20
MHz
20
1
14
1
Clock
Cycle
18
ns
Output Delay
TA = +25°C
V
14
Aperture Delay Time
TA = +25°C
V
1
1
ns
Aperture Jitter Time
TA = +25°C
V
5
5
ps-RMS
Acquisition Time
TA = +25°C
V
20
20
ns
2
18
ns
_______________________________________________________________________________________
10-Bit, 20Msps, TTL-Output ADC
(VCC = +5.0V, VEE = -5.2V, DVCC = +5.0V, VIN = ±2.0V, VSB = -2.0V, VST = +2.0V, fCLK = 20MHz, 50% clock duty cycle,
TA = TMIN to TMAX, unless otherwise noted.)
MAX1160A
MIN TYP MAX
MAX1160B
MIN TYP MAX
fIN = 1MHz
9.2
8.7
fIN = 3.58MHz
8.8
8.3
PARAMETER
CONDITIONS
TEST
LEVEL
UNITS
DYNAMIC PERFORMANCE
Effective Number of Bits
(ENOB)
fIN = 10MHz
7.5
TA = +25°C
fIN = 1MHz
Signal-to-Noise Ratio
(without harmonics)
(SNR)
TA = 0°C to +70°C,
TA = -25°C to +85°C
TA = +25°C
fIN = 3.58MHz
TA = 0°C to +70°C,
TA = -25°C to +85°C
TA = +25°C
fIN = 10MHz
TA = 0°C to +70°C,
TA = -25°C to +85°C
TA = +25°C
fIN = 1MHz
Total Harmonic Distortion
(THD)
TA = 0°C to +70°C,
TA = -25°C to +85°C
TA = +25°C
fIN = 3.58MHz
TA = 0°C to +70°C,
TA = -25°C to +85°C
TA = +25°C
fIN = 10MHz
TA = 0°C to +70°C,
TA = -25°C to +85°C
TA = +25°C
fIN = 1MHz
Signal-to-Noise and
Distortion Ratio
(SINAD)
TA = 0°C to +70°C,
TA = -25°C to +85°C
TA = +25°C
fIN = 3.58MHz
TA = 0°C to +70°C,
TA = -25°C to +85°C
TA = +25°C
Bits
7.0
I
57
60
54
57
IV
55
58
52
55
I
56
58
53
55
IV
54
56
51
53
I
50
53
47
49
IV
47
50
44
46
I
57
60
54
57
IV
54
57
51
54
I
56
58
53
55
IV
53
55
50
52
I
46
48
43
45
IV
45
47
42
44
I
55
57
52
54
IV
52
I
54
IV
51
dB
dB
49
55
51
52
dB
48
I
44
fIN = 10MHz
TA = 0°C to +70°C,
TA = -25°C to +85°C
47
41
44
IV
43
Spurious-Free
Dynamic Range (SFDR)
fIN = 1MHz
TA = +25°C
V
67
67
dB
Differential Phase
fIN = 3.58MHz
and 4.35MHz
TA = +25°C
V
0.2
0.2
Degrees
Differential Gain
fIN = 3.58MHz
and 4.35MHz
TA = +25°C
V
0.5
0.7
%
40
_______________________________________________________________________________________
3
MAX1160
ELECTRICAL CHARACTERISTICS (continued)
MAX1160
10-Bit, 20Msps, TTL-Output ADC
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5.0V, VEE = -5.2V, DVCC = +5.0V, VIN = ±2.0V, VSB = -2.0V, VST = +2.0V, fCLK = 20MHz, 50% clock duty cycle,
TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
TEST
LEVEL
CONDITIONS
MAX1160A
MIN TYP MAX
MAX1160B
MIN TYP MAX
2.4
2.4
UNITS
DIGITAL INPUTS
Logic 1 Voltage
V
Logic 0 Voltage
V
4.5
0.8
4.0
V
0.8
V
Maximum Input
Current Low
TA = +25°C
IV
0
5
20
0
5
20
µA
Maximum Input
Current High
TA = +25°C
IV
0
5
20
0
5
20
µA
Pulse Width Low (CLK)
IV
20
Pulse Width High (CLK)
IV
20
Logic 1 Voltage
IV
2.4
Logic 0 Voltage
IV
20
300
ns
20
300
ns
DIGITAL OUTPUTS
2.4
V
0.6
0.6
V
POWER-SUPPLY REQUIREMENTS
Voltages
Currents
VCC
IV
4.75
DVCC
IV
4.75
-VEE
IV
-4.95 -5.2
ICC
VI
118
145
118
145
DICC
VI
40
55
40
55
-IEE
VI
40
57
40
57
VI
1.0
1.3
1.0
1.3
V
1.0
Power Dissipation
Power-Supply Rejection
VCC = 5V ±0.25V, VEE = -5.2V ±0.25V
TEST LEVEL CODES
All electrical characteristics are subject to the following conditions:
All parameters having min/max specifications are guaranteed. The
Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any
blank section in the data column indicates that the specification is
not tested at the specified condition.
Unless otherwise noted, all tests are pulsed; therefore,
Tj = TC = TA.
TEST LEVEL
I
II
III
IV
V
VI
5.0
5.25
4.75
5.25
4.75
5.25
5.0
5.25
-5.45 -4.95 -5.2
-5.45
1.0
V
mA
W
LSB
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA = +25°C, and sample tested at the specified
temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characterization data.
Parameter is a typical value for information purposes only.
100% production tested at TA = +25°C. Parameter is guaranteed over specified
temperature range.
______________________________________________________________Pin Description
4
PIN
NAME
1, 13
DGND
2
D0
3–10
D1–D8
11
PIN
NAME
Digital Ground
FUNCTION
17, 26
AGND
TTL Output (LSB)
FUNCTION
Analog Ground
18, 25
VCC
+5V Supply (analog)
TTL Outputs
19
VFT
Force for Top of Reference Ladder
D9
TTL Output (MSB)
20
VST
Sense for Top of Reference Ladder
TTL Output Overrange
21
VIN
Analog Input
+5V Supply (digital)
22
VRM
Middle of Voltage Reference Ladder
12
D10
14, 28
DVCC
15
CLK
Clock
23
VSB
Sense for Bottom of Reference Ladder
16, 27
VEE
-5.2V Supply (analog)
24
VFB
Force for Bottom of Reference Ladder
_______________________________________________________________________________________
10-Bit, 20Msps, TTL-Output ADC
TOTAL HARMONIC DISTORTION vs.
INPUT FREQUENCY
70
fS = 20Msps
70
50
60
50
40
40
40
30
30
30
20
10
20
1
100
10
100
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
SNR, THD, SINAD vs.
SAMPLE RATE
SNR, THD, SINAD vs.
TEMPERATURE
fIN = 1MHz
70
SNR, THD, SINAD (dB)
SNR, THD
60
50
SNR
SINAD
40
100
SPECTRAL RESPONSE
SNR
0
fS = 20Msps
fIN = 1MHz
60
-30
THD
THD
55
SINAD
50
-60
-90
45
30
10
INPUT FREQUENCY (MHz)
65
MAX1160-04
80
1
MAX1160-06
1
AMPLITUDE (dB)
20
SNR, THD, SINAD (dB)
SINAD (dB)
THD (dB)
SNR (dB)
50
fS = 20Msps
70
60
60
80
MAX1160-05
fS = 20Msps
MAX1160-02
80
MAX1160-01
80
SIGNAL-TO-NOISE AND DISTORTION
vs. INPUT FREQUENCY
MAX1160-03
SIGNAL-TO-NOISE RATIO vs.
INPUT FREQUENCY
fS = 20Msps
fIN = 1MHz
40
20
1
10
100
-120
-25
0
SAMPLE RATE (Msps)
25
50
TEMPERATURE (°C)
______________Detailed Description
The MAX1160 requires few external components to
achieve the stated operation and performance. Figure
2 shows the typical interface requirements when using
the MAX1160 in normal circuit operation. The following
section provides a description of the pin functions, and
outlines critical performance criteria to consider for
achieving the optimal device performance.
75
0
1
2
3
4
5
6
7
8
9 10
INPUT FREQUENCY (MHz)
Power Supplies and Grounding
The MAX1160 requires -5.2V and +5V analog supply
voltages. The +5V supply is common to analog VCC
and digital DVCC. A ferrite bead in series with each
supply line reduces the transient noise injected into the
analog V CC . Connect these beads as close to the
device as possible. The connection between the beads
and the MAX1160 should not be shared with any other
device. Bypass each power-supply pin as close to the
device as possible. Use 0.1µF for VEE and VCC, and
0.01µF for DVCC (chip capacitors are recommended).
_______________________________________________________________________________________
5
MAX1160
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MAX1160
10-Bit, 20Msps, TTL-Output ADC
N+1
N
tpwH
CLK
N+2
tpwL
td
CLK
td
OUTPUT
N-2
DATA
N-1
DATA VALID
N
DATA VALID
N+1
Figure 1a. Timing Diagram
OUTPUT
DATA
DATA VALID
Figure 1b. Single-Event Clock
Table 1. Timing Parameters
PARAMETER
td
DESCRIPTION
CLK to Data Valid Propagation Delay
tpwH
CLK High Pulse Width
20
tpwL
CLK Low Pulse Width
20
The MAX1160 has two grounds: AGND and DGND.
These internal grounds are isolated on the device. Use
ground planes for optimum device performance. Use
DGND for the DVCC return path (typically 40mA) and
for the return path for all digital output logic interfaces.
Separate AGND and DGND from each other, connecting them together only through a ferrite bead at the
device.
Connect a Schottky or hot carrier diode between AGND
and VEE. The use of separate power supplies between
VCC and DVCC is not recommended due to potential
power-supply-sequencing latchup conditions. For optimum performance, use the recommended circuit
shown in Figure 2.
Voltage Reference
The MAX1160 requires the use of two voltage references: VFT and VFB. VFT is the force for the top of the
voltage-reference ladder (typically +2.5V); VFB (typically -2.5V) is the force for the bottom of the voltage-reference ladder. Both voltages are applied across an 800Ω
internal reference-ladder resistance. The +2.5V voltage
source for reference VFT must be current limited to
20mA (max) if a different driving circuit is used in place
of the recommended reference circuit shown in Figures
2 and 3. In addition, there are three reference-ladder
taps (VST, VRM, and VSB). VST is the sense for the top
of the reference ladder (+2V), VRM is the midpoint of
the ladder (typically 0V), and VSB is the sense for the
6
MIN
TYP
MAX
UNITS
14
18
ns
300
ns
ns
bottom of the reference ladder (-2V). The voltages at
VST and VSB are the device’s true full-scale input voltages when VFT and VFB are driven to the recommended voltages (typically +2.5V and -2.5V, respectively).
These points should be used to monitor the device’s
actual full-scale input range. When not being used, a
decoupling capacitor of 0.01µF (chip capacitor preferred) connected to AGND from each tap is recommended to minimize high-frequency noise injection.
Figure 2 shows an example of a recommended reference-driver circuit. IC1 is a MAX6225, a 2.5V reference
with an accuracy of 0.2%. The 10kΩ potentiometer R1
supports a minimum adjustable range of 0.6%. Use an
OP07 or equivalent device for IC2. R2 and R3 must be
matched to within 0.1% with good TC tracking to maintain 0.3LSB matching between VFT and VFB. If 0.1%
matching is not met, then R4 can be used to adjust the
VFB voltage to the desired level. Adjust VFT and VFB
such that VST and VSB are exactly +2V and -2V,
respectively.
The analog input range scales proportionally with respect
to the reference voltage if a different input range is
required. The maximum scaling factor for device operation is ±20% of the recommended reference voltages of
VFT and VFB. However, because the device is laser
trimmed to optimize performance with ±2.5V references,
its accuracy degrades if operated beyond a ±2% range.
_______________________________________________________________________________________
10-Bit, 20Msps, TTL-Output ADC
The analog input’s drive requirements are minimal
when compared to conventional flash converters. This
is due to the MAX1160’s extremely low (5pF) input
capacitance and very high (300kΩ) input resistance.
For example, for an input signal of ±2Vp-p with a
10MHz input frequency, the peak output current
required for the driving circuit is only 628µA.
Clock Input
The MAX1160 is driven from a single-ended TTL input
(CLK). The CLK pulse width (t pwH ) must be kept
between 20ns and 300ns to ensure proper operation of
the internal track/hold amplifier (Figure 1a). When operating the MAX1160 at sampling rates above 3Msps, it is
recommended that the clock input duty cycle be kept at
Analog Input
VIN is the analog input. The full-scale input range will
be 80% of the reference voltage, or ±2V with VFB =
-2.5V and VFT = +2.5V.
CLK
MAX1160
R5
100Ω
VIN
IC2
R4
10k
0.01µF
4
C3
0.01µF
R3
30k
2R
0.01µF
2R
D3
D2
SUCCESSIVE
INTERPOLATION
STAGE N
R
VFB
C5
0.01µF
VEE
= AGND
C6
0.1µF
C8
0.1µF
C10
0.01µF
C7
0.1µF
C9
0.1µF
C11
0.01µF
FB
= DGND
NOTES:
1) D1 = SCHOTTKY OR HOT CARRIER DIODE
2) FB = FERRITE BEAD, FAIR RITE #2743001111
TO BE MOUNTED AS CLOSELY TO THE DEVICE
AS POSSIBLE. THE FERRITE BEAD TO ADC
CONNECTION SHOULD NOT BE SHARED WITH
ANY OTHER DEVICE.
3) C1–C11 = CHIP CAPACITOR (RECOMMENDED)
MOUNTED AS CLOSE TO DEVICE'S PIN AS
POSSIBLE.
4) USE OF A SEPARATE SUPPLY FOR VCC AND DVCC
IS NOT RECOMMENDED.
5) R5 PROVIDES CURRENT LIMITING TO 45mA.
DIGITAL
OUTPUTS
D5
D4
D0 (LSB)
7 6
-2.5V
D8
D7
D6
D1
2R
VSB
1µF
SUCCESSIVE
INTERPOLATION
STAGE 1
VRM
C4
0.01µF
OP07
8
+5V
-5.2V
ANALOG
PRESCALER
2R
DGND
1
2
VST
DVCC
3
R2
30k
C1
0.01µF
DVCC
5
1µF
FB
FB
VTRIM
VCC
MAX6225
4 GND
D10 (OVERRANGE)
D9 (MSB)
R
VCC
R1
10k
C2
0.01µF
AGND
1µF
VFT
2.5V
AGND
6
IC1 VOUT
2 VIN
4
COARSE
ADC
DECODING NETWORK
±2.5V MAX
VEE
VIN
(±2V)
+5V
DGND
CLK
(TTL)
D1
10µF
-5.2V
10µF
+5V
Figure 2. Typical Operating Circuit
_______________________________________________________________________________________
7
MAX1160
The following errors are defined:
+FS error = top of ladder offset voltage
= ∆(+FS - VST + 1LSB)
-FS error = bottom of ladder offset voltage
= ∆(-FS - VSB - 1LSB)
where the +FS (full-scale) input voltage is defined as the
output transition between 11 1111 1110 and 11 1111 1111,
and the -FS input voltage is defined as the output transition between 00 0000 0000 and 00 0000 0001 (Table 2).
Table 2. Output Data Information
ANALOG
INPUT
OVERRANGE
D10
OUTPUT CODE
D9–D0
> +2V + 1/2LSB
1
11 1111 1111
+2V - 1LSB
0V
-2V + 1LSB
< 2V
0
0
0
0
11
ØØ
00
00
1111
ØØØØ
0000
0000
111Ø
ØØØØ
000Ø
0000
(Ø indicates the flickering bit between logic 0 and 1.)
50% to optimize performance, but performance will not
be degraded if kept within the 40% to 60% range. The
analog input signal is latched on the rising edge of CLK.
The clock input must be driven from fast TTL logic
(VIH ≤ 4.5V, tRISE < 6ns). In the event the clock is driven from a high current source, use a 100Ω resistor
(R5) in series to limit current to approximately 45mA.
Digital Outputs
The format of the output data (D0–D9) is straight binary
(Table 2). The outputs are latched on the rising edge of
CLK with a typical propagation delay of 14ns. There is
a one-clock-cycle latency between CLK and the valid
output data (Figure 1a).
The digital outputs’ rise and fall times are not symmetrical. Typical propagation delay is 14ns for the rise time
and 6ns for the fall time (Figure 4). The nonsymmetrical rise and fall times create approximately 8ns of invalid data.
Overrange Output
The overrange output (D10) is an indication that the
analog input signal has exceeded the positive full-scale
input voltage by 1LSB. When this condition occurs,
D10 will switch to logic 1. All other data outputs
(D0–D9) will remain at logic 1 as long as D10 remains
at logic 1. This feature makes it possible to include the
MAX1160 in higher-resolution systems.
Evaluation Board
The MAX1160 EV kit is available to help designers
demonstrate the MAX1160’s full performance. This
board includes a reference circuit, a clock-driver circuit, output data latches, and an on-board reconstruction of the digital data. A separate data sheet
describing the operation of this board is also available.
Contact the factory for price and availability.
VCC
N+1
N
CLK IN 2.4V
6ns
ANALOG PRESCALER
MAX1160
10-Bit, 20Msps, TTL-Output ADC
VIN
tRISE
6ns
typ
VFT
3.5V
DATA 2.4V
OUT
(ACTUAL) 0.8V
0.5V
(N - 2)
INVALID
DATA
(N - 1)
INVALID
DATA
N
tpd1
14ns typ
DATA OUT
(EQUIVALENT)
VEE
(N - 2)
INVALID
DATA
(N - 1)
INVALID
DATA
N
Figure 4. Digital Output Characteristics
Figure 3. Analog Equivalent Input Circuit
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.