Fairchild FAN1577A Dual synchronous dc/dc controller Datasheet

FAN1577A
Dual Synchronous DC/DC Controller
Features
Description
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Integrates Two Sets of MOSFET Drivers
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Maximum Input Supply Voltage: 15V
The FAN1577A is a high-efficiency, voltage-mode, dualchannel, synchronous DC/DC PWM controller for two
independent outputs. The two channels are operated
out of phase. The internal reference voltage is trimmed
to 0.7V±1.0%. It is connected to the error amplifier’s
positive terminal for voltage feedback regulation.
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Two Soft-Start / EN Function Pins
Two Independent PWM Controllers
Constant Frequency Operation: Free-running FixedFrequency Oscillator Programmable: 61kHz to 340kHz
Programmable Output as Low as 0.7V
Internal Error Amplifier Reference Voltage:
0.7V ±1.0%
Programmable Over-Current Protection (OCP)
30V HIGH Voltage Pin for Bootstrap Voltage
Output Over-Voltage Protection (OVP)
20-Pin SOP
A soft-start circuit ensures the output voltage can be
gradually and smoothly increased from zero to its final
regulated value. The soft-start pin can also be used for
chip-enable function. When two soft-start pins are
grounded, the chip is disabled, and the total operation
current can be reduced to under 0.7mA.
The fixed-frequency is programmable from 61kHz to
340kHz. The Over-Current Protection (OCP) level can
be programmed by an external current-sense resistor. It
has two integrated sets of internal MOSFET drivers.
FAN1577A is available in a 20-pin small-outline
package (SOP).
Applications
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CPU and GPU Vcore Power Supply
Power Supply Requiring Two Independent Outputs
Ordering Information
Part Number
Operating Temperature Range
FAN1577AMX
-40°C to +85°C
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
Package
20-Lead, Small-Outline Package
Packing Method
Tape & Reel
www.fairchildsemi.com
FAN1577A — Dual Synchronous DC/DC Controller
October 2010
FAN1577A — Dual Synchronous DC/DC Controller
Application Diagram
Figure 1.
Typical Application
Internal Block Diagram
Figure 2.
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
Functional Block Diagram
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2
20
TAHAA
FAN1577AM
F: Fairchild Logo
T: Assembly Plant Code
A: Year Code
H: Week Code
AA: Die Run Code
1
Figure 3.
Marking Diagram
Figure 4.
Marking Legend
Figure 5.
Pin Assignments
(Top View)
Pin Definitions
Name
Pin #
Type
Description
RT
1
Frequency
Select
An external resistor connecting this pin to GND can program the switching
frequency. The switching frequency is 61kHz when RT is open and becomes
340kHz when RT is shorted to ground.
IN1
2
Feedback
Inverting input of the error amplifier normally connected to the switching power
supply output through a resistor divider.
COMP1
3
Compensation
SS1/ENB
4
Soft-Start /
Enable
A 35/15µA internal current source charging an external capacitor for soft-start.
Pull down this pin and pin 17 to disable the chip.
CLP1
5
Over-Current
Protection
Over-current protection for high-side MOSFET. Connect a resistor from this pin
to the high-side supply voltage to program the OCP level.
BST1
6
Boost Supply
Supply for high-side driver. Connect to the internal bootstrap circuit.
DH1
7
CLN1
8
Output of the error amplifier and input to the PWM comparator. It is used for
feedback-loop compensation.
High-Side Drive Channel 1, high-side MOSFET gate driver pin.
Switch Node
Switch-node connection to the inductor. For channel 1, high-side driver’s
reference ground.
DL1
9
Low-Side Drive Low-side MOSFET gate driver pin.
PGND
10
Driver Ground
Driver circuit reference. Connect to low-side MOSFET GND.
VCC
11
Power Supply
Supply voltage input.
DL2
12
CLN2
13
Low-Side Drive Low-side MOSFET gate driver pin.
Switch Node
Switch-node connection to the inductor. For channel 2, high-side driver’s
reference ground.
DH2
14
BST2
15
High-Side Drive Channel 2 high-side MOSFET gate driver pin.
Boost Supply
Supply for high-side driver. Connect to the internal bootstrap circuit.
CLP2
16
Over-Current
Protection
Over-current protection for the high-side MOSFET. Connect a resistor from this
pin to the high-side supply voltage to program the OCP level.
SS2/ENB
17
Soft-Start /
Enable
A 35/15µA internal current source charging an external capacitor for soft-start.
Pull down this pin and pin 4 to disable the chip.
COMP2
18
Compensation
Output of the error amplifier and input to the PWM comparator. It is used for
feedback-loop compensation.
IN2
19
Feedback
Inverting input of the error amplifier. It is normally connected to the switching
power supply output through a resistor divider.
GND
20
Analog Ground The reference of internal control circuits.
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
www.fairchildsemi.com
3
FAN1577A — Dual Synchronous DC/DC Controller
Pin Configuration & Marking Information
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are
given with respect to the network ground terminal. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device.
Symbol
Max.
Unit
Supply Voltage, VCC to GND
16
V
BST1(or 2) –
CLN1(or 2)
BST1(2) to CLN1(2)
16
V
CLN1(or 2) –
GND
CLN1(2) to GND for 100ns Transient
18
V
BST1(or 2) –
GND
BST1(2) to GND for 100ns Transient
30
V
16
V
VCC+0.3
V
±1
V
VCC
Parameter
Min.
-4
DH1(or 2) –
CLN1(or 2)
CLN1(or 2),
DL1(or 2)
PGND
-0.3
PGND to GND
ΘJA
Thermal Resistance, Junction-Air
70
°C/W
TJ
Operating Junction Temperature
-40
+125
°C
TSTG
Storage Temperature Range
-65
+150
°C
ESD
Electrostatic Discharge
Protection Level
Human Body Model (HBM)
2
Charged Device Model (CDM)
1
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
VCC
Supply Voltage
TA
Operating Ambient Temperature
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
Min.
-40
Max.
Unit
+15
V
+85
°C
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4
FAN1577A — Dual Synchronous DC/DC Controller
Absolute Maximum Ratings
VCC=12V and TA= -40°C to +85°C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VCC UVLO
VCC_ON
Turn-On Threshold
VCC Ramp-Up
9.5
10.0
10.5
V
VCC_HYS
UVLO Hysteresis
VCC Ramp-Down
1.5
2.0
2.5
V
RRT=OPEN
55
61
67
RRT=GND
308
340
372
20kΩ＜RRT
-10
Oscillator
FOSC
Oscillator Frequency
FOSC,RT
Total Accuracy
DON_MAX
Maximum Duty Cycle
KHZ
10
%
%
85
90
95
0.693
0.700
0.707
Error Amplifier
VREF
△VREF
Internal Reference Voltage
VREF Temperature Coefficient
VCC=8V, VCC=15V, TA=25°C
(1)
o
TA=-40~85 C
V
O
0.03
MV/ C
AVOL
Open-Loop Voltage Gain
77
DB
BW
Unity Gain Bandwidth
3.5
MHZ
ISOURCE
Output Source Current
IN1=IN2=0.6V
60
80
100
µA
Output Sink Current
IN1=IN2=0.8V
250
400
600
µA
VH RAMP_PEAK Peak of VRAMP
Gate Output=DON_MAX
2.45
2.80
3.15
V
V RAMP_VALLEY Valley of VRAMP
No Gate Output
1.05
1.20
1.35
V
VCLP＜VCLN, VSS_Transition＞VSS
28
35
42
µA
VCLP＜VCLN, VSS_Transition＜VSS
13
16
19
µA
1.40
1.42
1.44
V
ISINK
Two-Stage Soft-Start
ISRC_1
ISRC_2
st
1 Soft-Start Charge Current
2
nd
Soft-Start Charge Current
st
VSS_TRANSITION Soft-Start Transition Point
ISINK
ISOURCE_1 Transit to
nd
ISOURCE_2
See Figure 6
Soft-Start Discharge Current
VCLP＞VCLN
OC Sink Current
VCC=12V
50
µA
Protections
IOCSET
TOT
90
120
150
µA
Over-Temperature
150
°C
TOT_HYS
Over-Temperature Hysteresis
20
°C
VOVP
Over-Voltage Protection of IN
VOVP/VIN
118
122
IDH
High-Side Current Source
VBST - VCLN=12V, VDH VCLN=6V
1.0
1.8
RDH
High-Side Sink Resistor
VBST - VCLN=12V
IDL
Low-Side Current Source
VCC=12V, VDL =6V
RDL
Low-Side Sink Resistor
VCC=12V
TDT
Dead Time
126
%
Output
(2)
2.8
1.0
A
3.8
1.8
Ω
A
2.8
3.8
Ω
VCC=12V, DH & DL=1000pF
50
70
90
NS
3.3
4.3
5.3
MA
0.7
1.0
MA
Total Operating Current
ICC_OP
Operating Supply Current
VCC=12V, No Load
ICC_SBY
Standby Current (Disabled)
SS1/ENB=SS2/ENB=0V
Notes:
1. Not tested in production; 30 pieces sampled.
2. When VDL falls less than 2V relative to VDH rising to 2V.
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
www.fairchildsemi.com
5
FAN1577A — Dual Synchronous DC/DC Controller
Electrical Characteristics
FAN1577A — Dual Synchronous DC/DC Controller
Timing Diagram
Figure 6.
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
Timing Chart of Two-Stage Soft-Start
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6
Figure 7.
Figure 9.
fSW vs. Temperature
Figure 8.
Operating Current vs. Temperature
Figure 10. Internal Reference Voltage (VREF)
vs. Temperature
Figure 11. First Soft-Start Charge
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
VCC_ON vs. Temperature
Figure 12. Over-Current Sink Current (IOCSET)
vs. Temperature
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FAN1577A — Dual Synchronous DC/DC Controller
Typical Characteristics
Unless otherwise noted, values are for VCC=12V, TA=+25°C, CSS1/ENB=150nF, and CSS2/ENB=168nF.
Figure 13. Power On at 0.3A Load
Figure 14. Power On at 3.6A Load
Figure 15. Power On at 9A Load
Figure 16. Power On at 18A Load
Figure 17. Power Off with 0.3A Load
Figure 18. Power Off with 18A Load
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
www.fairchildsemi.com
8
FAN1577A — Dual Synchronous DC/DC Controller
Typical Performance Characteristics
Unless otherwise noted, values are for VCC=12V, TA=+25°C, CSS1/ENB=150nF, and CSS2/ENB=168nF.
Figure 19. Phase Shift at 0.3A Load
Figure 20. Phase Shift at 18A Load
Figure 21. Dead Time at 0.3A Load (Rising Edge)
Figure 22. Dead Time at 0.3A Load (Falling Edge)
Figure 23. Dead Time at 18A Load (Rising Edge)
Figure 24. Dead Time at 18A Load (Falling Edge)
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
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FAN1577A — Dual Synchronous DC/DC Controller
Typical Performance Characteristics (Continued)
Unless otherwise noted, values are for VCC=12V, TA=+25°C, CSS1/ENB=150nF, and CSS2/ENB=168nF.
Figure 25. Load Transient Response (Step-Up)
20kΩ/22nF in Compensation Loop
Figure 27.
Over-Current Protection (OCP)
Figure 29.
Over-Voltage Protection (OVP)
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
Figure 26. Load Transient Response (Step-Down)
20kΩ/22nF in Compensation Loop
Figure 28.
Over-Current Protection (“Hiccup” Mode)
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FAN1577A — Dual Synchronous DC/DC Controller
Typical Performance Characteristics (Continued)
The FAN1577A is a dual-channel voltage-mode PWM
controller with two sets of synchronous MOSFET driving
circuits. The two channels are running 180-degrees out
of phase. FAN1577A has the following advantages.
Error Amplifier
The IN1 and IN2 pins are connected to the
corresponding internal error amplifier’s inverting input
and the outputs of the error amplifiers are connected to
the corresponding COMP1 and COMP2 pins. The
COMP1 and COMP2 pins are available for control-loop
compensation externally. Non-inverting inputs are
internally tied to a fixed 0.7V ±1.5% reference voltage.
Soft Start
An internal startup current (35/15µA) flows out of SS/EN
pin to charge an external capacitor. During the startup
sequence, FAN1577A isn’t enabled until the SS/ENB
pin is higher than 1.2V. From 1.2V to (1.2 + 1.6 x DON /
DON_MAX) V, the PWM duty cycle gradually increases
following the SS/ENB pin voltage to bring output rising.
After (1.2 + 1.6 x DON / DON_MAX) V, the soft-start period
ends and the SS/ENB pin continually rises to 4.8V.
When input power is abnormal, the external capacitor
on the SS pin is shorted to ground to disable the chip.
5
C SS1 × (1.4V - 1.2V) = 35uA × t 1 ; C SS1 × (1.2V + 1.6 × 12 - 1.4V) = 15 μA × t 2
0.9
; t 1 + t 2 = t SS1
3.3
C SS2 × (1.4V - 1.2V) = 35 μA × t 1 ; C SS2 × (1.2V + 1.6 × 12 - 1.4V) = 15 μ A × t 2
0.9
; t 1 + t 2 = t SS2
C SS1 × 1.2V = 35 μ A × t 3 ;
Oscillator Operation
The FAN1577A has a programmable-frequency
oscillator. The oscillator is running at 61kHz when the
RT pin is floating. The oscillator frequency can be
adjusted from 61kHz up to 340kHz by an external
resistor RRT between the RT pin and ground. The
oscillator generates a sawtooth wave that has a 90%
rising duty. The sawtooth wave voltage threshold is
from 1.2V to 2.8V. The frequency of oscillator can be
programmed according to the following equation:
(1)
C SS2 × 0.3V
C × (1.2V - 0.3V)
+ SS2
= t4
15 μ A
35 μ A
Setting the Output Voltage
; t 4 - t 3 = t time -shift
The FAN1577A can be set from 0.7V to 90% of VIN. The
output voltages are independently adjusted by voltage
dividers (R1 and Rf in Figure 31) connected to INx. The
external resister dividers can be calculated by:
Over-Current Protection (OCP)
Over-current protection is implemented by sensing the
voltage drop across the drain and source of the external
high-side MOSFET. Over-current protection is triggered
when the voltage drop on external high-side MOSFET
RDS(ON) is greater than the programmable current-limit
voltage threshold. 120µA flowing through an external
resistor between input voltage and the CLP pin sets the
threshold of current limit voltage. When over-current
condition is TRUE, the system is protected against the
cycle-by-cycle current limit. A counter counts a series of
over-current peak values for eight cycles; the soft-start
capacitor is discharged by a 50µA current until the
voltage on SS pin reaches 1.2V. During the discharge
period, the high-side driver is turned off and the lowside driver is turned on. Once the voltage on the
SS/ENB pin is under 1.2V, the normal soft-start
sequence is initiated and the 35/15µA current charges
the soft-start capacitor again.
IL(OCP)= [(RSENSE x IOCSET + VOFFSET) / RDS(ON) (VIN - VOUT) x VOUT / (fOSC x LOUT x VIN x 2) ]
(3)
fOSC, RT(kHz) = 61kHz + 8522 / RRT(kΩ)
VOUT = 0.7 × (1+R1/Rf)
(4)
Output Driver
The high-side gate drivers need an external
bootstrapping circuit to provide the required boost
voltage. The highest gate driver’s output (15V is the
allowed) on the high-side and low-side MOSFETs
forces external MOSFETs to have the lowest RDS(ON),
which results in higher efficiency.
Over-Temperature Protection (OTP)
The device is over-temperature protected. When chip
temperature is over 150°C, the chip enters 3-state
°
(high-side driver is turned off). The hysteresis is 20 C.
(2)
where VOFFSET ( ≒ 10mV) is the offset voltage
contributed by the internal OCP comparator.
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
www.fairchildsemi.com
11
FAN1577A — Dual Synchronous DC/DC Controller
Functional Description
FAN1577A is a voltage-mode controller. The control
loop is a single-voltage feedback path, including an
error amplifier and PWM comparator, as shown in
Figure 30. To achieve fast transient response and
accurate output regulation, an adequate compensator
design is necessary. A stable control loop has a 0dB
gain crossing with -20dB/decade slope and a phase
margin greater than 45°.
2. Compensation Frequency Equations
The compensation network consists of the error
amplifier and the impedance networks ZC and Zf as
Figure 31 shows.
Figure 31.
Figure 30.
Compensation Loop
Closed Loop
fP1 = 0
1. Modulator Frequency Equations
The modulator transfer function is the small-signal
transfer function of VOUT/VE/A. This transfer function is
dominated by a DC gain and the output filter (LO and
CO) with a double-pole frequency at fLC and a zero at
fESR. The DC gain of the modulator is the input voltage
(VIN) divided by the peak-to-peak oscillator voltage
ΔVRAMP(=1.6V). The first step is to calculate the complex
conjugate poles contributed by the LC output filter. The
output LC filter introduces a double pole, -40dB /
decade gain slope above its corner resonant frequency
and a total phase lag of 180 degrees. The resonant
frequency of the LC filter expressed as:
fP(LC) =
1
2π × L O × C O
fZ1 =
1
2π × R 2 × C 2
fP2 =
1
2π × R 2 × (C1 // C2 )
(7)
Compensation gain uses external impedance networks
ZC and Zf to provide a stable high-bandwidth loop.
High crossover frequency is desirable for fast transient
response, but often jeopardizes system stability. To
cancel one of the LC filter poles, place the zero before
the LC filter resonant frequency. Place the zero at 75%
of the LC filter resonant frequency. Crossover frequency
should be higher than the ESR zero, but less than 1/5
of the switching frequency. The second pole should be
placed at half the switching frequency.
(5)
The next step of compensation design is to calculate
the ESR zero contributed by the ESR associated with
the output capacitance. Note that this requires that the
output capacitor have enough ESR to satisfy stability
requirements. The ESR zero of the output capacitor is
expressed as:
fZ(ESR ) =
1
2π × CO × ESR
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
(6)
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12
FAN1577A — Dual Synchronous DC/DC Controller
Type II Compensation Design (for Output Capacitors with High ESR)
Layout is important in high-frequency switching converter
design. If designed improperly, PCB can radiate
excessive noise and contribute to converter instability.
Place the PWM power-stage components first. Mount
all the power components and connections in the top
layer with wide copper areas. The MOSFETs of buck,
inductor, and output capacitor should be as close to
each other as possible to reduce the radiation of EMI
due to the high-frequency current loop. If the output
capacitors are placed in parallel to reduce the ESR of
capacitor, equal sharing ripple current should be
considered. Place the input capacitor near the drain of
the high-side MOSFET. In multi-layer PCB, use one
layer as power ground and have a separate control
signal ground as the reference for all signals. To avoid
the signal ground being affected by noise and to
achieve the best load regulation, it should be connected
to the ground terminal of output.
ƒ
Place the bootstrap capacitor near the BSTx and
CLNx pins.
ƒ
The resistor on the RT pin should be near this pin
and the GND return should be short and kept away
from the noisy MOSFET GND (which is shorted
together with IC PGND pin to GND plane).
ƒ
Place the compensation components close to the
INx and COMPx pins.
ƒ
The feedback resistors for both regulators should
be located as close as possible to the relevant
INx pin with vias tied straight to the ground plane
as required.
ƒ
Minimize the length of the connections between the
input capacitors, CIN, and the power switchers
(MOSFETs) by placing them nearby.
ƒ
Position both the ceramic and bulk input capacitors
as close to the upper MOSFET drain as possible
and make the GND returns short (from the source
of lower MOSFET to GND of VIN capacitor.
ƒ
Position the output inductor and output capacitors
between the upper MOSFET, lower MOSFET, and
the load.
ƒ
AGND should be on the clearer plane and kept
away from the noisy MOSFET GND.
ƒ
PGND should be short, together with MOSFET
GND, then through a via to the GND plane.
Follow the below guidelines for best performance:
ƒ
Keep power traces wide and short to minimize
losses and ringing.
ƒ
The small-signal wiring traces from the DLx and
DHx pins to the MOSFET gates should be kept
short and wide enough to easily handle the several
amps of drive current.
ƒ
The critical, small-signal components include any
bypass capacitors (SMD-type of capacitors applied
at VCC and SSx/ENB pins), feedback components
(resistor divider), and compensation components
(between INx and COMPx pins). Position those
components close to their pins with a local, clear,
GND connection or directly to the ground plane.
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
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13
FAN1577A — Dual Synchronous DC/DC Controller
Layout Considerations
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
PIN ONE
INDICATOR
0.51
0.35
1.27
0.25
M
10
0.65
1.27
C B A
LAND PATTERN RECOMMENDATION
2.65 MAX
SEE DETAIL A
0.33
0.20
C
0.75
0.25
0.10 C
0.30
0.10
X 45°
SEATING PLANE
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) CONFORMS TO ASME Y14.5M-1994
GAGE PLANE
(R0.10)
0.25
8°
0°
1.27
0.40
SEATING PLANE
(1.40)
DETAIL A
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
SCALE: 2:1
Figure 32.
20-Lead Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
www.fairchildsemi.com
14
FAN1577A — Dual Synchronous DC/DC Controller
Physical Dimensions
FAN1577A — Dual Synchronous DC/DC Controller
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
www.fairchildsemi.com
15