ON MMSF5P02HD P-channel power mosfet Datasheet

MMSF5P02HD
Preferred Device
Power MOSFET
5 Amps, 20 Volts
P−Channel SO−8
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding high
energy in the avalanche and commutation modes and the drain−to−source
diode has a very low reverse recovery time. MiniMOSt devices are
designed for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dc−dc converters,
and power management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be used
for low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery
Life
• Logic Level Gate Drive − Can Be Driven by Logic ICs
• Miniature SO−8 Surface Mount Package − Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, With Soft Recovery
• IDSS Specified at Elevated Temperature
• Avalanche Energy Specified
• Mounting Information for SO−8 Package Provided
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5 AMPERES
20 VOLTS
RDS(on) = 30 mW
P−Channel
D
G
S
MARKING
DIAGRAM
SO−8
CASE 751
STYLE 13
8
S5P02H
LYWW
1
L
Y
WW
= Location Code
= Year
= Work Week
PIN ASSIGNMENT
N−C
1
8
Drain
Source
2
7
Drain
Source
3
6
Drain
Gate
4
5
Drain
Top View
ORDERING INFORMATION
Device
Package
MMSF5P02HDR2
SO−8
Shipping
2500 Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 4
1
Publication Order Number:
MMSF5P02HD/D
MMSF5P02HD
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1)
Rating
Symbol
Max
Unit
Drain−to−Source Voltage
VDSS
20
V
Drain−to−Gate Voltage (RGS = 1.0 MΩ)
VDGR
20
V
Gate−to−Source Voltage − Continuous
VGS
± 8.0
V
Thermal Resistance − Junction to Ambient
Total Power Dissipation @ TA = 25°C
Linear Derating Factor
Drain Current − Continuous @ TA = 25°C
Continuous @ TA = 70°C
Pulsed Drain Current (Note 2)
RTHJA
PD
50
2.5
20
8.7
7.0
43.5
°C/W
Watts
mW/°C
A
A
A
Thermal Resistance − Junction to Ambient
Total Power Dissipation @ TA = 25°C
Linear Derating Factor
Drain Current − Continuous @ TA = 25°C
Continuous @ TA = 70°C
Pulsed Drain Current (Note 2)
RTHJA
PD
80
1.56
12.5
6.9
5.5
35
°C/W
Watts
mW/°C
A
A
A
− 55 to
150
°C
1″ SQ.
FR−4 or G−10 PCB
10 seconds
Minimum
FR−4 or G−10 PCB
10 seconds
Operating and Storage Temperature Range
ID
ID
IDM
ID
ID
IDM
TJ, Tstg
Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C
(VDD = 20 Vdc, VGS = 4.5 Vdc, Peak IL = 19 Apk, L = 5.5 mH, RG = 25 W)
1. Negative sign for P−Channel devices omitted for clarity.
2. Repetitive rating; pulse width limited by maximum junction temperature.
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2
EAS
mJ
1000
MMSF5P02HD
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
20
−
−
10
−
−
−
−
−
−
1.0
25
−
−
100
0.7
−
0.9
2.6
1.4
−
−
−
22
35
30
45
10
5.0
−
−
−
−
gFS
14
18
−
Mhos
Ciss
−
1400
1960
pF
Coss
−
925
1300
Crss
−
370
520
td(on)
−
19
40
tr
−
28
55
td(off)
−
130
200
tf
−
90
150
QT
−
27.3
38
Q1
−
3.4
−
Q2
−
12
−
Q3
−
8.0
−
−
−
0.77
0.6
1.2
−
trr
−
95
180
ta
−
35
−
tb
−
60
−
QRR
−
0.151
−
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
(Cpk ≥ 2.0)
(Notes 3 & 5)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 16 Vdc, VGS = 0 Vdc)
(VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = ± 8.0 Vdc, VDS = 0)
IGSS
Vdc
mV/°C
μAdc
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
(Cpk ≥ 2.0)
(VDS = VGS, ID = 0.25 mAdc)
Threshold Temperature Coefficient (Negative)
(Notes 3 & 5)
Static Drain−to−Source On−Resistance
(VGS = 4.5 Vdc, ID = 6.4 Adc)
(VGS = 2.5 Vdc, ID = 5.1 Adc)
(Notes 3 & 5)
(Cpk ≥ 2.0)
On−State Drain Current
(VDS ≤ 5.0 V, VGS = 4.5 V)
(VDS ≤ 5.0 V, VGS = 2.5 V)
VGS(th)
RDS(on)
ID(on)
Forward Transconductance (VDS = 9.0 Vdc, ID = 6.4 Adc)
(Note 3)
Vdc
mV/°C
mΩ
A
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 16 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 6.0 Vdc, ID = 1.0 Adc,
VGS = 4.5 Vdc,
RG = 6.0 Ω) (Note 3)
Fall Time
Gate Charge
See Figure 8
(VDS = 6.0 Vdc, ID = 6.4 Adc,
VGS = 4.5 Vdc) (Note 3)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 3)
Reverse Recovery Time
See Figure 15
(IS = 2.5 Adc, VGS = 0 Vdc) (Note 3)
(IS = 2.5 Adc, VGS = 0 Vdc,
TJ = 125°C)
(IS = 2.5 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/μs) (Note 3)
Reverse Recovery Stored Charge
3. Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperature.
Max limit − Typ
5. Reflects typical values.
Cpk =
3 x SIGMA
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3
VSD
Vdc
ns
μC
MMSF5P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
I D , DRAIN CURRENT (AMPS)
10
12
VGS =
8
2.3 V
2.5 V
VDS ≥ 10 V
TJ = 25°C
ID, DRAIN CURRENT (AMPS)
12
2.7 V
3.1 V
8.0
3.7 V
2.1 V
4.5 V
6.0
4.0
1.9 V
2.0
10
8.0
6.0
100°C
4.0
25°C
TJ = −55°C
2.0
1.7 V
0
0
0.5
1.0
2.0
1.5
1.5
1.0
2.0
2.5
3.0
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
R DS(on), DRAIN−TO−SOURCE RESISTANCE (OHMS)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.06
ID = 6.4 A
TJ = 25°C
0.04
0.02
0
0
2.0
4.0
6.0
8.0
10
0.06
TJ = 25°C
2.5 V
0.04
VGS = 4.5 V
0.02
0
0
2.0
4.0
6.0
10
8.0
VGS, GATE−TO−SOURCE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.0
12
1000
VGS = 0 V
VGS = 4.5 V
ID = 5.1 A
TJ = 125°C
1.5
IDSS , LEAKAGE (nA)
R DS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
R DS(on)(W) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0
1.0
0.5
0
−50
100
100°C
25°C
10
1.0
−25
0
25
50
75
100
125
150
0
4.0
8.0
12
16
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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20
MMSF5P02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
6000
C, CAPACITANCE (pF)
Ciss
4000
TJ = 25°C
VGS = 0 V
Crss
2000
Ciss
Coss
Crss
0
−10
VGS
10
0 V
DS
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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5
20
MMSF5P02HD
10
1000
QT
8.0
4.0
VDS
VGS
3.0
Q1
6.0
Q2
2.0
4.0
TJ = 25°C
ID = 6.4 A
1.0
Q3
2.0
0
0
0
4.0
8.0
12
16
20
28
24
V DS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
t, TIME (ns)
V GS , GATE−TO−SOURCE VOLTAGE (VOLTS)
5.0
TJ = 25°C
ID = 1.0 A
VDD = 6.0 V
VGS = 4.5 V
td(off)
tf
100
tr
td(on)
10
1.0
10
QG, TOTAL GATE CHARGE (nC)
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
100
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
high di/dts. The diode’s negative di/dt during ta is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of tb/ta serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter trr), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short trr and low QRR specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
IS, SOURCE CURRENT (AMPS)
7.0
6.0
TJ = 25°C
VGS = 0 V
5.0
4.0
3.0
2.0
1.0
0
0.4
0.5
0.7
0.6
0.8
0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
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MMSF5P02HD
di/dt = 300 A/μs
Standard Cell Density
trr
I S , SOURCE CURRENT
High Cell Density
trr
tb
ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curve (Figure
12) defines the maximum simultaneous drain−to−source
voltage and drain current that a transistor can handle safely
when it is forward biased. Curves are based upon maximum
peak junction temperature and a case temperature (TC) of
25°C. Peak repetitive pulsed power limits are determined by
using the thermal response data in conjunction with the
procedures discussed in AN569, “Transient Thermal
Resistance − General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded, and that the
transition time (tr, tf) does not exceed 10 μs. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
1000
VGS = 20 V
SINGLE PULSE
TC = 25°C
EAS, SINGLE PULSE DRAIN-TO-SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
100
1 ms
10
10 ms
dc
1.0
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1.0
10
800
600
400
200
0
100
VDS = 25 V
VGS = 4.5 V
IL = 19 Apk
L = 5.5 mH
25
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
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MMSF5P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
10
1
0.1
D = 0.5
0.2
0.1
0.05
0.02
0.01
Normalized to θja at 10s.
Chip
0.0163 Ω
0.0652 Ω
0.1988 Ω
0.0307 F
0.1668 F
0.5541 F
0.6411 Ω
0.9502 Ω
0.01
1.9437 F
72.416 F
SINGLE PULSE
0.001
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
1.0E+00
1.0E+01
Figure 14. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 15. Diode Reverse Recovery Waveform
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8
1.0E+02
Ambient
1.0E+03
MMSF5P02HD
INFORMATION FOR USING THE SO−8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self−align when
subjected to a solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
0.024
0.6
0.050
1.270
inches
mm
SO−8 POWER DISSIPATION
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 1.6 Watts.
The power dissipation of the SO−8 is a function of the
input pad size. This can vary from the minimum pad size
for soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature of the die, RθJA, the thermal resistance from
the device junction to ambient; and the operating
temperature, TA. Using the values provided on the data
sheet for the SO−8 package, PD can be calculated as
follows:
PD =
PD =
150°C − 25°C
80°C/W
= 1.6 Watts
The 80°C/W for the SO−8 package assumes the
recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 1.6 Watts using the
footprint shown. Another alternative would be to use a
ceramic substrate or an aluminum core board such as
Thermal Cladt. Using board material such as Thermal
Clad, the power dissipation can be doubled using the same
footprint.
TJ(max) − TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
SOLDERING PRECAUTIONS
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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MMSF5P02HD
TYPICAL SOLDER HEATING PROFILE
temperature versus time. The line on the graph shows the
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density
board. The Vitronics SMD310 convection/infrared reflow
soldering system was used to generate this profile. The type
of solder used was 62/36/2 Tin Lead Silver with a melting
point between 177 −189°C. When this type of furnace is
used for solder reflow work, the circuit boards and solder
joints tend to heat first. The components on the board are
then heated by conduction. The circuit board, because it has
a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may
be up to 30 degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 16 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems, but it is a good starting point. Factors
that can affect the profile include the type of soldering
system in use, density and types of components on the
board, type of solder used, and the type of board or
substrate material being used. This profile shows
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
160°C
STEP 5
STEP 6
STEP 7
HEATING
VENT
COOLING
ZONES 4 & 7
205° TO 219°C
“SPIKE”
PEAK AT
170°C
SOLDER
JOINT
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
5°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 16. Typical Solder Heating Profile
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MMSF5P02HD
PACKAGE DIMENSIONS
SO−8
CASE 751−07
ISSUE V
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
XXXXXX
ALYW
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
STYLE 13:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0_
8_
0.010
0.020
0.228
0.244
N.C.
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
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ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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