Catalyst CAT24WC17PI-1.8 2k/4k/8k/16k-bit serial e2prom Datasheet

Preliminary
CAT24WC03/05/09/17
2K/4K/8K/16K-Bit Serial E2PROM
FEATURES
■ 400 KHZ I2C Bus Compatible*
■ Self-Timed Write Cycle with Auto-Clear
■ 1.8 to 6.0Volt Operation
■ 1,000,000 Program/Erase Cycles
■ Low Power CMOS Technology
■ 100 Year Data Retention
■ Write Protect Feature
■ 8-pin DIP, 8-pin SOIC and 8-pin TSSOP Package
–Top 1/2 Array Protected When WP at VIH
■ Commercial, Industrial and Automotive
Temperature Ranges
■ 16-Byte Page Write Buffer
DESCRIPTION
ments. The CAT24WC03/05/09/17 features a 16-byte
page write buffer. The device operates via the I2C bus
serial interface, has a special write protection feature,
and is available in 8-pin DIP or 8-pin SOIC
The CAT24WC03/05/09/17 is a 2K/4K/8K/16K-bit Serial
CMOS E2PROM internally organized as 256/512/1024/
2048 words of 8 bits each. Catalyst’s advanced CMOS
technology substantially reduces device power require-
PIN CONFIGURATION
DIP Package (P)
1
2
3
4
A0
A1
A2
VSS
8
7
6
5
BLOCK DIAGRAM
EXTERNAL LOAD
SOIC Package (J)
VCC
WP
SCL
SDA
1
2
3
4
A0
A1
A2
VSS
8
7
6
5
VCC
VSS
TSSOP Package (U)
SDA
(** Available for 24WC03 only)
A0
A1
A2
VSS
1
2
3
4
SS
8
7
6
5
SENSE AMPS
SHIFT REGISTERS
DOUT
ACK
VCC
WP
SCL
SDA
VCC
WP
SCL
SDA
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
XDEC
WP
COLUMN
DECODERS
E2PROM
CONTROL
LOGIC
PIN FUNCTIONS
Pin Name
DATA IN STORAGE
Function
A0, A1, A2
Device Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
VCC
+1.8V to +6.0V Power Supply
VSS
Ground
HIGH VOLTAGE/
TIMING CONTROL
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
24WCXX F03
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25063-00 2/98 S-1
CAT24WC03/05/09/17
Preliminary
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) .................................. 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Units
Reference Test Method
1,000,000
Cycles/Byte
MIL-STD-883, Test Method 1033
Data Retention
100
Years
MIL-STD-883, Test Method 1008
VZAP(3)
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
ILTH(3)(4)
Latch-up
100
mA
NEND(3)
TDR
(3)
Parameter
Min.
Endurance
Max.
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol
Max.
Units
Test Conditions
Power Supply Current
3
mA
fSCL = 100 KHz
Standby Current (VCC = 5.0V)
0
µA
VIN = GND or VCC
ILI
Input Leakage Current
10
µA
VIN = GND to VCC
ILO
Output Leakage Current
10
µA
VOUT = GND to VCC
VIL
Input Low Voltage
–1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
ICC
IS
(5)
Parameter
Min.
Typ.
VOL1
Output Low Voltage (VCC = 3.0V)
0.4
V
IOL = 3 mA
VOL2
Output Low Voltage (VCC = 1.8V)
0.5
V
IOL = 1.5 mA
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Test
Max.
Units
Conditions
CI/O(3)
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
CIN(3)
Input Capacitance (A0, A1, A2, SCL, WP)
6
pF
VIN = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby Current (ISB) = 0µA (<900nA).
Doc. No. 25063-00 2/98 S-1
2
CAT24WC03/05/09/17
Preliminary
A.C. CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.8V, 2.5V
Min.
Max.
4.5V-5.5V
Min.
Max.
Units
FSCL
Clock Frequency
100
400
kHz
TI(1)
Noise Suppression Time
Constant at SCL, SDA Inputs
200
200
ns
tAA
SCL Low to SDA Data Out
and ACK Out
3.5
1
µs
tBUF(1)
Time the Bus Must be Free Before
a New Transmission Can Start
tHD:STA
Start Condition Hold Time
tLOW
4.7
1.2
µs
4
0.6
µs
Clock Low Period
4.7
1.2
µs
tHIGH
Clock High Period
4
0.6
µs
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
0.6
µs
tHD:DAT
Data In Hold Time
0
0
ns
tSU:DAT
Data In Setup Time
50
50
ns
tR(1)
SDA and SCL Rise Time
1
0.3
µs
SDA and SCL Fall Time
300
300
ns
tF
(1)
tSU:STO
Stop Condition Setup Time
tDH
Data Out Hold Time
4
0.6
µs
100
100
ns
Power-Up Timing(1)(2)
Symbol
Parameter
Max.
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
Write Cycle Limits
Symbol
Parameter
tWR
Write Cycle Time
Min.
Typ.
Max
Units
10
ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
3
Doc. No. 25063-00 2/98 S-1
CAT24WC03/05/09/17
Preliminary
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The CAT24WC03/05/09/17 supports the I2C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. Data transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC03/05/
09/17 operates as a Slave device. Both the Master and
Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is
activated. A maximum of 8 devices (24WC03), 4 devices
(24WC05), 2 devices (24WC09) and 1 device (24WC17)
may be connected to the bus as determined by the
device address inputs A0, A1, and A2.
SCL: Serial Clock
The CAT24WC03/05/09/17 serial clock input pin is used
to clock all data transfers into or out of the device. This
is an input pin.
SDA: Serial Data/Address
The CAT24WC03/05/09/17 bidirectional serial data/address pin is used to transfer data into and out of the
device. The SDA pin is an open drain output and can be
wire-ORed with other open drain or open collector
outputs.
A0, A1, A2: Device Address Inputs
These inputs set device address when cascading multiple devices. When these pins are left floating the
default values are zeros.
A maximum of eight devices can be cascaded when
using 24WC03 device. All three address pins are used
Figure 1. Bus Timing
tHIGH
tF
tLOW
tR
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
tAA
tBUF
tDH
SDA OUT
5020 FHD F03
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
Doc. No. 25063-00 2/98 S-1
STOP BIT
4
5020 FHD F05
CAT24WC03/05/09/17
Preliminary
I2C BUS PROTOCOL
for 24WC03. If only one 24WC03 is addressed on the
bus, all three address pins (A0, A1, and A2) can be left
floating or connected to VSS
The following defines the features of the I2C bus protocol:
A total of four devices can be addressed on a single bus
when using 24WC05 device. Only A1 and A2 address
pins are used with this device. The A0 address pin is a
no connect pin and can be tied to VSS or left floating. If
only one 24WC05 is being addressed on the bus, the
address pins (A1 and A2) can be left floating or connected to VSS.
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
Only two devices can be cascaded when using 24WC09.
The only address pin used with this device is A2. The A0
and A1address pins are no connect pins and can be tied
to VSS or left floating. If only one 24WC09 is being
addressed on the bus, the address pin (A2) can be left
floating or connected to VSS.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC03/05/09/17
monitor the SDA and SCL lines and will not respond until
this condition is met.
The 24WC17 is a stand alone device. In this case, all
address pins (A0, A1and A2) are no connect pins and
can be tied to VSS or left floating.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
WP: Write Protect
If the WP pin is tied to VCC the upper half of memory array
becomes Write Protected (READ only)(locations 80H to
FFH for 24WC03, locations 100H to 1FFH for 24WC05,
locations 200H to 3FFH for 24WC09, locations 400H to
7FFH for 24WC17). When the WP pin is tied to VSS or
left floating normal read/write operations are allowed to
the device.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
5020 FHD F06
Figure 5. Slave Address Bits
24WC03
1
0
1
0
A2
A1
A0
R/W
24WC05
1
0
1
0
A2
A1
a8
R/W
24WC09
1
0
1
0
A2
a9
a8
R/W
24WC17
1
0
1
0
a10
a9
a8
R/W
* A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.
** a8, a9 and a10 correspond to the address of the memory array address word.
***A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
5
Doc. No. 25063-00 2/98 S-1
CAT24WC03/05/09/17
Preliminary
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24WC03/05/09/17 (see Fig. 5). The
next three significant bits (A2, A1, A0) are the device
address bits and define which device or which part of the
device the Master is accessing. Up to eight CAT24WC03,
four CAT24WC05, two CAT24WC09, and one
CAT24WC17 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24WC03/05/09/17 will continue to transmit data. If no acknowledge is sent by the
Master, the device terminates data transmission and
waits for a STOP condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24WC03/05/09/17. After receiving
another acknowledge from the Slave, the Master device
transmits the data byte to be written into the addressed
memory location. The CAT24WC03/05/09/17 acknowledge once more and the Master generates the STOP
condition, at which time the device begins its internal
programming cycle to nonvolatile memory. While this
internal cycle is in progress, the device will not respond
to any request from the Master device.
After the Master sends a START condition and the slave
address byte, the CAT24WC03/05/09/17 monitors the
bus and responds with an acknowledge (on the SDA
line) when its address matches the transmitted slave
address. The CAT24WC03/05/09/17 then performs a
Read or Write operation depending on the state of the
R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
Page Write
The CAT24WC03/05/09/17 responds with an acknowledge after receiving a START condition and its slave
address. If the device has been selected along with a
write operation, it responds with an acknowledge after
receiving each 8-bit byte.
The CAT24WC03/05/09/17 writes up to 16 bytes of data
in a single write cycle, using the Page Write operation.
The Page Write operation is initiated in the same manner
as the Byte Write operation, however instead of terminating after the initial word is transmitted, the Master is
allowed to send up to 15 additional bytes. After each byte
has been transmitted the CAT24WC03/05/09/17 will
respond with an acknowledge, and internally increment
When the CAT24WC03/05/09/17 is in a READ mode it
transmits 8 bits of data, releases the SDA line, and
Figure 6. Byte Write Timing
S
T
A
R
T
BUS ACTIVITY:
MASTER
SDA LINE
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
O
P
DATA
S
P
A
C
K
A
C
K
5020 FHD F08
A
C
K
Figure 7. Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
S
T
O
P
DATA n+P
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
24WCXX F09
24WCXX FO9
Doc. No. 25063-00 2/98 S-1
6
CAT24WC03/05/09/17
Preliminary
the low order address bits by one. The high order bits
remain unchanged.
device’s failure to send an acknowledge after the first
byte of data is received.
If the Master transmits more than 16 bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be overwritten.
READ OPERATIONS
The READ operation for the CAT24WC03/05/09/17 is
initiated in the same manner as the write operation with
the one exception that the R/W bit is set to a one. Three
different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ.
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24WC03/05/09/17 in a single write cycle.
Immediate Address Read
Acknowledge Polling
The CAT24WC03/05/09/17’s address counter contains
the address of the last byte accessed, incremented by
one. In other words, if the last READ or WRITE access
was to address N, the READ immediately following
would access data from address N+1. If N=E (where E
= 255 for 24WC03, 511 for 24WC05, 1023 for 24WC09,
and 2047 for 24WC17), then the counter will ‘wrap
around’ to address 0 and continue to clock out data.
After the CAT24WC03/05/09/17 receives its slave address information (with the R/W bit set to one), it issues
an acknowledge, then transmits the 8-bit byte requested.
The master device does not send an acknowledge but
will generate a STOP condition.
The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24WC03/05/09/17 initiates the internal write cycle. ACK polling can be initiated immediately.
This involves issuing the start condition followed by the
slave address for a write operation. If the CAT24WC03/
05/09/17 is still busy with the write operation, no ACK will
be returned. If the CAT24WC03/05/09/17 has completed the write operation, an ACK will be returned and
the host can then proceed with the next read or write
operation.
Selective Read
WRITE PROTECTION
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24WC03/05/09/17 acknowledge the
word address, the Master device resends the START
condition and the slave address, this time with the R/W
bit set to one. The CAT24WC03/05/09/17 then responds
with its acknowledge and sends the 8-bit byte requested.
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the upper half (locations 80H
to FFH for 24WC03, locations 100H to 1FFH for 24WC05,
locations 200H to 3FFH for 24WC09, locations 400H to
7FFH for 24WC17) of the memory array is protected and
becomes read only. The CAT24WC03/05/09/17 will
accept both slave and byte addresses, but the memory
location accessed is protected from programming by the
Figure 8. Immediate Address Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
S
P
A
C
K
DATA
N
O
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
7
STOP
5020 FHD F10
Doc. No. 25063-00 2/98 S-1
CAT24WC03/05/09/17
Preliminary
The master device does not send an acknowledge but
will generate a STOP condition.
respond with an acknowledge, thus sending the STOP
condition.
Sequential Read
The data being transmitted from the CAT24WC03/05/
09/17 is outputted sequentially with data from address N
followed by data from address N+1. The READ operation address counter increments all of the CAT24WC03/
05/09/17 address bits so that the entire memory array
can be read during one operation. If more than the E
(where E = 255 for 24WC03, 511 for 24WC05, 1023 for
24WC09, and 2047 for 24WC17) bytes are read out, the
counter will “wrap around” and continue to clock out data
bytes.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24WC03/05/09/17 sends the
initial 8-bit byte requested, the Master will respond with
an acknowledge which tells the device it requires more
data. The CAT24WC03/05/09/17 will continue to output
an 8-bit byte for each acknowledge sent by the Master.
The operation is terminated when the Master fails to
Figure 9. Selective Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
S
T
A
R
T
BYTE
ADDRESS (n)
S
S
T
O
P
SLAVE
ADDRESS
S
A
C
K
P
A
C
K
A
C
K
DATA n
N
O
A
C
K
24WCXX F11
Figure 10. Sequential Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
S
T
O
P
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
24WC03
Optional
Company ID
Product Number
24WC03: 2K
24WC05: 4K
24WC09: 8K
24WC17: 16K
J
-1.8
I
Temperature Range
Blank = Commercial (0˚ - 70˚C)
I = Industrial (-40˚ - 85˚C)
A = Automotive (-40˚ - 105˚C)*
Package
P: PDIP
J: SOIC (JEDEC)
U: TSSOP **
TE13
Tape & Reel
TE13: 2000/Reel
Operating Voltage
Blank: 2.5V - 6.0V
1.8: 1.8V - 6.0V
* -40˚ to +125˚C is available upon request
** Available for 24WC03
Notes:
(1) The device used in the above example is a 24WC03JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)
Doc. No. 25063-00 2/98 S-1
8
5020 FHD F12