N64T1630C1B
NanoAmp Solutions, Inc.
670 N. McCarthy Blvd. Suite 220, Milpitas, CA 95035
ph: 408-935-7777, FAX: 408-935-7770
www.nanoamp.com
Advance Information
64Mb Ultra-Low Power Asynchronous CMOS PSRAM
4M × 16 Bits
Overview
Features
The N64T1630C1B is an integrated memory
device containing a 64 Mbit Pseudo Static Random
Access Memory using a self-refresh DRAM array
organized as 4,194,304 words by 16 bits. It is
designed to be compatible in operation and
interface to standard 6T SRAMS. The device is
designed for low standby and operating current
and includes a power-down feature to
automatically enter standby mode. The device
includes a ZZ input for deep sleep as well as
several other power saving modes: Partial Array
Self Refresh mode where data is retained in a
portion of the array and Temperature
Compensated Refresh. Both these modes reduce
standby current drain. The N64T1630C1B can be
operated in a standard asynchronous mode and
data can also be read in a 4-word page mode for
fast access times. The die has separate power
rails, VccQ and VssQ for the I/O to be run from a
separate power supply from the device core.
• Dual voltage rails for optimum power & performance
Vcc - 2.7V - 3.3V
Vccq - 2.7V to 3.3V
• Fast Cycle Times
TACC < 70 nS (60ns future)
TPACC < 25 nS
• Very low standby current
ISB < 170µA
• Very low operating current
Icc < 25mA
• PASR (Partial Array Self Refresh)
• TCR (Temperature Compensated Refresh)
Table 1: Product Family
Part Number
Package
Type
Operating
Temperature
Power
Supply
I/O Supply
Speed
Standby
Current (ISB),
Max
N64T1630C1BZ
BGA
-25oC to +85oC
2.7 - 3.3V
2.7 - 3.3V
70ns
170µA
Ball Description
Ball Congiguration
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
ZZ
Pin Name
Pin Function
B
I/O8
UB
A3
A4
CE
I/O0
A0-A21
Address Inputs
C
I/O9
I/O10
A5
A6
I/O1
I/O2
WE
Write Enable Input
D
VSSQ I/O11
A17
A7
I/O3
VCC
CE
Chip Enable Input
E
VCCQ I/O12
A21
A16
I/O4
VSS
ZZ
Deep Sleep Input
F
I/O14 I/O13
A14
A15
I/O5
I/O6
OE
Output Enable Input
G
I/O15
A19
A12
A13
WE
I/O7
LB
Lower Byte Enable Input
H
A18
A8
A9
A10
A11
A20
UB
Upper Byte Enable Input
I/O0-I/O15
Data Inputs/Outputs
48 Pin BGA (top view)
6 x 8 mm
VCC
Power
VSS
Ground
VCCQ
Power I/O only
VSSQ
Ground I/O only
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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N64T1630C1B
NanoAmp Solutions, Inc.
Advance Information
Figure 1: Functional Block Diagram
Address
Inputs
A4 - A21
Page
Address
Decode
Logic
Address
Inputs
A0 - A3
Word
Address
Decode
Logic
4096K x 16
Input/
Output
Mux
and
Buffers
Memory
Array
I/O0 - I/O7
I/O8 - I/O15
CE
WE
Control
OE
UB
LB
Logic
ZZ
Table 2: Functional Description
CE
WE
OE
UB/LB
ZZ
I/O1
MODE
POWER
H
X
X
X
H
High Z
Standby2
Standby
L
L
X3
L1
H
Data In
Write
Active
L
H
L
L1
H
Data Out
Read
Active
L
H
H
L
H
High Z
Active
Standby4
L
L
X
X
L
High-Z
Set register
Active
H
X
X
X
L
High-Z
Deep Sleep
Deep Sleep
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only
I/O0 - IO7 are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Table 3: Capacitance1
Item
Symbol
Test Condition
Input Capacitance
CIN
CI/O
I/O Capacitance
Max
Unit
VIN = 0V, f = 1 MHz, TA = 25oC
6
pF
25oC
6
pF
VIN = 0V, f = 1 MHz, TA =
Min
1. These parameters are verified in device characterization and are not 100% tested
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
2
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Advance Information
Table 4: Absolute Maximum Ratings1
Item
Symbol
Rating
Unit
Voltage on any pin relative to VSS
VIN,OUT
–0.5 to VCCQ+0.3
V
Voltage on VCC Supply Relative to VSS
VCC
–0.2 to 3.6
V
Voltage on VCCQ Supply Relative to VSS
VCCQ
–0.2 to 4.0
V
Power Dissipation
PD
500
mW
Storage Temperature
TSTG
–55 to 150
oC
Operating Temperature
TA
-25 to +85
o
C
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 5: Operating Characteristics (Over Specified Temperature Range)
Item
Symbol
Comments
Min.
Max.
Unit
Supply Voltage
VCC
Supply Voltage for I/O
VCCQ
2.7
3.3
V
Input High Voltage
VIH
Vcc
3.3
V
0.8VCCQ
VCCQ+0.2
V
Input Low Voltage
VIL
–0.2
0.4
V
Output High Voltage
VOH
IOH = -0.2mA
Output Low Voltage
VOL
IOL = 0.2mA
0.2VCCQ
V
Input Leakage Current
ILI
VIN = 0 to VCC
1
µA
Output Leakage Current
ILO
OE = VIH or Chip Disabled
1
µA
Read/Write Operating Current1
ICC
VIN=VCCQ or 0V
Chip Enabled, IOUT = 0
25
mA
Page Mode Operating Current
ICCP
VIN=VCCQ or 0V
Chip Enabled, IOUT = 0
15
mA
Standby Current2
VIN = VCC or 0V
ISB
VIN = VCC or 0V
Chip Disabled
VCC = VCCMAX, tA= 85oC
170
µA
0.8VCCQ
100
V
1. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to
drive output capacitance expected in the actual system.
2. This device assumes a standby mode if the chip is disabled (CE high). In order to achieve low standby current all inputs must
be within 0.2 volts of either VCC or VSS.
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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N64T1630C1B
NanoAmp Solutions, Inc.
Advance Information
Table 6: Timing Test Conditions
Item
Input Pulse Level
VSS to VCCQ
Input Rise and Fall Time (10% to 90%)
1.6ns
Input Timing Reference Levels
0.5 VCCQ
Output Timing Reference Levels
0.5 VCCQ
Operating Temperature
-25 oC to +85 oC
Figure 2: Output Load Circuit
VCCQ
R1
I/O
R2
30 pF
Output Load
Table 7: Ouput Load
VCCQ
R1/R2
3.0V
4.5KΩ
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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N64T1630C1B
NanoAmp Solutions, Inc.
Advance Information
Table 8: Timings
Read
Cycle
Write
Cycle
Item
Symbol
Read Cycle Time
-70
Unit
Min
Max
tRC
70
20k
Page Mode Cycle Time
tPC
25
Address Access Time
tAA
70
ns
Page Mode Access Time
tPA
25
ns
Chip Enable to Valid Output
tCO
70
ns
Output Enable to Valid Output
tOE
20
ns
Byte Select to Valid Output
tBO
70
ns
Chip Enable to Low-Z output
tLZ
10
ns
Output Enable to Low-Z Output
tOLZ
5
ns
Byte Select to Low-Z Output
tBLZ
10
ns
Chip Disable to High-Z Output
tHZ
0
8
ns
Output Disable to High-Z Output
tOHZ
0
8
ns
Byte Select Disable to High-Z Output
tBHZ
0
8
ns
Output Hold from Address Change
tOH
5
Write Cycle Time
tWC
70
Page Mode Max Write Cycle
ns
ns
ns
20k
ns
tPGMAX
20k
ns
Chip Enable Active Time
tCE
20k
ns
Chip Enable HIGH Time
tCEH
5
ns
Chip Enable to End of Write
tCW
70
ns
Address Valid to End of Write
tAW
70
ns
Byte Select to End of Write
tBW
70
ns
Chip Enable to Low-Z
tLZ
10
ns
Write Pulse Width
tWP
45
ns
Write Recovery Time
tWR
0
ns
Write to High-Z Output
tWHZ
0
Address Setup Time
tAS
0
ns
Data to Write Time Overlap
tDW
25
ns
Data Hold from Write Time
tDH
0
ns
End Write to Low-Z Output
tOW
5
ns
WE High Time
tWEH
7.5
ns
Page Write Cycle Time
tPWC
25
ns
Page Mode Data to Write Time Overlap
tPDW
20
ns
Page Mode Data Hold From Write Time
tPDH
0
ns
8
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
ns
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N64T1630C1B
NanoAmp Solutions, Inc.
Advance Information
Figure 3: Timing of Read Cycle (CE = OE = VIL, WE = VIH)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Data Valid
Figure 4: Timing Waveform of Read Cycle (WE=VIH)
tRC
Address
tAA
CE
tCO
tHZ
tBHZ
tLZ
tBO
LB, UB
tBLZ
tOE
tOHZ
OE
tOLZ
Data Out
High-Z
Data Valid
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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NanoAmp Solutions, Inc.
Advance Information
Figure 5: Timing Waveform of Page Mode Read Cycle (WE=VIH)
tRC
Address
tPC
tPC
tAA
CE
tCO
tHZ
tLZ
tBHZ
tBO
LB, UB
tBLZ
tOHZ
tOE
OE
tOLZ
Data Out
High-Z
tPA
Data Valid
tPA
tOH
tPA
Data Valid
Data Valid
Data Valid
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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N64T1630C1B
NanoAmp Solutions, Inc.
Advance Information
Figure 6: Timing Waveform of Write Cycle (WE control)
tWC
Address
tAW
tWR
tCW
CE
tCE
tBW
LB, UB
tAS
tWP
WE
tDW
High-Z
tDH
Data Valid
Data In
tWHZ
tOW
High-Z
Data Out
Figure 7: Timing Waveform of Write Cycle (CE Control)
tWC
Address
tAW
tWR
tCW
CE
tAS
tCE
tBW
LB, UB
tWP
WE
tZ
tDW
tDH
Data Valid
Data In
tWHZ
Data Out
High-Z
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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N64T1630C1B
NanoAmp Solutions, Inc.
Advance Information
Figure 8: Timing Waveform of Write Cycle (UB, LB control)
tWC
Address
tAW
tWR
tCW
CE
tAS
tBW
LB, UB
tWP
WE
tLZ
tDW
tDH
Data Valid
Data In
tWHZ
Data Out
High-Z
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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N64T1630C1B
NanoAmp Solutions, Inc.
Advance Information
Figure 9: Timing Waveform for Sucessive WE Write Cycles
tWC
Address
tAS
tWR
tAS
tWR
CE
LB, UB
tWEH
tWP
tWP
WE
tDW
Data In
tDH
tDW
tDH
High-Z
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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N64T1630C1B
NanoAmp Solutions, Inc.
Advance Information
Figure 10: Timing Waveform of Page Mode Write Cycle
tPGMAX
Page Address
(A4 - A21)
tWC
tPWC
Word Address
(A0 - A3)
tCEH
tAS
CE
tCW
tWP
WE
tLBW, tUBW
LB, UB
tDW
Data In
tDH
tPDW
tPDH
tPDW
tPDH
High-Z
tPGMAX means any page address (A4-A21) must be changed at least once in a 20us period
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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NanoAmp Solutions, Inc.
N64T1630C1B
Advance Information
Power Up Requirements
After power is applied to bring Vcc and VccQ up, CE should be brought high. Once CE is high, a 150µs
delay is required to ensure proper operation. After a 150µs delay, the device is now ready for operation or
programming of the mode register.
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
12
NanoAmp Solutions, Inc.
N64T1630C1B
Advance Information
Power Savings Modes
In the N64T1630C1B device there are several power savings modes. The three modes are:
• Partial Array Self Refresh
• Temperature Compensated Refresh
• Deep Sleep Mode
The operation of the power saving modes is controlled by the settings of bits contained in the Mode Register. This definition of the Mode Register is shown in Figure 11 and the various bits are used to enable and
disable the various low power modes as well as enabling Page Mode operation. The Mode Register is set
by using the timings defined in Figure 12.
1) Partial Array Self Refresh (PAR)
In this mode of operation, the internal refresh operation can be restricted to a 16Mb, 32Mb or 48Mb portion
of the array. The array partition to be refreshed is determined by the respective bit settings in the Mode
Register. The register settings for the PASR operation are defined in Table 10. In this PASR mode, when
ZZ is active low, only the portion of the array that is set in the register is refreshed. The data in the remainder of the array will be lost. The PASR operating mode is only available during standby time (ZZ low) and
once ZZ is returned high, the device resumes full array refresh. All future PASR cycles will use the contents
of the Mode Register that has been previously set. To change the address space of the PASR mode, the
Mode Register must be reset using the previously defined procedures. For PASR to be activated, the register bit, A4 must be set to a ‘1’ value, “PASR Enabled”. If this is the case, PASR will be activated 10us
after ZZ is brought low. If the A4 register bit is set equal to ‘0’, PASR will not be activated.
2) Temperature Compensated Refresh (TCR)
In this mode of operation, the internal refresh rate can be optimized for the operating temperature used an
this can then lower standby current. The DRAM array in the PSRAM must be refreshed internally on a regular basis. At higher temperatures, the DRAM cell must be refreshed more often than at lower tempertures. By setting the temperature of operation in the Mode Register, this refresh rate can be optimized to
yield the lowest standby current at the given operating temperature. There are four different temperature
settings that can be programmed in to the PSRAM. These are defined in Figure 11.
3) Deep Sleep Mode
In this mode of operation, the internal refresh is turned off and all data integrity of the array is lost. Deep
Sleep is entered by bringing ZZ low with the A4 register bit set to a ‘0’, “Deep Sleep Enabled”. If this is the
case, Deep Sleep will be entered 10us after ZZ is brought low. The device will remain in this mode as long
as ZZ remains low. If the A4 register bit is set equal to ‘1’, Deep Sleep will not be activated.
Other Mode Register Settings
The Page Mode operation can also be enabled and disabled using the Mode Register. Register bit A7
controls the operation of Page Mode and setting this bit to a ‘1’, enables Page Mode. If the register bit A7
is set to a ‘0’, Page Mode operation is disabled.
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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Advance Information
Figure 11: Mode Register
A21 - A10
A9 - A8
A7
A6
A5
A4
0
0
1
1
Temp
Compensated
Refresh
0 = 16 words
1 = 32 words
0 = 64 words
1 = 128 words
A2
A1
A0
Reserved
Must set to ‘0’
Page Length
Reserved
Must set to all 0
A3
PASR Section
1
0 = 15oC
0
1 = 45oC
0
0 = 70oC
1
1 = 85oC (default)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1 = Top 1/4 array
0 = Top 1/2 array
1 = Top 3/4 array
0 = No PASR
1 = Bottom 1/4 array
0 = Bottom 1/2 array
1 = Bottom 3/4 array
0 = Full array (default)
Page Mode
0 = Page Mode Disabled (default)
1 = Page Mode Enabled
Deep Sleep Enable/Disable
0 = Deep Sleep Enabled
1 = PASR Enabled (default)
Figure 12: Mode Register Update Timings (UB, LB, OE are Don’t Care)
tWC
Address
tAS
tAW
tWR
CE
tCW
tWP
WE
tCDZZ
tZZWE
ZZ
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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NanoAmp Solutions, Inc.
Advance Information
Figure 13: Deep Sleep Mode - Entry/Exit Timings
tZZMIN
ZZ
tR
tCDZZ
CE
Table 9: Mode Register Update and Deep Sleep Timings
Item
Symbol
Min
Chip deselect to ZZ low
tCDZZ
5
ZZ low to WE low
tZZWE
10
Max
Unit
Note
ns
500
ns
Write register cycle time
tWC
70/85
ns
1
Chip enable to end of write
tCW
70/85
ns
1
Address valid to end of write
tAW
70/85
ns
1
Write recovery time
tWR
0
ns
Address setup time
tAS
0
ns
Write pulse width
tWR
40
ns
tZZMIN
10
us
tR
150
us
Deep Sleep Pulse Width
Deep Sleep Recovery
1) Minimum cycle time for writing register is equal to speed grade of product.
Table 10: Address Patterns for PASR (A4 = 1)
A2
1
1
1
1
0
0
0
0
A1
1
1
0
0
1
1
0
0
A0
1
0
1
0
1
0
1
0
Active Section
Top quarter of die
Top half of die
Top three quarter of die
No PASR
Bottom quarter of die
Bottom half of die
Bottom three quarter of die
Full array
Address space
300000h - 3FFFFFh
200000h - 3FFFFFh
100000h - 3FFFFFh
None
000000h - 0FFFFFh
000000h - 1FFFFFh
000000h - 2FFFFFh
000000h - 3FFFFFh
Size
1Mb x 16
2Mb x 16
3Mb x 16
0
1Mb x 16
2Mb x 16
3Mb x 16
4Mb x 16
Density
16Mb
32Mb
48Mb
0
16Mb
32Mb
48Mb
64Mb
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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NanoAmp Solutions, Inc.
Advance Information
Table 11: Deep ICC Characteristics for N64T1630C1B
Item
PASR Mode
Standby Current
Symbol
IPASR
Item
VIN = VCC or 0V,
Chip Disabled, tA= 85oC
Symbol
Deep Sleep Current
IZZ
Typ
None
1/4 Array
1/2 Array
3/4 Array
Full Array
Symbol
Max
Temperature
ITCR
15oC
70
45oC
85
70oC
105
85oC
170
Temperature Compensated
Refresh Current
Item
Array
Partition
Test
Test
VIN = VCC or 0V,
Chip in ZZ mode, tA= 25oC
Typ
Typ
30
Max
Max
Max
Unit
70
105
110
115
170
µA
Unit
µA
Unit
µA
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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NanoAmp Solutions, Inc.
Advance Information
Package Dimensions
0.23±0.05
0.90±0.10
D
A1 BALL PAD
CORNER (3)
1. 0.30±0.05 DIA.
E
2. SEATING PLANE - Z
0.15 Z
0.08
TOP VIEW
Z
SIDE VIEW
1. DIMENSION IS MEASURED AT THE
A1 BALL PAD
MAXIMUM SOLDER BALL DIAMETER.
CORNER
PARALLEL TO PRIMARY Z.
SD
e
SE
2. PRIMARY DATUM Z AND SEATING
PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE
SOLDER BALLS.
3. A1 BALL PAD CORNER I.D. TO BE
MARKED BY INK.
K TYP
J TYP
e
BOTTOM VIEW
e = 0.75
D
6±0.10
SD
SE
J
K
BALL
MATRIX
TYPE
0.375
0.375
1.125
1.375
FULL
E
8±0.10
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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NanoAmp Solutions, Inc.
Advance Information
Figure 14: Ordering Information
N64T1630C1BZ-XXI
Performance
70 = 70ns
Note: Add -T&R following the part number for Tape and Reel. Orders will be
considered in tray if not noted.
Table 12: Revision History
Revision
Date
Change Description
A
June 2004
B
January 2005
Original ADVANCED Datasheet
Changed maximum Vcc rating
C
January 2005
General Update
D
May 2005
Isb change to 170uA
E
July 2005
Changed Vih to 0.8VccQ
© 2004 NanoAmp Solutions, Inc. All rights reserved.
NanoAmp Solutions, Inc. ("NanoAmp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice.
NanoAmp does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration purposes only and they vary depending upon specific applications.
NanoAmp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does NanoAmp assume any liability arising out of the application
or use of any product or circuit described herein. NanoAmp does not authorize use of its products as critical components in any application in which the failure of the NanoAmp
product may be expected to result in significant injury or death, including life support systems and critical medical instrument.
Stock No. 23357- Rev E 07/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
18