−48 V Hot Swap Controller and Digital Power Monitor with PMBus Interface ADM1075 Data Sheet FEATURES PRODUCT HIGHLIGHTS Constant power foldback for FET SOA protection Precision (<1.0%) current and voltage measurement Controls inrush and faults for negative supply voltages Suitable for wide input range due to internal shunt regulator 25 mV/50 mV full-scale sense voltage Fine tune current limit to allow use of standard sense resistor Soft start inrush current limit profiling 1% accurate UVH and OV pins, 1.5% accurate UVL pin PMBus/I2C interface for control, telemetry, and fault recording 28-lead LFCSP and TSSOP −40°C to 105°C junction temperature (TJ) operating range 1. APPLICATIONS 5. Telecommunication and data communication equipment Central office switching −48 V distributed power systems Negative power supply control High availability servers 6. 2. 3. 4. Constant Power Foldback. Maximum FET power set by a PLIM resistor divider. This eases complexity when designing to maintain FET SOA. Adjustable Current Limit. The current limit is adjustable via the ISET pin allowing for the use of a standard value sense resistor. 12-Bit ADC. Accurate voltage, current, and power measurements. Also enables calculation of energy consumption over time. PMBus/I2C Interface. PMBus fast mode compliant interface used to read back status and data registers and set warning and fault limits. Fault Recording. Latched status registers provide useful debugging information to help trace faults in high reliability systems. Built-In Soft Start. Soft start capacitor controls inrush current profile with di/dt control. FUNCTIONAL BLOCK DIAGRAM –48V RTN (0V) RDROP 12V VIN SPLYGD VCC AND REFERENCE GENERATOR VEE UVH UVL OV SHDN RESTART POWER ACCUMULATOR POWER MULTIPLIER UNDERVOLTAGE AND OVERVOLTAGE DETECTOR DIGITAL AND PMBUS 5V LATCH GPO1/ALERT1/CONV GPO2/ALERT2 SDAO SDAI SCL 3.3V 2.8V CLOAD DC-TO-DC CONVERTER ...etc. GND ADR 12-BIT ADC ADC_AUX ADC_V PWRGD FET POWER FOLDBACK CONTROL DRAIN PLIM VCAP FAULT TIMER ISET ADuM1250 VEE GATE CONTROL GATE CURRENT LIMIT SENSE+ N-FET SDA_ISO SCL_ISO RSENSE SENSE– SS VEE_G VEE 09312-001 TIMER –48V Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved. ADM1075 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ADM1075 Information Commands........................................ 31 Applications....................................................................................... 1 Status Commands ...................................................................... 31 Product Highlights ........................................................................... 1 GPO and Alert Pin Setup Commands .................................... 32 Functional Block Diagram .............................................................. 1 Power Monitor Commands ...................................................... 32 Revision History ............................................................................... 3 Warning Limit Setup Commands ............................................ 33 General Description ......................................................................... 4 PMBus Direct Format Conversion .......................................... 34 Specifications..................................................................................... 5 Voltage and Current Conversion Using LSB Values.............. 35 Serial Bus Timing ......................................................................... 9 ADM1075 Alert Pin Behavior ...................................................... 36 Absolute Maximum Ratings.......................................................... 10 Faults and Warnings .................................................................. 36 Thermal Resistance .................................................................... 10 Generating an Alert ................................................................... 36 ESD Caution................................................................................ 10 Handling/Clearing an Alert ...................................................... 36 Pin Configuration and Function Description ............................ 11 SMBus Alert Response Address ............................................... 37 Typical Performance Characteristic............................................. 13 Example Use of SMBus Alert Response Address ................... 37 Theory of Operation ...................................................................... 20 Digital Comparator Mode......................................................... 37 Powering the ADM1075............................................................ 20 PMBus Command Reference........................................................ 38 Current Sense Inputs.................................................................. 21 Register Details ............................................................................... 39 Current Limit Reference............................................................ 21 Operation Command Register ................................................. 39 Setting the Current Limit (ISET) ............................................. 22 Clear Faults Register .................................................................. 39 Soft Start ...................................................................................... 22 PMBus Capability Register ....................................................... 39 Constant Power Foldback (PLIM) ........................................... 22 IOUT OC Warn Limit Register................................................ 39 TIMER ......................................................................................... 23 VIN OV Warn Limit Register................................................... 39 Hot Swap Fault Retry ................................................................. 24 VIN UV Warn Limit Register................................................... 39 Fast Response to Severe Overcurrent ...................................... 24 PIN OP Warn Limit Register.................................................... 40 UV and OV ................................................................................. 24 Status Byte Register .................................................................... 40 PWRGD ....................................................................................... 25 Status Word Register.................................................................. 40 DRAIN......................................................................................... 25 IOUT Status Register ................................................................. 41 SPLYGD ....................................................................................... 25 Input Status Register .................................................................. 41 LATCH......................................................................................... 25 Manufacturing Specific Status Register................................... 42 SHDN ........................................................................................... 25 Read EIN Register ...................................................................... 43 RESTART ..................................................................................... 25 Read VIN Register...................................................................... 43 FET Health .................................................................................. 26 Power Monitor ............................................................................ 26 Isolation ....................................................................................... 26 PMBus Interface ............................................................................. 28 Device Addressing...................................................................... 28 SMBus Protocol Usage............................................................... 28 Packet Error Checking............................................................... 28 SMBus Message Formats ........................................................... 29 Group Commands...................................................................... 30 Hot Swap Control Commands ................................................. 31 Read IOUT Register................................................................... 43 Read PIN Register ...................................................................... 43 PMBus Revision Register .......................................................... 43 Manufacturing ID Register ....................................................... 44 Manufacturing Model Register ................................................ 44 Manufacturing Revision Register............................................. 44 Peak IOUT Register ................................................................... 44 Peak VIN Register ...................................................................... 45 Peak VAUX Register .................................................................. 45 Power Monitor Control Register.............................................. 45 Rev. A | Page 2 of 52 Data Sheet ADM1075 Power Monitor Configuration Register ...................................45 Read EIN_EXT Register ............................................................49 ALERT1 Configuration Register...............................................46 Read VAUX Register...................................................................50 ALERT2 Configuration Register...............................................47 VAUX OV Warn Limit Register................................................50 IOUT WARN2 Limit Register...................................................48 VAUX UV Warn Limit Register................................................50 Device Configuration Register..................................................48 VAUX Status Register .................................................................50 Power Cycle Register ..................................................................49 Outline Dimensions........................................................................51 Peak PIN Register .......................................................................49 Ordering Guide ...........................................................................51 Read PIN_EXT Register.............................................................49 REVISION HISTORY 4/12—Rev. 0 to Rev. A Added 28-Lead LFCSP ...................................................... Universal Changes to Features Section and Product Highlights Section....1 Change to Test Conditions/Comments column for GATE Pin Parameter ....................................................................................4 Changes to ADC Conversion Time comments in Table 1...........8 Changes to Table 4 ..........................................................................10 Added Figure 4; Renumbered Sequentially; and changes to Table 5 ...............................................................................................11 Changes to Current Limit Reference Section ..............................21 Changes to Voltage and Current Conversion Using LSB Values Section ..................................................................................35 Changes to Table 8 ..........................................................................38 Changes to Table 20 ........................................................................43 Changes to Table 25 through Table 27 .........................................44 Changes to Table 32 ........................................................................45 Changes to Table 38 and Table 39 .................................................49 Changes to Outline Dimensions and Ordering Guide...............51 10/11—Revision 0: Initial Version Rev. A | Page 3 of 52 ADM1075 Data Sheet GENERAL DESCRIPTION The ADM1075 is a full feature, negative voltage, hot swap controller with constant power foldback and high accuracy digital current and voltage measurement that allows boards to be safely inserted and removed from a live −48 V backplane. The part provides precise and robust current limiting and protection against both transient and nontransient short circuits and overvoltage and undervoltage conditions. The ADM1075 typically operates from a negative voltage of −35 V to −80 V and, due to shunt regulation, has excellent voltage transient immunity. The operating range of the part is flexible due to the shunt regulator, and the part can be powered directly by a 10 V rail to save shunt power dissipation (see the Powering the ADM1075 section for more details). A full-scale current limit of 25 mV or 50 mV can be selected by choosing the appropriate model. The maximum current limit is set by the combination of the sense resistor, RSENSE, and the input voltage on the ISET pin, using external resistors. This allows fine tuning of the trip voltage so that standard sense resistors can be used. Inrush current is limited to this programmable value by controlling the gate drive of an external N-channel FET. A builtin soft start function allows control of the inrush current profile by an external capacitor on the soft start (SS) pin. An external capacitor on the TIMER pin determines the maximum allowed on-time for when the system is in current limit. This is based on the safe operating area (SOA) limits of the MOSFET. A constant power foldback scheme is used to control the power dissipation in the MOSFET during power-up and fault conditions. The ADM1075 regulates the current dynamically to ensure that the power in the MOSFET is within SOA limits as VDS changes. After the timer has expired, the device shuts down the MOSFET. The level of this power, along with the TIMER regulation time, can be set to ensure that the MOSFET remains within the SOA limits. The ADM1075 employs a limited consecutive retry scheme when the LATCH pin is tied to the SHDN pin. In this mode, if the load current reaches the limit, the FET gate is pulled low after the timer expires and retries after a cooling period for seven attempts only. If the fault remains, the device latches off, and the MOSFET is disabled until a manual restart is initiated. Alternatively, the ADM1075 can be set to retry only once by isolating the LATCH pin from the SHDN pin. The part can also be configured to retry an infinite number of times with a 10 second interval between restarts by connecting the GPO2 pin to the RESTART pin. The ADM1075 has separate UVx and OV pins for undervoltage and overvoltage detection. The FET is turned off if a nontransient voltage less than the undervoltage threshold (typically −35 V) is detected on the UVx pins or if greater than the overvoltage threshold (typically −80 V) is detected on the OV pin. The operating voltage range of the ADM1075 is programmable via resistor networks on the UVx and OV pins. The hysteresis levels on the overvoltage detectors can also be altered by selecting the appropriate resistors. There are two separate UVx pins to allow accurate programming of hysteresis. In the case of a short circuit, the ADM1075 has a fast response circuit to detect and respond adequately to this event. If the sense voltage exceeds 1.5 times the normal current limit, a high current (750 mA minimum) gate pull-down switch is activated to shut down the MOSFET as quickly as possible. There is a default internal glitch filter of 900 ns. If a longer filter time or different severe overcurrent limit is required, these parameters can be adjusted via the PMBus™ interface. The ADM1075 also includes a 12-bit ADC to provide digital measurement of the voltage and load current. The current is measured at the output of the internal current sense amplifier and the voltage from the ADC_V input. This data can be read across the PMBus interface. The PMBus interface allows a controller to read current, voltage, and power measurements from the ADC. Measurements can be initiated by a PMBus command or can be set up to run continuously. The user can read the latest conversion data whenever it is required. A power accumulator is also provided to report total power consumed in a user specified period (total energy). Up to four unique I2C addresses can be created, depending on the configuration of the ADR pin. The GPO1/ALERT1/CONV and GPO2/ALERT2 outputs can be used as a flag to warn a microcontroller or FPGA of one or more fault/warning conditions becoming active. The fault type and level is programmed across the PMBus, and the user can select which faults/warnings activate the alert. Other functions include • • • Rev. A | Page 4 of 52 PWRGD output, which can be used to enable a power module (the DRAIN and GATE pins are monitored to determine when the load capacitance is fully charged) SHDN input to manually disable the GATE drive RESTART input to remotely initiate a 10 second shutdown Data Sheet ADM1075 SPECIFICATIONS VEE = −48 V, VSENSE = (VSENSE+ − VSENSE−) = 0 mV, shunt regulation current = 10 mA, TJ = −40°C to +105°C, unless otherwise noted. Table 1. Parameter SYSTEM SUPPLY Voltage Transient Immunity Typical Operating Voltage SHUNT REGULATOR Operating Supply Voltage Range, VIN Quiescent Supply Current Undervoltage Lockout, VUVLO_RISING Undervoltage Lockout Hysteresis Power Directly Without Shunt UV PINS—UNDERVOLTAGE DETECTION Undervoltage Rising Threshold, VUVH Undervoltage Falling Threshold, VUVL Total Undervoltage Hysteresis Undervoltage Fault Filter UV Propagation Delay UVL/UVH Input Current OV PIN—OVERVOLTAGE DETECTION Overvoltage Rising Threshold, VOVR Overvoltage Hysteresis Current Overvoltage Fault Filter OV Propagation Delay OV Input Current GATE PIN Gate Voltage High Gate Voltage Low Pull-Up Current Pull-Down Current (Regulation) Pull-Down Current (UV/OV/OC) Pull-Down Current (Severe OC) Pull-Down On-Time (Severe OC) Gate Hold-Off Resistance SENSE+, SENSE− SENSE+, SENSE− Input Current, ISENSEx SENSE+, SENSE− Input Imbalance, IΔSENSEx VCAP Internally Regulated Voltage, VVCAP ISET ISET Reference Select Threshold, VISETRSTH ISET Internal Reference, VCLREF Gain of Current Sense Amplifier, AVCSAMP ISET Input Current, IISET ADM1075-1 ONLY (GAIN = 50) Hot Swap Sense Voltage Hot Swap Sense Voltage Current Limit, VSENSECL Min Typ Max Unit Test Conditions/Comments −35 V V Determined by external component, RSHUNT 13 V 5.5 9.2 600 11.5 mA V mV V 1.01 0.913 7.5 8 50 V V mV μs μs nA 1.01 5.7 3.75 4 50 V μA μs μs nA 13 100 −30 V mV μA μA mA mA μs Ω IGATE = −1.0 μA IGATE = 100 μA VGATE = 0 V to 8 V; VSS = 2 V VGATE ≥ 2 V VGATE ≥ 2 V VGATE ≥ 6 V 100 μA 1 μA VSENSE ≤ 65 mV for ADM1075-1, per individual pin; VSENSE ≤ 130 mV for ADM1075-2, per individual pin IΔSENSEx = ISENSE+ − ISENSE− −200 −80 11.5 12.3 9.2 0.99 0.887 1.0 0.9 100 3.5 5 1 0.99 4.3 1.75 1.0 5 2 1 11 −50 100 5 750 8 12 10 10 1500 2000 16 20 Shunt regulation voltage, IIN = 5.5 mA to 30 mA, maximum IIN dependent on TA, θJA (see the Powering the ADM1075 section) VIN = 13 V When UVL and UVH are tied together UV low to GATE pull-down active OV high to GATE pull-down active 0 V ≤ VIN ≤ 9.2 V 2.66 2.7 2.74 V 0 ≤ IVCAP ≤ 100 μA; CVCAP = 1 μF 1.35 1.5 1 50/25 1.65 100 V V V/V nA If VISET > VISETRSTH an internal 1 V reference (VCLREF) is used Accuracies included in total sense voltage accuracies Accuracies included in total sense voltage accuracies VISET ≤ VCAP 19.4 20 20.6 mV VISET > 1.65 V; VGATE = 3 V; IGATE = 0 μA; VSS ≥ 2 V; VPLIM = 0 V 24.5 19.5 14.5 25 20 15 25.5 20.5 15.5 mV mV mV VISET = 1.25 V; VGATE = 3 V; IGATE = 0 μA; VSS ≥ 2 V; VPLIM = 0 V VISET = 1.0 V; VGATE = 3 V; IGATE = 0 μA; VSS ≥ 2 V; VPLIM = 0 V VISET = 0.75 V; VGATE = 3 V; IGATE = 0 μA; VSS ≥ 2 V; VPLIM = 0 V Rev. A | Page 5 of 52 ADM1075 Parameter Constant Power Active Circuit Breaker Offset, VCBOS Severe Overcurrent Voltage Threshold, VSENSEOC Response Time Glitch Filter Duration Total Response Time ADM1075-2 ONLY (GAIN = 25) Hot Swap Sense Voltage Hot Swap Sense Voltage Current Limit, VSENSECL Constant Power Active Circuit Breaker Offset, VCBOS Severe Overcurrent Voltage Threshold, VSENSEOC1 Response Time Glitch Filter Duration Data Sheet Min 9.4 4.5 1.4 0.6 Typ 10 5 2 0.75 Max 11.0 5.7 2.6 0.95 Unit mV mV mV mV 23 28 38 43 25 30 40 45 27 32 42 47 mV mV mV mV 50 200 ns 500 900 ns 6.2 10.7 μs 44 57 μs 180 300 ns 610 950 ns 7 13 μs 45 60 μs Test Conditions/Comments VISET > 1.65 V; VGATE = 3 V; IGATE = 0 μA; VSS ≥ 2 V; VPLIM = 0.2 V VISET > 1.65 V; VGATE = 3 V; IGATE = 0 μA; VSS ≥ 2 V; VPLIM = 0.4 V VISET > 1.65 V; VGATE = 3 V; IGATE = 0 μA; VSS ≥ 2 V; VPLIM = 1.2 V Circuit breaker voltage, VCB = VSENSECL − VCBOS Activates high current gate pull-down VISET > 1.65 V; VSS ≥ 2 V; optional select through PMBus VISET > 1.65 V; VSS ≥ 2 V; default at power-up VISET > 1.65 V; VSS ≥ 2 V; optional select through PMBus VISET > 1.65 V; VSS ≥ 2 V; optional select through PMBus VISET > 1.65 V; VSS ≥ 2 V; VSENSE step from 18 mV to 52 mV; optional select through PMBus VISET > 1.65 V; VSS ≥ 2 V; VSENSE step from 18 mV to 52 mV; default at power-up VISET > 1.65 V; VSS ≥ 2 V; VSENSE step from 18 mV to 52 mV; optional select through PMBus VISET > 1.65 V; VSS ≥ 2 V; VSENSE step from 18 mV to 52 mV; optional select through PMBus VISET > 1.65 V; VSS ≥ 2 V; VSENSE step from 18 mV to 52 mV; optional select through PMBus VISET > 1.65 V; VSS ≥ 2 V; VSENSE step from 18 mV to 52 mV; default at power-up VISET > 1.65 V; VSS ≥ 2 V; VSENSE step from 18 mV to 52 mV; optional select through PMBus VISET > 1.65 V; VSS ≥ 2 V; VSENSE step from 18 mV to 52 mV; optional select through PMBus 39.2 40 40.8 mV VISET > 1.65 V; VGATE = 3 V; IGATE = 0 μA; VSS ≥ 2 V; VPLIM = 0 V 49.2 39.2 29.2 19 9.2 3 1.1 50 40 30 20 10 4 1.5 50.8 40.8 30.8 21.9 11.2 5.0 1.9 mV mV mV mV mV mV mV 46 56 76 86 50 60 80 90 54 64 84 94 mV mV mV mV VISET = 1.25 V; VGATE = 3 V; IGATE = 0 μA; VSS ≥ 2 V; VPLIM = 0 V VISET = 1.0 V; VGATE = 3 V; IGATE = 0 μA; VSS ≥ 2 V; VPLIM = 0 V VISET = 0.75 V; VGATE = 3 V; IGATE = 0 μA; VSS ≥ 2 V; VPLIM = 0 V VISET > 1.65 V; VGATE = 3 V; IGATE = 0 μA; VSS ≥ 2 V; VPLIM = 0.2 V VISET > 1.65 V; VGATE = 3 V; IGATE = 0 μA; VSS ≥ 2 V; VPLIM = 0.4 V VISET > 1.65 V; VGATE = 3 V; IGATE = 0 μA; VSS ≥ 2 V; VPLIM = 1.2 V Circuit breaker voltage, VCB = VSENSECL − VCBOS Activates high current gate pull-down VISET > 1.65 V; VSS ≥ 2 V; optional select through PMBus VISET > 1.65 V; VSS ≥ 2 V; default at power-up VISET > 1.65 V; VSS ≥ 2 V; optional select through PMBus VISET > 1.65 V; VSS ≥ 2 V; optional select through PMBus 50 200 ns 400 900 ns 6.2 10.7 μs 44 57 μs Rev. A | Page 6 of 52 VISET > 1.65 V; VSS ≥ 2 V; VSENSE step from 36 mV to 104 mV; optional select through PMBus VISET > 1.65 V; VSS ≥ 2 V; VSENSE step from 36 mV to 104 mV; default at power-up VISET > 1.65 V; VSS ≥ 2 V; VSENSE step from 36 mV to 104 mV; optional select through PMBus VISET > 1.65 V; VSS ≥ 2 V; VSENSE step from 36 mV to 104 mV; optional select through PMBus Data Sheet Parameter Total Response Time SOFT START SS Pull-Up Current, ISS Default VSENSECL Limit SS Pull-Down Current TIMER Timer Pull-Up Current (POR), ITIMERUPPOR Timer Pull-Up Current (OC Fault), ITIMERUPFLT Timer Pull-Down Current (Retry), ITIMERDNRT Timer Retry/OC Fault Current Ratio Timer Pull-Down Current (Hold), ITIMERDNHOLD Timer High Threshold, VTIMERH Timer Low Threshold, VTIMERL PLIM PLIM Active Threshold Input Current, IPLIM Minimum Current Clamp, VICLAMP DRAIN DRAIN Voltage at Which PWRGD Asserts ADC_AUX/ADC_V Input Current SHDN PIN Input High Voltage, VIH Input Low Voltage, VIL Glitch Filter Internal Pull-Up Current RESTART PIN Input High Voltage, VIH Input Low Voltage, VIL Glitch Filter Internal Pull-Up Current SPLYGD PIN Output Low Voltage, VOL_LATCH Leakage Current LATCH PIN Output Low Voltage, VOL_LATCH Leakage Current GPO1/ALERT1/CONV PIN Output Low Voltage, VOL_GPO1 ADM1075 Min 180 Typ Max 300 Unit ns 610 950 ns 7 13 μs 45 60 μs −11.5 0.6 −10 1.25 −8.5 1.9 μA mV 1.2 2.5 3.8 mV 100 −4 −63 1.7 μA −2 −57 2.3 0.98 0.03 −3 −60 2 3.33 100 1.0 0.05 0.08 0.09 75 1.9 Test Conditions/Comments VISET > 1.65 V; VSS ≥ 2 V; VSENSE step from 36 mV to 104 mV; optional select through PMBus VISET > 1.65 V; VSS ≥ 2 V; VSENSE step from 36 mV to 104 mV; default at power-up VISET > 1.65 V; VSS ≥ 2 V; VSENSE step from 36 mV to 104 mV; optional select through PMBus VISET > 1.65 V; VSS ≥ 2 V; VSENSE step from 36 mV to 104 mV; optional select through PMBus VSS = 0V When VSENSE reaches this level, ISS is enabled, ramping; VSS = 0 V; ADM1075-1 only (gain = 50) When VSENSE reaches this level, ISS is enabled, ramping; VSS = 0 V; ADM1075-2 only (gain = 25) VSS = 1 V Initial power-on reset; VTIMER = 0.5 V Overcurrent fault; 0.05 V ≤ VTIMER ≤ 1 V After a fault when GATE is off; VTIMER = 0.5 V Defines the limits of the autoretry duty cycle Holds TIMER at 0 V when inactive; VTIMER = 0.5 V 1.02 0.07 μA μA μA % μA V V 100 0.1 100 125 V nA mV VISET > 1.65 V VPLIM ≤ 1 V VPLIM = 1.2 V; VSENSE_IMIN = (VICLAMP ÷ gain) = minimum allowed current control 2 2.1 V IDRAIN ≤ 50 μA 100 nA 0 V ≤ VADC ≤ 1.5 V V V μs μA Pull-up to VIN V V μs μA Pull-up to VIN 0.4 1.5 100 1 V V nA μA ISPLYGD = 1 mA ISPLYGD = 5 mA VSPLYGD ≤ 2 V; SPLYGD pin disabled VSPLYGD ≤ 14 V; SPLYGD pin disabled 0.4 1.5 100 1 V V nA μA ILATCH = 1 mA ILATCH = 5 mA VLATCH ≤ 2 V; LATCH pin disabled VLATCH ≤ 14 V; LATCH pin disabled 0.4 1.5 V V IGPO = 1 mA IGPO = 5 mA 1.1 0.8 1 8 1.1 0.8 1 8 Rev. A | Page 7 of 52 ADM1075 Data Sheet Parameter Leakage Current Min Input High Voltage, VIH Input Low Voltage, VIL Glitch Filter GPO2/ALERT2 PIN Output Low Voltage, VOL_GPO2 1.1 Typ Unit nA μA V V μs Test Conditions/Comments VGPO ≤ 2 V; GPO disabled VGPO = 14 V; GPO disabled Configured as CONV pin Configured as CONV pin Configured as CONV pin 0.4 1.5 100 1 V V nA μA IGPO = 1 mA IGPO = 5 mA VGPO ≤ 2 V; GPO disabled VGPO = 14 V; GPO disabled 0.4 1.5 100 V V V nA IPWRGD = 1 mA IPWRGD = 5 mA ISINK = 100 μA; VOL_PWRGD = 0.4 V VPWRGD ≤ 2 V; PWRGD active 1 μA VPWRGD = 14 V; PWRGD active 0.8 1 Leakage Current PWRGD PIN Output Low Voltage, VOL_PWRGD VIN That Guarantees Valid Output Leakage Current Max 100 1 1 CURRENT AND VOLTAGE MONITORING Current Sense Absolute Error (ADM1075-1) −0.01 0.05 0.07 0.04 ±0.7 ±0.85 ±0.85 ±2.8 ±1.0 ±1.4 ±2.7 ±5.9 % % % % % % % % −0.03 −0.03 −0.03 −0.04 ±0.65 ±0.7 ±0.7 ±1.35 ±0.75 ±0.9 ±1.7 ±3.0 +0.8 % % % % % % % % % 191 263 219 301 μs μs 2.830 3.987 3.243 4.568 ms ms 22.54 31.79 14 25.83 36.43 ms ms μs Current Sense Absolute Error (ADM1075-2) ADC_V/ADC_AUX Absolute Accuracy ADC Conversion Time Power Multiplication Time −0.8 Rev. A | Page 8 of 52 25 mV input range; 128 sample averaging (unless otherwise noted) VSENSE = 25 mV VSENSE = 20 mV VSENSE = 20 mV; 16 sample averaging VSENSE = 20 mV; 1 sample averaging VSENSE = 15 mV VSENSE = 10 mV VSENSE = 5 mV VSENSE = 2.5 mV 50 mV input range; 128 sample averaging (unless otherwise noted) VSENSE = 50 mV VSENSE = 40 mV VSENSE = 40 mV; 16 sample averaging VSENSE = 40 mV; 1 sample averaging VSENSE = 30 mV VSENSE = 20 mV VSENSE = 10 mV VSENSE = 5 mV 0.6 V ≤ VADC ≤ 1.5 V 1 sample of voltage and current; from command received to valid data in register VAUX disabled VAUX enabled 16 samples of voltage and current averaged; from command received to valid data in register VAUX disabled VAUX enabled 128 samples of voltage and current averaged; from command received to valid data in register VAUX disabled (default on power-up) VAUX enabled Data Sheet ADM1075 Parameter ADR PIN Address Set to 00 Input Current for Address 00 Address Set to 01 Address Set to 10 Address Set to 11 Input Current for Address 11 Min Typ 0 −40 135 −1 2.1 −22 150 3 SERIAL BUS DIGITAL INPUTS (SDAI/SDAO, SCL) Input High Voltage, VIH Input Low Voltage, VIL Output Low Voltage, VOL Input Leakage, ILEAK-PIN Nominal Bus Voltage, VDD Capacitive Load per Bus Segment, CBUS Capacitance for SDAI, SDAO, or SCL Pin, CPIN Input Glitch Filter, tSP Max Unit 0.8 V μA kΩ μA V μA 165 +1 10 1.1 V V V μA μA V pF pF ns 0.8 0.4 +10 +5 5.5 400 −10 −5 2.7 5 0 Test Conditions/Comments See Table 6 Connect to VEE VADR = 0 V to 0.8 V Resistor to VEE No connect state; maximum leakage current allowed Connect to VCAP VADR = 2.0 V to VCAP; must not exceed the maximum allowable current draw from VCAP 50 IOL = 4 mA, SDAO only Device is not powered 3 V to 5 V ±10% SERIAL BUS TIMING Table 2. Parameter fSCLK tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tSU;DAT tLOW tHIGH tR 2 tF tOF 2 Min Typ 1.3 0.6 0.6 0.6 300 100 1.3 0.6 20 20 20 + 0.1 × CBUS Max 400 900 300 300 250 Unit kHz μs μs μs μs ns ns μs μs ns ns ns Test Conditions/Comments SDAI and SDAO tied together. tR = (VIL(MAX) – 0.15) to (VIH3V3 + 0.15) and tF = 0.9 VDD to (VIL(MAX) – 0.15); where VIH3V3 = 2.1 V, and VDD = 3.3 V. tLOW SCL tF VIH VIL tHD;DAT tHD;STA SDA tR tHIGH tSU;STA tSU;DAT tSU;STO VIH VIL P tBUF S S Figure 2. Serial Bus Timing Diagram Rev. A | Page 9 of 52 P 09312-002 1 Description Clock frequency Bus free time Start hold time Start setup time Stop setup time SDA 1 hold time SDA1 setup time SCL low time SCL high time SCL, SDA1 rise time SCL, SDA1 fall time SCL, SDA1 output fall time ADM1075 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN Pin to VEE UVL Pin to VEE UVH Pin to VEE OV Pin to VEE ADC_V Pin to VEE ADC_AUX Pin to VEE SS Pin to VEE TIMER Pin to VEE VCAP Pin to VEE ISET Pin to VEE SPLYGD Pin to VEE LATCH Pin to VEE RESTART Pin to VEE SHDN Pin to VEE PWRGD Pin to VEE DRAIN Pin to VEE SCL Pin to VEE SDAI Pin to VEE SDAO Pin to VEE ADR Pin to VEE GPO1/ALERT1/CONV Pin to VEE Rating −0.3 V to +14 V −0.3 V to +4 V −0.3 V to +4 V −0.3 V to +4 V −0.3 V to +4 V −0.3 V to +4 V −0.3 V to (VCAP + 0.3 V) −0.3 V to (VCAP + 0.3 V) −0.3 V to +4 V −0.3 V to +4 V −0.3 V to +18 V −0.3 V to +18 V −0.3 V to +18 V −0.3 V to +18 V −0.3 V to +18 V −0.3 V to (VCAP + 0.3 V) −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to (VCAP + 0.3 V) −0.3 V to +18 V GPO2/ALERT2 Pin to VEE −0.3 V to +18 V PLIM Pin to VEE GATE Pin to VEE SENSE+ Pin to VEE SENSE− Pin to VEE VEE to VEE_G Continuous Current into Any Pin Storage Temperature Range Operating Junction Temperature Range Lead Temperature, Soldering (10 sec) Junction Temperature −0.3 V to +4 V −0.3 V to +18 V −0.3 V to +4 V −0.3 V to +0.3 V −0.3 V to +0.3 V ±10 mA −65°C to +125°C −40°C to +105°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 28-Lead TSSOP 28-Lead LFCSP 1 θJA1 68 35 Measured on JEDEC 4-layer board in still air. ESD CAUTION 300°C 150°C Rev. A | Page 10 of 52 θJC 20 4 Unit °C/W °C/W Data Sheet ADM1075 24 VEE PLIM 6 23 SPLYGD VCAP 7 TOP VIEW (Not to Scale) 22 ADC_AUX ADC_V 8 21 PWRGD ISET 9 20 SCL SS 10 19 SDAI TIMER 11 18 SDAO LATCH 12 17 GPO2/ALERT2 ADR 13 16 GPO1/ALERT1/CONV SHDN 14 15 RESTART 21 SENSE– OV 1 PLIM 2 VCAP 3 ADC_V 4 ISET 5 20 VEE 19 SPLYGD ADM1075 18 ADC_AUX 17 PWRGD TOP VIEW (Not to Scale) SS 6 TIMER 7 16 SCL 15 SDAI NOTES 1. EXPOSED PAD. SOLDER THE EXPOSED PAD TO THE BOARD TO IMPROVE THERMAL DISSIPATION. THE EXPOSED PAD CAN BE CONNECTED TO VEE. 09312-003 ADM1075 23 GATE 5 22 SENSE+ SENSE– OV SDAO 14 25 GPO2/ALERT2 13 4 25 DRAIN 24 VEE_G SENSE+ UVL RESTART 11 26 GPO1/ALERT1/CONV 12 3 27 UVH 26 VIN GATE UVH SHDN 10 VEE_G 27 8 9 28 2 LATCH ADR 1 VIN 09312-004 DRAIN 28 UVL PIN CONFIGURATION AND FUNCTION DESCRIPTION Figure 4. LFCSP Pin Configuration Figure 3. TSSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. TSSOP LFCSP 1 25 Mnemonic DRAIN Description Connect to the drain pin of the FET through a resistor. The current in this resistor is used to determine the VDS of the MOSFET. This is used for PWRGD. 2 26 VIN 3 27 UVH 4 28 UVL 5 1 OV 6 2 PLIM 7 3 VCAP 8 4 ADC_V 9 5 ISET 10 6 SS 11 7 TIMER 12 8 LATCH 13 9 ADR Shunt Regulated Positive Supply to Chip. Connect to the positive supply rail via a shunt resistor. A 1 μF capacitor to VEE is recommended on the VIN pin. Undervoltage Rising Input Pin. An external resistor divider is used from the supply to this pin to allow an internal comparator to detect if the supply is under the UVH limit. Undervoltage Falling Input Pin. An external resistor divider is used from the supply to this pin to allow an internal comparator to detect if the supply is under the UVL limit. Overvoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an internal comparator to detect if the supply is above the OV limit. The voltage on this pin is proportional to the VDS voltage of the FET. As the PLIM voltage changes, the current limit automatically adjusts to maintain constant power across the FET. A capacitor with a value of 1 μF or greater should be placed on this pin to maintain good accuracy. This is an internal regulated supply. This pin can be used as a reference to program the ISET pin voltage. This pin is used to read back the input voltage using the internal ADC. It can be connected to the OV string or a separate divider. This pin allows the current limit threshold to be programmed. The default limit is set when this pin is connected directly to VCAP. Alternatively, using a resistor divider from VCAP, the current limit can be adjusted to achieve a user defined sense voltage. An external reference can also be used. A capacitor is used on this pin to set the inrush current soft start ramp profile. The voltage on the soft start pin controls the current sense voltage limit, allowing control over the inrush current profile. Timer Pin. An external capacitor, CTIMER, sets an initial timing cycle delay and a fault delay. The GATE pin turns off when the voltage on the TIMER pin exceeds the upper threshold. This pin signals the device latching off after an overcurrent fault. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for additional details. PMBus Address Pin. This pin can be tied low, tied to VCAP, left floating, or tied low through a resistor to set four different PMBus addresses. Rev. A | Page 11 of 52 ADM1075 Data Sheet Pin No. TSSOP LFCSP 14 10 Mnemonic 15 11 RESTART 16 12 GPO1/ALERT1 /CONV 17 13 GPO2/ALERT2 18 19 20 21 14 15 16 SDAO SDAI SCL 17 PWRGD 22 23 18 ADC_AUX 19 SPLYGD 24 25 20 21 VEE SENSE− 26 22 SENSE+ 27 23 GATE 28 24 VEE_G EPAD EPAD SHDN Description Drive this pin low to shut down the gate. Internal weak pull-up to VIN. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for additional details. Falling Edge Triggered 10 sec Automatic Restart. The gate remains off for 10 seconds, and then powers back up. Internal weak pull-up to VIN. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for additional details. General-Purpose Digital Output (GPO1). Alert (ALERT1). This pin can be configured to generate an alert signal when one or more fault or warning conditions have been detected. Conversion (CONV). This pin can be used as an input signal to control when a power monitor ADC sampling cycle begins. This pin defaults to indicate FET health mode at power-up. There is no internal pull-up on this pin. General-Purpose Digital Output (GPO2). Alert (ALERT2). This pin can be configured to generate an alert signal when one or more fault or warning conditions have been detected. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for further details. This pin defaults to indicate a seven-attempt fail at power-up. There is no internal pull-up on this pin. PMBus Serial Data Output. This is a split version of the SDA for easy use with optocouplers. PMBus Serial Data Input. This is a split version of the SDA for easy use with optocouplers. PMBus Clock Pin. Open-drain input requires an external resistive pull-up. Power-Good Signal. This pin is used to indicate that the FET is no longer in the linear region and capacitors are fully charged. See the PWRGD section for details on assert and deassert. This pin is used to read back a voltage using the internal ADC. This pin asserts low when the supply is within the UV and OV limits set by the UVx and OV pins. Chip Ground Pin. Must connect to –VIN rail (lowest potential). Negative Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog current limit. The hot swap operation controls the external FET gate to maintain the (VSENSE+ − VSENSE−) sense voltage. This pin also connects to the VEE node, but should be routed separately. Positive Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog current limit. The hot swap operation controls the external FET gate to maintain the (VSENSE+ − VSENSE−) sense voltage. This pin also connects to the FET source node. Gate Output Pin. This pin is the gate drive of an external N-channel FET. It is driven by the FET drive controller. The FET drive controller regulates to a maximum load current by regulating the GATE pin. GATE is held low while the supply is out of the voltage range. Chip Ground Pin. Must connect to –VIN rail (lowest potential). The PCB layout should configure this pin as the gate pull-down return. Exposed Pad. Solder the exposed pad to the board to improve thermal dissipation. The exposed pad can be connected to VEE. Rev. A | Page 12 of 52 Data Sheet ADM1075 TYPICAL PERFORMANCE CHARACTERISTIC 10.0 5.0 4.5 9.5 4.0 RISING 9.0 8.5 3.0 UVLO (V) IIN (mA) 3.5 2.5 2.0 FALLING 8.0 7.5 1.5 7.0 1.0 –35 –20 –5 10 25 40 55 70 85 100 115 TEMPERATURE (°C) 6.0 –50 09312-005 0 –50 –35 –20 Figure 5. IIN vs. Temperature –5 10 25 40 55 TEMPERATURE (°C) 70 85 100 115 85 100 115 09312-008 6.5 0.5 Figure 8. UVLO vs. Temperature 14.0 10 13.5 9 12.5 IIN = 30mA 12.0 IIN = 5.5mA VGATE LOW (mV) VIN (V) 13.0 11.5 8 7 6 11.0 –35 –20 –5 10 25 40 55 70 85 100 115 TEMPERATURE (°C) 4 –50 09312-006 10.0 –50 –35 –20 –5 10 25 40 55 TEMPERATURE (°C) 70 09312-009 5 10.5 Figure 9. VGATE Low vs. Temperature (IGATE = 100 μA) Figure 6. VIN vs. Temperature 100 14 +105°C +85°C +25°C –40°C 12 10 IIN (mA) VGATE HIGH (V) 10 1 0µA 5µA 8 6 4 1 2 3 4 5 6 7 8 VIN (V) 9 10 11 12 13 Figure 7. IIN vs. VIN 0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 10. VGATE High vs. Temperature Rev. A | Page 13 of 52 100 120 09312-010 0.1 09312-007 2 ADM1075 Data Sheet 50 14 45 12 10 IGATE PULL-UP (µA) IGATE PULL-DOWN (mA) 40 8 6 4 35 30 25 20 15 10 2 –20 –5 10 25 40 55 70 85 100 115 TEMPERATURE (°C) 0 09312-011 –35 0 2 4 6 8 10 12 14 VGATE (V) Figure 11. IGATE Pull-Down vs. Temperature 09312-014 5 0 –50 Figure 14. IGATE Pull-Up vs. VGATE 12 0 –2 SS PULL-UP CURRENT (µA) IGATE PULL-DOWN (mA) 10 8 6 4 –4 –6 –8 –10 –12 –14 –16 2 2 4 6 8 VGATE (V) 10 12 14 –20 –50 09312-012 0 –35 –20 –5 10 25 40 55 70 85 100 115 100 115 TEMPERATURE (°C) Figure 12. IGATE Pull-Down vs. VGATE 09312-015 –18 0 Figure 15. SS Pull-Up Current vs. Temperature 0 0 –5 –10 –10 ITIMER PULL-UP (µA) –20 –25 –30 –35 –30 –40 –50 –60 –40 –50 –50 –35 –20 –5 10 25 40 55 70 85 TEMPERATURE (°C) 100 115 –80 –50 –35 –20 –5 10 25 40 55 70 85 TEMPERATURE (°C) Figure 16. ITIMER Pull-Up vs. Temperature Figure 13. IGATE Pull-Up vs. Temperature Rev. A | Page 14 of 52 09312-016 –70 –45 09312-013 IGATE PULL-UP (µA) –20 –15 ADM1075 200 –1 180 –2 160 –3 –4 –5 –6 –7 140 120 100 80 60 –8 40 –9 20 –10 –50 –35 –20 –5 10 25 40 55 70 85 100 115 TEMPERATURE (°C) 0 –50 –35 –20 –5 10 25 40 55 70 85 100 115 100 115 100 115 TEMPERATURE (°C) 09312-020 PLIM THRESHOLD (mV) 0 09312-017 ITIMER POR PULL-UP (µA) Data Sheet Figure 20. PLIM Threshold vs. Temperature Figure 17. ITIMER POR Pull-Up vs. Temperature 200 6 PLIM CURRENT CLAMP (mV) ITIMER RETRY PULL-DOWN (µA) 180 5 4 3 2 1 160 140 120 100 80 60 40 –35 –20 –5 10 25 40 55 70 85 100 115 TEMPERATURE (°C) 0 –50 09312-018 0 –50 –35 –20 –5 10 25 40 55 70 85 TEMPERATURE (°C) 09312–021 20 Figure 21. PLIM Current Clamp vs. Temperature Figure 18. ITIMER Retry Pull-Down vs. Temperature 3.0 1000 2.5 800 VCAP (V) 2.0 600 1.5 400 1.0 200 0.5 0 –50 –35 –20 –5 10 25 40 55 70 85 TEMPERATURE (°C) 100 115 0 –50 –35 –20 –5 10 25 40 55 70 85 TEMPERATURE (°C) Figure 22. VCAP vs. Temperature (IVCAP = 100 μA) Figure 19. TIMER Threshold vs. Temperature Rev. A | Page 15 of 52 09312-022 LOW 09312-019 TIMER THRESHOLD (mV) HIGH ADM1075 Data Sheet 16 UVH 1000 14 UVL 12 RESTART TIME (s) UVx THRESHOLD (mV) 800 600 400 10 8 6 4 200 –35 –20 –5 10 25 40 55 70 85 100 115 TEMPERATURE (°C) 0 –40 09312-023 0 –50 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 23. UVx Threshold vs. Temperature 09312-026 2 Figure 26. Restart Time vs. Temperature 1000 900 SEVERE OC RESPONSE TIME (ns) OV THRESHOLD (mV) 1000 800 600 400 200 900ns GLITCH FILTER 800 700 600 500 400 200ns GLITCH FILTER 300 200 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) 115 0 –50 09312-024 –35 –35 –20 10 25 40 55 70 85 100 115 TEMPERATURE (°C) Figure 27. Severe OC Response vs. Temperature Figure 24. OV Threshold vs. Temperature 60000 100 57.5µs GLITCH FILTER SEVERE OC RESPONSE TIME (ns) 80 60 40 20 SENSE– SENSE+ 0 –20 –40 –60 50000 40000 30000 20000 10.7µs GLITCH FILTER 10000 0 20 40 60 80 VSENSE (mV) 100 120 Figure 25. ISENSE vs. VSENSE 0 –50 –35 –20 –5 10 25 40 55 70 85 TEMPERATURE (°C) Figure 28. Severe OC Response vs. Temperature Rev. A | Page 16 of 52 100 115 09312-028 –80 –100 09312-025 ISENSE (µA) –5 09312-027 100 0 –50 ADM1075 50 1.8 45 1.6 40 1.4 35 VSENSECL (mV) 2.0 1.2 1.0 0.8 0.6 0.4 0.2 0 –50 –35 –20 –5 10 25 40 55 70 = 1.65V = 1.25V = 1.0V = 0.75V = 0.25V = 0.125V 85 100 ADM1075-2 +85°C ADM1075-2 +25°C ADM1075-2 –40°C ADM1075-1 +85°C ADM1075-1 +25°C ADM1075-1 –40°C 30 25 20 15 10 5 115 TEMPERATURE (°C) 0 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 VPLIM (V) Figure 29. Circuit Breaker Offset vs. Temperature, ADM1075-1 Figure 32. VSENSECL vs. PLIM 2.0 25 1.8 1.6 20 ACCURACY (%) 1.4 1.2 1.0 0.8 0.4 0.2 0 –50 –35 –20 –5 10 25 40 55 70 85 100 10 ADM1075-1 5 ADM1075-2 115 TEMPERATURE (°C) 0 0 0.5 1.0 1.5 09312-132 0.6 = 1.65V = 1.25V = 1.0V = 0.75V = 0.25V = 0.125V 15 1.5 09312-133 ISET ISET ISET ISET ISET ISET 09312-030 CIRCUIT BREAKER OFFSET, VCBOS (mV) 0.1 09312-032 ISET ISET ISET ISET ISET ISET 09312-029 CIRCUIT BREAKER OFFSET, VCBOS (mV) Data Sheet ISET (V) Figure 33. Worst-Case Hot Swap VSENSE Accuracy vs. ISET Figure 30. Circuit Breaker Offset vs. Temperature, ADM1075-2 60 50 45 ADM1075-2 50 40 VSENSECL (mV) 30 25 ADM1075-1 20 15 10 40 30 ADM1075-2 20 ADM1075-1 10 5 0 –50 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) 115 09312-031 VSENSECL (mV) 35 0 0 0.5 1.0 ISET (V) Figure 34. Typical Hot Swap VSENSECL vs. ISET Figure 31. VSENSECL vs. Temperature, ISET = 1.65 V Rev. A | Page 17 of 52 ADM1075 Data Sheet 50 140 225% 120 35 SEVERE OC THRESHOLD (mV) SEVERE OC THRESHOLD (mV) 200% 40 150% 30 125% 25 20 15 10 225% 100 200% 80 150% 60 125% 40 ISET UNDEFINED IN GREY AREA 20 5 –35 –20 –5 10 25 40 55 70 85 100 115 TEMPERATURE (°C) 0 0.25 09312-035 0 –50 0.45 0.65 0.85 1.05 1.25 1.45 09312-237 45 1.65 ISET (V) Figure 38. Severe OC Threshold vs. ISET, ADM1075-2 Figure 35. Severe OC Threshold vs. Temperature, ADM1075-1, ISET = 1.65 V 7 100 225% 90 6 5 70 150% ACCURACY (%) 60 125% 50 40 30 3 ADM1075-2 2 20 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) 115 0 09312-036 0 –50 Figure 36. Severe OC Threshold vs. Temperature, ADM1075-2, ISET = 1.65 V 0 10 20 30 40 50 60 SENSE VOLTAGE (mV) 09312-138 1 10 Figure 39. Worst-Case Current Sense Power Monitor Error vs. Current Sense Voltage (VSENSE) 70 2.0 1.8 60 225% 50 1.6 1.4 200% 40 PWRGD GPO1 GPO2 LATCH SPLYGD 1.2 VOL (V) 150% 30 1.0 0.8 125% 0.6 20 ISET UNDEFINED IN GREY AREA 0.4 10 0.2 0 0.25 0.45 0.65 0.85 1.05 1.25 1.45 1.65 ISET (V) 09312-136 SEVERE OC THRESHOLD (mV) ADM1075-1 4 Figure 37. Severe OC Threshold vs. ISET, ADM1075-1 0 0 1 2 3 4 5 6 IOL (mA) Figure 40. VOL vs. IOL Rev. A | Page 18 of 52 7 8 9 10 09312-040 SEVERE OC THRESHOLD (mV) 200% 80 Data Sheet 00 DECODE ADM1075 10 DECODE 11 DECODE 01 DECODE 3.0 2.5 1.5 1.0 0.5 0 –25 –20 –15 –10 –5 IADR (µA) 0 5 09312-041 VADR (V) 2.0 Figure 41. VADR vs. IADR Rev. A | Page 19 of 52 ADM1075 Data Sheet THEORY OF OPERATION When circuit boards are inserted into a live backplane, discharged supply bypass capacitors draw large transient currents from the backplane power bus as they charge. Such transient currents can cause permanent damage to connector pins, as well as dips on the backplane supply that can reset other boards in the system. The ADM1075 is intended to control the powering on and off of a board in a controlled manner, allowing the board to be removed from, or inserted into, a live backplane by protecting it from excess currents. The ADM1075 can reside either on the backplane or on the removable board. A minimal load current requirement is assumed when charging the load capacitance. If the load current is too large relative to the regulation current, it may not be possible to charge the load capacitance. The PWRGD pin can be used to disable the load until the load capacitance is fully charged. POWERING THE ADM1075 The ADM1075 typically operates from a negative supply of −35 V to −80 V and can tolerate transient voltages of up to −200 V. The VIN pin is a positive supply pin with respect to chip ground. It is a current-driven supply and is shunt regulated to 12 V internally. It should be connected to the most positive supply terminal (usually −48 V RTN or 0 V) through a dropper resistor. The resistor should be chosen such that it always supplies enough current to overcome the maximum quiescent supply current of the chip while not exceeding the maximum allowable shunt current. After the system supply range has been established, an appropriate value for the dropper resistor can be calculated. RSHUNT _ MAX = Care must be taken to ensure that the power rating of the shunt resistor is sufficient. The power may be as high as 2 W at extreme supply conditions. Multiple shunt resistors can be used in series or in parallel to share power between resistors. PR _ SHUNT = VI = (VIN _ MAX − VSHUNT _ MIN ) × I MAX where: I MAX = VIN _ MAX − VSHUNT _ MIN The VIN pin provides the majority of the bias current for the device. The remainder of the current needed to control the gate drive and to best regulate the VGS voltage is supplied by the SENSE± pins. The VEE and SENSE− pins are connected to the same voltage rail, although through separate traces to prevent accuracy loss in the sense voltage measurement (see Figure 42). –48V RTN RSHUNT VIN _ MIN − VSHUNT _ MAX 1µF I SHUNT _ MIN CLOAD VIN GATE VEE ISHUNT_MAX can be calculated based on the maximum ambient temperature (TA(MAX)) in the application, the maximum junction temperature (TJ(MAX) = 105°C), and the θJA value of the package from Table 4. Worst-case internal power is at VIN(MAX) from Table 1. θJA × VIN ( MAX ) RSHUNT The power dissipation in the shunt resistor can be saved if a suitable voltage rail is available to power the chip directly. This voltage rail must be well regulated to ensure that it is always greater than the UVLO threshold but less than the minimum shunt regulation voltage. The power directly without shunt specification in Table 1 shows the limits this voltage rail must meet. Note that this voltage is referenced to VEE. I SHUNT _ MAX TJ ( MAX ) − TA( MAX ) 105°C − 80°C = 28 mA 68°C/W × 13 V Tolerance of supplies and resistors should also be accounted for to ensure that the shunt current is always within the desired range. VIN _ MAX − VSHUNT _ MIN where: VIN_MIN and VIN_MAX are the supply voltage extremes (that is, 35 V, 80 V). VSHUNT_MIN and VSHUNT_MAX are the shunt regulator voltage data sheet specifications (see Table 1). ISHUNT_MIN is the maximum quiescent supply current (minimum shunt current). ISHUNT_MAX is the maximum shunt input current. I SHUNT _ MAX = I SHUNT _ MAX = ADM1075 SENSE+ Q1 RSENSE SENSE– VEE 09312-042 RSHUNT _ MIN = For example, the maximum shunt current with a TSSOP device at 80°C maximum ambient can be calculated as Figure 42. Powering the ADM1075 The available shunt current range should be wide enough to accommodate most telecommunication input voltage ranges. In an application where a wider input voltage range is possible, some external circuitry may be required to meet the shunt regulation current specifications. The applications diagram in Figure 43 shows an example of such a circuit, using a Zener diode and a bipolar junction transistor (BJT) device as an external pre-regulator on the −48 V supply. This ensures that the shunt regulation current is always within specification even at the extremes of supply voltage. Rev. A | Page 20 of 52 Data Sheet ADM1075 –48V RTN VIN Rb1 = 100kΩ Rb2 = 640Ω ADM1075 Q1 GATE Ib = 6µA TO 33µA 10.3V (5.5mA TO 10mA) 11V RDROP = 15Ω –48V SENSE+ BIAS CURRENT CLOAD SENSE– VIN 1µF VEE GATE VEE ADM1075 Q1 SENSE+ Figure 45. Connection of Multiple Sense Resistors to SENSE± Pins CURRENT LIMIT REFERENCE RSENSE 09312-137 SENSE– VEE Figure 43. Wide Input Supply Range CURRENT SENSE INPUTS The load current is monitored by measuring the voltage drop across an external sense resistor, RSENSE. An internal current sense amplifier provides a gain of 25 or 50 (depending on the model) to the voltage drop detected across RSENSE. The result is compared to an internal reference and detects when an overcurrent condition occurs. VIN + OVERCURRENT GATE ×25/50 – + – 1V REF SENSE+ Q1 RSENSE VEE I GATE = VCURR _ LIM × g m where gm, the gate transconductance, = 660 μS. An internal current limit reference selector block continuously compares the ISET, soft start, and foldback (derived from PLIM) voltages, determines which is the lowest at any given time, and uses it as the current limit reference. This ensures that the programmed current limit, ISET, is used in normal operation and the soft start and foldback features reduce the current limit when required. The foldback and soft start voltages change during different stages of operation and are clamped to a lower level of 100 mV (typical) to prevent zero current flow due to the current limit being too low. SENSE– 09312-043 ADM1075 The current limit reference voltage determines the load current level to which the ADM1075 limits the current during an overcurrent event. This is the reference voltage to which the gained up current sense voltage is compared to determine if the limit is reached. This current limit voltage, shown in Figure 46, is then converted to a gate current to regulate the GATE pin. Figure 44. Hot-Swap Current Sense Amplifier PLIM ADM1075 The SENSE± inputs can be connected to multiple parallel sense resistors, which can affect the voltage drop detected by the ADM1075. The current flowing through the sense resistors creates an offset, resulting in reduced accuracy. To achieve better accuracy, averaging resistors should be used to sum the sense nodes of each sense resistor, as shown in Figure 45. The typical value for the averaging resistors is 10 Ω. The value of the averaging resistors is chosen to be much greater than the trace resistance between the sense resistor terminals and the inputs to the ADM1075. This greatly reduces the effects of differences in the trace resistances. GATE DRIVE LOGIC ISET REF SELECT VCAP 1.0V CURRENT LIMIT VOLTAGE – CURRENT LIMIT 10µA GATE TIMEOUT + + CURRENT LIMIT CONTROL – SENSE– FLB ( = 0.1/PLIM) SS VEE Figure 46. Current Limit Reference Selection Rev. A | Page 21 of 52 SENSE+ ×25/50 09312-045 CIN 09312-044 18V TO 75V ADM1075 Data Sheet V Assuming VISET equals the voltage on the ISET pin, the resistor divider should be sized to set the ISET voltage as follows: FLB SS 1V VISET = (VSENSE × 50) for ADM1075-1 or VISET = (VSENSE × 25) for ADM1075-2 ISET where VSENSE is the sense voltage limit. The VCAP rail can also be used as the pull-up supply for setting the I2C address. The VCAP pin should not be used for any other purpose. To guarantee accuracy specifications, care must be taken to not load the VCAP pin by more than 100 μA. CURRENT LIMIT REFERENCE t 09312-046 SOFT START 0.1V Figure 47. Interaction of Soft Start, Foldback, and ISET Current Limits SETTING THE CURRENT LIMIT (ISET) The maximum current limit is partially determined by selecting a sense resistor to match the current sense voltage limit on the controller for the desired load current. However, as currents become larger, the sense resistor value becomes smaller and resolution can be difficult to achieve when selecting the appropriate sense resistor value. The ADM1075 provides an adjustable sense voltage limit to deal with this issue. The device allows the user to program the required current sense voltage limit from 15 mV to 25 mV for the ADM1075-1 and from 30 mV to 50 mV for the ADM1075-2. The default value of 20 mV/40 mV is achieved by connecting the ISET pin directly to the VCAP pin (VCAP > 1.65 V ISET reference select threshold). This configures the device to use an internal 1 V reference, which equates to 20 mV/40 mV at the sense inputs (see Figure 48(a)). VCAP VCAP C1 C1 ISET ISET ADM1075 (PARTIAL) VEE (B) 09312-047 (A) When the load current generates a sense voltage equal to VCB, a 10 μA current source is enabled, which charges the SS capacitor and results in a linear ramping voltage on the SS pin. The current limit reference also ramps up accordingly, allowing the regulated load current to ramp up, while avoiding sudden transients during power-up. The SS capacitor value is given by C SS = I SS × t VISET where ISS = 10 μA, and t is the SS ramp time. For example, a 10 nF capacitor gives a soft start time of 1 ms. CONSTANT POWER FOLDBACK (PLIM) R2 VEE VCB = VSENSECL − VCBOS Note that the SS voltage may intersect with the PLIM or foldback (FLB) voltage, and the current limit reference may change to follow PLIM (see Figure 47). This has minimal impact on startup because the output voltage rises at a similar rate to SS. R1 ADM1075 (PARTIAL) A capacitor connected to the SS pin determines the inrush current profile. Before the FET is enabled, the output voltage of the current limit reference selector block is clamped at 100 mV. This, in turn, holds the current limit reference at approximately 2 mV for the ADM1075-1 or 4 mV for the ADM1075-2. When the FET is requested to turn on, the SS pin is held at ground until the voltage between the SENSE+ and SENSE− pins (VSENSE) reaches the circuit breaker voltage, VCB. Figure 48. (a) Fixed 20 mV/40 mV Current Sense Limit (b) Adjustable 15 mV to 50 mV Current Sense Limit To set the sense voltage in the 15 mV to 50 mV range, a resistor divider is used to apply a reference voltage to the ISET pin (see Figure 48(b)). The VCAP pin has a 2.7 V internally generated voltage that can be used to set a voltage at the ISET pin. Foldback is a method that actively reduces the current limit as the voltage drop across the FET increases. It keeps the power across the FET below the programmed value during power-up, overcurrent, or short-circuit events. This allows a smaller FET to be used, resulting in significant cost savings. The foldback method employed is a constant power foldback scheme, meaning power in the FET is held constant regardless of the VDS of the FET. This simplifies the task of ensuring that the FET is always operating within the SOA region. The ADM1075 detects the voltage drop across the FET by monitoring the voltage on the drain of the FET (via the PLIM pin). The device relies on the principle that the source of the FET is at the most negative expected supply voltage, and the magnitude of the drain voltage is relative to that of the VDS of the FET. Using a resistor divider from the drain of the FET to Rev. A | Page 22 of 52 Data Sheet ADM1075 1000 the PLIM pin, the relationship of VDS to VPLIM can be controlled. The foldback voltage, VFLB, is the input to the current limit reference selector block and is defined as 1µs 10µs 100 VFLB = 0.1/VPLIM ID (A) 100µs 1ms 10 1 MAX 200W POWER DISSIPATION 10ms DC 20V × 10A = 200W 60V × 3.33A = 200W 0.1 0.1 1 10 VDS (V) 1000 100 09312-143 The resistor divider should be designed to generate a VFLB voltage equal to ISET when the VDS of the FET (and thus VPLIM) rises above the desired power level. If ISET = 1 V, VPLIM needs to be 0.1 V at the point where constant power takes over (VFLB = ISET). For example, to generate a 200 W constant power limit at 10 A current limit, the maximum VDS is required to be 20 V at the current limit. Therefore, the resistor divider must be 200:1 to generate a 0.1 V PLIM voltage at VDS = 20 V. As VPLIM continues to increase, the current limit reference follows VFLB because it is now the lowest voltage input to the current limit reference selector block. This results in a reduction of the current limit, and, therefore, the regulated load current. To prevent complete current flow restriction, a clamp becomes active when the current limit reference reaches 100 mV. The current limit cannot drop below this level. This 200 W constant power example is illustrated in terms of FET SOA and real scope plots in Figure 49 and Figure 50. Figure 49. FET SOA CURRENT LIMIT ADJUSTING GATE IIN 3,4 VIN When VFLB has control of the current limit reference, the regulation current through the FET is VDS 200W CONSTANT POWER where ID is the external FET drain current, and Gain is the sense amplifier gain. 1,2 M1 ID = 0.1/(VPLIM × Gain × RSENSE) 09312-144 ID = VFLB/(Gain × RSENSE) Figure 50. 200 W Constant Power Scope Plot, CH1 = VIN; CH2 = VDS; CH3 = GATE; CH4 = System Current; M1 = FET Power ID = 0.1/(VDS × D × Gain × RSENSE) where D is the resistor divider factor on PLIM. TIMER Therefore, the FET power is calculated as The TIMER pin handles several timing functions with an external capacitor, CTIMER. There are two comparator thresholds: VTIMERH (1.0 V) and VTIMERL (0.05 V). The four timing current sources are a 3 μA pull-up, a 60 μA pull-up, a 2 μA pull-down, and a 100 μA pull-down. PFET = ID × VDS = 0.1/(D × Gain × RSENSE) Because PFET does not have any dependency on VDS, it remains constant. Therefore, the FET power for a given system can be set by adjusting the divider (D) driving the PLIM pin. The limits to the constant power system are when VFLB > ISET (or 1 V if VISET > VISETRSTH) or when VFLB < 100 mV (100 mV max clamp on VCLREF). With an ISET voltage of 1 V, this gives a 10:1 foldback current range. These current and voltage levels, together with the value of CTIMER chosen by the user, determine the initial timing cycle time, the fault current limit time, and the hot swap retry duty cycle. The TIMER capacitor value is determined using the following equation: CTIMER = (tON × 60 μA)/VTIMERH where tON is the time that the FET is allowed to spend in regulation. The choice of CTIMER is based on matching this time with the SOA requirements of the FET. Foldback can be used here to simplify selection. When VIN is connected to the backplane supply, the internal supply of the ADM1075 must be charged up. A very short time later when the internal supply is fully up and above the undervoltage lockout voltage (UVLO), the device comes out of reset. During this first short reset period, the GATE and TIMER pins are both held low. The ADM1075 then goes through an initial Rev. A | Page 23 of 52 ADM1075 Data Sheet timing cycle. The TIMER pin is pulled up with 3 μA. When the TIMER reaches the VTIMERH threshold (1.0 V), the first portion of the initial cycle is complete. The 100 μA current source then pulls down the TIMER pin until it reaches VTIMERL (0.05 V). The initial cycle duration is related to CTIMER by the following equation: t INITIAL = VTIMERH × CTIMER (VTIMERH − VTIMERL ) × CTIMER + 3 μA 100 μA For example, a 470 nF capacitor results in a power-up delay of approximately 160 ms. Provided the UV and OV detectors are inactive when the initial timing cycle terminates, the device is ready to start a hot swap operation. When the voltage across the sense resistor reaches the circuit breaker trip voltage, VCB, the 60 μA timer pull-up current is activated, and the gate begins to regulate the current at the current limit. This initiates a ramp-up on the TIMER pin. If the sense voltage falls below this circuit breaker trip voltage before the TIMER pin reaches VTIMERH (1.0 V), the 60 μA pull-up is disabled, and the 2 μA pull-down is enabled. The circuit breaker trip voltage is not the same as the hot swap sense voltage current limit. There is a small circuit breaker offset, VCBOS, which means that the timer actually starts a short time before the current reaches the defined current limit. However, if the overcurrent condition is continuous and the sense voltage remains above the circuit breaker trip voltage, the 60 μA pull-up remains active and the FET remains in regulation. This allows the TIMER pin to reach VTIMERH and initiate the GATE shutdown. The LATCH pin is pulled low immediately. In latch-off mode, the TIMER pin is switched to the 2 μA pulldown when it reaches the VTIMERH threshold. The LATCH pin remains low. While the TIMER pin is being pulled down, the hot swap controller is kept off and cannot be turned back on. When the voltage on the TIMER pin goes below the VTIMERL threshold, the hot swap controller can be reenabled by toggling the UVx pin or by using the PMBus OPERATION command to toggle the ON bit from on to off and then on again. HOT SWAP FAULT RETRY The ADM1075 turns off the FET after an overcurrent fault. With the default pin configuration, the part latches off after an overcurrent fault and LATCH goes active low. This condition can then be reset by either a power cycling event or a low signal to either the SHDN input or RESTART input. It can also be reset by toggling the UVx pin, using the PMBus operation command or the PMBus power cycle command. If the LATCH pin is connected to the SHDN pin, the part makes seven attempts to hot swap before latching off. In this mode, the part uses the TIMER pin to time a delay between each attempt. In this way, a large load capacitance can be charged using consecutive current limit periods. The part can also be configured to autoretry an infinite number of times with a 10 second cooling period between each retry. Connecting LATCH to RESTART means that the part makes one hot swap attempt between each cooling period. Connecting LATCH to SHDN and GPO2/ALERT2 to RESTART means that the part makes seven hot swap attempts between each cooling period. The duty cycle of the automatic retry cycle is set by the ratio of 2 μA/60 μA, which approximates to being on ~4% of the time. The value of the timer capacitor determines the on time of this cycle, which is calculated as follows: tON = VTIMERH × (CTIMER/60 μA) tOFF = (VTIMERH − VTIMERL) × (CTIMER/2 μA) A 470 nF capacitor on the TIMER pin gives ~8 ms of on time (for example, to meet 10 ms SOA), and ~220 ms off time. FAST RESPONSE TO SEVERE OVERCURRENT The ADM1075 features a very fast detection circuit that quickly responds to severe overcurrent events such as short circuits. Such an event may cause catastrophic damage if not controlled very quickly. A fast response circuit ensures that the ADM1075 detects an overcurrent event at approximately 150% of the normal current limit (ISET) and responds and controls the current within 1 μs in most cases. The severe overcurrent threshold and glitch filter times are digitally programmable through the PMBus. The threshold can be selected as 125%, 150%, 200%, or 225% of the normal current limit, and the glitch filter time can be set to 200 ns, 900 ns, 10.7 μs, or 57 μs. This sets a maximum response time of 300 ns, 950 ns, 13 μs, or 60 μs. UV AND OV The ADM1075 monitors the supply voltage for undervoltage (UV) and overvoltage (OV) conditions. The OV pin is connected to the input of an internal voltage comparator, and its voltage level is internally compared with a 1 V voltage reference. The user can program the value of the OV hysteresis by varying the top resistor of the resistor divider on the pin. This impedance in combination with the 5 μA OV hysteresis current (current turned on after OV trips) sets the OV hysteresis voltage. OVRISING = OVTHRESHOLD × RTOP + R BOTTOM R BOTTOM OVFALLING ≈ OVRISING − (RTOP × 5 μA ) The UV detector is split into two separate pins, UVH and UVL. The voltage on the UVH pin is compared internally to a 1 V reference, whereas the UVL pin is compared to a 0.9 V reference. Therefore, if the pins are tied together, the UV hysteresis is 100 mV. The hysteresis can be adjusted by placing a resistor between UVL and UVH. Figure 51 illustrates the positive voltage monitoring input connection. An external resistor network divides the supply voltage for monitoring. An undervoltage event is detected when Rev. A | Page 24 of 52 Data Sheet ADM1075 the voltage connected to the UVL pin falls below 0.9 V, and the gate is shut down using the 10 mA pull-down device. The fault is cleared after UVH pin rises above 1.0 V. pin is used by the power-good circuitry to determine when PWRGD can be asserted. A resistor is required on the DRAIN pin to limit current on the pin to 50 μA. A 2 MΩ resistor is suitable to limit the current in most cases. Similarly, when an overvoltage event occurs and the voltage on the OV pin exceeds 1 V, the gate is shut down using the 10 mA pull-down device. SPLYGD The SPLYGD output indicates when the input supply is within the programmed voltage window. This is an open-drain output. An external pull-up resistor is required on this pin. –48V RTN (0V) RSHUNT C1 LATCH VIN UVH 1V + – 0.9V + – 1V – + UVL OV GATE ENABLE LOGIC ADM1075 GATE The LATCH output signals that the device has latched off after an overcurrent fault. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for additional details. Q1 SENSE+ RSENSE SHDN SENSE– The SHDN pin is a level-triggered input that allows the user to command a shutdown of the hot swap function. When this input is set low, the GATE output is switched to VEE to turn the FET off. This pin has an internal pull-up of approximately 8 μA, allowing it to be driven by an open-drain pull-down output or a push-pull output. The input threshold is ~1 V. 09312-048 VEE –48V Figure 51. Undervoltage and Overvoltage Supply Monitoring The maximum rating on the UVH pin is 4 V and the UVH threshold is 1 V. This limits the maximum input voltage to minimum input voltage ratio to 4:1. For example, if the UVH threshold is set at 20 V, the maximum input voltage is 80 V so as not to exceed the maximum ratings of the pin. If a wider input range is required, some protection circuitry is required on the UV pins to limit them to less than 4 V. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for additional details. PWRGD The PWRGD output indicates the status of the output voltage. As shown in Figure 52, the PWRGD output is derived from the DRAIN pin voltage. It is an open-drain output that pulls low when the voltage on DRAIN is less than 2 V and the GATE pin voltage is near its 12 V rail (power good). When a fault occurs or hot swap is turned off, the open-drain pull-down is disabled, allowing PWRGD to go high (power bad). PWRGD is guaranteed to be in a valid state for VIN ≥ 1 V. FET DRAIN IDRAIN = 50µA MAX RDRAIN DRAIN DIODE CLAMPS DRAIN TO 2V 2V 11V S Q R Q The UVH or UVL pin may work better as a system on/off pin if required. Toggling the UVx pin clears any faults (including GPO2/ALERT2 low after seven retry attempts). A switch shorting UVH or UVL to VEE works as an on/off switch. RESTART PWRGD 09312-049 GATE HOT SWAP DISABLE SIGNAL Care should be taken if using the SHDN pin as an on/off pin. Pulling the SHDN low always turns off the gate. However, taking SHDN high again turns on hot swap only if there have been less than seven faults/shutdown events within a 10 second period. The retry scheme is configured to set GPO2/ALERT2 low after seven faults. The SHDN pin cannot clear the GPO2/ ALERT2 fault. The retry counter is cleared after 10 seconds of power good. Therefore, this is not an issue if there is never going to be more than seven SHDN events within a 10 second period. Figure 52. Generation of PWRGD Signal DRAIN Because the source of the FET is always at or near the most negative system supply, the drain voltage is a close approximation to the VDS of the FET. When the voltage at the DRAIN pin is less than 2 V, it is assumed the FET is turned on. The DRAIN The RESTART pin is a falling edge triggered input that allows the user to command a 10 second automatic restart. When this input is set low, the gate turns off for 10 seconds, and then powers back up. The pin is falling edge triggered; therefore, holding RESTART low for more than 10 seconds generates only one restart. This pin has an internal pull-up of approximately 8 μA, allowing it to be driven by an open-drain pull-down output or a push-pull output. The input threshold is ~1 V. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for additional details. Rev. A | Page 25 of 52 ADM1075 Data Sheet The ADM1075 features a method of detecting a shorted pass FET. The FET health status can be used to generate an alert on the GPO1/ALERT1/CONV and GPO2/ALERT2 pins. By default, at power-up, an alert is generated on GPO1/ALERT1/CONV if the FET health status indicates a bad FET is present. FET health is considered bad if all of the following conditions are true: • • • The ADM1075 is holding the FET off, for example, during the initial power-on cycle time. VSENSE > 2 mV for the ADM1075-1 and 4 mV for the ADM1075-2. VGATE < ~1 V. POWER MONITOR The ADM1075 features an integrated ADC that accurately measures the current sense voltage and the ADC_V voltage. It can also optionally monitor the ADC_AUX voltage. The measured input voltage (ADC_V) and the current being delivered to the load are multiplied to give a power value that can be read back. Each power value is also added to an accumulator that can be read back to allow an external device to calculate the energy consumption of the load. The PEAK_IOUT, PEAK_VIN, and PEAK_VAUX commands can be used to read the highest peak current or voltage since the value was last cleared. An averaging function is provided for voltage and current that allows a number of samples to be averaged by the ADM1075. This function reduces the need for postprocessing of sampled data by the host processor. The number of samples that can be averaged is 2N, where N is in the range of 0 to 7. The power monitor current sense amplifier is bipolar and can measure both positive and negative currents. It has two input ranges and can be selected using the PMBus interface. The input ranges are ±25 mV and ±50 mV. The two basic modes of operation for the power monitor are single shot and continuous. In single-shot mode, the power monitor samples the input voltage and current a number of times, depending on the averaging value selected by the user. The ADM1075 returns a single value corresponding to the average voltage and current measured. When configured for continuous mode, the power monitor continuously samples voltage and current, making the most recent sample available to be read. The ADC runs in continuous mode by default at power-up. The single-shot mode can be triggered in a number of ways. The simplest is by selecting the single-shot mode using the PMON_CONFIG command and writing to the CONVERT bit using the PMON_CONTROL command. The CONVERT bit can also be written as part of a PMBus group command. Using a group command allows multiple devices to be written to as part of the same I2C bus transaction, with all devices executing the command when the stop condition appears on the bus. In this way, several devices can be triggered to sample at the same time. When the GPO1/ALERT1/CONV pin is set to the convert (CONV) mode, an external hardware signal can be used to trigger the single-shot sampling of one or more parts at the same time. Each time a current sense and input voltage measurement is taken, a power calculation is performed, multiplying the two measurements together. This can be read from the device using the READ_PIN command, returning the input power. At the same time, the calculated power value is added to a power accumulator register that may increment a rollover counter if the value exceeds the maximum accumulator value, and that also increments a power sample counter. The power accumulator and power sample counter are read back using the same READ_EIN command to ensure that the accumulated value and sample count are from the same point in time. The bus host reading the data assigns a timestamp to show when the data is read. By calculating the time difference between consecutive uses of READ_EIN and determining the delta in power consumed, it is possible for the host to determine the total energy consumed over that period. ISOLATION Isolation is usually required in −48 V systems because there can be a large voltage difference between different ground planes in the system. The ADM1075 is referenced to −48 V, whereas the MCU is usually referenced to 0 V. In almost all cases, the I2C signals must be isolated. Any other ADM1075 digital input and output signals that go to or come from the MCU must also be isolated. Analog Devices, Inc., provide a range of digital isolators using iCoupler® technology. iCoupler technology is based on chip scale transformers rather than the LEDs and photodiodes used in optocouplers. The ADuM1250 is a dual I2C isolator and can be used in conjunction with the ADM1075 for I2C isolation. –48V SIDE (PRIMARY) VDD1 100nF 5V –48V 10kΩ SDA 10kΩ SCL –48V ADuM1250 VDD1 ISOLATED SIDE (SECONDARY) 5V_ISO VDD2 SCL2 SDA2 SDA_ISO SCL1 SCL2 SCL_ISO GND1 GND2 100nF GND_ISO GND_ISO 09312-147 FET HEALTH Figure 53. ADuM1250 I2C Isolation In cases where more digital signals need to be isolated, the ADuM3200 is a dual-channel digital isolator whereas the ADuM5404 is a quad-channel isolator with isoPower®, an integrated, isolated dc-to-dc converter. The ADuM1250 and ADuM3200 must be powered from both the primary and secondary sides. The ADuM5404 only needs to Rev. A | Page 26 of 52 Data Sheet ADM1075 If a voltage rail is available on the primary side (3.3 V or 5 V referenced to VEE), that can be used to power the chip directly. Otherwise, the ADM1075 shunt voltage and/or the −48 V supply can be regulated down to power the part. A simple emitter follower circuit achieves this, as shown in Figure 54. 12V (SHUNT) –48V RTN 1kΩ 0.33W 20kΩ 6V 20k isoPower uses high frequency switching elements to transfer power through its transformer. Special precautions must be taken during printed circuit board (PCB) layout to meet emissions standards. See the AN-0971 Application Note for board layout recommendations. 5V AUX 1µF –48V –48V 09312-148 be powered from the secondary side and can provide power across the isolation barrier via the integrated dc-to-dc converter. Therefore, the ADuM5404 can be used to power the primary side of the ADuM1250 if both are used on the board. Some extra care is required if using the ADuM5404 to power the ADuM3200. If the power at the secondary side is enabled by the ADM1075, the isoPower solution may not work. Because isoPower is unpowered in this case, the ADuM3200 outputs are in an undefined state. If the SHDN input comes from the ADuM3200, it may be held low, and the ADM1075 never turns on the FET or enables power at the secondary side. Figure 54. Powering iCoupler from −48 V Supply Powering the iCouplers from the secondary side is usually straightforward because there is often a suitable voltage rail available. However, there is not always a suitable voltage rail available on the primary side (−48 V side). If the ADuM5404 is not used on the system, the ADuM1250 can be powered on the primary side in a number of different ways. Rev. A | Page 27 of 52 ADM1075 Data Sheet PMBus INTERFACE The I2C bus is a common, simple serial bus used by many devices to communicate. It defines the electrical specifications, the bus timing, the physical layer, and some basic protocol rules. SMBus is based on I2C and aims to provide a more robust and fault-tolerant bus. Functions such as bus timeout and packet error checking are added to help achieve this robustness, along with more specific definitions of the bus messages used to read and write data to devices on the bus. PMBus is layered on top of SMBus and, in turn, on I2C. Using the SMBus defined bus messages, PMBus defines a set of standard commands that can be used to control a device that is part of a power chain. The ADM1075 command set is based upon the PMBus™ Power System Management Protocol Specification, Part I and Part II, Revision 1.2. This version of the standard is intended to provide a common set of commands for communicating with dc-to-dc type devices. However, many of the standard PMBus commands can be mapped directly to the functions of a hot swap controller. Part I and Part II of the PMBus standard describe the basic commands and how they can be used in a typical PMBus setup. The following sections describe how the PMBus standard and the ADM1075 specific commands are used. DEVICE ADDRESSING The ADM1075 is available in two models: the ADM1075-1 and ADM1075-2. The PMBus address is seven bits in size. The upper five bits (MSBs) of the address word are fixed and are different for each model, as follows: • • ADM1075-1: Base address is 00100xx (0x10) ADM1075-2: Base address is 00110xx (0x18) The ADM1075-1 and ADM1075-2 have a single ADR pin that is used to select one of four possible addresses for a given model. The ADR pin connection selects the lowest two bits (LSBs) of the 7-bit address word (see Table 6). SMBus PROTOCOL USAGE All I2C transactions on the ADM1075 are performed using SMBus defined bus protocols. The following SMBus protocols are implemented by the ADM1075: • • • • • • • PACKET ERROR CHECKING The ADM1075 PMBus interface supports the use of the packet error checking (PEC) byte that is defined in the SMBus standard. The PEC byte is transmitted by the ADM1075 during a read transaction or sent by the bus host to the ADM1075 during a write transaction. The ADM1075 supports the use of PEC with all the SMBus protocols that it implements. The use of the PEC byte is optional. The bus host can decide whether to use the PEC byte with the ADM1075 on a messageby-message basis. There is no need to enable or disable PEC in the ADM1075. The PEC byte is used by the bus host or the ADM1075 to detect errors during a bus transaction, depending on whether the transaction is a read or a write. If the host determines that the PEC byte read during a read transaction is incorrect, it can decide to repeat the read if necessary. If the ADM1075 determines that the PEC byte sent during a write transaction is incorrect, it ignores the command (does not execute it) and sets a status flag. Within a group command, the host can choose to send or not send a PEC byte as part of the message to the ADM1075. Table 6. PMBus Addresses and ADR Pin Connection Value of Address LSBs 00 01 10 11 Send byte Receive byte Write byte Read byte Write word Read word Block read ADR Pin Connection Connect to VEE 150 kΩ resistor to VEE No connection (floating) Connect to VCAP Rev. A | Page 28 of 52 Data Sheet ADM1075 R = read bit W = write bit A = acknowledge bit (0) A = acknowledge bit (1) SMBus MESSAGE FORMATS Figure 55 to Figure 63 show all the SMBus protocols supported by the ADM1075, along with the PEC variant. In these figures, unshaded cells indicate that the bus host is actively driving the bus; shaded cells indicate that the ADM1075 is driving the bus. “A” represents the ACK (acknowledge) bit. The ACK bit is typically active low (Logic 0) if the transmitted byte is successfully received by a device. However, when the receiving device is the bus master, the acknowledge bit for the last byte read is a Logic 1, indicated by A. Figure 55 to Figure 63 use the following abbreviations: S = start condition Sr = repeated start condition P = stop condition SLAVE ADDRESS W A DATA BYTE A S SLAVE ADDRESS W A DATA BYTE A P PEC A P PEC A P 09312-050 S MASTER TO SLAVE SLAVE TO MASTER Figure 55. Send Byte and Send Byte with PEC SLAVE ADDRESS R A DATA BYTE A S SLAVE ADDRESS R A DATA BYTE A P 09312-051 S MASTER TO SLAVE SLAVE TO MASTER Figure 56. Receive Byte and Receive Byte with PEC SLAVE ADDRESS W A COMMAND CODE A DATA BYTE A S SLAVE ADDRESS W A COMMAND CODE A DATA BYTE A P PEC A P 09312-052 S MASTER TO SLAVE SLAVE TO MASTER Figure 57. Write Byte and Write Byte with PEC SLAVE ADDRESS W A COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE A S SLAVE ADDRESS W A COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE A P PEC A P 09312-053 S MASTER TO SLAVE SLAVE TO MASTER Figure 58. Read Byte and Read Byte with PEC SLAVE ADDRESS W A COMMAND CODE A DATA BYTE LOW A DATA BYTE HIGH A S SLAVE ADDRESS W A COMMAND CODE A DATA BYTE LOW A DATA BYTE HIGH A P PEC A MASTER TO SLAVE SLAVE TO MASTER Figure 59. Write Word and Write Word with PEC SLAVE ADDRESS DATA BYTE HIGH S W A SLAVE ADDRESS DATA BYTE HIGH COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE LOW A A COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE LOW A P W A A PEC A P 09312-055 S P 09312-054 S MASTER TO SLAVE SLAVE TO MASTER Figure 60. Read Word and Read Word with PEC Rev. A | Page 29 of 52 ADM1075 S Data Sheet SLAVE ADDRESS W DATA BYTE 1 S A DATA BYTE 2 A SLAVE ADDRESS W DATA BYTE 1 COMMAND CODE A A SLAVE ADDRESS DATA BYTE N COMMAND CODE DATA BYTE 2 A Sr A R A SLAVE ADDRESS DATA BYTE N A BYTE COUNT = N A A BYTE COUNT = N A P R A A PEC P 09312-056 A A Sr MASTER TO SLAVE SLAVE TO MASTER Figure 61. Block Read and Block Read with PEC ONE OR MORE DATA BYTES S DEVICE 1 ADDRESS W A COMMAND CODE 1 A LOW DATA BYTE Sr DEVICE 2 ADDRESS W A COMMAND CODE 2 A LOW DATA BYTE Sr DEVICE N ADDRESS W A COMMAND CODE N A LOW DATA BYTE A HIGH DATA BYTE A ONE OR MORE DATA BYTES A HIGH DATA BYTE A ONE OR MORE DATA BYTES HIGH DATA BYTE A P 09312-057 A MASTER TO SLAVE SLAVE TO MASTER Figure 62. Group Command ONE OR MORE DATA BYTES S DEVICE 1 ADDRESS W A COMMAND CODE 1 A LOW DATA BYTE Sr DEVICE 2 ADDRESS W A COMMAND CODE 2 A LOW DATA BYTE Sr DEVICE N ADDRESS W A COMMAND CODE N A LOW DATA BYTE A HIGH DATA BYTE A PEC 1 A A PEC 2 A A PEC N A P ONE OR MORE DATA BYTES A HIGH DATA BYTE ONE OR MORE DATA BYTES HIGH DATA BYTE 09312-058 A MASTER TO SLAVE SLAVE TO MASTER Figure 63. Group Command with PEC GROUP COMMANDS The PMBus standard defines what are known as group commands. Group commands are single bus transactions that send commands or data to more than one device at the same time. Each device is addressed separately, using its own address; there is no special group command address. A group command transaction can contain only write commands that send data to a device. It is not possible to use a group command to read data from devices. From an I2C protocol point of view, a normal write command consists of the following: • • • • I2C start condition Slave address bits and a write bit (followed by ACK from the slave device) One or more data bytes (each of which is followed by ACK from the slave device) I2C stop condition to end the transaction A group command differs from a nongroup command in that, after the data is written to one slave device, a repeated start condition is put on the bus followed by the address of the next slave device and data. This continues until all the devices have been written to, at which point the stop condition is put on the bus by the master device. The format of a group command and a group command with PEC is shown in Figure 63. Each device that is written to as part of the group command does not immediately execute the command written. The device must wait until the stop condition appears on the bus. At that point, all devices execute their commands at the same time. Using a group command, it is possible, for example, to turn multiple PMBus devices on or off at the same time. In the case of the ADM1075, it is also possible to issue a power monitor command that initiates a conversion, causing multiple ADM1075 devices to sample together at the same time. This is analogous to connecting the GPO1/ALERT1/CONV pins together and configuring the pin in the convert (CONV) mode to drive the power monitor sampling. Rev. A | Page 30 of 52 Data Sheet ADM1075 HOT SWAP CONTROL COMMANDS POWER_CYCLE Command OPERATION Command The POWER_CYCLE command can be used to request that the ADM1075 be turned off for ~10 seconds and then back on. This command can be useful if the processor that controls the ADM1075 is also powered off when the part is turned off. This command allows the processor to request that the ADM1075 turn off and back on again as part of a single command. The GATE pin that drives the FET is controlled by a dedicated hot swap state machine. The UVH, UVL, and OV input pins, along with the TIMER and SS pins and the current sense, all feed into the state machine and control when and how strongly the gate is turned off. It is also possible to control the hot swap GATE output using commands over the PMBus interface. The OPERATION command can be used to request the hot swap output to turn on. However, if the UV pin indicates that the input supply is less than required, the hot swap output is not turned on, even if the OPERATION command indicates that the output should be enabled. If the OPERATION command is used to disable the hot swap output, the GATE pin is held low, even if all hot swap state machine control inputs indicate that it can be enabled. The default state of the OPERATION command ON bit is 1; therefore, the hot swap output is always enabled when the ADM1075 comes out of UVLO. If the ON bit is never changed, the UV input is the hot swap master on/off control signal. By default, at power-up, the OPERATION command is disabled and must be enabled using the DEVICE_CONFIG command. This prevents inadvertent shutdowns of the hot swap controller by software. If the ON bit is set to 0 while the UV signal is high, the hot swap output is turned off. If the UV signal is low or if the OV signal is high, the hot swap output is already off and the status of the ON bit has no effect. If the ON bit is set to 1, the hot swap output is requested to turn on. If the UV signal is low or if the OV signal is high, setting the ON bit to 1 has no effect, and the hot swap output remains off. It is possible to determine at any time whether the hot swap output is enabled using the STATUS_BYTE or the STATUS_WORD command (see the Status Commands section). The OPERATION command can also be used to clear any latched faults in the status registers. To clear latched faults, set the ON bit to 0, and then reset it to 1. DEVICE_CONFIG Command The DEVICE_CONFIG command is used to configure certain settings within the ADM1075, for example, to modify the duration of the severe overcurrent glitch filter and to set the trip threshold. This command is also used to configure the polarity of the second IOUT current warnings. At power-up, the OPERATION command is disabled, and the ADM1075 responds with a NACK if the OPERATION command is received. To allow use of the OPERATION command, the OPERATION_CMD_EN bit must be set using the DEVICE_CONFIG command. ADM1075 INFORMATION COMMANDS CAPABILITY Command The CAPABILITY command can be used by host processors to determine the I2C bus features supported by the ADM1075. The features reported are the maximum bus speed and whether the device supports the packet error checking (PEC) byte and the SMBAlert reporting function. PMBUS_REVISION Command The PMBUS_REVISION command reports the version of Part I and Part II of the PMBus standard. MFR_ID, MFR_MODEL, and MFR_REVISION Commands The MFR_ID, MFR_MODEL, and MFR_REVISION commands return ASCII strings that can be used to facilitate detection and identification of the ADM1075 on the bus. These commands are read using the SMBus block read message type. This message type requires that the ADM1075 return a byte count corresponding to the length of the string data that is to be read back. STATUS COMMANDS The ADM1075 provides a number of status bits that are used to report faults and warnings from the hot swap controller and the power monitor. These status bits are located in six different registers that are arranged in a hierarchy. The STATUS_BYTE and STATUS_WORD commands provide eight bits and 16 bits of high level information, respectively. The STATUS_BYTE and STATUS_WORD commands contain the most important status bits, as well as pointer bits that indicate whether any of the four other status registers need to be read for more detailed status information. In the ADM1075, a particular distinction is made between faults and warnings. A fault is always generated by the hot swap controller and is defined by hardware component values. Three events can generate a fault. • • • Overcurrent condition that causes the hot swap timer to time out Overvoltage condition on the OV pin Undervoltage condition on the UVx pin When a fault occurs, the hot swap controller always takes some action, usually to turn off the GATE pin, which is driving the FET. A fault can also generate an SMBAlert on one or both of the GPOx/ALERTx pins. Rev. A | Page 31 of 52 ADM1075 Data Sheet All warnings in the ADM1075 are generated by the power monitor sampling voltage and current and then comparing these measurements to the threshold values set by the various limit commands. A warning has no effect on the hot swap controller, but it may generate an SMBAlert on one or both of the GPOx/ALERTx output pins. When a fault or warning status bit is set, it always means that the status condition—fault or warning—is active or was active at some point in the past. When a fault or warning bit is set, it is latched until it is explicitly cleared using either the OPERATION or the CLEAR_FAULTS command. Some other status bits are live, that is, they always reflect a status condition and are never latched. GPO AND ALERT PIN SETUP COMMANDS Two multipurpose pins are provided on the ADM1075: GPO1/ALERT1/CONV and GPO2/ALERT2. The GPO1/ALERT1/CONV and GPO2/ALERT2 pins have two output modes of operation. These pins can be configured independently over the PMBus as general-purpose digital outputs. They can both be configured to generate an SMBAlert when one or more fault/warning status bits become active in the PMBus status registers. For an example of how to configure these pins to generate an SMBAlert and how to respond and clear the condition, see the Example Use of SMBus Alert Response Address section. The GPO1/ALERT1/CONV pin can also be configured as an input (CONV) to drive the power monitor in single-shot run mode and to control when a power monitor ADC sampling cycle begins. This function can be used to synchronize sampling across multiple ADM1075 devices, if required. STATUS_BYTE and STATUS_WORD Commands The STATUS_BYTE and STATUS_WORD commands can be used to obtain a snapshot of the overall part status. These commands indicate whether it is necessary to read more detailed information using the other status commands. The low byte of the word returned by the STATUS_WORD command is the same byte returned by the STATUS_BYTE command. The high byte of the word returned by the STATUS_ WORD command provides a number of bits that can be used to determine which of the other status commands must be issued to obtain all active status bits. STATUS_INPUT Command The STATUS_INPUT command returns a number of bits relating to voltage faults and warnings and power warnings on the input supply. STATUS_IOUT Command ALERT1_CONFIG and ALERT2_CONFIG Commands Using combinations of bit masks, the ALERT1_CONFIG and ALERT2_CONFIG commands can be used to select the status bits that, when set, generate an SMBAlert signal to a processor. They can also be used to set a GPO mode on the pin, so that it is under software control. If this mode is set, the SMBAlert masking bits are ignored. On the ADM1075, one of the inputs can also be configured as a hardware-based convert control signal. If this mode is set, the GPO and SMBAlert masking bits are ignored. POWER MONITOR COMMANDS The ADM1075 provides a high accuracy, 12-bit current and voltage power monitor. The power monitor can be configured in a number of different modes of operation and can run in either continuous mode or single-shot mode with a number of different sample averaging options. The STATUS_IOUT command returns a number of bits relating to current faults and warnings on the output supply. STATUS_VAUX Command The STATUS_VAUX command returns a number of bits relating to current faults and warnings on the output supply. The power monitor can measure the following: STATUS_MFR_SPECIFIC Command The STATUS_MFR_SPECIFIC command is a standard PMBus command, but the contents of the byte returned is specific to the ADM1075. CLEAR_FAULTS Command The CLEAR_FAULTS command is used to clear fault and warnings bits when they are set. Fault and warnings bits are latched when they are set. In this way, a host can read the bits any time after the fault or warning condition occurs and determine which problem actually occurred. If the CLEAR_FAULTS command is issued and the fault or warning condition is no longer active, the status bit is cleared. If the condition is still active—for example, if an input voltage is below the undervoltage threshold of the UV pin—the CLEAR_FAULTS command attempts to clear the status bit, but that status bit is immediately set again. • • • Input voltage (VIN) Output current (IOUT) Auxiliary voltage (VAUX) The following quantities are then calculated: • • Input power (PIN) Input energy (EIN) PMON_CONFIG Command The power monitor can run in a number of different modes with different input voltage range settings. The PMON_CONFIG command is used to set up the power monitor. Rev. A | Page 32 of 52 Data Sheet ADM1075 The settings that can be configured are as follows: • • • • These registers can be read back using one of two commands, depending on the level of accuracy required for the energy accumulator and the desire to limit the frequency of reads from the ADM1075. Single-shot or continuous sampling Enable VAUX sampling Current input range Current and voltage sample averaging Modifying the power monitor settings while the power monitor is sampling is not recommended because it may cause spurious data or warnings to be generated. PMON_CONTROL Command Power monitor sampling can be initiated via software or via hardware, as follows: • • PMON_CONTROL command. This command can be used with single-shot or continuous mode. GPO1/ALERT1/CONV pin. If this pin is configured for convert mode, an external hardware signal can be used to take this pin high, triggering the single-shot sampling of one or more parts together. READ_VIN, READ_VAUX, and READ_IOUT Commands The ADM1075 power monitor measures the voltage developed across the sense resistor to provide a current measurement. The input voltage from the ADC_V pin is always measured, and the user can choose whether or not to measure the output voltage present on the ADC_AUX pin as well. READ_PIN, READ_PIN_EXT, READ_EIN, and READ_EIN_EXT Commands The VIN input voltage (12-bit) and IOUT current (12-bit) measurement values are multiplied by the ADM1075 to give the input power value. This is done using fixed point arithmetic and produces a 24-bit value. It is assumed that the numbers are of the 12.0 format, meaning there is no fractional part. It should be noted that only positive IOUT values are used to avoid returning a negative power. A bus host can read these values, and, using some difference calculations, determine the amount of energy consumed since the last read and the number of samples in that time. The bus host, using an external real-time clock, can then determine the power used in the last time period. To avoid the loss of data, the bus host must read at a rate that ensures the rollover counter does not wrap around more than once and, if it does wrap around, that the next rollover value is less than the previous one. The READ_EIN command returns the top 16 bits of the energy accumulator, the lower eight bits of the rollover counter, and the full 24 bits of the sample counter. The READ_EIN_EXT command returns the full 24 bits of the energy accumulator, the full 16 bits of the rollover counter, and the full 24 bits of the sample counter. The use of the longer rollover counter means that the time interval between reads of the part to ensure that no data is lost can be increased from seconds to minutes. PEAK_IOUT, PEAK_VIN, PEAK_VAUX, and PEAK_PIN Commands In addition to the standard PMBus commands for reading voltage and current, the ADM1075 provides commands that can report the maximum peak voltage, current, or power value since the peak value was last cleared. The peak values are updated only after the power monitor has sampled and averaged the current and voltage measurements. Individual peak values are cleared by writing a 0 value with the corresponding commands. WARNING LIMIT SETUP COMMANDS This 24-bit value can be read from the ADM1075 using the READ_PIN_EXT command, where the most significant bit (MSB) is always a zero because PIN_EXT is a twos complement binary value that is always positive. The ADM1075 power monitor can monitor a number of different warning conditions simultaneously and report any current or voltage values that exceed the user-defined thresholds using the status commands. The 16 most significant bits of the 24-bit value are used as the value for input power (PIN). The MSB of the 16-bit PIN word is always zero because PIN is a twos complement binary value that is always positive. All comparisons performed by the power monitor require the measured voltage or current value to be strictly greater or less than the threshold value. Each time a power calculation is performed, the 24-bit power value is added to a 24-bit energy accumulator register. This is a twos complement representation as well; therefore, the MSB is always zero. Each time this energy accumulator register rolls over from 0x7FFFFF to 0x000000, a 16-bit rollover counter is incremented. The rollover counter is straight binary, with a maximum value of 0xFFFF before it rolls over. There is also a 24-bit straight binary power sample counter that is incremented by one each time a power value is calculated and added to the energy accumulator. At power-up, all threshold limits are set to either minimum scale (for undervoltage or undercurrent conditions) or to maximum scale (for overvoltage, overcurrent or overpower conditions). This effectively disables the generation of any status warnings by default; warning bits are not set in the status registers until the user explicitly sets the threshold values. VIN_OV_WARN_LIMIT and VIN_UV_WARN_LIMIT Commands The VIN_OV_WARN_LIMIT and VIN_UV_WARN_LIMIT commands are used to set the OV and UV thresholds on the input voltage, as measured at the ADC_V pin. Rev. A | Page 33 of 52 ADM1075 Data Sheet VAUX_OV_WARN_LIMIT and VAUX_UV_WARN_LIMIT Commands The PIN_OP_WARN_LIMIT command is used to set the overpower (OP) threshold for the power measurement register. The sense resistor value used in the calculations to obtain the coefficients is expressed in milliohms. The m coefficients are defined as 2-byte twos complement numbers in the PMBus standard; therefore, the maximum positive value that can be represented is 32,767. If the m value is greater than that, and is to be stored in PMBus standard form, the m coefficients should be divided by 10, and the R coefficient increased by a value of 1. For example, if performing a power calculation on the ADM1075-1 with a 10 mΩ sense resistor, the m coefficient is 8549, and the R coefficient is 0. IOUT_OC_WARN_LIMIT Command Example 1 The IOUT_OC_WARN_LIMIT command is used to set the overcurrent (OC) threshold for the current flowing through the sense resistor. IOUT_OC_WARN_LIMIT requires a current limit value expressed in direct format. The VAUX_OV_WARN_LIMIT and VAUX_UV_WARN_ LIMIT commands are used to set the OV and UV thresholds on the output voltage, as measured at the ADC_VAUX pin on the ADM1075. PIN_OP_WARN_LIMIT Command IOUT_WARN2_LIMIT Command The IOUT_WARN2_LIMIT command provides a second current warning threshold that can be programmed. The polarity of this warning can be set to overcurrent or undercurrent using the DEVICE_CONFIG command. If the required current limit is 10 A, and the sense resistor is 2 mΩ, the first step is to determine the voltage coefficient. For an ADM1075-1, this is simply m = 806 × 2, giving 1612. Using Equation 1, and expressing X, in units of amps, Y = ((1612 × 10) + 20,475) × 10−1 Y = 3659.5 = 3660 (rounded up to integer form) PMBus DIRECT FORMAT CONVERSION Writing a value of 3660 with the IOUT_OC_WARN_LIMIT command sets an overcurrent warning at 10 A. The ADM1075 uses the PMBus direct format internally to represent real-world quantities such as voltage, current, and power values. A direct format number takes the form of a 2-byte, twos complement binary integer value. Example 2 It is possible to convert between direct format value and real-world quantities using the following equations. Equation 1 converts from real-world quantities to PMBus direct values, and Equation 2 converts PMBus direct format values to real-world values. To convert this value to the current flowing, use Equation 2, with m = 806 × 1 (for the ADM1075-1): R (1) −R (2) Y = (mX + b) × 10 X = 1/m × (Y × 10 − b) where: Y is the value in PMBus direct format. X is the real-world value. m is the slope coefficient, a 2-byte, twos complement integer. b is the offset, a 2-byte, twos complement integer. R is a scaling exponent, a 1-byte, twos complement integer. The same equations are used for voltage, current, and power conversions, the only difference being the values of the m, b, and R coefficients used. The READ_IOUT command returns a direct format value of 3341, representing the current flowing through a sense resistor of 1 mΩ. X = 1/806 × (3341 × 101 – 20,475) X = 16.05 A This means that when READ_IOUT returns a value of 3341, 16.05 A is flowing in the sense resistor. Note the following: • The same calculations that are used to convert power values also apply to the energy accumulator value returned by the READ_EIN command because the energy accumulator is a summation of multiple power values. • The READ_PIN_EXT and READ_EIN_EXT commands return 24-bit extended precision versions of the 16-bit values returned by READ_PIN and READ_EIN. The direct format values must be divided by 256 prior to being converted with the coefficients shown in Table 7. Table 7 lists all the coefficients required for the ADM1075. The coefficients shown are dependent on the value of the external sense resistor used in a given application. This means that an additional calculation must be performed to take the sense resistor value into account to obtain the coefficients for a specific sense resistor value. The resistor divider scaling factor on VIN/VAUX also needs to be taken into account when performing a voltage or power calculation (see Example 4). Rev. A | Page 34 of 52 Data Sheet ADM1075 Table 7. PMBus Conversion to Real-World Coefficients Coefficient m b R Voltage (V) 27,169 0 −1 ADM1075-1 806 × RSENSE 20,475 −1 Current (A) ADM1075-2 404 × RSENSE 20,475 −1 Example 3 The READ_VIN command returns a direct format value of 1726. The ADC_V pin is shorted to the OV pin, which is connected to the input supply via an 820 kΩ/11 kΩ resistor divider. To convert this value to the input voltage, use Equation 2 X = 1/27,169 × (1726 × 101 – 0) X = 0.635 V This corresponds to 0.635 V at the ADC_V pin. To obtain the input voltage, this must be amplified by the resistor divider ratio, X = 0.635 V × (820 kΩ + 11 kΩ)/11 kΩ = 47.99 V Example 4 The PIN_OP_WARN_LIMIT command requires a power limit value expressed in direct format. If the required power limit is 350 W and the sense resistor is 1 mΩ, the first step is to determine the m coefficient. Assuming an ADM1075-1 device, m = 8549 × 1 = 8549. The resistor divider on VIN scales down the power limit referenced to the ADC input. Assuming a 49 kΩ and 1 kΩ resistor divider on VIN, this gives a scaling factor of 0.02. Power (W)—Resistor Scaled ADM1075-1 ADM1075-2 8549 × RSENSE 4279 × RSENSE 0 0 −1 −1 To convert an ADC code to current in amperes, the following formulas can be used: VSENSE = LSBxmV × (IADC − 2048) IOUT = VSENSE/(RSENSE × 0.001) where: VSENSE = (VSENSE+) − (VSENSE−). LSB25mV = 12.4 μV. LSB50mV = 24.77 μV. IADC is the 12-bit ADC code. IOUT is the measured current value in amperes. RSENSE is the value of the sense resistor in milliohms. To convert an ADC code to a voltage, the following formula can be used: VM = LSBINPUTV × (VADC + 0.5) where: VM is the measured value in volts. VADC is the 12-bit ADC code. LSBINPUTV = 368 μV. To convert a current in amperes to a 12-bit value, the following formulas can be used (round the result to the nearest integer): Using Equation 1, VSENSE = IA × RSENSE × 0.001 Y = (8549 × (350 × 0.02)) × 10−1 ICODE = 2048 + (VSENSE/LSBxmV) Y = 5984.3 = 5984 (rounded to the nearest integer) Writing a value of 5984 with the PIN_OP_WARN_LIMIT command sets an overpower warning at 350 W. VOLTAGE AND CURRENT CONVERSION USING LSB VALUES The direct format voltage and current values returned by the READ_VIN, READ_VAUX, and READ_IOUT commands, and the corresponding peak versions are the actual data output directly from the ADM1075 ADC. Because the voltages and currents are a 12-bit ADC output code, they can also be converted to real-world values with knowledge of the size of the LSB on the ADC. The m, b, and R coefficients defined for the PMBus conversion are required to be whole integers by the standard and have therefore been rounded off slightly. Using this alternative method, with the exact LSB values, can provide slightly more accurate numerical conversions. where: VSENSE = (VSENSE+) − (VSENSE−). IA is the current value in amperes. RSENSE is the value of the sense resistor in milliohms. ICODE is the 12-bit ADC code. LSB25mV = 12.4 μV. LSB50mV = 24.77 μV. To convert a voltage to a 12-bit value, the following formula can be used (round the result to the nearest integer): VCODE = (VA/LSBINPUTV) − 0.5 where: VCODE is the 12-bit ADC code. VA is the voltage value in volts. LSBINPUTV = 368 μV. Rev. A | Page 35 of 52 ADM1075 Data Sheet ADM1075 ALERT PIN BEHAVIOR The ADM1075 provides a very flexible alert system, whereby one or more fault/warning conditions can be indicated to an external device. FAULTS AND WARNINGS A PMBus fault on the ADM1075 is always generated due to an analog event and causes a change in state in the hot swap output, turning it off. The three defined fault sources are as follows: • • • Undervoltage (UV) event detected on the UVH and UVL pins Overvoltage (OV) event detected on the OV pin Overcurrent (OC) event that causes a hot swap timeout 1. A value of 1 in a status register bit field always indicates a fault or warning condition. Fault and warning bits in the status registers are latched when set to 1. To clear a latched bit to 0— provided that the fault condition is no longer active—use the CLEAR_FAULTS command or use the OPERATION command to turn the hot swap output off and then on again. The latched status registers provide fault recording functionality. In the event of a fault, the HS_SHUTDOWN_CAUSE bits in the manufacturing specific status register (0x80) can be used to identify the fault source (UV, OV, or OC). Other status registers can also be checked for more fault and warning information. A warning is less severe than a fault and never causes a change in the state of the hot swap controller. The eight sources of a warning are defined as follows: • • • • • • • Any one or more of the faults and warnings listed in the Faults and Warnings section can be enabled and cause an alert, making the corresponding GPOx/ALERTx pin active. By default, the active state of a GPOx/ALERTx pin is low. For example, to use GPO1/ALERT1/CONV to monitor the IOUT OC warning from the ADC, the followings steps must be performed: Faults are continuously monitored, and, as long as power is applied to the device, they cannot be disabled. When a fault occurs, a corresponding status bit is set in one or more STATUS_xxx registers. • • By default, at power-up, the open-drain GPOx/ALERTx outputs are high impedance; therefore, the pins can be pulled high through resistors. No faults or warnings are enabled on the GPO2/ALERT2 pin at power-up; the user must explicitly enable the faults or warnings to be monitored. The FET health bad warning is active by default on the GPO1/ALERT1/CONV pin at power-up. CML: a communications error occurred on the I2C bus HS timer was active (HSTA): the current regulation was active but does not necessarily shut the system down IOUT OC warning from the ADC IOUT Warning 2 from the ADC VIN UV warning from the ADC VIN OV warning from the ADC VAUX UV warning from the ADC VAUX OV warning from the ADC PIN OP warning from the ADC 2. 3. If an IOUT sample is taken that is above the configured IOUT OC value, the GPO1/ALERT1/CONV pin is taken low, signaling an interrupt to a processor. HANDLING/CLEARING AN ALERT When faults/warnings are configured on the GPOx/ALERTx pins, the pins become active to signal an interrupt to the processor. (These pins are active low, unless inversion is enabled.) The GPOx/ALERTx signal performs the function of an SMBAlert. Note that the GPOx/ALERTx pins can become active independently of each other, but they are always made inactive together. A processor can respond to the interrupt in one of two basic ways: • GENERATING AN ALERT A host device can periodically poll the ADM1075 using the status commands to determine whether a fault/warning is active. However, this polling is very inefficient in terms of software and processor resources. The ADM1075 has two GPOx/ALERTx output pins that can be used to generate interrupts to a host processor, GPO1/ALERT1/CONV and GPO2/ALERT2. Set a threshold level with the IOUT_OC_WARN_LIMIT command. Set the IOUT_OC_WARN_EN1 bit in the ALERT1_CONFIG register Start the power monitor sampling on IOUT. • Rev. A | Page 36 of 52 If there is only one device on the bus, the processor can simply read the status bytes and issue a CLEAR_FAULTS command to clear all the status bits, which causes the deassertion of the GPOx/ALERTx line. If there is a persistent fault—for example, an undervoltage on the input—the status bits remain set after the CLEAR_FAULTS command is executed because the fault has not been removed. However, the GPOx/ALERTx line is not pulled low unless a new fault/ warning becomes active. If the cause of the SMBAlert is a power monitor generated warning and the power monitor is running continuously, the next sample generates a new SMBAlert after the CLEAR_FAULTS command is issued. If there are many devices on the bus, the processor can issue an SMBus alert response address command to find out which device asserted the SMBAlert line. The processor can read the status bytes from that device and issue a CLEAR_FAULTS command. Data Sheet ADM1075 SMBus ALERT RESPONSE ADDRESS 4. The SMBus alert response address (ARA) is a special address that can be used by the bus host to locate any devices that need to talk to it. A host typically uses a hardware interrupt pin to monitor the SMBus alert pins of a number of devices. When the host interrupt occurs, the host issues a message on the bus using the SMBus receive byte or receive byte with PEC protocol. 5. The special address used by the host is 0x0C. Any devices that have an SMBAlert signal return their own 7-bit address as the seven MSBs of the data byte. The LSB value is not used and can be either 1 or 0. The host reads the device address from the received data byte and proceeds to handle the alert condition. More than one device may have an active SMBAlert signal and attempt to communicate with the host. In this case, the device with the lowest address dominates the bus and succeeds in transmitting its address to the host. The device that succeeds disables its SMBusAlert signal. If the host sees that the SMBus alert signal is still low, it continues to read addresses until all devices that need to talk to it have successfully transmitted their addresses. EXAMPLE USE OF SMBus ALERT RESPONSE ADDRESS The full sequence of steps that occurs when an SMBAlert is generated and cleared is as follows: 1. 2. 3. A fault or warning is enabled using the ALERT1_CONFIG command, and the corresponding status bit for the fault or warning goes from 0 to 1, indicating that the fault/warning has just become active. The GPO1/ALERT1/CONV or GPO2/ALERT2 pin becomes active (low) to signal that an SMBAlert is active. The host processor issues an SMBus alert response address to determine which device has an active alert. 6. If there are no other active alerts from devices with lower I2C addresses, this device makes the GPO1/ALERT1/CONV or GPO2/ALERT2 pin inactive (high) during the NACK bit period after it sends its address to the host processor. If the GPO1/ALERT1/CONV or GPO2/ALERT2 pin stays low, the host processor must continue to issue SMBus alert response address commands to devices to find out the addresses of all devices whose status it must check. The ADM1075 continues to operate with the GPO1/ALERT1/ CONV or GPO2/ALERT2 pin inactive and the contents of the status bytes unchanged until the host reads the status bytes and clears them, or until a new fault occurs. That is, if a status bit for a fault/warning that is enabled on the GPO1/ALERT1/CONV or GPO2/ALERT2 pin and that was not already active (equal to 1) goes from 0 to 1, a new alert is generated, causing the GPO1/ALERT1/CONV or GPO2/ALERT2 pin to become active again. DIGITAL COMPARATOR MODE The GPO1/ALERT1/CONV and GPO2/ALERT2 pins can be configured to indicate if a user defined threshold for voltage, current, or power is being exceeded. In this mode, the output pin is live and is not latched when a warning threshold is exceeded. In effect, the pin acts as a digital comparator where the threshold is set using the warning limit threshold commands. The ALERTx_CONFIG command is used, as for the SMBAlert configuration, to select the specific warning threshold to be monitored. The GPO1/ALERT1/CONV or GPO2/ALERT2 pin then indicates if the measured value is above or below the threshold. Rev. A | Page 37 of 52 ADM1075 Data Sheet PMBus COMMAND REFERENCE Register addresses are in hexadecimal format. Table 8. PMBus Command Summary Command Code 0x01 0x03 0x19 0x4A 0x57 0x58 0x6B 0x78 0x79 0x7B 0x7C 0x80 0x86 0x88 0x8C 0x97 0x98 0x99 0x9A 0x9B 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xF6 Command Name OPERATION CLEAR_FAULTS CAPABILITY IOUT_OC_WARN_LIMIT VIN_OV_WARN_LIMIT VIN_UV_WARN_LIMIT PIN_OP_WARN_LIMIT STATUS_BYTE STATUS_WORD STATUS_IOUT STATUS_INPUT STATUS_MFR_SPECIFIC READ_EIN READ_VIN READ_IOUT READ_PIN PMBUS_REVISION MFR_ID MFR_MODEL MFR_REVISION PEAK_IOUT PEAK_VIN PEAK_VAUX PMON_CONTROL PMON_CONFIG ALERT1_CONFIG ALERT2_CONFIG IOUT_WARN2_LIMIT DEVICE_CONFIG POWER_CYCLE PEAK_PIN READ_PIN_EXT READ_EIN_EXT READ_VAUX VAUX_OV_WARN_LIMIT VAUX_UV_WARN_LIMIT STATUS_VAUX SMBus Transaction Type Read/write byte Send byte Read byte Read/write word Read/write word Read/write word Read/write word Read byte Read word Read byte Read byte Read byte Block read Read word Read word Read word Read byte Block read Block read Block read Read/write word Read/write word Read/write word Read/write byte Read/write byte Read/write word Read/write word Read/write word Read/write byte Send byte Read/write word Block read Block read Read word Read/write word Read/write word Read byte Number of Data Bytes 1 0 1 2 2 2 2 1 2 1 1 1 1 (byte count) + 6 (data) 2 2 2 1 1 (byte count) + 3 (data) 1 (byte count) + 9 (data) 1 (byte count) + 1 (data) 2 2 2 1 1 2 2 2 1 0 2 1 (byte count) + 3 (data) 1 (byte count) + 8 (data) 2 2 2 1 Rev. A | Page 38 of 52 Reset 0x00 Not applicable 0xB0 0x0FFF 0x0FFF 0x0000 0x7FFF 0x00 0x0000 0x00 0x00 0x00 0x06000000000000 0x0000 0x0000 0x0000 0x22 0x03 + ASCII “ADI” 0x09 + ASCII “ADM1075-1” or “ADM1075-2” 0x01 + ASCII “1” 0x0000 0x0000 0x0000 0x01 0x8F for ADM1075-1; 0x97 for ADM1075-2 0x8000 0x0004 0x0000 0x00 Not applicable 0x0000 0x03000000 0x080000000000000000 0x0000 0x0FFF 0x0000 0x00 Data Sheet ADM1075 REGISTER DETAILS OPERATION COMMAND REGISTER Address: 0x01, Reset: 0x00, Name: OPERATION Table 9. Bit Descriptions for OPERATION Bits 7 Bit Name ON Settings 0 1 [6:0] RESERVED Description Hot swap enable. Hot swap output disabled. Hot swap output enabled. Always reads as 0000000. Reset 0x0 Access RW 0x0 R Reset 0x1 0x01 0x1 Access R R R 0x0000 R Reset 0x0 0xFFF Access R RW Reset 0x0 0xFFF Access R RW Reset 0x0 0x0 Access R RW CLEAR FAULTS REGISTER Address: 0x03, Send Byte, No Data, Name: CLEAR_FAULTS PMBUS CAPABILITY REGISTER Address: 0x19, Reset: 0xB0, Name: CAPABILITY Table 10. Bit Descriptions for CAPABILITY Bits 7 [6:5] 4 Bit Name PEC_SUPPORT MAX_BUS_SPEED SMBALERT_SUPPORT [3:0] RESERVED Settings Description Always reads as 1. Packet error checking (PEC) is supported. Always reads as 01. Maximum supported bus speed is 400 kHz. Always reads as 1. Device supports SMBAlert and alert response address (ARA). Always reads as 0000. IOUT OC WARN LIMIT REGISTER Address: 0x4A, Reset: 0x0FFF, Name: IOUT_OC_WARN_LIMIT Table 11. Bit Descriptions for IOUT_OC_WARN_LIMIT Bits [15:12] [11:0] Bit Name RESERVED IOUT_OC_WARN_LIMIT Settings Description Always reads as 0000. Overcurrent threshold for the IOUT measurement through the sense resistor, expressed in ADC codes. VIN OV WARN LIMIT REGISTER Address: 0x57, Reset: 0x0FFF, Name: VIN_OV_WARN_LIMIT Table 12. Bit Descriptions for VIN_OV_WARN_LIMIT Bits [15:12] [11:0] Bit Name RESERVED VIN_OV_WARN_LIMIT Settings Description Always reads as 0000. Overvoltage threshold for the ADC_V pin measurement, expressed in ADC codes. VIN UV WARN LIMIT REGISTER Address: 0x58, Reset: 0x0000, Name: VIN_UV_WARN_LIMIT Table 13. Bit Descriptions for VIN_UV_WARN_LIMIT Bits [15:12] [11:0] Bit Name RESERVED VIN_UV_WARN_LIMIT Settings Description Always reads as 0000. Undervoltage threshold for the ADC_V pin measurement, expressed in ADC codes. Rev. A | Page 39 of 52 ADM1075 Data Sheet PIN OP WARN LIMIT REGISTER Address: 0x6B, Reset: 0x7FFF, Name: PIN_OP_WARN_LIMIT Table 14. Bit Descriptions for PIN_OP_WARN_LIMIT Bits 15 [14:0] Bit Name RESERVED PIN_OP_WARN_LIMIT Settings Description Always reads as 0. Overpower threshold for the PMBus power measurement, expressed in ADC codes. Reset 0x0 0x7FFF Access R RW Reset 0x0 0x0 Access R R 0x0 0x0 R R 0x0 R 0x0 0x0 R R 0x0 R Reset 0x0 0x0 Access R R STATUS BYTE REGISTER Address: 0x78, Reset: 0x00, Name: STATUS_BYTE Table 15. Bit Descriptions for STATUS_BYTE Bits 7 6 Bit Name RESERVED HOTSWAP_OFF Settings 0 1 5 4 RESERVED IOUT_OC_FAULT 0 1 3 VIN_UV_FAULT 0 1 2 1 RESERVED CML_FAULT 0 1 0 NONE_OF_THE_ABOVE 0 1 Description Always reads as 0. Live register. The hot swap gate drive output is enabled. The hot swap gate drive output is disabled, and the GATE pin is pulled down. This can be due to, for example, an overcurrent fault that causes the ADM1075 to latch off, an undervoltage condition on the UVx pin, or the use of the OPERATION command to turn the output off. Always reads as 0. Latched register. No overcurrent output fault detected. The hot swap controller detected an overcurrent condition and the time limit set by the capacitor on the TIMER pin has elapsed, causing the hot swap gate drive to shut down. Latched register. No undervoltage input fault detected on the UVH/UVL pins. An undervoltage input fault was detected on the UVH/UVL pins. Always reads as 0. Latched register. No communications error detected on the I2C/PMBus interface. An error was detected on the I2C/PMBus interface. Errors detected are unsupported command, invalid PEC byte, and incorrectly structured message. Live register. No other active status bit to be reported by any other status command. Active status bits are waiting to be read by one or more status commands. STATUS WORD REGISTER Address: 0x79, Reset: 0x0000, Name: STATUS_WORD Table 16. Bit Descriptions for STATUS_WORD Bits 15 14 Bit Name RESERVED IOUTPOUT_STATUS Settings 0 1 Description Always reads as 0. Live register. There are no active status bits to be read by STATUS_IOUT. There are one or more active status bits to be read by STATUS_IOUT. Rev. A | Page 40 of 52 Data Sheet Bits 13 Bit Name INPUT_STATUS ADM1075 Settings 0 1 12 MFR_STATUS 0 1 11 PGB_STATUS 0 1 [10:8] [7:0] RESERVED STATUS_BYTE Description Live register. There are no active status bits to be read by STATUS_INPUT. There are one or more active status bits to be read by STATUS_INPUT. Live register. There are no active status bits to be read by STATUS_MFR_SPECIFIC. There are one or more active status bits to be read by STATUS_MFR_SPECIFIC. Live register. The voltage on the DRAIN pin is above the required threshold, indicating that output power is considered good. This bit is the logical inversion of the PWRGD pin on the part. The voltage on the DRAIN pin is below the required threshold, indicating that output power is considered bad. Always reads as 000. This byte is the same as the byte returned by the STATUS_BYTE command. Reset 0x0 Access R 0x0 R 0x0 R 0x0 0x0 R R Reset 0x0 Access R 0x0 0x0 R R 0x0 R Reset 0x0 Access R 0x0 R 0x0 R IOUT STATUS REGISTER Address: 0x7B, Reset: 0x00, Name: STATUS_IOUT Table 17. Bit Descriptions for STATUS_IOUT Bits 7 Bit Name IOUT_OC_FAULT Settings 0 1 6 5 RESERVED IOUT_OC_WARN 0 1 [4:0] RESERVED Description Latched register. No overcurrent output fault detected. The hot swap controller detected an overcurrent condition and the time limit set by the capacitor on the TIMER pin has elapsed, causing the hot swap gate drive to shut down. Always reads as 0. Latched register. No overcurrent condition on the output supply detected by the power monitor using the IOUT_OC_WARN_LIMIT command. An overcurrent condition was detected by the power monitor using the IOUT_OC_WARN_LIMIT command. Always reads as 00000. INPUT STATUS REGISTER Address: 0x7C, Reset: 0x00, Name: STATUS_INPUT Table 18. Bit Descriptions for STATUS_INPUT Bits 7 Bit Name VIN_OV_FAULT Settings 0 1 6 VIN_OV_WARN 0 1 5 VIN_UV_WARN 0 1 Description Latched register. No overvoltage detected on the OV pin. An overvoltage was detected on the OV pin. Latched register. No overvoltage condition on the input supply detected by the power monitor. An overvoltage condition on the input supply was detected by the power monitor. Latched register. No undervoltage condition on the input supply detected by the power monitor. An undervoltage condition on the input supply was detected by the power monitor. Rev. A | Page 41 of 52 ADM1075 Bits 4 Bit Name VIN_UV_FAULT Data Sheet Settings 0 1 [3:1] 0 RESERVED PIN_OP_WARN 0 1 Description Latched register. No undervoltage detected on the UVx pin. An undervoltage was detected on the UVx pin. Always reads as 000. Latched register. No overpower condition on the input supply detected by the power monitor. An overpower condition on the input supply was detected by the power monitor. Reset 0x0 Access R 0x0 0x0 R R Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R MANUFACTURING SPECIFIC STATUS REGISTER Address: 0x80, Reset: 0x00, Name: STATUS_MFR_SPECIFIC Table 19. Bit Descriptions for STATUS_MFR_SPECIFIC Bits 7 Bit Name FET_HEALTH_BAD Settings 0 1 6 UV_CMP_OUT 0 1 5 OV_CMP_OUT 0 1 4 VAUX_STATUS 0 1 3 HS_INLIM_FAULT 0 1 [2:1] HS_SHUTDOWN_CAUSE 00 01 10 11 0 IOUT_WARN2 0 1 Description Latched register. FET behavior appears to be as expected. FET behavior suggests that the FET may be shorted. Live register. Input voltage to UVx pin is above threshold. Input voltage to UVx pin is below threshold. Live register. Input voltage to OV pin is below threshold. Input voltage to OV pin is above threshold. Latched register. There are no active status bits to be read by STATUS_VAUX. There are one or more active status bits to be read by STATUS_VAUX. Latched register. The ADM1075 has not actively limited the current into the load. The ADM1075 has actively limited current into the load. This bit differs from the IOUT_OC_FAULT bit in that the HS_INLIM bit is set immediately, whereas the IOUT_OC_FAULT bit is not set unless the time limit set by the capacitor on the TIMER pin elapses. Latched register. The ADM1075 is either enabled and working correctly, or has been shut down using the OPERATION command. An IOUT_OC_FAULT condition occurred that caused the ADM1075 to shut down. A VIN_UV_FAULT condition occurred that caused the ADM1075 to shut down. A VIN_OV_FAULT condition occurred that caused the ADM1075 to shut down. Latched register. No overcurrent condition on the output supply detected by the power monitor using the IOUT_WARN2_LIMIT command. An undercurrent or overcurrent condition on the output supply was detected by the power monitor using the IOUT_WARN2_LIMIT command. The polarity of the threshold condition is set by the IOUT_WARN2_OC_SELECT bit using the DEVICE_CONFIG command. Rev. A | Page 42 of 52 Data Sheet ADM1075 READ EIN REGISTER Address: 0x86, Reset: 0x06, 0x0000, 0x00, 0x000000, Name: READ_EIN Table 20. Bit Descriptions for READ_EIN Byte [0] Bit Name BYTE_COUNT [2:1] ENERGY_COUNT [3] ROLLOVER_COUNT [6:4] SAMPLE_COUNT Settings Description Always reads as 0x06, the number of data bytes that the block read command should expect to read. Energy accumulator value in direct format. Byte 2 is the high byte, and Byte 1 is the low byte. Internally, the energy accumulator is a 24-bit value, but only the most significant 16 bits are returned with this command. Use the READ_EIN_EXT to access the nontruncated version. Number of times that the energy count has rolled over, from 0x7FFF to 0x0000. This is a straight 8-bit binary value. This is the total number of PIN samples acquired and accumulated in the energy count accumulator. Byte 6 is the high byte, Byte 5 is the middle byte, and Byte 4 is the low byte. Reset 0x6 Access R 0x0 R 0x0 R 0x0 R Reset 0x0 0x0 Access R R Reset 0x0 0x0 Access R R Reset 0x0 Access R Reset 0x2 0x2 Access R R READ VIN REGISTER Address: 0x88, Reset: 0x0000, Name: READ_VIN Table 21. Bit Descriptions for READ_VIN Bits [15:12] [11:0] Bit Name RESERVED READ_VIN Settings Description Always reads as 0000. Input voltage from the ADC_V pin measurement, expressed in ADC codes. READ IOUT REGISTER Address: 0x8C, Reset: 0x0000, Name: READ_IOUT Table 22. Bit Descriptions for READ_IOUT Bits [15:12] [11:0] Bit Name RESERVED READ_IOUT Settings Description Always reads as 0000. Output current measurement through the sense resistor. READ PIN REGISTER Address: 0x97, Reset: 0x0000, Name: READ_PIN Table 23. Bit Descriptions for READ_PIN Bits [15:0] Bit Name READ_PIN Settings Description Input power from the VIN × IOUT calculation. PMBus REVISION REGISTER Address: 0x98, Reset: 0x22, Name: PMBUS_REVISION Table 24. Bit Descriptions for PMBUS_REVISION Bits [7:4] [3:0] Bit Name PMBUS_P1_REVISION PMBUS_P2_REVISION Settings 0000 0001 0010 Description Always reads as 0010, PMBus Specification Part I, Revision 1.2. Always reads as 0010, PMBus Specification Part II, Revision 1.2. Rev1.0. Rev1.1. Rev1.2. Rev. A | Page 43 of 52 ADM1075 Data Sheet MANUFACTURING ID REGISTER Address: 0x99, Reset: 0x03 + ASCII “ADI”, Name: MFR_ID Table 25. Bit Descriptions for MFR_ID Byte 0 Bit Name BYTE_COUNT 1 2 3 CHARACTER1 CHARACTER2 CHARACTER3 Settings Description Always reads as 0x03, the number of data bytes that the block read command should expect to read. Always reads as 0x41 = “A”. Always reads as 0x44 = “D”. Always reads as 0x49 = “I”. Reset 0x3 Access R 0x41 0x44 0x49 R R R MANUFACTURING MODEL REGISTER Address: 0x9A, Reset: 0x09 + ASCII “ADM1075-x”, Name: MFR_MODEL Table 26. Bit Descriptions for MFR_MODEL Byte 0 Bit Name BYTE_COUNT 1 2 3 4 5 6 7 8 9 CHARACTER1 CHARACTER2 CHARACTER3 CHARACTER4 CHARACTER5 CHARACTER6 CHARACTER7 CHARACTER8 CHARACTER9 Settings Description Always reads as 0x03, the number of data bytes that the block read command should expect to read. Always reads as 0x41 = “A”. Always reads as 0x44 = “D”. Always reads as 0x4D = “M”. Always reads as 0x31 = “1”. Always reads as 0x30 = “0”. Always reads as 0x37 = “7”. Always reads as 0x35 = “5”. Always reads as 0x2D = “-”. Always reads as 0x31 = “1” for ADM1075-1. Always reads as 0x32 = “2” for ADM1075-2. Reset 0x9 Access R 0x41 0x44 0x4D 0x31 0x30 0x37 0x35 0x2D 0x31 or 0x32 R R R R R R R R R Reset 0x1 Access R 0x31 R Reset 0x0 0x0 Access R R MANUFACTURING REVISION REGISTER Address: 0x9B, Reset: 0x01 + ASCII “1”, Name: MFR_REVISION Table 27. Bit Descriptions for MFR_REVISION Byte 0 Bit Name BYTE_COUNT 1 CHARACTER1 Settings Description Always reads as 0x01, the number of data bytes that the block read command should expect to read. Always reads as 0x31, Revision 1 of ADM1075. PEAK IOUT REGISTER Address: 0xD0, Reset: 0x0000, Name: PEAK_IOUT (writing 0x0000 clears the peak value) Table 28. Bit Descriptions for PEAK_IOUT Bits [15:12] [11:0] Bit Name RESERVED PEAK_IOUT Settings Description Always reads as 0000. Returns the peak IOUT current since the register was last cleared. Rev. A | Page 44 of 52 Data Sheet ADM1075 PEAK VIN REGISTER Address: 0xD1, Reset: 0x0000, Name: PEAK_VIN (writing 0x0000 clears the peak value) Table 29. Bit Descriptions for PEAK_VIN Bits [15:12] [11:0] Bit Name RESERVED PEAK_VIN Settings Description Always reads as 0000. Returns the peak VIN voltage since the register was last cleared. Reset 0x0 0x0 Access R R Reset 0x0 0x0 Access R R Reset 0x0 0x1 Access R RW Reset 0x1 Access RW 0x0 RW 0x0 0x1 or 0x2 R R 0x7 RW PEAK VAUX REGISTER Address: 0xD2, Reset: 0x0000, Name: PEAK_VAUX (writing 0x0000 clears the peak value) Table 30. Bit Descriptions for PEAK_VAUX Bits [15:12] [11:0] Bit Name RESERVED PEAK_VAUX Settings Description Always reads as 0000. Returns the peak VAUX voltage since the register was last cleared. POWER MONITOR CONTROL REGISTER Address: 0xD3, Reset: 0x01, Name: PMON_CONTROL Table 31. Bit Descriptions for PMON_CONTROL Bits [7:1] 0 Bit Name RESERVED CONVERT Settings Description Always reads as 0000000. 0 1 Power monitor is not running. Default. Starts the sampling of current and voltage with the power monitor. In single-shot mode, this bit clears itself after one complete cycle. In continuous mode, this bit must be written to 0 to stop sampling. POWER MONITOR CONFIGURATION REGISTER Address: 0xD4, Reset: 0x8F, Name: PMON_CONFIG Table 32. Bit Descriptions for PMON_CONFIG Bits 7 6 Bit Name PMON_MODE Settings Description 0 1 This setting selects single-shot sampling mode. Default. This setting selects continuous sampling mode. 0 Default. The power monitor samples the input voltage on ADC_V and IOUT. The power monitor also samples the voltage on the ADC_AUX pin. Always reads as 0. VAUX_ENABLE 1 5 [4:3] RESERVED IRANGE 00 01 10 11 [2:0] Reserved. Sets current sense range to 25 mV. Default for ADM1075-1. Sets current sense range to 50 mV. Default for ADM1075-2. Reserved. AVERAGING 000 001 010 011 100 101 110 111 Disables sample averaging for current and voltage. Sets sample averaging for current and voltage to two samples. Sets sample averaging for current and voltage to four samples. Sets sample averaging for current and voltage to eight samples. Sets sample averaging for current and voltage to 16 samples. Sets sample averaging for current and voltage to 32 samples. Sets sample averaging for current and voltage to 64 samples. Default. Sets sample averaging for current and voltage to 128 samples. Rev. A | Page 45 of 52 ADM1075 Data Sheet ALERT1 CONFIGURATION REGISTER Address: 0xD5, Reset: 0x8000, Name: ALERT1_CONFIG Table 33. Bit Descriptions for ALERT1_CONFIG Bits 15 Bit Name FET_HEALTH_BAD_EN1 Settings Description 0 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW Default. Disables generation of SMBAlert when the VAUX_UV_WARN bit is set. Generates SMBAlert when the VAUX_UV_WARN bit is set. HS_INLIM_EN1 0 0x0 Default. Disables generation of SMBAlert when the VAUX_OV_WARN bit is set. Generates SMBAlert when the VAUX_OV_WARN bit is set. VAUX_UV_WARN_EN1 0 RW Default. Disables generation of SMBAlert when the VIN_UV_WARN bit is set. Generates SMBAlert when the VIN_UV_WARN bit is set. VAUX_OV_WARN_EN1 0 0x0 Default. Disables generation of SMBAlert when the VIN_OV_WARN bit is set. Generates SMBAlert when the VIN_OV_WARN bit is set. VIN_UV_WARN_EN1 0 RW Default. Disables generation of SMBAlert when the IOUT_WARN2 bit is set. Generates SMBAlert when the IOUT_WARN2 bit is set. VIN_OV_WARN_EN1 0 0x0 Default. Disables generation of SMBAlert when the IOUT_OC_WARN bit is set. Generates SMBAlert when the IOUT_OC_WARN bit is set. IOUT_WARN2_EN1 0 RW Default. Disables generation of SMBAlert when the CML_FAULT bit is set. Generates SMBAlert when the CML_ FAULT bit is set. IOUT_OC_WARN_EN1 0 0x0 Default. Disables generation of SMBAlert when the VIN_UV_FAULT bit is set. Generates SMBAlert when the VIN_UV_FAULT bit is set. CML_ERROR_EN1 0 RW Default. Disables generation of SMBAlert when the VIN_OV_FAULT bit is set. Generates SMBAlert when the VIN_OV_FAULT bit is set. VIN_UV_FAULT_EN1 0 0x0 Default. Disables generation of SMBAlert when the IOUT_OC_FAULT bit is set. Generates SMBAlert when the IOUT_OC_FAULT bit is set. VIN_OV_FAULT_EN1 0 Access RW Disables generation of SMBAlert when the FET_HEALTH_BAD bit is set. Default. Generates SMBAlert when the FET_HEALTH_BAD bit is set. This bit is active from power-up so that a FET problem can be detected and flagged immediately without the need for software to set this bit. IOUT_OC_FAULT_EN1 0 Reset 0x1 Default. Disables generation of SMBAlert when the HS_INLIM_FAULT bit is set. Generates SMBAlert when the HS_INLIM_FAULT bit is set. Rev. A | Page 46 of 52 Data Sheet Bits 3 Bit Name PIN_OP_WARN_EN1 ADM1075 Settings Description 0 1 [2:1] 10 11 0 0x0 RW 0x0 RW Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW Default. GPO1 is configured to generate SMBAlerts. GPO1 can be used a general-purpose digital output pin. The GPO1_INVERT bit is used to change the output state. GPO1 is configured as a convert (CONV) input pin. This is digital comparator mode. The output pin now reflects the live status of the warning or fault bit selected for the output. In effect, this is a nonlatched SMBAlert. GPO1_INVERT 0 1 Access RW Default. Disables generation of SMBAlert when the PIN_OP_WARN bit is set. Generates SMBAlert when the PIN_OP_WARN bit is set. GPO1_MODE 00 01 Reset 0x0 Default. In GPO mode, the GPO1 pin is active low. In GPO mode, the GPO1 pin is active high. ALERT2 CONFIGURATION REGISTER Address: 0xD6, Reset: 0x0004, Name: ALERT2_CONFIG Table 34. Bit Descriptions for ALERT2_CONFIG Bits 15 Bit Name FET_HEALTH_BAD_EN2 Settings Description 0 1 14 IOUT_OC_FAULT_EN2 0 1 13 1 1 1 1 Default. Disables generation of SMBAlert when the IOUT_OC_WARN bit is set. Generates SMBAlert when the IOUT_OC_WARN bit is set. IOUT_WARN2_EN2 0 1 8 Default. Disables generation of SMBAlert when the CML_FAULT bit is set. Generates SMBAlert when the CML_ FAULT bit is set. IOUT_OC_WARN_EN2 0 9 Default. Disables generation of SMBAlert when the VIN_UV_FAULT bit is set. Generates SMBAlert when the VIN_UV_FAULT bit is set. CML_ERROR_EN2 0 10 Default. Disables generation of SMBAlert when the VIN_OV_FAULT bit is set. Generates SMBAlert when the VIN_OV_FAULT bit is set. VIN_UV_FAULT_EN2 0 11 Default. Disables generation of SMBAlert when the IOUT_OC_FAULT bit is set. Generates SMBAlert when the IOUT_OC_FAULT bit is set. VIN_OV_FAULT_EN2 0 12 Default. Disables generation of SMBAlert when the FET_HEALTH_BAD bit is set. Generates SMBAlert when the FET_HEALTH_BAD bit is set. This bit is active from power-up so that a FET problem can be detected and flagged immediately without the need for software to set this bit. Default. Disables generation of SMBAlert when the IOUT_WARN2 bit is set. Generates SMBAlert when the IOUT_WARN2 bit is set. VIN_OV_WARN_EN2 0 1 Default. Disables generation of SMBAlert when the VIN_OV_WARN bit is set. Generates SMBAlert when the VIN_OV_WARN bit is set. Rev. A | Page 47 of 52 ADM1075 Bits 7 Bit Name VIN_UV_WARN_EN2 Data Sheet Settings Description 0 1 6 1 5 1 4 1 3 1 [2:1] 10 11 0 0x0 RW 0x0 RW 0x2 RW 0x0 RW Reset 0x0 0x0 Access R RW Reset 0x00 0x0 Access R RW GPO2 is configured to generate SMBAlerts. GPO2 can be used a general-purpose digital output pin. The GPO2_INVERT bit is used to change the output state. Default. GPO2 is configured as a retry fail output. This is digital comparator mode. The output pin now reflects the live status of the warning or fault bit selected for the output. In effect, this is a nonlatched SMBAlert. GPO2_INVERT 0 1 RW Default. Disables generation of SMBAlert when the PIN_OP_WARN bit is set. Generates SMBAlert when the PIN_OP_WARN bit is set. GPO2_MODE 00 01 0x0 Default. Disables generation of SMBAlert when the HS_INLIM_FAULT bit is set. Generates SMBAlert when the HS_INLIM_FAULT bit is set. PIN_OP_WARN_EN2 0 RW Default. Disables generation of SMBAlert when the VAUX_UV_WARN bit is set. Generates SMBAlert when the VAUX_UV_WARN bit is set. HS_INLIM_EN2 0 0x0 Default. Disables generation of SMBAlert when the VAUX_OV_WARN bit is set. Generates SMBAlert when the VAUX_OV_WARN bit is set. VAUX_UV_WARN_EN2 0 Access RW Default. Disables generation of SMBAlert when the VIN_UV_WARN bit is set. Generates SMBAlert when the VIN_UV_WARN bit is set. VAUX_OV_WARN_EN2 0 Reset 0x0 Default. In GPO mode, the GPO2 pin is active low. In GPO mode, the GPO2 pin is active high. IOUT WARN2 LIMIT REGISTER Address: 0xD7, Reset: 0x0000, Name: IOUT_WARN2_LIMIT Table 35. Bit Descriptions for IOUT_WARN2_LIMIT Bits [15:12] [11:0] Bit Name RESERVED IOUT_WARN2_LIMIT Settings Description Always reads as 0000. Threshold for the IOUT measurement through the sense resistor, expressed in ADC codes. This value can be either an undercurrent or overcurrent, depending on the state of the IOUT_WARN2_OC_SELECT bit set using the DEVICE_CONFIG command. DEVICE CONFIGURATION REGISTER Address: 0xD8, Reset: 0x00, Name: DEVICE_CONFIG Table 36. Bit Descriptions for DEVICE_CONFIG Bits [7:6] 5 Bit Name RESERVED OPERATION_CMD_ENABLE Settings 0 1 Description Always reads as 00. Enable operation command. The OPERATION command is disabled, and the ADM1075 issues a NACK if the command is received. This setting provides some protection against a card accidentally turning itself off The OPERATION command is enabled, and the ADM1075 responds to it. Rev. A | Page 48 of 52 Data Sheet Bits 4 Bit Name IOUT_WARN2_OC_SELECT ADM1075 Settings 0 1 [3:2] OC_TRIP_SELECT 00 01 10 11 [1:0] OC_FILT_SELECT 00 01 10 11 Description Sets IOUT Warning 2 limit to OC or UC. Configures IOUT_WARN2_LIMIT as an undercurrent threshold Configured IOUT_WARN2_LIMIT as an overcurrent threshold Sets severe OC trip threshold. 125%. 150%. Default. 200%. 225%. Sets severe OC filter time. 200 ns. 900 ns. Default. 10.7 μs. 57 μs. Reset 0x0 Access RW 0x0 RW 0x0 RW Reset 0x0 Access R Reset 0x3 Access R 0x0 R Reset 0x8 Access R 0x0 R 0x0 R 0x0 R POWER CYCLE REGISTER Address: 0xD9, Send Byte, No Data, Name: POWER_CYCLE PEAK PIN REGISTER Address: 0xDA, Reset: 0x0000, Name: PEAK_PIN (writing 0x0000 clears the peak value) Table 37. Bit Descriptions for PEAK_PIN Bits [15:0] Bit Name PEAK_PIN Settings Description Returns the peak input power since the register was last cleared. READ PIN_EXT REGISTER Address: 0xDB, Reset: 0x03, 0x000000, Name: READ_PIN_EXT Table 38. Bit Descriptions for READ_PIN_EXT Byte [0] Bit Name BYTE_COUNT [3:1] READ_PIN_EXT Settings Description Always reads as 0x03, the number of data bytes that the block read command should expect to read. This is the result of the VIN × IOUT calculation that has not been truncated. Byte 3 is the high byte, Byte 2 is the middle byte, and Byte 1 is the low byte. READ EIN_EXT REGISTER Address: 0xDC, Reset: 0x08, 0x000000, 0x0000, 0x000000, Name: READ_EIN_EXT Table 39. Bit Descriptions for READ_EIN_EXT Byte [0] Bit Name BYTE_COUNT [3:1] ENERGY_EXT [5:4] ROLLOVER_EXT [8:6] SAMPLE_COUNT Settings Description Always reads as 0x08, the number of data bytes that the block read command should expect to read. This is the 24-bit energy accumulator in direct format. Byte 3 is the high byte, Byte 2 is the middle byte, and Byte 1 is the low byte. Number of times that the energy count has rolled over, from 0x7FFF to 0x0000. This is a straight 16-bit binary value. Byte 5 is the high byte, Byte 4 is the low byte. This is the total number of PIN samples acquired and accumulated in the energy count accumulator. Byte 8 is the high byte, Byte 7 is the middle byte, and Byte 6 is the low byte. Rev. A | Page 49 of 52 ADM1075 Data Sheet READ VAUX REGISTER Address: 0xDD, Reset: 0x0000, Name: READ_VAUX Table 40. Bit Descriptions for READ_VAUX Bits [15:12] [11:0] Bit Name RESERVED READ_VAUX Settings Description Always reads as 0000. Output voltage from the ADC_AUX pin measurement, expressed in ADC codes. Reset 0x0 0x0 Access R R Reset 0x0 0xFFF Access R RW Reset 0x0 0x0 Access R RW Reset 0x0 Access R 0x0 R 0x0 R VAUX OV WARN LIMIT REGISTER Address: 0xDE, Reset: 0x0FFF, Name: VAUX_OV_WARN_LIMIT Table 41. Bit Descriptions for VAUX_OV_WARN_LIMIT Bits [15:12] [11:0] Bit Name RESERVED VAUX_OV_WARN_LIMIT Settings Description Always reads as 0000. Overvoltage threshold for the ADC_AUX pin measurement, expressed in ADC codes. VAUX UV WARN LIMIT REGISTER Address: 0xDF, Reset: 0x0000, Name: VAUX_UV_WARN_LIMIT Table 42. Bit Descriptions for VAUX_UV_WARN_LIMIT Bits [15:12] [11:0] Bit Name RESERVED VAUX_UV_WARN_LIMIT Settings Description Always reads as 0000. Undervoltage threshold for the ADC_AUX pin measurement, expressed in ADC codes. VAUX STATUS REGISTER Address: 0xF6, Reset: 0x00, Name: STATUS_VAUX Table 43. Bit Descriptions for STATUS_VAUX Bits 7 Bit Name VAUX_OV_WARN Settings 0 1 6 VAUX_UV_WARN 0 1 [5:0] RESERVED Description Latched register. No overvoltage condition was detected on the ADC_AUX pin by the power monitor using the VAUX_OV_WARN_LIMIT command. An overvoltage condition was detected on the ADC_AUX pin by the power monitor using the VAUX_OV_WARN_LIMIT command. Latched register. No undervoltage condition was detected on the ADC_AUX pin by the power monitor using the VAUX_UV_WARN_LIMIT command. An undervoltage condition was detected on the ADC_AUX pin by the power monitor using the VAUX_UV_WARN_LIMIT command. Always reads as 000000. Rev. A | Page 50 of 52 Data Sheet ADM1075 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 1 6.40 BSC 14 PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 8° 0° 0.20 0.09 SEATING PLANE 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 64. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 0.30 0.25 0.18 PIN 1 INDICATOR 22 0.50 BSC 21 1 EXPOSED PAD 3.40 3.30 SQ 3.20 15 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 7 14 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SEATING PLANE PIN 1 INDICATOR 28 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-3. 09-13-2010-B 5.10 5.00 SQ 4.90 Figure 65. 28-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-28-6) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADM1075-1ACPZ ADM1075-1ACPZ-RL7 ADM1075-1ARUZ ADM1075-1ARUZ-RL7 ADM1075-2ACPZ ADM1075-2ACPZ-RL7 ADM1075-2ARUZ ADM1075-2ARUZ-RL7 EVAL-ADM1075EBZ 1 2 Temperature Range 2 −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 28-Lead LFCSP_WQ (25 mV full-scale VSENSE) 28-Lead LFCSP_WQ (25 mV full-scale VSENSE) 28-Lead TSSOP (25 mV full-scale VSENSE) 28-Lead TSSOP (25 mV full-scale VSENSE) 28-Lead LFCSP_WQ (50 mV full-scale VSENSE) 28-Lead LFCSP_WQ (50 mV full-scale VSENSE) 28-Lead TSSOP (50 mV full-scale VSENSE) 28-Lead TSSOP (50 mV full-scale VSENSE) Evaluation Board Z = RoHS Compliant Part. Operating junction temperature is −40°C to +105°C. Rev. A | Page 51 of 52 Package Option CP-28-6 CP-28-6 RU-28 RU-28 CP-28-6 CP-28-6 RU-28 RU-28 ADM1075 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09312-0-4/12(A) Rev. A | Page 52 of 52