LINER LTC1657IN Parallel 16-bit rail-to-rail micropower dac Datasheet

LTC1657
Parallel 16-Bit Rail-to-Rail
Micropower DAC
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DESCRIPTIO
FEATURES
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The LTC®1657 is a complete single supply, rail-to-rail
voltage output, 16-bit digital-to-analog converter (DAC) in
a 28-pin SSOP or PDIP package. It includes a rail-to-rail
output buffer amplifier, an internal 2.048V reference and
a double buffered parallel digital interface.
16-Bit Monotonic Over Temperature
Deglitched Rail-to-Rail Voltage Output: 8nV•s
5V Single Supply Operation
ICC: 650µA Typ
Maximum DNL Error: ±1LSB
Settling Time: 20µs to ±1LSB
Internal or External Reference
Internal Power-On Reset to Zero Volts
Asynchronous CLR Pin
Output Buffer Configurable for Gain of 1 or 2
Parallel 16-Bit or 2-Byte Double Buffered Interface
Narrow 28-Lead SSOP Package
Multiplying Capability
The LTC1657 operates from a 4.5V to 5.5V supply. It has
a separate reference input pin that can be driven by an
external reference. The full-scale output can be 1 or 2
times the reference voltage depending on how the X1/X2
pin is connected.
The LTC1657 is similar to Linear Technology Corporation’s
LTC1450 12-bit VOUT DAC family allowing an upgrade
path. It is the only buffered 16-bit parallel DAC in a 28-lead
SSOP package and includes an onboard reference for
stand alone performance.
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APPLICATIO S
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Instrumentation
Digital Calibration
Industrial Process Control
Automatic Test Equipment
Communication Test Equipment
, LTC and LT are registered trademarks of Linear Technology Corporation.
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BLOCK DIAGRA
5V
19 D15 (MSB)
18
23
22
REFOUT
REFHI
24
VCC
REFERENCE
2.048V
17
MSB
8-BIT
INPUT
REGISTER
16
15
14
Differential Nonlinearity
vs Input Code
13
12
1.0
16-BIT
DAC
REGISTER
D8
11 D7
10
16-BIT
DAC
+
–
9
8
7
6
VOUT
LSB
8-BIT
INPUT
REGISTER
R
R
5
4 D0 (LSB)
3 CSMSB
FROM
MICROPROCESSOR
DECODE LOGIC
1 WR
FROM
SYSTEM RESET
27 CLR
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
2 CSLSB
28 LDAC
25 0V TO
4.096V
DIFFERENTIAL NONLINEARITY (LSB)
DATA IN FROM
MICROPROCESSOR
DATA BUS
16384
32768
49152
DIGITAL INPUT CODE
65535
1657 G01
POWER-ON
RESET
GND
20
REFLO
X1/X2
21
26
1657 TA01
1
LTC1657
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
VCC to GND .............................................. – 0.5V to 7.5V
TTL Input Voltage, REFHI, REFLO,
X1/X2 ....................................................... – 0.5V to 7.5V
VOUT, REFOUT ............................ – 0.5V to (VCC + 0.5V)
Operating Temperature Range
LTC1657C ............................................. 0°C to 70°C
LTC1657I ........................................ – 40°C to 85°C
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
TOP VIEW
WR
1
28 LDAC
CSLSB
2
27 CLR
CSMSB
3
26 X1/X2
(LSB) D0
4
25 VOUT
D1
5
24 VCC
D2
6
23 REFOUT
D3
7
22 REFHI
D4
8
21 REFLO
D5
9
20 GND
LTC1657CGN
LTC1657CN
LTC1657IGN
LTC1657IN
D6 10
19 D15 (MSB)
D7 11
18 D14
D8 12
17 D13
D9 13
16 D12
D10 14
15 D11
N PACKAGE
28-LEAD PDIP
GN PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/ W (G)
TJMAX = 125°C, θJA = 58°C/ W (N)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded, REFOUT tied to REFHI,
REFLO tied to GND, X1/X2 tied to GND, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC (Note 2)
Resolution
Monotonicity
●
16
●
16
Bits
Bits
DNL
Differential Nonlinearity
Guaranteed Monotonic (Note 3)
●
±0.5
±1.0
LSB
INL
Integral Nonlinearity
(Note 3)
●
±4
±12
LSB
2
mV
±0.3
±3
mV
ZSE
Zero Scale Error
VOS
Offset Error
VOSTC
Offset Error Tempco
●
Measured at Code 200
0
●
±5
Gain Error
±2
●
Gain Error Drift
µV/°C
±16
0.5
LSB
ppm/°C
Power Supply
VCC
Positive Supply Voltage
For Specified Performance
●
5.5
V
ICC
Supply Current
4.5V ≤ VCC ≤ 5.5V (Note 4)
●
4.5
650
1200
µA
Short-Circuit Current Low
VOUT Shorted to GND
●
70
120
mA
Short-Circuit Current High
VOUT Shorted to VCC
●
80
140
mA
Output Impedance to GND
Input Code = 0
●
40
120
Ω
Output Line Regulation
Input Code = 65535, VCC = 4.5V to 5.5V
●
Op Amp DC Performance
2
4
mV/V
LTC1657
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded, REFOUT tied to REFHI,
REFLO tied to GND, X1/X2 tied to GND, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
±0.3
±0.7
MAX
UNITS
AC Performance
Voltage Output Slew Rate
(Note 5)
Voltage Output Settling Time
(Note 5) to 0.0015% (16-Bit Settling Time)
(Note 5) to 0.012% (13-Bit Settling Time)
●
Digital Feedthrough
Midscale Glitch Impulse
DAC Switch Between 8000H and 7FFFH
Output Voltage Noise Spectral Density
At 1kHz
V/µs
20
10
µs
µs
0.3
nV •s
8
nV •s
250
nV/√Hz
Digital I/O
VIH
Digital Input High Voltage
●
2.4
V
VIL
Digital Input Low Voltage
●
VOH
Digital Output High Voltage
●
VOL
Digital Output Low Voltage
●
0.4
V
ILEAK
Digital Input Leakage
VIN = GND to VCC
●
±10
µA
CIN
Digital Input Capacitance
(Note 6)
10
pF
0.8
VCC – 1
V
V
Switching Characteristics
tCS
CS (MSB or LSB) Pulse Width
●
40
ns
tWR
WR Pulse Width
●
40
ns
tCWS
CS to WR Setup
●
0
ns
tCWH
CS to WR Hold
●
0
ns
tDWS
Data Valid to WR Setup
●
40
ns
tDWH
Data Valid to WR Hold
●
0
ns
tLDAC
LDAC Pulse Width
●
40
ns
tCLR
CLR Pulse Width
●
40
ns
●
2.036
Reference Output (REFOUT)
Reference Output Voltage
Reference Output
Temperature Coefficient
2.048
2.060
15
V
ppm/°C
Reference Line Regulation
VCC = 4.5V to 5.5V
●
±1.5
mV/V
Reference Load Regulation
Measured at IOUT = 100µA
●
5
mV/A
Short-Circuit Current
REFOUT Shorted to GND
●
(Note 6) See Applications Information
X1/X2 Tied to VOUT
X1/X2 Tied to GND
●
●
0
0
●
16
50
100
mA
Reference Input
REFHI, REFLO Input Range
REFHI Input Resistance
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: External reference REFHI = 2.2V. VCC = 5V.
Note 3: Nonlinearity is defined from code 128 to code 65535 (full scale).
See Applications Information.
VCC – 1.5
VCC /2
25
V
V
kΩ
Note 4: Digital inputs at 0V or VCC.
Note 5: DAC switched between all 1s and all 0s.
Note 6: Guaranteed by design. Not subject to test.
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LTC1657
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TYPICAL PERFOR A CE CHARACTERISTICS
Minimum Supply Headroom for
Full Output Swing vs Load Current
Integral Nonlinearity
5
2.0
0.8
4
1.8
3
1.6
2
1.4
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
VCC – VOUT (V)
1.0
INTEGRAL NONLINEARITY (LSB)
DIFFERENTIAL NONLINEARITY (LSB)
Differential Nonlinearity
1
0
–1
16384
32768
49152
DIGITAL INPUT CODE
0.4
–4
0.2
–55°C
16384
32768
49152
DIGITAL INPUT CODE
65535
0
5
LOAD CURRENT (mA)
1657 G02
Offset Error vs Temperature
4.110
CODE ALL 0’S
∆VOUT ≤ 1LSB
10
1657 G03
Full-Scale Voltage vs
Temperature
1.2
1.0
0.9
4.105
0.8
0.6
25°C
0.4
–55°C
0.8
0.7
4.100
OFFSET (mV)
125°C
FULL-SCALE VOLTAGE (V)
OUTPUT PULL-DOWN VOLTAGE (V)
25°C
0
0
Minimum Output Voltage vs
Output Sink Current
0.2
0.8
–3
1657 G01
1.0
1.0
0.6
65535
125°C
1.2
–2
–5
0
CODE ALL 1’S
∆VOUT ≤ 1LSB
4.095
4.090
0.6
0.5
0.4
0.3
0.2
4.085
0.1
0
0
5
10
OUTPUT SINK CURRENT (mA)
4.080
–55
15
–25
5
35
65
TEMPERATURE (°C)
1657 G04
95
0
–55
125
1657 G05
Supply Current vs Logic Input
Voltage
700
7
680
Large-Signal Transient Response
5
VOUT UNLOADED
TA = 25°C
4
4
3
2
OUTPUT VOLTAGE (V)
SUPPLY CURRENT (µA)
SUPPLY CURRENT (mA)
660
5
640
620
VCC = 5.5V
600
VCC = 5V
580
VCC = 4.5V
560
0
2
520
0
1
2
3
4
LOGIC INPUT VOLTAGE (V)
5
1657 G07
4
3
1
540
1
125
1657 G06
Supply Current vs Temperature
8
6
–10
35
80
TEMPERATURE (°C)
500
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
1657 G08
0
TIME (20µs/DIV)
1657 G09
LTC1657
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PIN FUNCTIONS
WR (Pin 1): Write Input (Active Low). Used with CSMSB
and/or CSLSB to control the input registers. While WR and
CSMSB and/or CSLSB are held low, data writes into the
input register.
CSLSB (Pin 2): Chip Select Least Significant Byte (Active
Low). Used with WR to control the LSB 8-bit input registers. While WR and CSLSB are held low, the LSB byte
writes into the LSB input register. Can be connected to
CSMSB for simultaneous loading of both sets of input
latches on a 16-bit bus.
CSMSB (Pin 3): Chip Select Most Significant Byte (Active
Low). Used with WR to control the MSB 8-bit input
registers. While WR and CSMSB are held low, the MSB
byte writes into the MSB input register. Can be connected
to CSLSB for simultaneous loading of both sets of input
latches on a 16-bit bus.
D0 to D7 (Pins 4 to 11): Input data for the Least Significant
Byte. Written into LSB input register when WR = 0 and
CSLSB = 0.
D8 to D15 (Pins 12 to 19): Input data for the Most Significant Byte. Written into MSB input register when WR = 0
and CSMSB = 0.
GND (Pin 20): Ground.
REFLO (Pin 21): Lower input terminal of the DAC’s internal resistor ladder. Typically connected to Analog Ground.
An input code of (0000)H will connect the positive input of
the output buffer to this end of the ladder. Can be used to
offset the zero scale above ground.
REFHI (Pin 22): Upper input terminal of the DAC’s internal
resistor ladder. Typically connected to REFOUT. An input
code of (FFFF)H will connect the positive input of the
output buffer to 1LSB below this voltage.
REFOUT (Pin 23): Output of the internal 2.048V reference.
Typically connected to REFHI to drive internal DAC resistor
ladder.
VCC (Pin 24): Positive Power Supply Input. 4.5V ≤ VCC ≤
5.5V. Requires a 0.1µF bypass capacitor to ground.
VOUT (Pin 25): Buffered DAC Output.
X1/X2 (Pin 26): Gain Setting Resistor Pin. Connect to GND
for G = 2 or to VOUT for G = 1. This pin should always be
tied to a low impedance source, such as ground or VOUT,
to ensure stability of the output buffer when driving
capacitive loads.
CLR (Pin 27): Clear Input (Asynchronous Active Low). A
low on this pin asynchronously resets all input and DAC
registers to 0s.
LDAC (Pin 28): Load DAC (Asynchronous Active Low).
Used to asynchronously transfer the contents of the input
registers to the DAC register which updates the output
voltage. If held low, the DAC register loads data from the
input registers which will immediately update VOUT.
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LTC1657
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DIGITAL INTERFACE TRUTH TABLE
CLR
CSMSB
CSLSB
WR
LDAC
L
H
H
H
H
H
H
H
H
H
X
X
X
L
H
L
X
H
X
L
X
X
X
H
L
L
X
X
H
L
X
X
X
L
L
L
H
X
X
L
X
L
H
X
X
X
X
X
X
L
FUNCTION
Clears input and DAC registers to zero
Loads DAC register with contents of input registers
Freezes contents of DAC register
Writes MSB byte into MSB input register
Writes LSB byte into LSB input register
Writes MSB and LSB bytes into MSB and LSB input registers
Inhibits write to MSB and LSB input registers
Inhibits write to MSB input register
Inhibits write to LSB input register
Data bus flows directly through input and DAC registers
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TIMING DIAGRAM
t CS
CSLSB
t CS
CSMSB
t CWS
t WR
t CWH
t WR
WR
t LDAC
LDAC
t DWH
t DWS
DATA
DATA VALID
DAC UPDATE
DATA VALID
1657 TD
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LTC1657
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DEFI ITIO S
Resolution (n): Resolution is defined as the number of
digital input bits (n). It defines the number of DAC output
states (2n) that divide the full-scale range. Resolution does
not imply linearity.
Full-Scale Voltage (VFS): This is the output of the DAC
when all bits are set to 1.
Voltage Offset Error (VOS): Normally, the DAC offset is the
voltage at the output when the DAC is loaded with all zeros.
The DAC can have a true negative offset, but because the
part is operated from a single supply, the output cannot go
below zero. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown in Figure 1.
0V
Integral Nonlinearity (INL): End-point INL is the maximum deviation from a straight line passing through the
end points of the DAC transfer curve. Because the part
operates from a single supply and the output cannot go
below zero, the linearity is measured between full scale
and the code corresponding to the maximum offset
specification. The INL error at a given input code is
calculated as follows:
INL (In LSBs) = [VOUT – VOS – (VFS – VOS)
(code/65535)]
VOUT = The output voltage of the DAC measured at
the given input code
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
Zero-Scale Error (ZSE): The output voltage when the
DAC is loaded with all zeros. Since this is a single supply
part, this value cannot be less than 0V.
DAC CODE
1657 F01
Figure 1. Effect of Negative Offset
The offset of the part is measured at the code that corresponds to the maximum offset specification:
VOS = VOUT – [(Code)(VFS)/(2n – 1)]
Least Significant Bit (LSB): One LSB is the ideal voltage
difference between two successive codes.
Differential Nonlinearity (DNL): DNL is the difference
between the measured change and the ideal one LSB
change between any two adjacent codes. The DNL error
between any two codes is calculated as follows:
DNL = (∆VOUT – LSB)/LSB
∆V OUT = The measured voltage difference between
two adjacent codes
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
nV • s.
LSB = (VFS – VOS)/(2n – 1) = (VFS – VOS)/65535
Nominal LSBs:
LTC1657 LSB = 4.096V/65535 = 62.5µV
DAC Transfer Characteristic:
 REFHI – REFLO 
VOUT = G • 
 CODE + REFLO
65536


(
)
G = 1 for X1/X2 connected to VOUT
G = 2 for X1/X2 connected to GND
CODE = Decimal equivalent of digital input
(0 ≤ CODE ≤ 65535)
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LTC1657
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OPERATION
Parallel Interface
The data on the input of the DAC is written into the DAC’s
input registers when Chip Select (CSLSB and/or CSMSB)
and WR are at a logic low. The data that is written into the
input registers will depend on which of the Chip Selects
are at a logic low (see Digital Interface Truth Table). If WR
and CSLSB are both low and CSMSB is high, then only
data on the eight LSBs (D0 to D7) is written into the input
registers. Similarly, if WR and CSMSB are both low and
CSLSB is high, then only data on the eight MSBs (D8 to
D15) is written into the input registers. Data is written into
both the Least Significant Data Bits (D0 to D7) and the Most
Significant Bits (D8 to D15) at the same time if WR, CSLSB
and CSMSB are low. If WR is high or both CSMSB and
CSLSB are high, then no data is written into the input
registers.
Once data is written into the input registers, it can be
written into the DAC register. This will update the analog
voltage output of the DAC. The DAC register is written by
a logic low on LDAC. The data in the DAC register will be
held when LDAC is high.
When WR, CSLSB, CSMSB and LDAC are all low, the
registers are transparent and data on pins D0 to D15 flows
directly into the DAC register.
For an 8-bit data bus connection, tie the MSB byte data
pins to their corresponding LSB byte pins (D15 to D7, D14
to D6, etc).
Power-On Reset
The LTC1657 has an internal power-on reset that resets all
internal registers to 0’s on power-up (equivalent to the
CLR pin function).
Reference
The LTC1657 includes an internal 2.048V reference, giving the LTC1657 a full-scale range of 4.096V in the gainof-2 configuration. The onboard reference in the LTC1657
is not internally connected to the DAC’s reference resistor
string but is provided on an adjacent pin for flexibility.
Because the internal reference is not internally connected
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to the DAC resistor ladder, an external reference can be
used or the resistor ladder can be driven by an external
source in multiplying applications. The external reference
or source must be capable of driving the 16k (minimum)
DAC ladder resistance.
Internal reference output noise can be reduced with a
bypass capacitor to ground. (Note: The reference does not
require a bypass capacitor to ground for nominal operation.) When bypassing the reference, a small value resistor
in series with the capacitor is recommended to help reduce
peaking on the output. A 10Ω resistor in series with a 4.7µF
capacitor is optimum for reducing reference generated
noise. Internal reference output voltage noise spectral
density at 1kHz is typically 150nV/√Hz.
DAC Resistor Ladder
The high and low end of the DAC ladder resistor string
(REFHI and REFLO, respectively) are not connected internally on this part. Typically, REFHI will be connected to
REFOUT and REFLO will be connected to GND. X1/X2
connected to GND will give the LTC1657 a full-scale output
swing of 4.096V.
Either of these pins can be driven up to VCC – 1.5V when
using the buffer in the gain-of-1 configuration. The resistor
string pins can be driven to VCC/2 when the buffer is in the
gain of 2 configuration. The resistance between these two
pins is typically 25k (16k min).
Voltage Output
The output buffer for the LTC1657 can be configured for
two different gain settings. By tying the X1/X2 pin to GND,
the gain is set to 2. By tying the X1/X2 pin to VOUT, the gain
is set to unity.
The LTC1657 rail-to-rail buffered output can source or
sink 5mA within 500mV of the positive supply voltage or
ground at room temperature. The output stage is equipped
with a deglitcher that results in a midscale glitch impulse
of 8nV • s. The output swings to within a few millivolts of
either supply rail when unloaded and has an equivalent
output resistance of 40Ω when driving a load to the rails.
LTC1657
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APPLICATIONS INFORMATION
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC /2. If VREF = VCC /2 and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 1c. No full-scale limiting
can occur if VREF is less than (VCC – FSE)/2.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
VCC
VREF = VCC /2
POSITIVE
FSE
OUTPUT
VOLTAGE
INPUT CODE
(c)
VCC
VREF = VCC /2
OUTPUT
VOLTAGE
0
32768
INPUT CODE
(a)
65535
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
1657 F02
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC /2
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LTC1657
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TYPICAL APPLICATIO S
the onboard reference is always sourcing current and
never has to sink any current even when VOUT is at full
scale. The LT1077 output will have a wide bipolar output
swing of – 4.096V to 4.096V as shown in the figure below.
With this output swing, 1LSB = 125µV.
This circuit shows how to make a bipolar output 16-bit
DAC with a wide output swing using an LTC1657 and an
LT1077. R1 and R2 resistively divide down the LTC1657
output and an offset is summed in using the LTC1657
onboard 2.048V reference and R3 and R4. R5 ensures that
A Wide Swing, Bipolar Output 16-Bit DAC
5V
0.1µF
24
5:19
DATA (0:15)
2
CSLSB
3
µP
VCC
CSMSB
1
VOUT
LTC1657
WR
28
25
R1
100k
1%
LDAC
27
CLR
X1/X2 REFLO GND
26
21
REFHI REFOUT
20
22
23
R2
200k
1%
TRANSFER CURVE
4.096
5V
3
7
+
6
LT1077
2
–
R3
100k
1%
VOUT:
(2)(DIN)(4.096)
– 4.096V
65536
4
R4
– 5V 200k
1%
1657 TA05
VOUT
32768
0
65535
DIN
R5
100k
1%
– 4.096
This circuit shows a digitally programmable current source
from an external voltage source using an external op amp,
an LT1218 and an NPN transistor (2N3440). Any digital
word from 0 to 65535 is loaded into the LTC1657 and its
output correspondingly swings from 0V to 4.096V. This
voltage will be forced across the resistor RA. If RA is
chosen to be 412Ω, the output current will range from
0mA at zero scale to 10mA at full scale. The minimum
voltage for VS is determined by the load resistor RL and
Q1’s VCESAT voltage. With a load resistor of 50Ω, the
voltage source can be 5V.
Digitally Programmable Current Source
5V
22
5:19
2
µP
3
1
28
27
DATA (0:15)
23
5V < VS < 100V
FOR RL ≤ 50Ω
0.1µF
REFHI REFOUT VCC
CSLSB
CSMSB
LTC1657
VOUT
WR
3
+
X1/X2 REFLO GND
26
21
2
–
RL
7
LT1218
LDAC
CLR
25
6
Q1
2N3440
(DIN)(4.096)
(65536)(RA)
≈ 0mA TO 10mA
IOUT =
4
20
RA
412Ω
1%
1657 TA04
10
LTC1657
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
28-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.386 – 0.393*
(9.804 – 9.982)
0.033
(0.838)
REF
28 27 26 25 24 23 22 21 20 19 18 17 1615
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
0.015 ± 0.004
× 45°
(0.38 ± 0.10)
0.0075 – 0.0098
(0.191 – 0.249)
2 3
4
5 6
7
8
9 10 11 12 13 14
0.053 – 0.069
(1.351 – 1.748)
0.004 – 0.009
(0.102 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.0250
(0.635)
BSC
0.008 – 0.012
(0.203 – 0.305)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN28 (SSOP) 1098
N Package
28-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.370*
(34.789)
MAX
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0.255 ± 0.015*
(6.477 ± 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.130 ± 0.005
(3.302 ± 0.127)
0.045 – 0.065
(1.143 – 1.651)
0.020
(0.508)
MIN
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
8.255
+0.889
–0.381
)
0.125
(3.175)
MIN
0.065
(1.651)
TYP
0.005
(0.127)
MIN
0.100
(2.54)
BSC
0.018 ± 0.003
(0.457 ± 0.076)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
N28 1098
11
LTC1657
U
TYPICAL APPLICATIO
This circuit shows how to measure negative offset. Since
LTC1657 operates on a single supply, if its offset is
negative, the output for code 0 limits at 0V. To measure
this negative offset, a negative supply is needed, connect
resistor R1 as shown in the figure. The output voltage is
the negative offset when code 0 is loaded in.
Negative Offset Measurement
5V
22
5:19
2
3
µP
1
28
27
23
24
0.1µF
REFHI REFOUT VCC
DATA (0:15)
CSLSB
CSMSB
LTC1657
VOUT
WR
25
R1
100k
LDAC
CLR
X1/X2 REFLO GND
26
21
–5V
20
1657 TA06
Although LTC1657 output is up to 4.096V with its internal
reference, higher voltages can be achieved with the help of
another op amp. The following circuit shows how to
increase the output swing of LTC1657 by using an LT1218.
As shown in the configuration, the output of LTC1657 is
amplified by 8 for an output swing of 0V to 32.768V, or a
convenient 0.5mV/LSB.
A Higher Voltage Output DAC
TRANSFER CURVE
VOUT
5V
22
5:19
2
3
µP
1
28
27
DATA (0:15)
23
0.1µF 36V
24
REFHI REFOUT VCC
32.768 (V)
0.1µF
CSLSB
CSMSB
LTC1657
VOUT
WR
25
+
7
LT1218
LDAC
CLR
3
X1/X2 REFLO GND
26
21
2
–
6
VOUT =
4
20
R1
1k
1%
( )
(DIN)(4.096)
R2
1+
65536
R1
0
R2
6.98k
1%
65535
DIN
1657 TA07
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1446(L)
Dual 12-Bit VOUT DACs in SO-8 Package
VCC = 5V (3V), VOUT = 0V to 4.095V (0V to 2.5V)
LTC1450(L)
Single 12-Bit VOUT DACs with Parallel Interface
VCC = 5V (3V), VOUT = 0V to 4.095V (0V to 2.5V)
LTC1458(L)
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
VCC = 5V (3V), VOUT = 0V to 4.095V (0V to 2.5V)
LTC1650
Single 16-Bit VOUT Industrial DAC in 16-Pin SO
VCC = ±5V, Low Power, Deglitched, 4-Quadrant Multiplying VOUT
LTC1655(L)
Single 16-Bit VOUT DAC with Serial Interface in SO-8
VCC = 5V (3V), Low Power, Deglitched, VOUT = 0V to 4.096V
(0V to 2.5V)
12
Linear Technology Corporation
1657f LT/TP 0400 4K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1999