ON NCN6001DTBR2G Compact smart card interface ic Datasheet

NCN6001
Compact Smart Card
Interface IC
The NCN6001 is an integrated circuit dedicated to the smart card
interface applications. The device handles any type of smart card
through a simple and flexible microcontroller interface. On top of that,
thanks to the built−in chip select pin, several couplers can be
connected in parallel.
The device is particularly suited for low cost, low power
applications, with high extended battery life coming from extremely
low quiescent current.
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1
TSSOP−20
DTB SUFFIX
CASE 948E
Features
•
•
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•
•
•
•
•
•
•
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•
100% Compatible with ISO 7816−3, EMV and GIE−CB Standards
Fully GSM Compliant
Wide Battery Supply Voltage Range: 2.7 < VCC < 5.5 V
Programmable CRD_VCC Supply Handles 1.8 V, 3.0 V or 5.0 V
Card Operation
Programmable Rise and Fall Card Clock Slopes
Programmable Card Clock Divider
Built−in Chip Select Logic Allows Parallel Coupling Operation
ESD Protection on Card Pins (8.0 kV, Human Body Model)
Supports up to 40 MHz Input Clock
Built−in Programmable CRD_CLK Stop Function Handles Run or
Low State
Programmable CRD_CLK Slopes to Cope with Wide Operating
Frequency Range
Fast CRD_VCC Turn−on and Turn−off Sequence
These are Pb−Free Devices
PIN CONNECTIONS
I/O 1
20 CRD_IO
INT 2
19 CRD_RST
CLK_IN 3
18 CRD_DET
MOSI 4
17 CRD_CLK
CLK_SPI 5
16 GND
EN_RPU 6
15 C4/S0
MISO 7
14 C8/S1
CS 8
13 CRD_VCC
VCC 9
12 Lout_H
Lout_L 10
11 PWR_GND
(Top View)
Typical Applications
•
•
•
•
E−Commerce Interface
Automatic Teller Machine (ATM) Smart Card
Point of Sales (POS) System
Pay TV System
MARKING DIAGRAM
20
NCN
6001
ALYWG
G
1
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 32 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 6
1
Publication Order Number:
NCN6001/D
NCN6001
VCC
J1
9
GND
1
2
U1
CRD_DET
VCC
CRD_IO
I/O
CRD_RST
INT
MICROCONTROLLER
3
4
5
7
8
6
R1
47 k
10
CLK_IN
CRD_CLK
CRD_VCC
MOSI
CLK_SPI
C4/S0
MISO
C8/S1
GND
CS
EN_RPU
Lout_L
VCC
18
20
7
19
2
17
3
13
5
15
GND
1
14
4
16
8
C2
10 F
11
PWR_GND
Lout_H
NCN6001
GND
18
Swa
Swb
I/O
RST
CLK
GND
ISO7816
10 F
C1
17
VCC
C4
C8
SMARTCARD_C
12
L1
GND
GND
22 H
Figure 1. Typical Application
VCC
PROGRAMMABLE
CARD DETECTION
50 k
INT
2
CS
8
INTERRUPT BLOCK
18 CRD_DET
500 k
VCC
MOSI
4
CLK_SPI
5
9
DC/DC CONVERTER
3 States
ADDRESS DECODING
7
DUAL 8−BIT
SHIFT REGISTER
MISO
b7
b6
b5
b4
b3
b2
b1
b0
b0
b1
VCC
10 Lout_L
12 Lout_H
13 CRD_VCC
11 PWR_GND
EN_RPU
6
I/O
CLOCK
DIVIDER
20 k
1
b5
b6
b4
15 C4/S0
CARD PINS DRIVER
3
ISO7816 SEQUENCER
CLK_IN
b2
b3
LOGIC CONTROL
b7
GND
14 C8/S1
19 CRD_RST
17 CRD_CLK
20 CRD_IO
20 k
GROUND
16
CRD_VCC
GND
Figure 2. Block Diagram
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NCN6001
PIN FUNCTIONS AND DESCRIPTION
TSSOP
Name
Type
Description
1
I/O
Input/Output
Pullup
2
INT
OUTPUT
Pullup
This pin is activated LOW when a card has been inserted and detected by CRD_DET pin.
Similarly, an interrupt is generated when the CRD_VCC output is overloaded, or when the card
has been extracted whatever be the transaction status (running or standby).
The INT signal is reset to High according to Table 7 and Figure 10. On the other hand, the pin
is forced to a logic High when the input voltage VCC drops below 2.0 V.
3
CLK_IN
CLOCK
INPUT
High
impedance
The built−in Schmitt trigger receiver makes this pin suitable for a large type of clock signal
(Figure 29). This pin can be connected to either the microcontroller master clock, or to a
crystal signal, to drive the external smart cards. The signal is fed to the internal clock selector
circuit and translated to the CRD_CLK pin at either the same frequency, or divided by 2 or 4,
depending upon the programming mode.
Note: The chip guarantees the EMV 50% Duty Cycle when the clock divider ratio is 1/2 or 1/4,
even when the CLK_IN signal is out of the 45% to 55% range specified by ISO and EMV
specifications.
Care must be observed, at PCB level, to minimize the pick−up noise coming from the CLK_IN
line.
4
MOSI
INPUT
Master Out Slave In: SPI Data Input from the external microcontroller. This byte contents the
address of the selected chip among the four possible, together with the programming code for
a given interface.
5
CLK_SPI
INPUT
Clock Signal to synchronize the SPI data transfer. The built−in Schmitt trigger receiver makes
this pin compatible with a wide range of input clock signal (Figure 29). This clock is fully
independent from the CLK_IN signal and does not play any role with the data transaction.
6
EN_RPU
INPUT, Logic
7
MISO
OUTPUT
8
CS
INPUT
This pin synchronizes the SPI communication and provides the chip address and selected
functions.
All the NCN6001 functions, both programming and card transaction, are disabled when
CS = H.
9
VCC
POWER
This pin is connected to the NCN6001 supply voltage and must be bypassed to ground by
a 10 F/6.0 V capacitor.
Since tantalum capacitors have relative high ESR, using low ESR ceramic type (MURATA
X5R, Resr < 100 m) is highly recommended.
10
Lout_L
POWER
The Low Side of the external inductor is connected between this pin and pin 12 to provide the
DC/DC function. The current flowing into this inductor is internally sensed and no external
shunt resistor is used. Typically, Lout = 22 H, with DSR < 2.0 , yields a good efficiency
performance for a maximum 65 mA DC output load.
Note: The inductor shall be sized to handle the 450 mA peak current flowing during the DC/DC
operation (see CoilCraft manufacturer data sheet).
This pin is connected to an external microcontroller interface. A bidirectional level translator
adapts the serial I/O signal between the smart card and the microcontroller. The level
translator is enabled when CS = L, the sub address has been selected and the system
operates in the Asynchronous mode. When a Synchronous card is in use, this pin is
disconnected and the data and the transaction take place with the MISO b3 register.
The internal pullup resistor connected on the C side is activated and visible by the selected
chip only.
This pin is used to activate the I/O internal pullup resistor according to the here below true
table:
EN_RPU = Low → I/O Pullup resistor disconnected
EN_RPU = High → I/O Pullup resistor connected
When two or more NCN6001 chips shares the same I/O bus, one chip only shall have the
internal pullup resistor enabled to avoid any overload of the I/O line.
Moreover, when Asynchronous and Synchronous cards are handled by the interfaces, the
activated I/O pullup resistor must preferably be the one associated with the Asynchronous
circuit.
On the other hand, since no internal pullup bias resistor is built in the chip, pin 6 must be
connected to the right voltage level to make sure the logic function is satisfied.
Master In Slave Out: SPI Data Output from the NCN6001. This byte carries the state of the
interface, the serial transfer being achieved according to the programmed mode (Table 2),
using the same CLK_SPI signal and during the same MOSI time frame. The three high bits
[b7:b5] have no meaning and shall be discarded by the microcontroller. An external 4.7 k Pull
down resistor might be necessary to avoid misunderstanding of the pin 7 voltage during the
High Z state.
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NCN6001
PIN FUNCTIONS AND DESCRIPTION (continued)
TSSOP
Name
Type
11
PWR_GND
POWER
This pin is the Power Ground associated with the built−in DC/DC converter and must be
connected to the system ground together with GROUND pin 16. Using good quality ground
plane is recommended to avoid spikes on the logic signal lines.
Description
12
Lout_H
POWER
The High Side of the external inductor is connected between this pin and pin 10 to activate the
DC/DC function. The built−in NMOS and PMOS devices provide the switching function
together with the CRD_VCC voltage rectification (Figure 16).
13
CRD_VCC
POWER
This pin provides the power to the external card. It is the logic level “1” for CRD_IO,
CRD_RST, CRD_C4, CRD_C8 and CRD_CLK signals.
The energy stored by the DC/DC external inductor Lout must be smoothed by a 10 F/Low
ESR capacitor, connected across CRD_VCC and GND. Using ceramic type of capacitor
(MURATA X5R, ESR < 50 m) is strongly recommended. In the event of a CRD_VCC UVLOW
voltage, the NCN6001 detects the situation and feedback the information in the STATUS bit.
The device does not take any further action, particularly the DC/DC converter is neither
stopped nor re programmed by the NCN6001. It is up to the external MPU to handle the
situation.
However, when the CRD_VCC is overloaded, the NCN6001 shuts off the DC/DC converter,
runs a Power Down ISO sequence and reports the fault in the STATUS register.
Since high transient current flows from this pin to the load, care must be observed, at PCB
level, to minimize the series ESR and ESL parasitic values. The NCN6001 demo board
provides an example of a preferred PCB layout.
14
C8/S1
I/O
Auxiliary mixed analog/digital line to handle either a synchronous card, or as Chip Select
Identification (MISO, Bit 0): see Figure 8. The pin is driven by an open drain stage, the pullup
resistor being connected to the CRD_VCC supply. When the pin is used as a logic input
(asynchronous cards), the positive logic condition applies:
Connected to GND → Logic = Zero
Connected to VCC or left Open → Logic = One
A built−in accelerator circuit makes sure the output positive going rise time is fully within the
ISO/EMV specifications.
NOTE:
15
C4/S0
I/O
The pin is capable of reading the logic level when the chip operates an asynchronous
interface, but is not intended to read the data from the external card when operated in
the synchronous mode. It merely returns the logic state forced during a write
instruction to the card.
Auxiliary mixed analog/digital line to handle either a synchronous card, or as Chip Select
Identification (MISO, Bit 1): see Figure 8. The pin is driven by an open drain stage, the pullup
resistor being connected to the CRD_VCC supply. When the pin is used as a logic input
(asynchronous cards), the positive logic condition applies:
Connected to GND → Logic = Zero
Connected to VCC or left Open → Logic = One
A built−in accelerator circuit makes sure the output positive going rise time is fully within the
ISO/EMV specifications.
NOTE:
The pin is capable of reading the logic level when the chip operates an asynchronous
interface, but is not intended to read the data from the external card when operated in
the synchronous mode. It merely returns the logic state forced during a write
instruction to the card.
16
GND
SIGNAL
The logic and low level analog signals shall be connected to this ground pin. This pin must be
externally connected to the PWR_GND pin 12. The designer must make sure no high current
transients are shared with the low signal currents flowing into this pin.
17
CRD_CLK
OUTPUT
This pin is connected to the CLK pin of the card connector. The CRD_CLK signal comes from
the clock selector circuit output. An internal active pull down NMOS device forces this pin to
Ground during either the CRD_VCC startup sequence, or when CRD_VCC = 0 V.
The rise and fall slopes, either FAST or SLOW, of this signal can be programmed by the MOSI
message (Table 2).
Care must be observed, at PCB level, to minimize the pick−up noise coming from the
CRD_CLK line.
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NCN6001
PIN FUNCTIONS AND DESCRIPTION (continued)
TSSOP
Name
Type
Description
18
CRD_DET
INPUT
The signal coming from the external card connector is used to detect the presence of the card.
A built−in pullup low current source biases this pin High, making it active LOW, assuming one
side of the external switch is connected to ground. A built−in digital filter protect the system
against voltage spikes present on this pin.
The polarity of the signal is programmable by the MOSI message, according to the logic state
depicted Table 2. On the other hand, the meaning of the feedback message contained in the
MISO register bit b4, depends upon the SPI mode of operation as defined here below:
SPI Normal Mode: The MISO bit b4 is High when a card is inserted, whatever be the polarity
of the card detect switch.
SPI Special Mode: The MISO bit b4 copies the logic state of the Card detect switch as
depicted here below, whatever be the polarity of the switch used to handle the detection:
CRD_DET = Low → MISO/b4 = Low
CRD_DET = High → MISO/b4 = High
In both cases, the chip must be programmed to control the right logic state (Table 2).
Since the bias current supplied by the chip is very low, typically 5.0 A, care must be observed
to avoid low impedance or cross coupling when this pin is in the Open state.
19
CRD_RST
OUTPUT
This pin is connected to the RESET pin of the card connector. A level translator adapts the
RESET signal from the microcontroller to the external card. The output current is internally
limited to 15 mA.
The CRD_RST is validated when CS = Low and hard wired to Ground when the card is
deactivated, by and internal active pull down circuit.
Care must be observed, at PCB design level, to avoid cross coupling between this signal and
the CRD_CLK clock.
20
CRD_IO
I/O
Pullup
This pin handles the connection to the serial I/O pin of the card connector. A bidirectional level
translator adapts the serial I/O signal between the card and the microcontroller. An internal
active pull down MOS device forces this pin to Ground during either the CRD_VCC startup
sequence, or when CRD_VCC = 0 V. The CRD_IO pin current is internally limited to 15 mA.
Care must be observed, at PCB design level, to avoid cross coupling between this signal and
the CRD_CLK clock.
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NCN6001
MAXIMUM RATINGS (TA = +25°C unless otherwise noted)
Symbol
Value
Unit
Power Supply Voltage
Rating
VCC
6.0
V
Power Supply Current
Note: This current represents the maximum peak current the
pin can sustain, not the NCN6001 average consumption.
Ibat
500
mA
Power Supply Current
ICC
150 (Internally Limited)
mA
Digital Input Pins
Vin
−0.5 V < Vin < VCC +0.5 V, but < 6.0 V
V
Digital Input Pins
Iin
±5.0
mA
Digital Output Pins
Vout
−0.5 V < Vin < VCC +0.5 V, but < 6.0 V
V
Digital Output Pins
Iout
±10
mA
Card Interface Pins
Vcard
−0.5 V < Vcard < CRD_VCC +0.5 V
V
Card Interface Pins, excepted CRD_CLK
Icard
15 (Internally Limited)
mA
Inductor Current
ILout
500 (Internally Limited)
mA
ESD Capability (Note 1)
Standard Pins
Card Interface Pins
CRD_DET
VESD
2.0
8.0
4.0
kV
kV
kV
Power Dissipation @ Tamb = +85°C
Thermal Resistance, Junction−to−Air (RJA)
PDS
RJA
320
125
mW
°C/W
Operating Ambient Temperature Range
TA
−25 to +85
°C
Operating Junction Temperature Range
TJ
−25 to +125
°C
TJmax
+150
°C
Tstg
−65 to +150
°C
Maximum Junction Temperature (Note 2)
Storage Temperature Range
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Human Body Model, R = 1500 , C = 100 pF.
2. Absolute Maximum Rating beyond which damage to the device may occur.
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NCN6001
DIGITAL PARAMETERS @ 2.7 V < VCC < 5.5 V (−25°C to +85°C ambient temperature, unless otherwise noted).
Note: Digital inputs undershoot < − 0.3 V to ground, Digital inputs overshoot < 0.3 V to VCC.
Pin
Symbol
Min
Typ
Max
Input Asynchronous Clock Duty Cycle = 50%
@ VCC = 3.0 V Over the Temperature Range
@ VCC = 5.0 V Over the Temperature Range
3
FCLKIN
−
−
−
−
30
40
Input Clock Rise Time
Input Clock Fall Time
3
Ftr
Ftf
2.5
2.5
−
−
−
−
ns
ns
Input SPI Clock
5
FCLKSPI
−
−
15
MHz
Input CLK_SPI Rise/Fall Time @ Cout = 30 pF
5
trspi, tfspi
−
−
12
ns
Input MOSI Rise/Fall Time @ Cout = 30 pF
4
trmosi,
tfmosi
−
−
12
ns
Output MISO Rise/Fall Time @ Cout = 30 pF
7
trmiso,
tfmiso
−
−
12
ns
Input CS Rise/Fall Time
8
trstr, tfstr
−
−
12
ns
tRIO
tFIO
−
−
−
−
0.8
0.8
s
s
20
50
80
k
0.70 * VCC
−
VCC
0
−
0.3 * VCC
VCC −1.0 V
−
VCC
−
−
0.4
33
−
−
Rating
I/O Data Transfer Switching Time, both directions
(I/O and CRD_IO), @ Cout = 30 pF
I/O Rise Time * (Note 4)
I/O Fall Time
INT Pullup Resistance
MHz
1, 20
2
RITA
Positive Going Input High Voltage Threshold
(CLK_IN, MOSI, CLK_SPI, EN_RPU, CS)
2, 3, 4, 5,
6, 8
VIA
Negative Going Input High Voltage Threshold
(CLK_IN, MOSI, CLK_SPI, EN_RPU, CS)
2, 3, 4, 5,
6, 8
VILLA
Output High Voltage
INT, MISO @ OH = −10 A
2, 7
VOH
Output Low Voltage
INT, MISO @ OH = 200 A
2, 7
Delay Between Two Consecutive CLK_SPI Sequence
Unit
5
V
V
V
VOL
tdclk
V
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Since a 20 k (typical) pullup resistor is provided by the NCN6001, the external MPU can use an Open Drain connection. On the other hand,
NMOS smart cards can be used straightforward.
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NCN6001
POWER SUPPLY @ 2.7 V < VCC < 5.5 V (−25°C to +85°C ambient temperature, unless otherwise noted).
Pin
Symbol
Min
Typ
Max
Unit
Input Power Supply
Rating
9
VCC
2.70
−
5.50V
V
Standby Supply Current Conditions:
INT = CLK_IN = CLK_SPI = CS = H
I/O = MOSI = EN_RPU = H, No Card Inserted
VCC = 3.0 V
VCC = 5.0 V
9
ICCsb
DC Operating Current
CLK_IN = Low, All Card Pins Unloaded
@ VCC = 3.3 V, CRD_VCC = 5.0 V
@ VCC = 5.5 V, CRD_VCC = 5.0 V
9
VCC Under Voltage DetectionHigh
VCC Under Voltage DetectionLow
VCC Under Voltage (Note 6)
9
Output Card Supply Voltage
@ 2.7 V < VCC < 5.5 V
CRD_VCC = 1.8 V @ Iload = 35 mA
CRD_VCC = 3.0 V @ Iload = 60 mA
CRD_VCC = 5.0 V @ Iload = 65 mA
13
Maximum Continuous Output Current
@ CRD_VCC = 1.8 V
@ CRD_VCC = 3.0 V
@ CRD_VCC = 5.0 V
13
Output Over Current Limit
VCC = 3.3 V, CRD_VCC = 1.8 V, 3.0 V or 5.0 V
VCC = 5.0 V, CRD_VCC = 1.8 V, 3.0 V or 5.0 V
13
Output Dynamic Peak Current
@ CRD_VCC = 1.8 V, 3.0 V or 5.0 V, Cout = 10 F
(Notes 4 and 5)
13
Output Card Supply Voltage Ripple
@ VCC = 3.6 V, Lout = 22 H, Cout1 = Cout2 = 4.7 F
Ceramic X7R, Iout = 55 mA
CRD_VCC = 5.0 V
CRD_VCC = 3.0 V (Note 4)
CRD_VCC = 1.8 V
13
Output Card Supply Turn On Time @
Lout = 22 F, Cout1 = 10 F Ceramic
VCC = 2.7 V, CRD_VCC = 5.0 V
13
Output Card Supply Shut Off Time @
Cout1 = 10 F, Ceramic
VCC = 2.7 V, CRD_VCC = 5.0 V, VCCOFF < 0.4 V
13
−
−
25
35
50
60
ICCop
VCCLH
VCCLL
VCCPOR
mA
−
−
−
−
0.5
1.5
2.20
2.00
1.50
−
−
−
2.70
2.60
2.20
1.65
2.75
4.75
−
1.80
3.00
5.00
1.95
3.25
5.25
35
60
65
−
−
−
−
−
−
−
−
100
150
−
−
100
−
−
V
V
VC2H
VC3H
VC5H
ICC
mA
Iccov
mA
Iccd
mA
−
mV
−
−
−
35
35
35
−
−
−
−
−
500
−
100
250
s
VCCTON
s
VCCTOFF
4. Ceramic X7R, SMD type capacitors are mandatory to achieve the CRD_VCC specifications. When an electrolytic capacitor is used, the
external filter must include a 220 nF, max 50 m ESR capacitor in parallel, to reduce both the high frequency noise and ripple to a minimum.
Depending upon the PCB layout, it might be necessary to use two 4.7 F/6.0 V/ceramic/X5R/SMD 0805 in parallel, yielding an improved
CRD_VCC ripple over the temperature range.
5. Pulsed current, according to ISO7816−3, paragraph 4.3.2.
6. No function externally available during the VCC POR sequence.
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NCN6001
SMART CARD INTERFACE @ 2.7 V < VCC < 5.5 V (−25°C to +85°C ambient temperature, unless otherwise noted).
Note: Digital inputs undershoot < −0.3 V to ground, Digital inputs overshoot < 0.3 V to VCC.
Pin
Symbol
Min
Typ
Max
Unit
VOH
VOL
tR
tF
CRD_VCC − 0.5
0
−
−
−
−
−
−
CRD_VCC
0.4
100
100
V
V
ns
ns
FCRDCLK
VOH
VOL
−
CRD_VCC – 0.5
0
20
CRD_VCC
+0.4
MHz
V
V
FCRDDC
45
40
40
55
60
60
%
%
%
Rise & Fall time @ CRD_VCC = 1.80 V to 5.0 V
Fast Mode
Output CRD_CLK Rise time @ Cout = 30 pF
Output CRD_CLK Fall time @ Cout = 30 pF
tress
tfcs
−
−
2.1
1.9
4
4
ns
ns
Rise & Fall time @ CRD_VCC = 1.80 V to 5.0 V
Slow Mode
Output CRD_CLK Rise time @ Cout = 30 pF
Output CRD_CLK Fall time @ Cout = 30 pF
trills
tulsa
−
−
11.5
10.8
16
16
ns
ns
400
−
−
−
−
−
0.8
0.8
CRD_VCC
0.4
kHz
s
s
V
V
Rating
CRD_RST @ CRD_VCC = 1.8 V, 3.0 V, 5.0 V
Output RESET VOH @ Irst = −200 A
Output RESET VOL @ Irst = 200 A
Output RESET Rise Time @ Cout = 30 pF
Output RESET Fall Time @Cout = 30 pF
19
CRD_CLK as a function of CRD_VCC
17
CRD_VCC = +5.0 V or 3.0 V or 1.8V
Output Frequency
Output VOH @ Icrd_clk = −200 A
Output VOL @ Icrd_clk = 200 A
CRD_CLK Output Duty Cycle
CRD_VCC = 5.0 V
CRD_VCC = 3.0 V
CRD_VCC = 1.8 V (Note 7)
CRD_IO @ CRD_VCC = 1.8 V 3.0 V, 5.0 V
CRD_IO Data Transfer Frequency
CRD_IO Rise time @ Cout = 30 pF
CRD_IO Fall time @ Cout = 30 pF
Output VOH @ Icrd_clk = −20 A
Output VOL @ Icrd_clk = 500 A, VIL = 0 V
20
CRD_IO Pullup Resistor
20
RCRDPU
14
20
26
k
CRD_C8 Output Rise and Fall Time @ Cout = 30 pF
14
tRC8, tFC8
−
−
100
ns
CRD_C4 Output Rise and Fall Time @ Cout = 30 pF
15
tRC4, tFC4
−
−
100
ns
CRD_C4 and CRD_C8 Data Transfer Frequency
14, 15
FC48
−
400
−
kHz
CRD_C8, CRD_C4 Output Voltages
High Level @ Irst = −200 A
Low Level @ Irst = +200 A
14, 15
VOH, VOL
CRD_VCC – 0.5
0
−
−
−
0.4
V
V
C8/S0 and C4/S0 Address Bias Current (Note 8)
14, 15
Ibc4c8
−
1.0
−
A
TCRDIN
TCRDOFF
25
25
50
50
150
150
s
s
FIO
tRIO
tFIO
VOH
VOL
−
−
−
CRD_VCC
0
− 0.5
Card Detection Digital Filter Delay:
Card Insertion
Card Extraction
18
Card Insertion or Extraction Positive Going Input High Voltage
18
VIHDET
0.70 * VCC
−
VCC
V
Card Insertion or Extraction Negative Going Input Low Voltage
18
VILDET
0
−
0.30 * VCC
V
Card Detection Bias Pullup Current @ VCC = 5.0 V
18
IDET
−
10
−
A
Output Peak Max Current Under Card Static Operation
Mode @ CRD_VCC = 3.0 V or = 5.0 V
CRD_RST, CRD_IO, CRD_C4, CRD_C8
1, 20
Icrd_iorst
−
−
15
mA
Output Peak Max Current Under Card Static Operation
Mode @ CRD_VCC = 3.0 V or = 5.0 V
CRD_CLK
17
Icrd_clk
−
−
70
mA
7. Parameter guaranteed by design, function 100% production tested.
8. Depending upon the environment, using and external pullup resistor might be necessary to cope with PCB surface leakage current.
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NCN6001
PROGRAMMING
Write Register
"
WRT_REG
The CRD_RST pin reflects the content of the MOSI
WRT_REG[b4] during the chip programming sequence.
Since this bit shall be Low to address the internal register of
the chip, care must be observed as this signal will be
immediately transferred to the CRD_RST pin.
The WRT_REG register handles three command bits
[b5:b7] and five data bits [b0:b4] as depicted in Table 1.
These bits are concatenated into a single byte to accelerate
the programming sequence. The register can be updated
when CS is low only.
Table 1. WRT_REG BITS DEFINITIONS
b0,
b1
If (b7 + b6 + b5) <> 110 and (b7 + b6 + b5) <> 101 and (b7 + b6 + b5) <> 111 then
Case 00
CRD_VCC = 0 V
Case 01
CRD_VCC = 1.8 V
Case 10
CRD_VCC = 3.0 V
Case 11
CRD_VCC = 5.0 V
Else if (b7 + b6 + b5) = 110 then
b1 drives C4
b0 drives C8
Else if (b7 + b6 + b5) = 101 then
Case (b4 + b3 + b2 + b1 + b0) = 0000
CRD_DET = NO
Case (b4 + b3 + b2 + b1 + b0) = 0001
CRD_DET = NC
Case (b4 + b3 + b2 + b1 + b0) = 0010
SPI_MODE = Special
Case (b4 + b3 + b2 + b1 + b0) = 0011
SPI_MODE = Normal
End if
b2,
b3
If (b7 + b6 + b5) <> 110 and (b7 + b6 + b5) <> 101 and (b7 + b6 + b5) <> 111 then
Case 00
CRD_CLK = L
Case 01
CRD_CLK = CLK_IN
Case 10
CRD_CLK = CLK_IN/2
Case 11
CRD_CLK = CLK_IN/4
Else if (b7 + b6 + b5) = 110 then
b3 drives CRD_CLK
b2 drives CRD_IO
Else if (b7 + b6 + b5) = 101 then
Case (b4 + b3 + b2 + b1 + b0) = 0000
CRD_DET = NO
Case (b4 + b3 + b2 + b1 + b0) = 0001
CRD_DET = NC
Case (b4 + b3 + b2 + b1 + b0) = 0010
SPI_MODE = Special
Case (b4 + b3 + b2 + b1 + b0) = 0011
SPI_MODE = Normal
End if
b4
Drives CRD_RST pin (Note 10)
b5,
b6,
b7
000
001
010
011
100
110
101
111
Select Asynchronous Card #0 (Note 9), four chips bank CS signal
Select Asynchronous Card #1 (Note 9), four chips bank CS signal
Select Asynchronous Card #2 (Note 9), four chips bank CS signal
Select Asynchronous Card #3 (Note 9), four chips bank CS signal
Select External Asynchronous Card, dedicated CS signal
Select External Synchronous Card, dedicated CS signal
Set Card Detection Switch polarity, Set SPI_MODE normal or special. Set CRD_CLK slopes Fast or Slow.
Reserved for future use
9. When operating in Asynchronous mode, [b5:b7] are compared with the external voltage levels present pins C4/S0 and C8/S1 (respectively
pins 15 and 14).
10. The CRD_RST pin reflects the content of the MOSI WRT_REG[b4] during the chip programming sequence. Since this bit shall be Low to
address the internal register of the chip, care must be observed as this signal will be immediately transferred to the CRD_RST pin.
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NCN6001
Table 2. WRT_REG BITS DEFINITIONS AND FUNCTIONS
ADDRESS
PARAMETERS
CHIP
BANK
MOSI bits
[b3:b2]
MOSI bits
[b1:b0]
MOSI bits
[b7:b0]
1
b7
b6
b5
b4
b3
b2
b1
b0
CRD_CLK
CRD_VCC
CRD_DET
1
0
X
X
RST
0
0
0
0
Low
0
−
1
0
X
X
RST
0
1
0
1
1/1
1.8 V
−
1
0
X
X
RST
1
0
1
0
1/2
3.0 V
−
1
0
X
X
RST
1
1
1
1
1/4
5.0 V
−
1
1
0
1
0
0
0
0
0
−
−
NO
1
1
0
1
0
0
0
0
1
−
−
NC
1
1
0
1
0
0
0
1
0
−
−
Special
1
1
0
1
0
0
0
1
1
−
−
Normal
1
1
0
1
0
0
1
0
0
−
−
SLO_SLP
1
1
0
1
0
0
1
0
1
−
−
FST_SLP
1
1
1
1
−
−
−
−
−
−
−
RFU
2
1
0
0
RST
0
0
0
0
Low
0
−
2
1
0
0
RST
0
1
0
1
1/1
1.8 V
−
2
1
0
0
RST
1
0
1
0
1/2
3.0 V
−
2
1
0
0
RST
1
1
1
1
1/4
5.0 V
−
2
1
1
0
RST
CLK
I/O
C4
C8
−
−
Data to Sync. Card
2
1
0
1
0
0
0
0
0
−
−
NO
2
1
0
1
0
0
0
0
1
−
−
NC
2
1
0
1
0
0
0
1
0
−
−
Special
2
1
0
1
0
0
0
1
1
−
−
Normal
2
1
0
1
0
0
1
0
0
−
−
SLO_SLP
2
1
0
1
0
0
1
0
1
−
−
FST_SLP
2
1
1
1
−
−
−
−
−
−
−
RFU
11. Chip Bank 1 = Asynchronous cards, four slots addresses 1 to 4.
Chip Bank 2 = Asynchronous or synchronous card, single slot.
12. Address 101 and bits [b0 : b4] not documented in the table are reserved for future use.
Address 111 is reserved for future use.
likely to happen if the system uses a common Chip Select
line. It is strongly recommended to run a dedicated CS bit to
any external circuit intended to use the $111xxxxx code.
On the other hand, the CRD_RST signal will be forced to
Low when the internal register of the chip is programmed to
accommodate different hardware conditions (NO/NC,
Special/Normal, SLO_SLP/FST_SLP). Generally speaking,
such a configuration shall take place during the Power On
Reset to avoid CRD_RST activation.
Although using the %111XXXXX code is harmless from
a NCN6001 silicon standpoint, care must be observed to
avoid uncontrolled operation of the interface sharing the
same digital bus. When this code is presented on the digital
bus, the CRD_RST signal of any interface sharing the CS
signal, immediately reflects the digital content of the MOSI
bit b4 register. Similarly, the MISO register of the shared
interface is presented on the SPI port. Consequently, data
collision, at MISO level, and uncontrolled card operation are
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NCN6001
Read Register
"
READ_REG
either on the Positive going (SPI_MODE = Special) or upon
the Negative going slope (SPI_MODE = Normal) of the
CLK_SPI signal. The external microcontroller shall discard
the three high bytes since they carry no valid data.
The READ_REG register contains the data read from the
interface and from the external card. The selected register is
transferred to the MISO pin during the MOSI sequence
(CS = Low). Table 3 gives the bits definition.
Depending upon the programmed SPI_MODE, the
content of READ_REG is transferred on the MISO line
Table 3. MOSI AND MISO BITS IDENTIFICATIONS AND FUNCTIONS
MOSI
MISO
b7
b6
b5
b4
b3
b2
b1
b0
Operating Mode
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
RST
RST
RST
RST
RST
RST
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
I/O
VCC
VCC
VCC
VCC
VCC
C4
VCC
VCC
VCC
VCC
VCC
C8
Asynchronous, Program Chip
Asynchronous, Program Chip
Asynchronous, Program Chip
Asynchronous, Program Chip
Asynchronous, Program Chip
Synchronous, Sets Card Bits
z
z
z
Card Detect
I/O
C4
C8
PWR Monitor
Read Back Data
ASYNCHRONOUS MODE
In this mode, the CRD_C4 and CRD_C8 pins are used to
define the physical addresses of the interfaces when a bank
of up to four NCN6001 share the same digital bus.
CRD_VCC output voltage shall be done by sending
a previous MOSI message according to Table 1 and Table 2.
The CRD_RST pin reflects the content of the MOSI
WRT_REG[b4] during the chip programming sequence.
Since this bit shall be Low to address the internal register of
the chip, care must be observed as this signal will be
immediately transferred to the CRD_RST pin.
Since no physical address can exist when the chip operates
in this mode, the MOSI register must use the format
%100XXXXX to program the chip (%100 prefix, XXXXX
data).
SYNCHRONOUS MODE
In this mode, CRD_C4 and CRD_C8 are connected to the
smart card and it is no longer possible to share the CS signal
with other device. Consequently, a dedicated Chip Select
signal must be provided when the interfaces operate in
a multiple operation mode (Figure 33).
On the other hand, since bits [b4 – b0] of the MOSI
register contain the smart card data, programming the
Example:
LDAA
STAA
LDAA
STAA
LDAA
STAA
#%10010111
MOSI
#%11010011
MOSI
#%00111110
MOSI
;set RST = H, CLK = 1/1, VCC = 5.0 V
;SYNC. Card: set RST = H, CLK = L, IO = L, C4 = H, C8= H
;ASYNC. Card: set RST = H, CLK = ¼, VCC = 3.0 V
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NCN6001
CRD_VCC OPERATION
The built−in DC/DC converter provides the CRD_VCC
voltage and can be programmed to run one of the three
possible values, 1.8V, 3.0V or 5.0V, assuming the input
voltage VCC is within the 2.7V to 5.5V range. In any case,
CRD_VCC is voltage regulated, together with a current
overload detection. On the other hand, the power conversion
is automatically switched to handle either a boost or a buck
mode of operation, depending upon the difference between
the input voltage VCC and the output supply CRD_VCC.
The CRD_VCC output current is a function of the VCC
input value as depicted in Table 5.
STARTUP DEFAULT CONDITIONS
At startup, when the VCC power supply is turned on,
the internal POR circuit sets the chip in the default
conditions as defined in Table 4.
Table 4. STARTUP DEFAULT CONDITIONS
CRD_DET
Normally Open
CRD_VCC
Off
CRD_CLK
tr and tf = SLOW
CRD_CLK
Low
Protocol
Special Mode
Table 5. CRD_VCC OUTPUT VOLTAGE RANGE
CARD DETECTION
The card is detected by the external switch connected pin
18. The internal circuit provides a positive bias of this pin
and the polarity of the insertion/extraction is programmable
by the MOSI protocol as depicted in Table 2.
The bias current is 1.0A typical and care must be
observed to avoid leakage to ground from this pin to
maintain the logic function. In particular, using a low
impedance probe (< 1.0M) may lead to uncontrolled
operation during the debug.
Depending upon the programmed condition, the card can
be detected either by a Normally Open (default condition) or
a Normally Close switch (Table 2). On the other hand, the
meaning of the feedback message contained in the MISO
register bit b4, depends upon the SPI mode of operation as
defined here below:
SPI Normal Mode: the MISO bit b4 is High when a card is
inserted, whatever be the polarity of the card detect switch.
SPI Special Mode: the MISO bit b4 copies the logic state of
the Card detect switch as depicted here below, whatever be
the polarity of the switch used to handle the detection:
CRD_DET = Low → MISO/b4 = Low
CRD_DET = High → MISO/b4 = High
CRD_VCC
Comments
1.80 V
Maximum Output DC Current = 35 mA
3.0 V
Maximum Output DC Current = 60 mA
5.0 V
Maximum Output DC Current = 65 mA
Whatever the CRD_VCC output voltage may be,
a built−in comparator makes sure the voltage is within the
ISO7816−3/ EMV specifications. If the voltage is no longer
within the minimum/maximum values, the DC/DC is
switched Off, the Power Down sequence takes place and an
interrupt is presented at the INT pin 2.
POWERUP SEQUENCE
The Powerup Sequence makes sure all the card related
signals are Low during the CRD_VCC positive going slope.
These lines are validated when CRD_VCC is above the
minimum specified voltage (depending upon the
programmed CRD_VCC value).
Figure 3. Typical Startup CRD_VCC Sequence
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NCN6001
current absorbed by the internal NMOS transistor built
across CRD_VCC and GROUND. These behaviors are
depicted in Figure 4.
Since these parameters have finite values, depending
upon the external constraints, the designer must take care of
these limits if the tON or the tOFF provided by the data sheets
does not meet his requirements.
At powerup, the CRD_VCC voltage rise time depends
upon the current capability of the DC/DC converter
associated with the external inductor L1 and the reservoir
capacitor connected across CRD_VCC and GROUND.
During this sequence, the average input current is 300 mA
typical (Figure 3), assuming the system is fully loaded
during the startup. Finally, the application software is
responsible for the smart card signal sequence.
On the other hand, at turn off, the CRD_VCC fall time
depends upon the external reservoir capacitor and the peak
Figure 4. CRD_VCC Typical Rise and Fall Time
Figure 5. Startup Sequence with ATR
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NCN6001
POWER DOWN SEQUENCE
The NCN6001 provides an automatic Power Down
sequence, according to the ISO7816−3 specifications, and
the communication session terminates immediately. The
sequence is launched when the card is extracted, or when the
CRD_VCC voltage is overloaded as described by the
ISO/CEI 7816−3 sequence depicted hereafter:
ISO7816−3 sequence:
"Force RST to Low
"Force CLK to Low, unless it is already in this state
"Force C4 & C8 to Low
"Force CRD_IO to Low
"Shut Off the CRD_VCC supply
Since the internal digital filter is activated for any card
insertion or extraction, the physical power sequence will be
activated 50 s (typical) after the card has been extracted. Of
course, such a delay does not exist when the MPU
intentionally launches the power down. Figure 6 shows the
oscillogram captured in the NCN6001 demo board.
The internal active pull down NMOS connected across
CRD_VCC and GND discharges the external reservoir
capacitor in 100 s (typical), assuming Cout = 10 F.
Typical delay between each signal is 500 ns
Figure 6. Typical Power Down Sequence
The internal active pull down NMOS connected across CRD_VCC and GND discharges the external reservoir capacitor in
100s (typical), assuming Cout = 10F.
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NCN6001
DATA I/O LEVEL SHIFTER
The level shifter accommodates the voltage difference
that might exist between the microcontroller and the smart
card. A pulsed accelerator built−in circuit provides the fast
positive going transient according to the ISO7816−3
specifications. The basic I/O level shifter is depicted in
Figure 7.
VCC
9
6
EN_RPU
U1
PMOS
VCC
200 ns
Q1
R1
CRD_VCC
200 ns
13
Q2
R2
18 k
18 k
CRD_IO
I/O
20
1
Q3
Q4
CARD ENABLE
SYNC
Q5
LOGIC AND
LEVEL SHIFT
POR
SEQ 1
GND
CRD_VCC
MOSI/b2
Q5
VCC
From MOSI
decoding
GND
MOSI/b3
Figure 7. Basic I/O Internal Circuit
The transaction is valid when the Chip Select pin is Low,
the I/O signal being Open Drain or Totem Pole on either
sides.
Since the device can operate either in a single or a multiple
card system, provisions have been made to avoid CRD_IO
current overload. Depending upon the selected mode of
operation (ASYNC. or Sync), the card I/O line is
respectively connected to either I/O pin 1, or to the MOSI
register byte bit 2. On the other hand, the logic level present
at the card I/O is feedback to the C via the MISO register
bit 3. The logic level present at pin 6 controls the connection
of the internal pullup as depicted in Table 6.
Table 6. I/O PULLUP RESISTOR TRUE TABLE
EN_RPU
I/O Pullup Resistor
Device
Operation
Low
Open, 18 k disconnected
Parallel Mode
High
Internal 18 k pullup active
Single Device
NOTE:
NOTE: Both sides of the interface run with open drain load
(worst case condition).
Figure 8. Typical I/O Rise and Fall Time
18 k typical value
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NCN6001
GENERAL PURPOSE CRD_C4 AND CRD_C8
These two pins can be used as a logic input to define the
address of a given interface (in the range $00 to $11), or as
a standard C4/C8 access to the smart card’s channels. Since
VCC
these pins can be directly connected to the VCC power
supply, both output stages are built with switched
NMOS/PMOS totem pole as depicted in Figure 9.
Vmax
CRD_VCC
LEVEL
SHIFTER
WRT_C4
U1
Q2
SWITCHED
BIAS
U3
R1
C4
ADDRESS
1
CONTROL
2
3
READ_C4
U4
3
Q1
1
U8
2
VCC
I=1A
CRD_VCC
U5
3
500 R
1
U7
U2
GND
Q3
U6
2
ESD
U9
GND
Figure 9. Typical CRD_C4 Output Drive and Logic Control
The switched Totem Pole structure provides the fast
positive going transient when the related pin is forced to the
High state during a data transfer. In the event of a low
impedance connected across C4 or C8 to ground, the current
flow is limited to 15 mA, according to the ISO7816−3
specification.
The two general purpose pins can transfer data from the
external microcontroller to the card and read back the logic
state, but none of these pins can read the data coming from
the external smart card. On the other hand, both C4 and C8
can read input logic, hence the physical address of a given
chip.
In order to sustain the 8 kV ESD specified for these pins,
an extra protection structure Q3 has been implemented to
protect the MOS gates of the input circuit.
The C4 and C8 pins are biased by an internal current
source to provide a logic one when the pin is left open. In this
case, care must be observed to avoid relative low impedance
to ground to make sure the pin is at a High logic level.
However, it is possible to connect the pin to VCC (battery
supply) to force the logic input to a High level, regardless of
the input bias. Thanks to the CONTROL internal signal, the
system automatically adapts the mode of operation (chip
address or data communication) and, except the leakage, no
extra current is drawn from the battery to bias these pins
when the logic level is High.
When any of these pins is connected to GND, a continuous
1 A typical sink current will be absorbed from the battery
supply.
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NCN6001
INTERRUPT
When the system is powered up, the INT pin is set to High
upon POR signal. The interrupt pin 2 is forced LOW when
either a card is inserted/extracted, or when a fault is
developed across the CRD_VCC output voltage. This signal
is neither combined with the CS signal, nor with the chip
address. Consequently, an interrupt is placed on the C input
as soon as one of the condition is met.
The INT signal is clear to High upon one of the condition
given in Table 7.
Table 7. INTERRUPT RESET LOGIC
Interrupt Source
CS
CRD_VCC
Chip Address
Card Insertion
L
>0
Selected Chip MOSI[b7 : B5] = 0xx or MOSI[b7 : B5] = 101
Card Insertion
L
=0
Selected Chip MOSI[b7 :B5] = 0xx or MOSI[b7 : B5] = 101
Over Load
L
=0
Selected Chip MOSI[b7 : B5] = 0xx or MOSI[b7 : B5] = 101
When several interfaces share the same digital C bus, it is up to the software to pool the chips, using the MISO register to
identify the source of the interrupt.
T0
T1
T2
T3
T4
T5
T6
T8 T9
T10
T11
CS
INT
CRD_DET
MOSI_b0
MOSI_b1
1
2
3
T7
CRD_VCC > 0 V
CRD_VCC = 0 V
OVER LOAD
CRD_VCC
Figure 10. Basic Interrupt Function
Table 8. INTERRUPT RESET LOGIC OPERATION
T0
A card has been inserted into the reader and detected by the CRD_DET signal. The NCN6001 pulls down the interrupt line.
T1
The C sets the CS signal to Low, the chip is now active, assuming the right address has been placed by the MOSI register.
T2
The C acknowledges the interrupt and resets the INT to High by the MOSI [B1 : B0 ] logic state: CRD_VCC is programmed
higher than zero volt.
T3
The card has been extracted from the reader, CRD_DET goes Low and an interrupt is set (INT = L). On the other hand, the
PWR_DOWN sequence is activated by the NCN6001.
T4
The interrupt pin is clear by the zero volt programmed to the interface.
T5
Same as T0
T6
The C start the DC/DC converter, the interrupt is cleared (same as T2)
T7
An overload has been detected by the chip : the CRD_VCC voltage is zero, the INT goes Low.
T8
The card is extracted from the reader, CRD_DET goes Low and an interrupt is set (INT = L).
T9
The card is re−inserted before the interrupt is acknowledged by the C: the INT pin stays Low.
T10
The C acknowledges the interrupt and reset the INT to High by the MOSI [B1 : B0 ] logic state: CRD_VCC is programmed
higher than zero volt.
T11
The Chip Select signal goes High, all the related NCN6001 interface(s) are deactivated and no further programming or
transaction can take place.
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NCN6001
SPI PORT
The product communicates to the external
microcontroller by means of a serial link using
a Synchronous Port Interface protocol, the CLK_SPI being
Low or High during the idle state. The NCN6001 is not
intended to operate as a Master controller, but execute
commands coming from the MPU.
The CLK_SPI, the CS and the MOSI signals are under the
microcontroller’s responsibility. The MISO signal is
generated by the NCN6001, using the CLK_SPI and CS
CS
SPI_CLK
lines to synchronize the bits carried out by the data byte.
The basic timings are given in Figure 11 and Figure 12.
The system runs with two internal registers associated with
the MOSI and MISO data:
WRT_REG is a write only register dedicated to the MOSI
data.
READ_REG is a read only register dedicated to the MISO
data.
MPU Asserts Chip Select
MPU Enables
Clock
NCN6001 Reads Bit
MPU Sends Bit
MOSI
tclr
RST_COUNTER
NCN6001 Sends Bit
from READ_REG
MPU Reads Bit
MISO
Figure 11. Basic SPI Timings and Protocol
To accommodate the simultaneous MISO transmit, an
internal logic identifies the chip address on the fly (reading
and decoding the three first bits) and validates the right data
present on the line. Consequently, the data format is MSB
first to read the first three signal as bits B5, B6 and B7. The
chip address is decoded from this logic value and validates
the chip according to the C4 and C8 conditions (Figure 12).
When the CS line is High, no data can be written or read
on the SPI port. The two data lines becomes active when
CS = Low, the internal shift register is cleared and the
communication is synchronized by the negative going edge
of the CS signal. The data present on the MOSI line is
considered valid on the negative going edge of the CLK_SPI
clock and is transferred to the shift register on the next
positive edge of the same CLK_SPI clock.
CS
MPU Asserts Chip Set
B7
SPI_CLK
MOSI
B6
B5
CHIP
ADDRESS
B3
B2
B1
B0
COMMAND AND CONTROL
LSB
MSB
ADDRESS
DECODE
MISO
B4
MPU Enables Clock
The Chip Address is decoded on the third clock pulse.
MISO Line = High Impedance
The MISO signal is activated and data transferred
Figure 12. Chip Address Decoding Protocol and MISO Sequence
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19
NCN6001
When the eight bits transfer is completed, the content of
the internal shift register is latched on the positive going
edge of the CS signal and the NCN6001 related functions are
updated accordingly.
Select Chip from SYNCHRONOUS Bank
Chip Nx
tdclk
Chip Ny
CS
SPI_CLK
MPU Enables B7 B6
Clock
B5
CHIP
ADDRESS
MOSI
B4
B3
B2
B1
B0
B7 B6
B5
B4
B3
B2
B1
B0
COMMAND
AND CONTROL
MSB
LSB
MSB
LSB
SET_RST
SET_CLK
SET_VCC
ADDRESS
DECODE
MISO
Special Mode
MISO Line = High Impedance
MISO Line = High Impedance
MISO
Normal Mode
Normal Mode: MISO is synchronized with
the SPI_CLK Negative going slope
Special Mode: MISO
is synchronized with
the SPI_CLK Positive
going slope
Figure 13. Basic Multi Command SPI Bytes
When two SPI bytes are sequentially transferred on the
MOSI line, the CLK_SPI sequence must be separated by at
least one half positive period of this clock (see tdclk
parameter).
The oscillograms shown in Figure 14 and Figure 15
illustrate the SPI communication protocol (source:
NCN6001 demo board).
Since the four chips present in the Asynchronous Bank
have an individual physical address, the system can control
several of these chips by sending the data content within the
same CS frame as depicted in Figure 13. The bits are
decoded on the fly and the related sub blocks are updated
accordingly. According to the SPI general specification, no
code or activity will be transferred to any chip when the CS
is High.
Figure 14. Programming Sequence, Chip Address = $03
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NCN6001
Protocol: Special Mode
Protocol: Standard SPI
Figure 15. MISO Read Out Sequences
DC/DC OPERATION
The power conversion is based on a full bridge structure
capable to handle either step up or step down power supply
(Figure 16). The operation is fully automatic and, beside the
output voltage programming, does not need any further
adjustments.
VCC
CRD_VCC
6
10 F
C1
13
Q1
Q7
GND
CMD_3.0V
CMD_5.0V
CMD_STOP
MIXED LOGIC/ANALOG BLOCK
CMD_1.8V
C2
10 F
Q2
L1
10
G_Q1
GND
12
22 H
Q3
Q5
Q6
Q4
GND
G_Q3
G_HIZ
11
PWR_GND
GND
G_Q4
G_Q2
G_Q7
Figure 16. Basic DC/DC Converter
In order to achieve the 250 s max time to discharge
CRD_VCC to 400 mV called by the EMV specifications, an
active pull down NMOS is provided (Q7) to discharge the
external CRD_VCC reservoir capacitor. This timing is
guaranteed for a 10 F maximum load reservoir capacitor
value (Figure 4).
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NCN6001
The system operates with a two cycles concept (all comments are referenced to Figure 16 and Figure 17):
1 − Cycle 1
Q1 and Q4 are switched ON and the inductor L1 is charged by the energy supplied by the external battery.
During this phase, the pair Q2/Q3 and the pair Q5/Q6 are switched OFF.
The current flowing the two MOSFET Q1 and Q4 is internally monitored and will be switched OFF when
the Ipeak value (depending upon the programmed output voltage value) is reached. At this point, Cycle 1 is
completed and Cycle 2 takes place. The ON time is a function of the battery voltage and the value of the inductor network (L and Zr) connected across pins 10/11.
A 4 s timeout structure ensures the system does run in a continuous Cycle 1 loop
2 − Cycle 2
Q2 and Q3 are switched ON and the energy stored into the inductor L1 is dumped into the external load
through Q2. During this phase, the pair Q1/Q4 and the pair Q5/Q6 are switched OFF.
The current flow period is constant (900 ns typical) and Cycle 1 repeats after this time if the CRD_VCC
voltage is below the specified value.
When the output voltage reaches the specified value (1.8 V, 3.0 V or 5.0 V), Q2 and Q3 are switched OFF
immediately to avoid over voltage on the output load. In the meantime, the two extra NMOS Q5 and Q6 are
switched ON to fully discharge any current stored into the inductor, avoiding ringing and voltage spikes over
the system. Figure 17 illustrates the theoretical waveforms present in the DC/DC converter.
Charge CRD_VCC
ton
CRD_VCC Charged
Next CRD_VCC Charge
(Time is Not to Scale)
toff
Q1/Q4
Q2/Q3
Q5/Q6
Ipeak
IL
CRD_VCC Voltage Regulated
Vripple
CRD_VCC
Figure 17. Theoretical DC/DC Operating Waveforms
the temperature range and the combination of standard parts
provide an acceptable –20% to +20% tolerance, together
with a low cost. Table 9 gives a quick comparison between
the most common type of capacitors. Obviously, the
capacitor must be SMD type to achieve the extremely low
ESR and ESL necessary for this application. Figure 18
illustrates the CRD_VCC ripple observed in the NCN6001
demo board depending upon the type of capacitor used to
filter the output voltage.
When the CRD_VCC is programmed to zero volt, or when
the card is extracted from the socket, the active pull down Q7
rapidly discharges the output reservoir capacitor, making
sure the output voltage is below 0.4 V when the card slides
across the ISO contacts.
Based on the experiments carried out during the
NCN6001 characterization, the best comprise, at time of
printing this document, is to use two 4.7 F/10 V/
ceramic/X7R capacitors in parallel to achieve the
CRD_VCC filtering. The ESR will not extend 50 m over
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NCN6001
Table 9. CERAMIC/ELECTROLYTIC CAPACITORS COMPARISON
Manufacturers
Type/Series
Format
Max Value
Tolerance
Typ. Z @ 500 kHz
MURATA
CERAMIC/GRM225
0805
10 F/6.3 V
−20%/+20%
30 m
MURATA
CERAMIC/GRM225
0805
4.7 F/6.3 V
−20%/+20%
30 m
VISHAY
Tantalum/594C/593C
−
10 F/16 V
−
450 m
VISHAY
Electrolytic/94SV
−
10 F/10 V
−20%/+20%
400 m
−
Electrolytic Low Cost
−
10 F/10 V
−35%/+50%
2.0 The DC/DC converter is capable to start with a full load
connected to the CRD_VCC output as depicted in Figure 19.
In this example, the converter is fully loaded when the
system starts from zero.
Test Conditions: Cout = 2x 4.7 F/6 V/ceramic X7R,
Temp = +25°C
Iout = Maximum Specification
Figure 19. Output Voltage Startup Under Full Load
Conditions
Figure 18. Typical CRD_VCC Ripple Voltage
74
The curves illustrate the typical behavior under full output
current load (35 mA, 60 mA and 65 mA), according to EMV
specifications.
Vout = 3.0 V
72
70
Vout = 5.0 V
Eff(%)
68
66
Vout = 1.8 V
64
62
60
58
2.5
3.0
3.5
4.0
Vbat (V)
4.5
5.0
5.5
Lout = 22 H/ESR = 2 Figure 20. CRD_VCC Efficiency as a Function of the
Input Supply Voltage
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NCN6001
During the operation, the inductor is subject to high peak
current as depicted Figure 21 and the magnetic core must
sustain this level of current without damage. In particular,
the ferrite material shall not be saturated to avoid
uncontrolled current spike during the charge up cycle.
Moreover, since the DC/DC efficiency depends upon the
losses developed into the active and passive components,
selecting a low ESR inductor is preferred to reduce these
losses to a minimum.
Test Conditions: Input VCC voltage = 5.0 V
Current = 200 mA/div
Tamb = +20°C
Figure 21. Typical Inductor Current
On the other hand, the circuit is designed to make sure no
over current exist over the full temperature range. As
a matter of fact, the output current limit is reduced when the
temperature increases: see Figure 23.
According to the ISO7816−3 and EMV specifications, the
interface shall limits the CRD_VCC output current to
200 mA maximum, under short circuit conditions.
The NCN6001 supports such a parameter, the limit being
depending upon the input and output voltages as depicted in
Figure 22.
160
180
Vo = 5.0 V
160
140
Vo = 3.0 V
140
Iout (mA)
120
Iout
Vo = 5.0 V
150
100
80
Vo = 1.8 V
60
Vo = 3.0 V
130
120
40
Vo = 1.8 V
110
20
100
−25
0
2
3
4
5
6
Vbat
−5
15
35
55
75
95
115
TEMPERATURE (°C)
Iomax = F (Vbat)
Figure 23. Output Current Limit as a Function of
the Temperature
Figure 22. Output Current Limits
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NCN6001
SMART CARD CLOCK DIVIDER
The main purpose of the built−in clock generator is
threefold:
last flip flop, thus yielding a constant 50% duty cycle,
whatever be the divider ratio (Figure 24). Consequently, the
output CRD_CLK frequency division can be delayed by
four CLK_IN pulses and the microcontroller software must
take this delay into account prior to launch a new data
transaction. On the other hand, the output signal Duty Cycle
cannot be guaranteed 50% if the division ratio is 1 and if the
input Duty Cycle signal is not within the 46–56% range.
The input signals CLK_IN and MOSI/b3 are
automatically routed to the level shifter and control block
according to the mode of operation.
1. Adapts the voltage level shifter to cope with the
different voltages that might exist between the
MPU and the Smart Card.
2. Provides a frequency division to adapt the Smart
Card operating frequency from the external clock
source.
3. Controls the clock state according to the smart
card specification.
In addition, the NCN6001 adjusts the signal coming from
the microprocessor to get the Duty Cycle window as defined
by the ISO7816−3 specification.
The byte content of the SPI port, B2 & B3, fulfills the
programming functions when CS is Low as depicted in
Figure 25 and Figure 24. The clock input stage (CLK_IN)
can handle a 20 MHz frequency maximum signal, the
divider being capable to provide a 1:4 ratio. Of course, the
ratio must be defined by the engineer to cope with the Smart
Card considered in a given application and, in any case, the
output clock [CRD_CLK] shall be limited to 20 MHz
maximum. In order to minimize the dI/dt and dV/dV
developed in the CRD_CLK line, the output stage includes
a special function to adapt the slope of the clock signal for
different applications. This function is programmed by the
MOSI register (Table 2: WRT_REG Bits Definitions and
Functions) whatever be the clock division.
In order to avoid any duty cycle out of the smart card
ISO7816−3 specification, the divider is synchronized by the
CLOCK_IN
CLOCK : 1
Internal
CLOCK
Divider
CLOCK : 2
CLOCK : 4
B2
These bits program
CLOCK = 1:1 ratio
B3
Clock is updated upon
CLOCK: 4 rising edge
CRD_CLK
CLOCK programming is activated
by the B2 + B3 logic state
Figure 24. Typical Clock Divider Synchronization
VCC
CRD_VCC
CLK_IN
U1
DIGITAL_MUX
ASYNC
B2
B3
B
Programming
CRD_CLK
Division
OUT
SYNC
LEVEL SHIFTER
AND CONTROL
SEL
A
SYNC
B0
B1
Programming
CRD_CLK Slope
NOTE: Bits [B0...B3] come from SPI data
Figure 25. Basic Clock Divider and Level Shifter
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CRD_CLK
NCN6001
The input clock can be divided by 1/1, ½ or ¼, depending
upon the specific application, prior to be applied to the smart
card driver. On the other hand, the positive and negative
going slopes of the output clock (CRD_CLK) can be
programmed to optimize the operation of the chip
(Table 10). The slope of the output clock can be
programmed on the fly, independently of either the
CRD_VCC voltage or the operating frequency, but care
must be observed as the CRD_RST will reflect the logic
state present at MOSI/b4 register.
Table 10. OUTPUT CLOCK RISE AND FALL TIME SELECTION
B0
B1
CRD_CLK
Division Ratio
CRD_CLK
SLO_SLP
CRD_CLK
FST_SLP
0
0
−
Output Clock = Low
Output Clock = Low
0
1
1
10 ns (typ.)
2 ns (typ.)
1
0
1/2
10 ns (typ.)
2 ns (typ.)
1
1
1/4
10 ns (typ.)
2 ns (typ.)
Figure 26. Force CRD_CLK to Low
Figure 27. Force CRD_CLK to Active Mode
Figure 28. CRD_CLK Programming
Note: Waveforms recorded without external compensation
network.
Figure 29. CRD_CLK Operating Low Speed (Top Trace),
Full Speed (Bottom Trace)
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NCN6001
INPUT SCHMITT TRIGGERS
All the Logic Input pins have built−in Schmitt trigger
circuits to protect the NCN6001 against uncontrolled
operation. The typical dynamic characteristics of the related
pins are depicted in Figure 30.
The output signal is guaranteed to go High when the input
voltage is above 0.70* VCC, and will go Low when the input
voltage is below 0.30* VCC.
or under voltage situation, updates the READ_REG register
accordingly and forces INT pin to Low. This register can be
read out by the MPU.
Battery Voltage: Both the over and under voltage are
detected by the NCN6001, the READ_REG register being
updated accordingly. The external MPU can read the register
through the MISO pin to take whatever is appropriate to
cope with the situation.
ESD PROTECTION
The NCN6001 includes silicon devices to protect the pins
against the ESD spikes voltages. To cope with the different
ESD voltages developed across these pins, the built−in
structures have been designed to handle either 2.0 kV, when
related to the microcontroller side, or 8.0 kV when
connected with the external contacts. Practically, the
CRD_RST, CRD_CLK, CRD_IO, CRD_C4, and CRD_C8
pins can sustain 8.0 kV, the maximum short circuit current
being limited to 15 mA. The CRD_VCC pin has the same
ESD protection, but can source up to 65 mA continuously,
the absolute maximum current being internally limited to
150 mA.
OUTPUT
Vbat
ON
OFF
INPUT
0.3 Vbat
0.7 Vbat
Vbat
Figure 30. Typical Schmitt Trigger Characteristic
PRINTED CIRCUIT BOARD LAYOUT
Since the NCN6001 carries high speed currents together
with high frequency clock, the printed circuit board must be
carefully designed to avoid the risk of uncontrolled
operation of the interface.
A typical single sided PCB layout is provided in Figure 32
highlighting the ground technique. Dual face printed circuit
board may be necessary to solve ringing and cross talk with
the rest of the system.
SECURITY FEATURES
In order to protect both the interface and the external smart
card, the NCN6001 provides security features to prevent
catastrophic failures as depicted hereafter.
Pin Current Limitation: In the case of a short circuit to
ground, the current forced by the device is limited to 15 mA
for any pins, except CRD_CLK pin. No feedback is
provided to the external MPU.
DC/DC Operation: The internal circuit continuously
senses the CRD_VCC voltage and, in the case of either over
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J1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
CONTROL AND I/O
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Figure 31. NCN6001 Engineering Test Board Schematic Diagram
1
TP15
GND
1
2
4.7 k
GND
GND
GND
P1
EX_CLK
R5
J9
GROUND
Identify NCN6001
Demo Board
1k
VCC
CLK_SEL
3 2 1
GND
VCC
D1
INT
TP2
VCC
VCC
LoutL
D4
10
9
1
2
3
7
8
5
4
2N2222
GND
Q1
22 H
L1
12
47 k
R7
LoutH
GND
R8
47 R See
Note
GND
22 pF
C3
C8
4.7 F
C8
TP13
C7
4.7 F
GND
5
GND
J4
SMARTCARD_D
11
Swa
10 Swb
7
I/O
2
RST
3
CLK
4
C4
8
1 C8
VCC
GND
GND
CLK
C4 VCC
TP11 TP12 TP14
See
Note
RST
TP10
CRD_IO
TP9
CRD_DET
TP8
CRD_DET 18
VCC
20
CRD_IO
I/O
19
INT
CRD_RST 17
CLK_IN CRD_CLK
MISO
CRD_VCC 13
CS
CLK_SP
15
MOSI
C4/S0 14
C8/S1 16
PWR_GND 11
6
GND
EN_RPU
U2
10 F
GND
C2
2.2 K CRD_VCC
R4
47 k
R6
VCC
MOSI
TP7
CLK_SP
TP6
MISO
TP5
CS
TP4
CLK_IN I/O
TP1
TP3
NOTE:
R9
J5
I/O
INT
2.2 k
R1
C1
CS
CLK_SP1
MOSI
MISO
10 F
VCC
NCN6001
TEST BOARD SCHEMATIC DIAGRAM
ISO7816
Capacitor C2 and Resistor R8 are adjusted at final
checkout. Depending upon the PCB layout, these
two components may or may not be necessary.
NCN6001
Component Side (Top)
Copper Side (Bottom)
Top side
Figure 32. NCN6001 Demo Board Printed Circuit Board Layout
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NCN6001
Table 11. DEMO BOARD BILL OF MATERIAL
Desig.
Part Type
Footprint
Description
Supplier
Part Number
C1
10 F
1206
Capacitor
MURATA
GRM40−X5R−106K6.3
C2
10 F
1206
Capacitor
MURATA
GRM40−X5R−106K6.3
C3
22 pF
805
Capacitor
MURATA
C7
4.7 F
1206
Capacitor
MURATA
GRM40−034X5R−475K6.3
C8
4.7 F
1206
Capacitor
MURATA
GRM40−034X5R−475K6.3
D1
VCC
SIP2
LED Diode
Radio Spares
180−8467
D4
CRD_VCC
SIP2
LED Diode
Radio Spares
180−8495
J1
CONTROL & I/O
IDC50
Fujitsu
FCN−704Q050−AU/M
J4
SMARTCARD
SMARTCARD_ISO
Smart Card Connector
FCI
7434−L01−35S01
J5
CLK_SEL
SIP3
Connector
J9
GROUND
GND_TEST
Connector
L1
22 H
1008
Inductor
CoilCraft
1008PS−223−M
P1
EX_CLK
SMB
SMB Connector
Radio Spares
112−2993
Q1
2N2222
TO−18
NPN
ON Semiconductor
R1
2.2 k
805
Radio Spares
R4
2.2 k
805
Radio Spares
R5
4.7 k
805
Radio Spares
R6
47 k
805
Radio Spares
R7
47 k
805
Radio Spares
R8
47 R
805
Radio Spares
R9
1.0 k
805
Radio Spares
TP1
CLK_IN
TEST_POINT
TEST_POINT
Radio Spares
203−4910
TP10
RST
TEST_POINT
TEST_POINT
Radio Spares
203−4910
TP11
CLK
TEST_POINT
TEST_POINT
Radio Spares
203−4910
TP12
C4
TEST_POINT
TEST_POINT
Radio Spares
203−4910
TP13
C8
TEST_POINT
TEST_POINT
Radio Spares
203−4910
TP14
VCC
TEST_POINT
TEST_POINT
Radio Spares
203−4910
TP15
GND
TEST_POINT
TEST_POINT
Radio Spares
203−4910
TP2
INT
TEST_POINT
TEST_POINT
Radio Spares
203−4910
TP3
I/O
TEST_POINT
TEST_POINT
Radio Spares
203−4910
TP4
CS
TEST_POINT
TEST_POINT
Radio Spares
203−4910
TP5
MISO
TEST_POINT
TEST_POINT
Radio Spares
203−4910
TP6
CLK_SPI
TEST_POINT
TEST_POINT
Radio Spares
203−4910
TP7
MOSI
TEST_POINT
TEST_POINT
Radio Spares
203−4910
TP8
DET
TEST_POINT
TEST_POINT
Radio Spares
203−4910
TP9
CRD_IO
TEST_POINT
TEST_POINT
Radio Spares
203−4910
U1
NCN6001
ON Semiconductor
13. All resistors are ±5%, ¼ W , unless otherwise noted. All capacitors are ceramic, ±10%, 6.3 V, unless otherwise noted.
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NCN6001
Lout_L
Lout_H
L1
22 H
NCN6001
9
1
2
3
4
5
7
8
6
10
10
J5
ISO7816
ASYNCHRONOUS
Swa
17
18
Swb
7
I/O
2
RST
3
CLK
5
GND
1
VCC
4
C4 8
C8
SMARTCARD
GND
C6
10 F
GND
18
20
19
17
13
15
14
16
11
12
U4
CRD_DET
VCC
I/O
CRD_IO
INT
CRD_RST
CLK_IN
CRD_CLK
MOSI
CRD_VCC
C4/S0
CLK_SPI
MISO
C8/S1
CS
GND
PWR_GND EN_RPU
Lout_H
Lout_L
9
1
2
3
4
5
7
8
6
9
1
2
3
4
5
7
8
6
VCC
10
10
L5
22 H
NCN6001
ISO7816
ASYNCHRONOUS
CLK
GND
SMARTCARD
C2
10 F
GND
ADDRESS = $00
17
Swa
18
GND 18
Swb
20
7
I/O
2
19
RST
17
3
CLK
13
5
GND
15
1
VCC
V
14
4 CC
8 C4
16
C8
11
SMARTCARD
C2
12
Lout_H
10 F
L2
22 H
NCN6001
9
1
2
3
4
5
7
8
6
Swb
I/O
RST
1
V
4 CC
8 C4
C8
U2
CRD_DET
VCC
I/O
CRD_IO
INT
CRD_RST
CLK_IN
CRD_CLK
MOSI
CRD_VCC
C4/S0
CLK_SPI
MISO
C8/S1
CS
GND
EN_RPU PWR_GND
Lout_L
Swa
ISO7816
GND
12
18
7
2
3
5
GND
ASYNCHRONOUS
10
GND
ADDRESS = $01
17
Swa
18
GND 18
Swb
20
7
I/O
2
19
RST
17
3
CLK
13
5
GND
15
1
V
14
4 CC
VCC
8 C4
16
C8
11
C2
SMARTCARD
12
10 F
Lout_L
Lout_H
GND
ADDRESS = $02
L3
22 H
NCN6001
17
Swa
U5
18
GND 18
Swb
CRD_DET
VCC
20
7
I/O
CRD_IO
I/O
2
19
RST
INT
CRD_RST
17
3
CLK_IN
CRD_CLK
CLK
13
5
MOSI
GND
CRD_VCC
15
1
C4/S0
CLK_SPI
V
14
4 CC
MISO
C8/S1
VCC
C4
8
16
C8
CS
GND
11
EN_RPU PWR_GND
C2 SMARTCARD
12
10 F
Lout_L
Lout_H
GND
L4
22 H
ADDRESS = $03
NCN6001
U3
CRD_DET
VCC
I/O
CRD_IO
INT
CRD_RST
CLK_IN
CRD_CLK
MOSI
CRD_VCC
C4/S0
CLK_SPI
MISO
C8/S1
CS
GND
EN_RPU PWR_GND
ISO7816
STROBE_ASYNC
STROBE_SYNC
17
18
20
19
17
13
15
14
16
11
ASYNCHRONOUS
GND
U1
CRD_DET
VCC
I/O
CRD_IO
INT
CRD_RST
CLK_IN
CRD_CLK
MOSI
CRD_VCC
C4/S0
CLK_SPI
MISO
C8/S1
CS
GND
EN_RPU PWR_GND
ISO7816
9
1
2
3
4
5
7
8
6
10 F
MICROCONTROLLER
C1
MULTIPLE SMART CARD READER
ASYNCHRONOUS
VCC
Figure 33. Typical Multiple Parallel Interfaces
The five interfaces share a common microcontroller bus,
a bank of four NCN6001 supporting asynchronous card with
a dedicated CS line, the fifth one being used by to the
synchronous or asynchronous transactions with a unique CS
line. On the other hand, the only activated I/O pullup resistor
shall be one of the Asynchronous bank.
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31
NCN6001
ABBREVIATIONS
Lout_L and Lout_H
Cout
DC/DC External Inductor
Output Capacitor
Class A
5V Smart Card
Class B
3V Smart Card
CRD_C4
Interface IC Card Digital Control
CRD_C8
Interface IC Card Digital Control
CRD_CLK
Interface IC Card Clock Input
CRD_DET
Card Insertion/Extraction Detection
CRD_IO
Interface IC Card Data Link
CRD_RST
Interface IC Card RESET Input
CRD_VCC
Interface IC Card Power Supply Line
CRD_VCC
Card Power Supply Input
Cs
Parasitic Stray Capacitance
CS
Chip Select
EMV
Europay Master Card Visa
FST_SLP
CRD_CLK Fast Slope (tr and tf)
GIE−CB
Groupement Inter Economique − Carte Bancaire
ICC
Current at Card VCC Pin
INT
Interrupt
ISO
International Standards Organization
C
Microcontroller
MISO
Master In Slave Out: Data from the Interface
MOSI
Master Out Slave In: Data from the External Microcontroller
NC
Normally Close
NO
Normally Open
POR
Power On Reset
RFU
Reserved Future Use
SPI
Serial Port Interface
T0
Smart Card Data Transfer Procedure by Bytes
T1
Smart Card Data Transfer Procedure by Strings
SLO_SLP
CRD_CLK Slow Slope (tr and tf)
VCC
MPU Power Supply Voltage
ORDERING INFORMATION
Device
NCN6001DTBR2G
Package
Shipping†
TSSOP−20
(Pb−Free)
2,500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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32
NCN6001
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
−U−
L
PIN 1
IDENT
SECTION N−N
0.25 (0.010)
N
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
K
K1
10
M
0.15 (0.006) T U
S
A
−V−
N
F
DETAIL E
−W−
C
G
D
H
0.100 (0.004)
−T− SEATING
DETAIL E
SOLDERING FOOTPRINT
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
ON Semiconductor and the
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For additional information, please contact your local
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NCN6001/D