a +2.5 V to +5.5 V, 120 A, 2-Wire Interface, Voltage Output 8-/10-/12-Bit DACs AD5301/AD5311/AD5321* GENERAL DESCRIPTION FEATURES AD5301: Buffered Voltage Output 8-Bit DAC AD5311: Buffered Voltage Output 10-Bit DAC AD5321: Buffered Voltage Output 12-Bit DAC 6-Lead SOT-23 and 8-Lead SOIC Packages Micropower Operation: 120 A @ 3 V 2-Wire (I 2C ® Compatible) Serial Interface Data Readback Capability +2.5 V to +5.5 V Power Supply Guaranteed Monotonic By Design Over All Codes Power-Down to 50 nA @ 3 V Reference Derived from Power Supply Power-On-Reset to Zero Volts On-Chip Rail-to-Rail Output Buffer Amplifier Three Power-Down Functions The AD5301/AD5311/AD5321 are single 8-, 10- and 12-bit buffered voltage-output DACs that operate from a single +2.5 V to +5.5 V supply consuming 120 µA at 3 V. The on-chip output amplifier allows rail-to-rail output swing with a slew rate of 0.7 V/µs. It uses a 2-wire (I2C compatible) serial interface that operates at clock rates up to 400 kHz. Multiple devices can share the same bus. The reference for the DAC is derived from the power supply inputs and thus gives the widest dynamic output range. These parts incorporate a power-on-reset circuit, which ensures that the DAC output powers-up to zero volts and remains there until a valid write takes place. The parts contain a power-down feature which reduces the current consumption of the device to 50 nA at 3 V and provides software-selectable output loads while in power-down mode. APPLICATIONS Portable Battery Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators The low power consumption in normal operation make these DACs ideally suited to portable battery-operated equipment. The power consumption is 0.75 mW at 5 V, 0.36 mW at 3 V reducing to 1 µW in all power-down modes. FUNCTIONAL BLOCK DIAGRAM VDD AD5301/AD5311/AD5321 REF SCL SDA INTERFACE LOGIC DAC REGISTER 8-/10-/12-BIT DAC VOUT BUFFER A0 POWER-DOWN LOGIC A1* RESISTOR NETWORK POWER-ON RESET GND PD* *AVAILABLE ON 8-LEAD VERSION ONLY I2 C is a registered trademark of Philips Corporation. *Protected by U.S. Patent No. 5684481, other patent pending. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD5301/AD5311/AD5321–SPECIFICATIONS (V DD = +2.5 V to +5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; All specifications T MIN to TMAX unless otherwise noted.) Parameter1 Min B Version2 Typ Max Units Conditions/Comments 8 ± 0.15 ± 0.02 ±1 ± 0.25 Bits LSB LSB Guaranteed Monotonic by Design Over All Codes 10 ± 0.5 ± 0.05 ±4 ± 0.5 Bits LSB LSB Guaranteed Monotonic by Design Over All Codes 3, 4 DC PERFORMANCE AD5301 Resolution Relative Accuracy Differential Nonlinearity AD5311 Resolution Relative Accuracy Differential Nonlinearity AD5321 Resolution Relative Accuracy Differential Nonlinearity Zero Code Error Full-Scale Error Gain Error Zero Code Error Drift5 Gain Error Drift5 12 ±2 ± 0.3 +5 ± 0.15 ± 0.15 –20 –5 OUTPUT CHARACTERISTICS5 Minimum Output Voltage Maximum Output Voltage DC Output Impedance Short Circuit Current 0.001 VDD – 0.001 1 50 20 2.5 6 Power-Up Time LOGIC INPUTS (A0, A1, PD)5 Input Current VIL, Input Low Voltage VIH, Input High Voltage Bits LSB LSB mV % of FSR % of FSR µV/°C ppm of FSR/°C ± 16 ± 0.8 +20 ± 1.25 ±1 V min V max Ω mA mA µs µs ±1 0.8 0.6 0.5 µA V V V V V V pF 2.4 2.1 2.0 Pin Capacitance 3 LOGIC INPUTS (SCL, SDA) VIH, Input High Voltage VIL, Input Low Voltage IIN, Input Leakage Current VHYST, Input Hysteresis CIN, Input Capacitance Glitch Rejection6 Guaranteed Monotonic by Design Over All Codes All Zeros Loaded to DAC, See Figure 9 All Ones Loaded to DAC, See Figure 9 This is a measure of the minimum and maximum drive capability of the output amplifier. VDD = +5 V VDD = +3 V Coming Out of Power-Down Mode. VDD = +5␣ V Coming Out of Power-Down Mode. VDD = +3␣ V VDD = +5 V ± VDD = +3 V ± VDD = +2.5 V VDD = +5 V ± VDD = +3 V ± VDD = +2.5 V 10% 10% 10% 10% 5 0.7 VDD –0.3 0.05 VDD 6 VDD + 0.3 V 0.3 VDD V ±1 µA V pF 50 ns VIN = 0 V to VDD Pulsewidth of Spike Suppressed 5 LOGIC OUTPUT (SDA) VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = +4.5 V to +5.5 V VDD = +2.5 V to +3.6 V IDD (Power-Down Mode) VDD = +4.5 V to +5.5 V VDD = +2.5 V to +3.6 V 0.4 0.6 ±1 V V µA pF ISINK = 3 mA ISINK = 6 mA 5.5 V 150 120 250 220 µA µA IDD Specification Is Valid for All DAC Codes DAC Active and Excluding Load Current VIH = V DD and VIL = GND VIH = V DD and VIL = GND 0.2 0.05 1 1 µA µA VIH = V DD and VIL = GND VIH = V DD and VIL = GND 6 2.5 NOTES 1 See Terminology. 2 Temperature ranges are as follows: B Version: –40°C to +105°C. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5301 (Code 7 to 250); AD5311 (Code 28 to 1000); AD5321 (Code 112 to 4000). 5 Guaranteed by Design and Characterization, not production tested. 6 Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns. Specifications subject to change without notice . –2– REV. 0 AD5301/AD5311/AD5321 (VDD = +2.5 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; All specifications T MIN to TMAX unless AC CHARACTERISTICS1 otherwise noted.) Parameter2 Min B Version3 Typ Max Output Voltage Settling Time AD5301 AD5311 AD5321 Slew Rate Major-Code Change Glitch Impulse Digital Feedthrough 6 7 8 0.7 12 0.3 8 9 10 Units µs µs µs V/µs nV-s nV-s Conditions/Comments VDD = +5 V 1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex) 1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex) 1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex) 1 LSB Change Around Major Carry NOTES 1 See Terminology 2 Guaranteed by design and characterization, not production tested. 3 Temperature ranges are as follows: B Version: –40°C to +105°C. Specifications subject to change without notice. TIMING CHARACTERISTICS1 (V DD Parameter2 fSCL t1 t2 t3 t4 t5 t6 3 t7 t8 t9 t10 t11 Cb = +2.5 V to +5.5 V. All specifications TMIN to TMAX unless otherwise noted.) Limit at TMIN, T MAX (B Version) Units Conditions/Comments 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 250 300 20 + 0.1Cb4 400 kHz max µs min µs min µs min µs min ns min µs max µs min µs min µs min µs min ns max ns min ns max ns max ns min pF max SCL Clock Frequency SCL Cycle Time tHIGH, SCL High Time tLOW, SCL Low Time tHD,STA, Start/Repeated Start Condition Hold Time tSU,DAT, Data Setup Time tHD,DAT, Data Hold Time tSU,STA, Setup Time for Repeated Start tSU,STO, Stop Condition Setup Time tBUF, Bus Free Time Between a STOP Condition and a START Condition tR, Rise Time of Both SCL and SDA when Receiving May be CMOS Driven tF, Fall Time of SDA when Receiving tF, Fall Time of Both SCL and SDA when Transmitting Capacitive Load for Each Bus Line NOTES 1 See Figure 1. 2 Guaranteed by design and characterization, not production tested. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V IH MIN of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 4 Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 V DD. Specifications subject to change without notice. REV. 0 –3– AD5301/AD5311/AD5321 SDA t9 t3 t11 t10 t4 SCL t4 t6 t2 t5 START CONDITION t7 t8 t1 STOP CONDITION REPEATED START CONDITION Figure 1. 2-Wire Serial Interface Timing Diagram ABSOLUTE MAXIMUM RATINGS 1, 2 (TA = +25°C unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V SCL, SDA to GND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V PD, A1, A0 to GND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V VOUT to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +105°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . . +150°C SOT-23 Package Power Dissipation . . . . . . . . . . . . . . . . . . . (TJ max – TA)/θJA θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 229.6°C/W µSOIC Package Power Dissipation . . . . . . . . . . . . . . . . . . . (TJ max – TA)/θJA θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. ORDERING GUIDE Model Temperature Range Package Description Package Option Branding Information AD5301BRT AD5301BRM AD5311BRT AD5311BRM AD5321BRT AD5321BRM –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C SOT-23 µSOIC SOT-23 µSOIC SOT-23 µSOIC RT-6 RM-8 RT-6 RM-8 RT-6 RM-8 D8B D8B D9B D9B DAB DAB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5301/AD5311/AD5321 features proprietary ESD protection circuitry, perma nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 AD5301/AD5311/AD5321 PIN FUNCTION DESCRIPTION SOIC Pin No. SOT-23 Pin No. Mnemonic Function 1 6 VDD 2 3 4 5 5 N/A 4 N/A A0 A1 VOUT PD 6 3 SCL 7 2 SDA 8 1 GND Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and the supply should be decoupled with a 10 µF in parallel with a 0.1 µF capacitor to GND. Address Input. Sets the Least Significant Bit of the 7-bit slave address. Address Input. Sets the 2nd Least Significant Bit of the 7-bit slave address. Buffered analog output voltage from the DAC. The output amplifier has rail-to-rail operation. Active low control input that acts as a hardware power-down option. This pin overrides any software power-down option. The DAC output goes three-state and the current consumption of the part drops to 50 nA @ 3 V (200 nA @ 5 V). Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit input shift register. Clock rates of up to 400 kbit/s can be accommodated in the I2C compatible interface. SCL may be CMOS/TTL driven. Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit input shift register during the write cycle and used to read back one or two bytes of data (one byte for the AD5301, two bytes for the AD5311/AD5321) during the read cycle. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. If not used in readback mode, SDA may be CMOS/TTL driven. Ground reference point for all circuitry on the part. PIN CONFIGURATIONS 6-Lead SOT-23 (RT-6) 8-Lead SOIC (RM-8) AD5301/AD5311/AD5321 AD5301/AD5311/AD5321 GND 1 6 VDD VDD 1 TOP VIEW 5 A0 (Not to Scale) SCL 3 4 VOUT REV. 0 8 GND SDA TOP VIEW A1 3 (Not to Scale) 6 SCL SDA 2 –5– A0 2 7 VOUT 4 5 PD AD5301/AD5311/AD5321 TERMINOLOGY RELATIVE ACCURACY GAIN ERROR This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. For the DAC, Relative Accuracy or Integral Nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer function. Typical INL vs. Code plots can be seen in Figures 2 to 4. ZERO CODE ERROR DRIFT This is a measure of the change in zero code error with a change in temperature. It is expressed in µV/°C. DIFFERENTIAL NONLINEARITY Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB maximum ensures monotonicity. These DACs are guaranteed monotonic by design over all codes. Typical DNL vs. Code plots can be seen in Figures 5 to 7. GAIN ERROR DRIFT This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. MAJOR CODE TRANSITION GLITCH ENERGY Major Code Transition Glitch Energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-secs and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). ZERO CODE ERROR Zero Code Error is a measure of the output error when zero code (00H) is loaded to the DAC register. Ideally, the output should be 0 V. The Zero Code Error of the AD5301/AD5311/ AD5321 is always positive because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and output amplifier. It is expressed in mV, see Figure 9. DIGITAL FEEDTHROUGH Digital Feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device but is measured when the DAC is not being written to. It is specified in nV-secs and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s and vice versa. FULL-SCALE ERROR Full-Scale Error is a measure of the output error when full scale is loaded to the DAC register. Ideally, the output should be VDD – 1 LSB. Full-scale error is expressed in percent of FSR (fullscale range). A plot can be seen in Figure 9. –6– REV. 0 Typical Performance Characteristics– AD5301/AD5311/AD5321 12 3 1.0 VDD = +5V VDD = +5V INL ERROR – LSBs 0 8 INL ERROR – LSBs 2 0.5 INL ERROR – LSBs TA = +258C VDD = +5V TA = +258C TA = +258C 1 0 –1 4 0 –4 –0.5 –8 –2 0 50 100 150 CODE 200 –3 250 Figure 2. AD5301 Typical INL Plot –12 200 400 600 CODE 800 1000 Figure 3. AD5311 Typical INL Plot 0.3 0 DNL ERROR – LSBs 0 –0.1 2000 CODE 3000 4000 1.0 TA = +258C VDD = +5V 0.4 0.1 1000 Figure 4. AD5321 Typical INL Plot 0.6 TA = +258C VDD = +5V 0.2 DNL ERROR – LSBs 0 TA = +258C VDD = +5V DNL ERROR – LSBs –1.0 0.2 0 –0.2 0.5 0 –0.5 –0.4 –0.2 –0.3 0 100 150 CODE 50 200 250 Figure 5. AD5301 Typical DNL Plot –0.6 0 200 1000 –1.0 0 1000 2000 CODE 3000 4000 Figure 7. AD5321 Typical DNL Plot VDD = +5V 8 0.75 6 ZERO SCALE 0.50 4 MAX INL 0.25 FREQUENCY MAX DNL 2 ERROR – ERROR – LSBs 800 10 VDD = +5V 0 –0.25 MIN INL MIN DNL 0 –2 VDD = +5V FULL SCALE –6 –0.75 VDD = +3V –4 –0.50 –8 0 40 80 TEMPERATURE – 8C Figure 8. AD5301 INL Error and DNL Error vs. Temperature REV. 0 600 CODE Figure 6. AD5311 Typical DNL Plot 1.00 –1.00 –40 400 120 –10 –40 –20 20 60 0 40 80 TEMPERATURE – 8C 100 Figure 9. Zero-Code Error and FullScale Error vs. Temperature –7– 80 90 100 110 120 130 140 150 160 170 180 190 200 IDD – mA Figure 10. IDD Histogram with VDD = +3 V and VDD = +5 V AD5301/AD5311/AD5321 5 200 160 4 150 140 3V SOURCE 2 120 100 VDD = 3V 80 –408C +1058C 100 +258C 60 3V SINK 1 VDD = 5V IDD – mA 3 IDD – mA VOUT – V 200 TA = +258C 180 5V SOURCE 50 40 5V SINK 20 0 0 3 6 9 0 15 12 ZERO-SCALE 0 2.7 FULL-SCALE 3.2 CODE I – mA Figure 11. Source and Sink Current Capability Figure 12. Supply Current vs. Code 1.0 5.2 Figure 13. Supply Current vs. Supply Voltage 300 VDD = +5V TA = +258C LOAD = 2kV AND 200pF TO GND TA = +258C 250 0.8 VDD = +5V 200 0.6 IDD – mA IDD – mA 3.7 4.2 4.7 VDD – Volts 0.4 –408C +258C INCREASING DECREASING 150 CH1 100 VOUT VDD = +3V 0.2 50 +1058C 0 2.7 3.2 3.7 4.2 VDD – Volts 4.7 0 5.2 Figure 14. Power-Down Current vs. Supply Voltage␣ 0 1.0 2.0 3.0 V – Volts 4.0 5.0 Figure 15. Supply Current vs. Logic Input Voltage for SDA and SCL Voltage Increasing and Decreasing CH1 1V, TIME BASE = 5ms/DIV Figure 16. Half-Scale Settling (1/4 to 3/4 Scale Code Charge) 2.50 VDD = +5V TA = +258C TA = +258C VOUT CH1 VOUT – Volts VDD 2.49 2.48 CH1 CH2 VOUT CH2 SCL 2.47 CH1 1V, CH2 1V, TIME BASE = 20ms/DIV Figure 17. Power-On Reset to 0 V CH1 1V, CH2 5V, TIME BASE = 1ms/DIV Figure 18. Exiting Power-Down to Midscale –8– Figure 19. Major-Code Transition REV. 0 AD5301/AD5311/AD5321 VDD 2.440 REF(+) DAC REGISTER V – Volts 2.445 RESISTOR STRING REF(–) 2.450 VOUT OUTPUT BUFFER AMPLIFIER Figure 21. DAC Channel Architecture RESISTOR STRING The resistor string section is shown in Figure 22. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic over all codes. 2.455 1ns/DIV Figure 20. Digital Feedthrough GENERAL DESCRIPTION The AD5301/AD5311/AD5321 are single resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10 and 12 bits respectively. Data is written via a 2-wire serial interface. They operate from single supplies of +2.5 V to +5.5 V and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/µs. The power-supply (VDD) acts as the reference to the DAC. The devices have three programmable powerdown modes, in which the DAC may be turned off completely with a high-impedance output, or the output may be pulled low by an on-chip resistor. See Power-Down section. R R R TO OUTPUT AMPLIFIER DIGITAL-TO-ANALOG SECTION R The architecture of the DAC channel consists of a resistorstring DAC followed by an output buffer amplifier. The voltage at the VDD pin provides the reference voltage for the DAC. Figure 21 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by: VOUT = R Figure 22. Resistor String VDD × D 2N OUTPUT AMPLIFIER where: N = DAC resolution D = decimal equivalent of the binary code which is loaded to the DAC register: 0–255 for AD5301 (8 Bits) 0–1023 for AD5311 (10 Bits) 0–4095 for AD5321 (12 Bits) The output buffer amplifier is capable of generating output voltages to within 1 mV from either rail, which gives an output range of 0.001 V to VDD – 0.001 V. It is capable of driving a load of 2 kΩ to GND and VDD, in parallel with 500 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 11. The slew rate is 0.7 V/µs with a half-scale settling time to ± 0.5 LSB (at 8 bits) of 6 µs with the output unloaded. POWER-ON RESET The AD5301/AD5311/AD5321 are provided with a power-on reset function, ensuring that they power up in a defined state. The DAC register is filled with zeros and remains so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC output while the device is powering up. REV. 0 –9– AD5301/AD5311/AD5321 SERIAL INTERFACE 2-WIRE SERIAL BUS The AD5301/AD5311/AD5321 are controlled via an I2Ccompatible serial bus. The DACs are connected to this bus as slave devices (no clock is generated by the AD5301/AD5311/ AD5321 DACs). The AD5301/AD5311/AD5321 has a 7-bit slave address. In the case of the 6-pin device, the 6 MSBs are 000110 and the LSB is determined by the state of the A0 pin. In the case of the 8-pin device, the 5 MSBs are 00011 and the 2 LSBs are determined by the state of the A0 and A1 pins. A1 and A0 allow the user to use up to four of these DACs on one bus. The 2-wire serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, which is when a high to low transition on the SDA line occurs while SCL is high. The following byte is the address byte which consists of the 7-bit slave address followed by an R/W bit (this bit determines whether data will be read from or written to the slave device). The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the Acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master will read from the slave device. However, if the R/W bit is low, the master will write to the slave device. 2. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an Acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. 3. When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In Write mode, the master will pull the SDA line high during the 10th clock pulse to establish a STOP condition. In Read mode, the master will issue a No Acknowledge for the 9th clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the 10th clock pulse and then high during the 10th clock pulse to establish a STOP condition. In the case of the AD5301/AD5311/AD5321, a write operation contains two bytes whereas a read operation may contain one or two bytes. See Figures 24 to 29 below for a graphical explanation of the serial interface. A repeated write function gives the user flexibility to update the DAC output a number of times after addressing the part only once. During the write cycle, each multiple of two data bytes will update the DAC output. For example, after the DAC has acknowledged its address byte, and receives two data bytes, the DAC output will update after the two data bytes, if another two data bytes are written to the DAC while it is still the addressed slave device, these data bytes will also cause an output update. Repeat read of the DAC is also allowed. INPUT SHIFT REGISTER The input shift register is 16 bits wide. Figure 23 illustrates the contents of the input shift register for each part. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCL. The timing diagram for this operation is shown in Figure 1. The 16-bit word consists of four control bits followed by 8, 10 or 12 bits of data, depending on the device type. MSB (Bit 15) is loaded first. The first two bits are “don’t cares.” The next two are control bits that control the mode of operation of the device (normal mode or any one of three power-down modes). See Power Down Modes section for a complete description. The remaining bits are left-justified DAC data bits, starting with the MSB and ending with the LSB. DB15 (MSB) X X DB0 (LSB) PD1 PD0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X DATA BITS Figure 23a. AD5301 Input Shift Register Contents DB15 (MSB) X X DB0 (LSB) PD1 PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X DATA BITS Figure 23b. AD5311 Input Shift Register Contents DB15 (MSB) X X DB0 (LSB) PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS Figure 23c. AD5321 Input Shift Register Contents –10– REV. 0 AD5301/AD5311/AD5321 low. This address byte is followed by the 16-bit word in the form of two control bytes. The write operations for the three DACs are shown in the figures below. WRITE OPERATION When writing to the AD5301/AD5311/AD5321 DACs, the user must begin with an address byte, after which the DAC will acknowledge that it is prepared to receive data by pulling SDA SCL SDA 0 0 0 START COND BY MASTER 1 1 A1* A0 R/W X ACK BY AD5301 ADDRESS BYTE X PD1 PD0 D7 D6 D5 D4 ACK BY AD5301 MOST SIGNIFICANT CONTROL BYTE SCL SDA D3 D2 D1 D0 X X X X ACK BY AD5301 LEAST SIGNIFICANT CONTROL BYTE *THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION. STOP COND BY MASTER Figure 24. AD5301 Write Sequence SCL SDA 0 0 START COND BY MASTER 0 1 1 A1* A0 R/W X ACK BY AD5311 ADDRESS BYTE X PD1 PD0 D9 D8 D7 D6 ACK BY AD5311 MOST SIGNIFICANT CONTROL BYTE SCL SDA D5 D4 D3 D2 D1 D0 X X ACK BY AD5311 LEAST SIGNIFICANT CONTROL BYTE *THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION. STOP COND BY MASTER Figure 25. AD5311 Write Sequence SCL SDA 0 0 START COND BY MASTER 0 1 1 A1* A0 R/W X ACK BY AD5321 ADDRESS BYTE X PD1 D7 D6 D5 D4 D3 D2 D1 LEAST SIGNIFICANT CONTROL BYTE D0 ACK BY AD5321 *THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION. STOP COND BY MASTER Figure 26. AD5321 Write Sequence REV. 0 –11– D11 D10 D9 MOST SIGNIFICANT CONTROL BYTE SCL SDA PD0 D8 ACK BY AD5321 AD5301/AD5311/AD5321 of the eight data bits in the DAC register. However, in the case of the AD5311 and AD5321, the readback consists of two bytes that contain both the data and the power-down mode bits. The read operations for the three DACs are shown in the figures below. READ OPERATION When reading data back from the AD5301/AD5311/AD5321 DACs, the user must begin with an address byte after which the DAC will acknowledge that it is prepared to transmit data by pulling SDA low. There are two different read operations. In the case of the AD5301, the readback is a single byte that consists SCL SDA 0 0 0 START COND BY MASTER 1 1 A1* A0 R/W D7 D6 D5 ACK BY AD5301 ADDRESS BYTE D4 D3 D2 D1 D0 NO ACK BY MASTER DATA BYTE STOP COND BY MASTER *THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION. Figure 27. AD5301 Readback Sequence SCL SDA 0 0 0 START COND BY MASTER 1 1 A1* A0 R/W X ACK BY AD5311 ADDRESS BYTE X PD1 PD0 D9 D8 D7 D6 ACK BY MASTER MOST SIGNIFICANT BYTE SCL SDA D5 D4 D3 D2 D1 D0 X X NO ACK BY MASTER LEAST SIGNIFICANT BYTE *THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION. STOP COND BY MASTER Figure 28. AD5311 Readback Sequence SCL SDA 0 0 START COND BY MASTER 0 1 1 A1* A0 R/W X ACK BY AD5321 ADDRESS BYTE X PD1 PD0 D11 MOST SIGNIFICANT BYTE D10 D9 D8 ACK BY MASTER SCL SDA D7 D6 D5 D4 D3 D2 LEAST SIGNIFICANT BYTE D1 D0 NO ACK BY MASTER *THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION. STOP COND BY MASTER Figure 29. AD5321 Readback Sequence –12– REV. 0 AD5301/AD5311/AD5321 POWER-DOWN MODES APPLICATIONS The AD5301/AD5311/AD5321 have very low power consumption, dissipating typically 0.36 mW with a 3 V supply and 0.75 mW with a 5 V supply. Power consumption can be further reduced when the DAC is not in use by putting it into one of three power-down modes, which are selected by Bits 13 and 12 (PD1 and PD0) of the control word. Table I shows how the state of the bits corresponds to the mode of operation of the DAC. USING REF19x AS A POWER SUPPLY Because the supply current required by the AD5301/AD5311/ AD5321 is extremely low, the user has an alternative option to use a REF19x voltage reference (REF195 for +5 V or REF193 for +3 V) to supply the required voltage to the part, see Figure 31. +15V Table I. PD1/PD0 Operating Modes REF195 PD1 PD0 Operating Mode 0 0 1 1 0 1 0 1 Normal Operation Power-Down (1 kΩ Load to GND) Power-Down (100 kΩ Load to GND) Power-Down (Three-State Output) +5V 150mA TYP VDD 2-WIRE SERIAL INTERFACE AD5301/ AD5311/ AD5321 SDA SCL VOUT = 0V TO 5V Figure 31. REF195 as Power Supply to AD5301/AD5311/ AD5321 The software power-down modes programmed by PD0 and PD1 may be overridden by the PD pin on the 8-pin version. Taking this pin low puts the DAC into three-state power-down mode. If PD is not used it should be tied high. When both bits are set to 0, the DAC works normally with its normal power consumption of 150 µA at 5 V, while for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the DAC amplifier. There are three different options. The output is connected internally to GND through a 1 kΩ resistor, a 100 kΩ resistor or it is left open-circuited (Three-State). Resistor tolerance = ± 20%. The output stage is illustrated in Figure 30. This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than +5 V or +3 V (e.g., +15 V). The REF19x will output a steady supply voltage for the AD5301/AD5311/AD5321. If the low dropout REF195 is used, the current it needs to supply to the AD5301/ AD5311/AD5321 is 150 µA. This is with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. The total current required (with a 2 kΩ load on the DAC output and full scale loaded to the DAC) is: 150 µA + (5 V/2 k Ω) = 2.65 mA The load regulation of the REF195 is typically 2 ppm/mA which results in an error of 5.3 ppm (26.5 µV) for the 2.65 mA current drawn from it. This corresponds to a 0.00136 LSB error. BIPOLAR OPERATION USING THE AD5301/AD5311/ AD5321 RESISTORSTRING DAC AMPLIFIER POWER-DOWN CIRCUITRY The AD5301/AD5311/AD5321 has been designed for singlesupply operation but a bipolar output range is also possible using the circuit in Figure 32. The circuit below will give an output voltage range of ± 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. VOUT RESISTOR NETWORK R2 = 10kV Figure 30. Output Stage During Power-Down +5V +5V The bias generator, the output amplifier, the resistor string and all other associated linear circuitry are all shut down when the power-down mode is activated. However, the contents of the DAC register are unchanged when in power-Down. The time to exit power-down is typically 2.5 µs for VDD = 5 V and 6 µs when VDD = 3 V. See Figure 18 for a plot. R1 = 10kV AD820/ OP295 VDD 10mF 0.1mF 65V VOUT AD5301/ AD5311/ AD5321 –5V 2-WIRE SERIAL INTERFACE Figure 32. Bipolar Operation with the AD5301/AD5311/ AD5321 REV. 0 –13– AD5301/AD5311/AD5321 The output voltage for any input code can be calculated as follows: Further changes, in the SDA line driver, may be made to make the system more CMOS-compatible and save more power. As the SDA line is bidirectional, it cannot be made fully CMOScompatible. A switched pull-up resistor can be combined with a CMOS device with an open-circuit (three-state) input such that the CMOS SDA driver is enabled during write cycles and I2C mode is enabled during shared cycles, i.e., readback, acknowledge bit cycles, start and stop conditions. VOUT = [(V DD × (D/2N) × (R1 + R2)/R1) – VDD × (R2/R1)] where D is the decimal equivalent of the code loaded to the DAC. N is the DAC resolution. With VDD = 5 V, R1 = R2 = 10 kΩ: VOUT = (10 × D/2N) – 5 V POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The AD5301/AD5311/AD5321 should be decoupled to GND with a 10 µF in parallel with 0.1 µF capacitor, located as close to the package as possible. The 10 µF capacitor should be the tantalum bead type, while a ceramic 0.1 µF capacitor will provide sufficient low impedance path to ground at high frequencies. The power supply lines of the AD5301/AD5311/AD5321 should use as large a trace as possible to provide low impedance paths. A ground line routed between the SDA and SCL lines will help reduce crosstalk between them (not required on a multilayer board as there will be a ground plane layer, but separating the lines will help). MULTIPLE DEVICES ON ONE BUS Figure 33 shows four AD5301 devices on the same serial bus. Each has a different slave address since the state of their A0 and A1 pins is different. This allows each DAC to be written to or read from independently. The master device output bus line drivers are open-drain pull downs in a fully I2C-compatible interface. CMOS DRIVEN SCL AND SDA LINES For single or multisupply systems where the minimum SCL swing requirements allow it, a CMOS SCL driver may be used, the SCL pull-up resistor can be removed, making the SCL bus line fully CMOS compatible. This will reduce power consumption in both the SCL driver and receiver devices. The SDA line remains open-drain, I2C-compatible. +5V RP RP SDA MASTER SCL VDD SDA A1 SCL VOUT A0 VDD SDA A1 SCL VOUT A0 AD5301 VDD SDA A1 SCL VOUT A0 AD5301 SDA A1 SCL VOUT A0 AD5301 AD5301 Figure 33. Multiple AD5301 Devices on One Bus –14– REV. 0 AD5301/AD5311/AD5321 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 6-Lead SOT-23 (RT-6) 0.071 (1.80) 0.059 (1.50) 6 5 4 1 2 3 C3531–8–7/99 0.122 (3.10) 0.106 (2.70) 0.118 (3.00) 0.098 (2.50) PIN 1 0.037 (0.95) BSC 0.075 (1.90) BSC 0.051 (1.30) 0.035 (0.90) 0.057 (1.45) 0.035 (0.90) 10° 0.020 (0.50) SEATING 0.009 (0.23) 0° 0.010 (0.25) PLANE 0.003 (0.08) 0.006 (0.15) 0.000 (0.00) 0.022 (0.55) 0.014 (0.35) 8-Lead SOIC (RM-8) 0.122 (3.10) 0.114 (2.90) 8 5 0.193 (4.90) BSC 0.122 (3.10) 0.114 (2.90) 1 4 PIN 1 0.0256 (0.65) BSC 0.006 (0.15) 0.002 (0.05) 0.028 (0.70) 0.016 (0.40) PRINTED IN U.S.A. 0.016 (0.40) 0.010 (0.25) 0.037 (0.95) 0.030 (0.75) 0.043 (1.10) MAX 68 08 SEATING 0.009 (0.23) PLANE 0.005 (0.13) REV. 0 –15–