H7N0602LD, H7N0602LS, H7N0602LM Silicon N Channel MOS FET High Speed Power Switching REJ03G1130-0600 Rev.6.00 Oct 16, 2006 Features • Low on-resistance RDS (on) = 4.1 mΩ typ. • 4.5 V gate drive devices • High Speed Switching Outline RENESAS Package code: PRSS0004AE-A (Package name: LDPAK (L) ) RENESAS Package code: PRSS0004AE-B (Package name: LDPAK (S)-(1) ) 4 4 1. Gate 2. Drain 3. Source 4. Drain 1 1 2 2 3 3 H7N0602LD H7N0602LS RENESAS Package code: PRSS0004AE-C (Package name: LDPAK (S)-(2) ) D 4 G 1 2 3 H7N0602LM Rev.6.00 Oct 16, 2006 page 1 of 8 S H7N0602LD, H7N0602LS, H7N0602LM Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Avalanche current Avalanche energy Channel dissipation Channel temperature Storage temperature Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. Value at Tc = 25°C 3. Value at Tch = 25°C, Rg ≥ 50 Ω Symbol VDSS VGSS ID ID (pulse) Note 1 IDR IAP Note 3 EAR Note 3 Pch Note 2 Tch Tstg Value 60 ±20 85 340 85 65 362 100 150 –55 to +150 Unit V V A A A A mJ W °C °C Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate to source breakdown voltage Zero gate voltage drain current Gate to source leak current Gate to source cutoff voltage Forward transfer admittance Static drain to source on state resistance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate to source charge Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time Body to drain diode forward voltage Body to drain diode reverse recovery time Note: 4. Pulse test Rev.6.00 Oct 16, 2006 page 2 of 8 Symbol V (BR) DSS V (BR) GSS IDSS IGSS VGS (off) |yfs| RDS (on) Ciss Coss Crss Qg Qgs Qgd td (on) tr td (off) tf VDF trr Min 60 ±20 — — 1.5 70 — — — — — — — — — — — — — — Typ — — — — — 120 4.1 6.2 9000 1000 470 140 30 30 55 290 140 50 0.95 45 Max — — 10 ±10 2.5 — 5.2 9.0 — — — — — — — — — — — — Unit V V µA µA V S mΩ mΩ pF pF pF nC nC nC ns ns ns ns V ns Test Conditions ID = 10 mA, VGS = 0 IG = ±100 µA, VDS = 0 VDS = 60 V, VGS = 0 VGS = ±16 V, VDS = 0 VDS = 10 V, ID = 1 mA Note 4 ID = 45 A, VDS = 10 V Note 4 ID = 45 A, VGS = 10 V Note 4 ID = 45 A, VGS = 4.5 V Note 4 VDS = 10 V VGS = 0 f = 1 MHz VDD = 25 V VGS = 10 V ID = 85 A VGS = 10 V ID = 45 A RL = 0.67 Ω Rg = 4.7 Ω IF = 85 A, VGS = 0 IF = 85 A, VGS = 0 diF/dt = 100 A/µs H7N0602LD, H7N0602LS, H7N0602LM Main Characteristics Maximum Safe Operation Area Power vs. Temperature Derating 1000 ID (A) 300 120 Drain Current Channel Dissipation Pch (W) 160 80 40 50 100 150 Case Temperature Operation in this area is 1 limited by RDS(on) 3 3 10 80 3.5 V 40 VDS (V) 160 80 40 Tc = 75°C 25°C –25°C VGS = 3 V 0 0 2 4 6 Drain to Source Voltage 8 0 10 VDS (V) Pulse Test 400 300 ID = 50 A 100 20 A 10 A 0 0 4 8 12 16 20 Gate to Source Voltage VGS (V) Rev.6.00 Oct 16, 2006 page 3 of 8 2 3 4 5 VGS (V) Static Drain to Source on State Resistance vs. Drain Current Drain to Source on State Resistance RDS(on) (mΩ) Drain to Source Saturation Voltage VDS(on) (mV) 500 1 Gate to Source Voltage Drain to Source Saturation Voltage vs. Gate to Source Voltage 200 100 120 4V 0 30 VDS = 10 V Pulse Test 4.5 V ID (A) 160 1 200 Pulse Test 6V 0.3 Typical Transfer Characteristics Drain Current ID (A) 10 V 120 Drain Current PW = 10 ms (1shot) Drain to Source Voltage Tc (°C) Typical Output Characteristics 200 µs DC Operation (Tc = 25°C) 10 0.1 0.1 200 µs 30 Ta = 25°C 0 0 s 100 0.3 0 10 10 1m 100 Pulse Test 30 10 VGS = 4.5 V 10 V 3 1 1 3 10 30 100 300 Drain Current ID (A) 1000 H7N0602LD, H7N0602LS, H7N0602LM Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) Drain to Source on State Resistance RDS(on) (mΩ) Static Drain to Source on State Resistance vs. Temperature 20 Pulse Test 16 50 A 12 ID = 10, 20 A 8 VGS = 4.5 V 4 10, 20, 50 A 10 V 0 –50 0 50 100 Case Temperature 150 200 1000 Tc = –25°C 300 100 25°C 30 75°C 10 3 VDS = 10 V Pulse Test 1 1 3 Tc (°C) Capacitance C (pF) Reverse Recovery Time trr (ns) 30 10 3000 1000 Coss 1 0.1 100 10 30 Reverse Drain Current Ciss 10000 300 3 100 VGS = 0 f = 1 MHz 0 10 12 40 8 20 VDD = 50 V 25 V 10 V 0 0 40 80 120 160 Gate Charge Qg (nc) Rev.6.00 Oct 16, 2006 page 4 of 8 30 40 50 4 0 200 1000 tf Switching Time t (ns) VDD = 50 V 25 V 10 V 60 V DS 16 VGS (V) 20 ID = 85 A VGS 20 Switching Characteristics Gate to Source Voltage Drain to Source Voltage VDS (V) Dynamic Input Characteristics 80 Crss Drain to Source Voltage VDS (V) IDR (A) 100 1000 30000 3 1 300 100000 100 0.3 100 Typical Capacitance vs. Drain to Source Voltage di / dt = 100 A / µs VGS = 0, Ta = 25°C 300 30 Drain Current ID (A) Body to Drain Diode Reverse Recovery Time 1000 10 tr 300 100 30 td(off) td(on) tr tf 10 3 VGS = 10 V, VDD = 30 V PW = 5 µs, duty ≤ 1 % Rg = 4.7 Ω 1 0.1 0.3 1 3 Drain Current 10 30 ID (A) 100 H7N0602LD, H7N0602LS, H7N0602LM Maximum Avalanche Energy vs. Channel Temperature Derating Repetitive Avalanche Energy EAR (mJ) Reverse Drain Current IDR (A) Reverse Drain Current vs. Source to Drain Voltage 200 10 V 160 120 80 5V VGS = 0, –5 V 40 Pulse Test 0 0 0.4 0.8 1.2 1.6 Source to Drain Voltage 2.0 500 IAP = 65 A VDD = 25 V duty < 0.1 % Rg ≥ 50 Ω 400 300 200 100 0 25 VSD (V) 50 75 100 125 150 Channel Temperature Tch (°C) Normalized Transient Thermal Impedance γ s (t) Normalized Transient Thermal Impedance vs. Pulse Width 3 Tc = 25°C 1 D=1 0.5 0.3 0.2 θch – c (t) = γ s (t) • θch – c 0.1 0.1 θch – c = 1.25°C/W, Tc = 25°C 0.05 PDM 0.02 0.03 D= 1 0.0 pulse t ho 1s 0.01 10 µ PW T PW T 100 µ 1m 10 m 100 m 10 1 Pulse Width PW (S) Avalanche Test Circuit VDS Monitor Avalanche Waveform L EAR = 1 • L • IAP2 • 2 VDSS VDSS – VDD IAP Monitor Rg V(BR)DSS IAP D.U.T VDD VDS ID Vin 15 V 50 Ω 0 Rev.6.00 Oct 16, 2006 page 5 of 8 VDD H7N0602LD, H7N0602LS, H7N0602LM Switching Time Test Circuit Waveform 90% Vout Monitor Vin Monitor D.U.T. Rg Vin Vout Vin 10 V VDS = 30 V 10% 10% 90% td(on) Rev.6.00 Oct 16, 2006 page 6 of 8 10% RL tr 90% td(off) tf H7N0602LD, H7N0602LS, H7N0602LM Package Dimensions RENESAS Code PRSS0004AE-A MASS[Typ.] 1.40g 4.44 ± 0.2 1.3 ± 0.15 1.3 ± 0.2 1.37 ± 0.2 0.76 ± 0.1 2.54 ± 0.5 2.54 ± 0.5 JEITA Package Code SC-83 RENESAS Code PRSS0004AE-B 2.49 ± 0.2 11.0 ± 0.5 0.2 0.86 +– 0.1 Package Name LDPAK(S)-(1) Unit: mm 10.2 ± 0.3 8.6 ± 0.3 11.3 ± 0.5 0.3 10.0 +– 0.5 Previous Code LDPAK(L) / LDPAK(L)V Previous Code LDPAK(S)-(1) / LDPAK(S)-(1)V 0.4 ± 0.1 MASS[Typ.] 1.30g (1.5) 10.0 Rev.6.00 Oct 16, 2006 page 7 of 8 2.54 ± 0.5 0.4 ± 0.1 0.3 3.0 +– 0.5 2.54 ± 0.5 0.2 0.86 +– 0.1 7.8 7.0 2.49 ± 0.2 0.2 0.1 +– 0.1 1.37 ± 0.2 1.3 ± 0.2 7.8 6.6 1.3 ± 0.15 + 0.3 – 0.5 8.6 ± 0.3 (1.5) (1.4) 4.44 ± 0.2 10.2 ± 0.3 Unit: mm 1.7 JEITA Package Code (1.4) Package Name LDPAK(L) 2.2 H7N0602LD, H7N0602LS, H7N0602LM JEITA Package Code RENESAS Code PRSS0004AE-C Previous Code LDPAK(S)-(2) / LDPAK(S)-(2)V MASS[Typ.] 1.35g 7.8 6.6 (2.3) 10.0 2.49 ± 0.2 0.2 0.1 +– 0.1 7.8 7.0 1.3 ± 0.15 + 0.3 – 0.5 8.6 ± 0.3 (1.5) (1.4) 4.44 ± 0.2 10.2 ± 0.3 Unit: mm 1.7 Package Name LDPAK(S)-(2) 2.2 1.37 ± 0.2 2.54 ± 0.5 0.2 0.86 +– 0.1 2.54 ± 0.5 0.4 ± 0.1 0.3 5.0 +– 0.5 1.3 ± 0.2 Ordering Information Part Name H7N0602LD-E H7N0602LSTL-E H7N0602LMTL-E Quantity 500 pcs 1000 pcs 1000 pcs Shipping Container Box (Conductive Sack) Taping Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.6.00 Oct 16, 2006 page 8 of 8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. 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