ATMEL AT17F16 In-system programmable (isp) via 2-wire bus Datasheet

Features
• Programmable 16,777,216 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
• 3.3V Output Capability
• 5V Tolerant I/O Pins
• Program Support using the Atmel ATDH2200E System or Industry Third-party
•
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•
•
•
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Programmers
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT40K and AT94K Devices, Altera® FLEX®, APEX™ Devices,
Lucent® ORCA® FPGAs, Xilinx® XC3000, XC4000, XC5200, Spartan®, Virtex® FPGAs,
Motorola® MPA1000 FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Low-power CMOS FLASH Process
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Footprint Packages), 20-lead PLCC and 44-lead TQFP Packages
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Low-power Standby Mode
Single Device Capable of Holding 4-bit Stream Files Allowing Simple System
Reconfiguration
Fast Serial Download Speeds up to 33 MHz
Endurance: 10,000 Write Cycles Typical
Green (Pb/Halide-free/RoHS Compliant) Package Options Available
FPGA
Configuration
Flash Memory
AT17F16
1. Description
The AT17F Series of In-System Programmable Configuration PROMs (Configurators)
provide an easy-to-use, cost-effective configuration memory for Field Programmable
Gate Arrays. The AT17F Series device is packaged in the 8-lead LAP, 20-lead PLCC
and 44-lead TQFP, see Table 1-1. The AT17F Series Configurator uses a simple
serial-access procedure to configure one or more FPGA devices.
The AT17F Series Configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1.
Package
AT17F Series Packages
AT17F16
8-lead LAP
Yes
20-lead PLCC
Yes
44-lead TQFP
Yes
3392F–CNFG–2/08
2. Pin Configuration
8-lead LAP
DATA
CLK
RESET/OE
CE
1
2
3
4
8
7
6
5
VCC
SER_EN
CEO (A2)
GND
18
17
16
15
14
9
10
11
12
13
4
5
6
7
8
NC
SER_EN
PAGE_EN
READY
CEO (A2)
NC
GND
PAGESEL0
NC
NC
CLK
NC
RESET/OE
PAGESEL1
CE
3
2
1
20
19
NC
DATA
NC
VCC
NC
20-lead PLCC
44
43
42
41
40
39
38
37
36
35
34
NC
CLK
NC
NC
DATA
PAGE_EN
VCC
NC
NC
SER_EN
NC
44 TQFP
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
NC
RESET/OE
PAGESEL0
CE
NC
NC
GND
PAGESEL1
NC
CEO(A2)
NC
12
13
14
15
16
17
18
19
20
21
22
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
2
AT17F16
3392F–CNFG–2/08
AT17F16
3. Block Diagram
READY
PAGE_EN
PAGESEL0
PAGESEL1
Power-on
Reset
Reset
Clock/Oscillator
Logic
CEO(A2)
Config. Page
Select
Serial Download Logic
2-wire Serial Programming
Flash
Memory
CLK
CE/WE/OE
Data
Address
DATA
CE
Control Logic
RESET/OE
SER_EN
4. Device Description
The control signals for the configuration memory device (CE, RESET/OE and CLK) interface
directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration device without requiring an external
intelligent controller.
The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the
address counter. When RESET/OE is driven Low, the configuration device resets its address
counter and tri-states its DATA pin. The CE pin also controls the output of the AT17F Series
Configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the
DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA
output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and
the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device tri-states
the DATA pin to avoid contention with other configurators. Upon power-up, the address counter
is automatically reset.
3
3392F–CNFG–2/08
5. Pin Description
Table 5-1.
Pin Description
AT17F16
5.1
Name
I/O
8
LAP
20
PLCC
44
TQFP
DATA
I/O
1
2
40
CLK
I
2
4
43
PAGE_EN
I
–
16
39
PAGESEL0
I
–
11
14
PAGESEL1
I
–
7
19
RESET/OE
I
3
6
13
CE
I
4
8
15
GND
–
5
10
18
CEO
O
6
14
21
A2
I
READY
O
–
15
23
SER_EN
I
7
17
35
VCC
–
8
20
38
DATA(1)
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
5.2
CLK(1)
Clock input. Used to increment the internal address and bit counter for reading and
programming.
5.3
PAGE_EN(2)
Input used to enable page download mode. When PAGE_EN is high the configuration download
address space is partitioned into 4 equal pages. This gives users the ability to easily store and
retrieve multiple configuration bitstreams from a single configuration device. This input works in
conjunction with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired.
When SER_EN is Low (ISP mode) this pin has no effect.
Notes:
1. This pin has an internal 20 kΩ pull-up resistor.
2. This pin has an internal 30 kΩ pull-down resistor.
4
AT17F16
3392F–CNFG–2/08
AT17F16
5.4
PAGESEL[1:0](2)
Page select inputs. Used to determine which of the 4 memory pages are targeted during a serial
configuration download. The address space for each of the pages is shown in Table 5-2. When
SER_EN is Low (ISP mode) these pins have no effect.
Table 5-2.
5.5
Address Space
Paging Decodes
AT17F16 (16 Mbits)
PAGESEL = 00, PAGE_EN = 1
00000 – 3FFFFh
PAGESEL = 01, PAGE_EN = 1
40000 – 7FFFFh
PAGESEL = 10, PAGE_EN = 1
80000 – BFFFFh
PAGESEL = 11, PAGE_EN = 1
C0000 – FFFFFh
PAGESEL = XX, PAGE_EN = 0
00000 – FFFFFh
RESET/OE(1)
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the
data output driver.
5.6
CE(1)
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address
counter and enables the data output driver. A High level on CE disables both the address and bit
counters and forces the device into a low-power standby mode. Note that this pin will not
enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low).
5.7
GND
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
5.8
CEO
Chip Enable Output (when SER_EN is High). This output goes Low when the internal address
counter has reached its maximum value. If the PAGE_EN input is set High, the maximum value
is the highest address in the selected partition. The PAGESEL[1:0] inputs are used to make the
4 partition selections. If the PAGE_EN input is set Low, the device is not partitioned and the
address maximum value is the highest address in the device, see Table 5-2 on page 5. In a
daisy chain of AT17F Series devices, the CEO pin of one device must be connected to the CE
input of the next device in the chain. It will stay Low as long as CE is Low and OE is High. It will
then follow CE until OE goes Low; thereafter, CEO will stay High until the entire EEPROM is
read again.
5.9
A2(1)
Device selection input, (when SER_EN Low). The input is used to enable (or chip select) the
device during programming (i.e., when SER_EN is Low). Refer to the AT17F Programming
Specification available on the Atmel web site for additional details.
Notes:
1. This pin has an internal 20 kΩ pull-up resistor.
2. This pin has an internal 30 kΩ pull-down resistor.
5
3392F–CNFG–2/08
5.10
READY
Open collector reset state indicator. Driven Low during power-up reset, released when power-up
is complete. (recommended 4.7 kΩ pull-up on this pin if used).
5.11
SER_EN(1)
The serial enable input must remain High during FPGA configuration operations. Bringing
SER_EN Low enables the 2-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to VCC.
5.12
VCC
+3.3V (±10%).
Notes:
1. This pin has an internal 20 kΩ pull-up resistor.
2. This pin has an internal 30 kΩ pull-down resistor.
6
AT17F16
3392F–CNFG–2/08
AT17F16
6. FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending
on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The AT17F Serial Configuration PROM has been
designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xilinx applications.
7. Control of Configuration
Most connections between the FPGA device and the AT17F Serial Configurator PROM are simple and self-explanatory.
• The DATA output of the AT17F Series Configurator drives DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of the AT17F Series Configurator.
• The CEO output of any AT17F Series Configurator drives the CE input of the next
Configurator in a cascade chain of configurator devices.
• SER_EN must be connected to VCC or allowed to float to logic High via the internal pull-up
resistor (except during ISP).
• The READY pin is available as an open-collector indicator of the device’s reset status; it is
driven Low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete.
• PAGE_EN must be held Low if download paging is not desired. The PAGESEL[1:0] inputs
must be tied off High or Low. If paging is desired, PAGE_EN must be High and the PAGESEL
pins must be set to High or Low such that the desired page is selected, see Table 5-2 on
page 5.
8. Cascading Serial Configuration Devices
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration
memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator asserts its
CEO output Low and disables its DATA line driver. The second configurator recognizes the Low
level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if
the RESET/OE on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be
tied to its inactive (High) level.
7
3392F–CNFG–2/08
9. Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial bus. The programming is done at VCC supply only. Programming
super voltages are generated inside the chip. The AT17F parts are read/write at 3.3V nominal.
Refer to the AT17F Programming Specification available on the Atmel web site
(www.atmel.com) for more programming details. AT17F devices are supported by the Atmel
ATDH2200E programming system along with many third party programmers.
10. Standby Mode
The AT17F Series Configurators enter a low-power standby mode whenever SER_EN is High
and CE is asserted High. In this mode, the AT17F Configurator consumes less than 5 mA of current at 3.6V. The output remains in a high-impedance state regardless of the state of the OE
input.
8
AT17F16
3392F–CNFG–2/08
AT17F16
11. Absolute Maximum Ratings*
Operating Temperature................................... -40° C to +85° C
*NOTICE:
Storage Temperature .................................... -65° C to +150° C
Voltage on Any Pin
with Respect to Ground ..............................-0.1V to VCC +0.5V
Supply Voltage (VCC) .........................................-0.5V to +4.0V
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods of time may affect device reliability.
Maximum Soldering Temp. (10 sec. @ 1/16 in.)............ 260° C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
12. Operating Conditions
AT17F Series Configurator
Symbol
Description
Min
Max
Units
Commercial
Supply voltage relative to GND
-0° C to +70° C
2.97
3.63
V
Industrial
Supply voltage relative to GND
-40° C to +85° C
2.97
3.63
V
VCC
13. DC Characteristics
AT17F16
Symbol
Description
Min
Max
Units
VIH
High-level Input Voltage
2.0
VCC
V
VIL
Low-level Input Voltage
0
0.8
V
VOH
High-level Output Voltage (IOH = -2.5 mA)
VOL
Low-level Output Voltage (IOL = +3 mA)
VOH
High-level Output Voltage (IOH = -2 mA)
VOL
Low-level Output Voltage (IOL = +3 mA)
0.4
V
ICCA
Supply Current, Active Mode (3.6V 33 MHz)
40
mA
IL
Input or Output Leakage Current (VIN = VCC or GND)
10
µA
Commercial
2
mA
ICCS
Supply Current, Standby Mode
Industrial
2
mA
2.4
V
Commercial
0.4
2.4
V
V
Industrial
-10
9
3392F–CNFG–2/08
14. AC Characteristics
CE
TSCE
TSCE
THCE
RESET/OE
TLC
THOE
THC
CLK
TOE
TOH
TCAC
TDF
TCE
DATA
TOH
15. AC Characteristics when Cascading
RESET/OE
CE
CLK
TCDF
DATA
FIRST BIT
LAST BIT
TOCK
TOCE
TOOE
CEO
TOCE
10
AT17F16
3392F–CNFG–2/08
AT17F16
16. AC Characteristics
AT17F16
Symbol
Description
TOE(2)
OE to Data Delay
TCE(2)
CE to Data Delay
TCAC(2)
CLK to Data Delay
TOH
Data Hold from CE, OE, or CLK
TDF(3)
CE or OE to Data Float Delay
TLC
CLK Low Time
THC
CLK High Time
TSCE
Min
Typ
Max
Units
50
ns
Industrial
55
ns
Commercial
55
ns
Industrial(1)
60
ns
30
ns
30
ns
Commercial
(1)
Commercial
3
(1)
Industrial
Commercial
(1)
Industrial
0
ns
0
ns
Commercial
(1)
Industrial
Commercial
15
ns
15
ns
15
ns
Industrial
15
ns
Commercial
15
ns
Industrial
15
ns
CE Setup Time to CLK
(to guarantee proper counting)
Commercial
20
ns
Industrial(1)
25
ns
CE Hold Time from CLK
(to guarantee proper counting)
Commercial
0
ns
THCE
Industrial
0
ns
RESET/OE Low Time
(guarantees counter is reset)
Commercial
20
ns
THOE
Industrial(1)
20
ns
Maximum Input Clock Frequency
SEREN = 0
Commercial
FMAX
FMAX
Maximum Input Clock Frequency
SEREN = 1
TWR
Write Cycle Time(4)
TEC
Erase Cycle Time(4)
Notes:
(1)
(1)
(1)
10
MHz
Industrial
10
MHz
Commercial
33
MHz
33
MHz
(1)
(1)
Industrial
Commercial
12
µs
Industrial
12
µs
Commercial
25
s
25
s
(1)
(1)
Industrial
1. Preliminary specifications for military operating range only.
2. AC test lead = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady-state active levels.
4. See the AT17F Programming Specification for procedural information.
11
3392F–CNFG–2/08
16.1
AC Characteristics When Cascading
AT17F16
Symbol
Description
TCDF(3)
CLK to Data Float Delay
TOCK(2)
CLK to CEO Delay
TOCE(2)
CE to CEO Delay
TOOE(2)
RESET/OE to CEO Delay
FMAX
Maximum Input Clock Frequency
Notes:
Min
Max
Units
Commercial
50
ns
Industrial
50
ns
Commercial
50
ns
Industrial
55
ns
Commercial
35
ns
Industrial
40
ns
Commercial
35
ns
Industrial
35
ns
Commercial
33
MHz
Industrial
33
MHz
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
17. Thermal Resistance Coefficients
Package Type
8CN4
20J
44A
Note:
12
Leadless Array Package (LAP)
Plastic Leaded Chip Carrier (PLCC)
Thin Plastic Quad Flat Package (TQFP)
AT17F16
θJC [° C/W]
θJA [° C/W]
(1)
–
–
θJC [° C/W]
–
θJA [° C/W](1)
–
θJC [° C/W]
17
θJA [° C/W]
(1)
62
1. Airflow = 0 ft/min.
AT17F16
3392F–CNFG–2/08
AT17F16
18. Ordering Information
Memory Size
Ordering Code
Package(1)(2)
Operation Range
AT17F16-30TQC
44A - 44 TQFP
Commercial
(0° C to 70° C)
AT17F16-30TQI
44A - 44 TQFP
Industrial
(-40° C to 85° C)
16-Mbit
Notes:
1. For the -30BJC and -30BJI packages, customers may migrate to the AT17F32-BJU.
2. For the -30JC and -30JI packages, customers may migrate to the AT17F16-30JU.
19. Green Package Options (Pb/Halide-free/RoHS Compliant)
Memory Size
Ordering Code
Package
Operation Range
16-Mbit
AT17F16-30CU
AT17F16-30JU
8CN4 - 8 LAP
20J - 20 PLCC
Industrial
(-40° C to 85° C)
Package Type
8CN4
8-lead, 6 mm x 6 mm x 1.04 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOIC Packages
20J
20-lead, Plastic J-leaded Chip Carrier (PLCC)
44A
44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP)
13
3392F–CNFG–2/08
20. Packaging Information
20.1
8CN4 – LAP
Marked Pin1 Indentifier
E
A
A1
D
Side View
Top View
Pin1 Corner
L1
0.10 mm
TYP
8
1
COMMON DIMENSIONS
(Unit of Measure = mm)
e
7
2
6
3
b
5
4
e1
L
Bottom View
Note:
SYMBOL
MIN
NOM
MAX
A
0.94
1.04
1.14
A1
0.30
0.34
0.38
b
0.45
0.50
0.55
D
5.89
5.99
6.09
E
5.89
5.99
6.09
e
1.27 BSC
e1
1.10 REF
NOTE
1
L
0.95
1.00
1.05
1
L1
1.25
1.30
1.35
1
1. Metal Pad Dimensions.
2. All exposed metal area shall have the following finished platings.
Ni: 0.0005 to 0.015 mm
Au: 0.0005 to 0.001 mm
2/15/08
Package Drawing Contact:
[email protected]
14
TITLE
8CN4, 8-lead (6 x 6 x 1.04 mm Body),
Lead Pitch 1.27mm,
Leadless Array Package (LAP)
GPC
DMH
DRAWING NO.
8CN4
REV.
D
AT17F16
3392F–CNFG–2/08
AT17F16
20.2
20J – PLCC
PIN NO. 1
1.14(0.045) X 45˚
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
e
E1
E
D2/E2
B1
B
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
9.779
–
10.033
D1
8.890
–
9.042
E
9.779
–
10.033
E1
8.890
–
9.042
D2/E2
7.366
–
8.382
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
20J
B
15
3392F–CNFG–2/08
20.3
44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
11.75
12.00
12.25
D1
9.90
10.00
10.10
E
11.75
12.00
12.25
E1
9.90
10.00
10.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
10/5/2001
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
44A
B
AT17F16
3392F–CNFG–2/08
AT17F16
21. Revision History
Revision Level – Release Date
History
D – March 2006
Added last-time buy for AT17F16-30CC and AT17F16-30CI.
E – August 2007
Removed -30CC and -30CI devices from ordering information.
Announced last-time buy for -30JC, -30BJC, -30JI, and -30BJI
devices.
F – February 2008
Removed -30JC, -30JI, -30BJC and -30BJI devices from ordering
information.
17
3392F–CNFG–2/08
18
AT17F16
3392F–CNFG–2/08
AT17F16
19
3392F–CNFG–2/08
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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