ADS1118 www.ti.com SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 Ultra-Small, Low-Power, SPI™-Compatible, 16-Bit Analog-to-Digital Converter and Temperature Sensor with Internal Reference Check for Samples: ADS1118 FEATURES DESCRIPTION • The ADS1118 is a precision analog-to-digital converter (ADC) with 16 bits of resolution offered in an ultra-small, leadless QFN-10 package or an MSOP-10 package. The ADS1118 is designed with precision, power, and ease of implementation in mind. The ADS1118 features an onboard reference and oscillator. Data are transferred via a serial peripheral interface (SPI). The ADS1118 operates from a single power supply ranging from 2V to 5.5V. 1 23 • • • • • • • • • Ultra-Small QFN Package: 2mm × 1,5mm × 0,4mm Wide Supply Range: 2.0V to 5.5V Low Current Consumption: – Continuous Mode: Only 150μA – Single-Shot Mode: Auto Shutdown Programmable Data Rate: 8SPS to 860SPS Single-Cycle Settling Internal Low-Drift Voltage Reference Internal Temperature Sensor: – 0.5°C Max Error Internal Oscillator Internal PGA Four Single-Ended or Two Differential Inputs APPLICATIONS • • • Temperature Measurement: – Thermocouple Measurement – Cold Junction Compensation – Thermistor Measurement Portable Instrumentation Factory Automation and Process Controls The ADS1118 can perform conversions at rates up to 860 samples per second (SPS). An onboard programmable gain amplifier (PGA) is available on the ADS1118 that offers input ranges from the supply to as low as ±256mV. This range allows both large and small signals to be measured with high resolution. The ADS1118 also features an input multiplexer (MUX) that provides two differential or four single-ended inputs. The ADS1118 can also function as a high-accuracy temperature sensor. This temperature sensor can be used for system-level temperature monitoring or cold junction compensation for thermocouples. The ADS1118 operates either in continuous conversion mode or a single-shot mode that automatically powers down after a conversion. Single-shot mode significantly reduces current consumption during idle periods. The ADS1118 is specified from –40°C to +125°C. 2V 0.1 F 2V 1Mȍ GND 500ȍ 0.1 F GND AIN0 VDD 1 F 1Mȍ 500ȍ ADS1118 Voltage Reference AIN1 0.1 F SCLK GND GND 2V 1Mȍ MUX PGA GND 500ȍ 0.1 F DIN Oscillator AIN3 500ȍ GND 0.1 F CS DOUT/DRDY AIN2 1 F 1Mȍ 16-bit Ȉǻ ADC SPI Interface High Accuracy Temp Sensor GND GND GND 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2012, Texas Instruments Incorporated ADS1118 SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) ADS1118 VDD to GND Analog input current Analog input current V 100, momentary mA 10, continuous mA –0.3 to VDD + 0.3 V –0.3 to +5.5 V Human body model (HBM) JEDEC standard 22, test method A114-C.01, all pins ±4000 V Charged device model (CDM) JEDEC standard 22, test method C101, all pins ±1000 V –40 to +125 °C +150 °C –60 to +150 °C Analog input voltage to GND DIN, DOUT/DRDY, SCLK, CS voltage to GND ESD ratings Operating temperature range Maximum junction temperature Storage temperature range (1) UNIT –0.3 to +5.5 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PRODUCT FAMILY 2 DEVICE RESOLUTION (Bits) MAXIMUM SAMPLE RATE (SPS) SPECIAL FEATURES PGA INTERFACE INPUT CHANNELS (Differential/ Single-Ended) ADS1118 16 860 Temperature sensor Yes SPI 2/4 ADS1018 12 3300 Temperature sensor Yes SPI 2/4 ADS1115 16 860 Comparator Yes I2C 2/4 ADS1114 16 860 Comparator Yes I2C 1/1 2 ADS1113 16 860 None No I C 1/1 ADS1015 12 3300 Comparator Yes I2C 2/4 ADS1014 12 3300 Comparator Yes I2C 1/1 ADS1013 12 3300 None No I2C 1/1 Copyright © 2010–2012, Texas Instruments Incorporated ADS1118 www.ti.com SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS Maximum/minimum specifications at –40°C to +125°C, VDD = 3.3V, data rate = 8SPS, and full-scale (FS) = ±2.048V, unless otherwise noted. Typical values are at +25°C, VDD = 3.3V, data rate = 8SPS, and full-scale (FS) = ±2.048V, unless otherwise noted. ADS1118 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input voltage (1) VIN = (AINP) – (AINN) Analog input voltage AINP or AINN to GND ±4.096/PGA GND Differential input impedance V VDD V See Table 1 Common-mode input impedance FS = ±6.144V (1) 8 MΩ FS = ±4.096V (1), ±2.048V 6 MΩ FS = ±1.024V 3 MΩ FS = ±0.512V, ±0.256V 100 MΩ 8, 16, 32, 64, 128, 250, 475, 860 SPS SYSTEM PERFORMANCE Resolution No missing codes 16 Data rate (DR) Data rate variation All data rates –10 Output noise Integral nonlinearity Offset error Gain error DR = 8SPS, FS = ±2.048V, best fit (2) % 1 LSB ±2 LSB FS = ±2.048V, differential inputs ±0.1 FS = ±2.048V, single-ended inputs ±0.25 LSB FS = ±2.048V 0.002 LSB/°C FS = ±2.048V, with dc supply variation 0.2 LSB/V FS = ±2.048V at +25°C 0.01 FS = ±0.256V 7 FS = ±2.048V 5 (3) Gain drift (3) (4) FS = ±6.144V (1) 0.15 % ppm/°C 40 5 Gain power-supply rejection PGA gain match (3) 10 See Typical Characteristics Offset drift Offset power-supply rejection Bits ppm/°C ppm/°C 10 ppm/V Match between any two PGA gains 0.01 0.1 Gain match Match between any two inputs 0.01 0.1 Offset match Match between any two inputs 0.6 LSB At dc and FS = ±0.256V 105 dB At dc and FS = ±2.048V 100 dB Common-mode rejection At dc and FS = ±6.144V (1) % % 90 dB fCM = 60Hz, DR = 860SPS 105 dB fCM = 50Hz, DR = 860SPS 105 dB TEMPERATURE SENSOR Temperature sensor range –40 Temperature sensor resolution Temperature sensor accuracy (1) (2) (3) (4) +125 0.03125 °C °C/LSB 0°C to +70°C 0.2 ±0.5 –40°C to +125°C 0.4 ±1 °C °C vs supply 0.03125 ±0.25 °C/V This parameter expresses the full-scale range of the ADC scaling. In no event should more than the smaller of VDD + 0.3V or 5.5V be applied to this device. Best fit INL covers 99% of full-scale. Includes all errors from onboard PGA and reference. Not production tested; ensured by characterization. Copyright © 2010–2012, Texas Instruments Incorporated 3 ADS1118 SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Maximum/minimum specifications at –40°C to +125°C, VDD = 3.3V, data rate = 8SPS, and full-scale (FS) = ±2.048V, unless otherwise noted. Typical values are at +25°C, VDD = 3.3V, data rate = 8SPS, and full-scale (FS) = ±2.048V, unless otherwise noted. ADS1118 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic level VIH 0.7VDD VDD V VIL GND 0.2VDD V VOH IOH = 1mA 0.8VDD VOL IOL = 1mA GND V 0.2VDD V Input leakage IH VIH = 5.5V ±10 μA IL VIL = GND ±10 μA 5.5 V 2 μA 5 μA 200 μA POWER-SUPPLY REQUIREMENTS Power-supply voltage 2 Power-down current at +25°C 0.5 Power-down current up to +125°C Supply current Operating current at +25°C 150 Operating current up to +125°C Power dissipation 300 μA VDD = 5.0V 0.9 mW VDD = 3.3V 0.5 mW VDD = 2.0V 0.3 mW TEMPERATURE Storage temperature –60 +150 °C Specified temperature –40 +125 °C THERMAL INFORMATION ADS1118 THERMAL METRIC (1) DGS UNITS 10 PINS θJA Junction-to-ambient thermal resistance θJCtop Junction-to-case (top) thermal resistance 51.5 θJB Junction-to-board thermal resistance 108.4 ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter 106.5 θJCbot Junction-to-case (bottom) thermal resistance n/a (1) 4 186.8 2.7 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 PIN CONFIGURATIONS RUG PACKAGE QFN-10 (TOP VIEW) DGS PACKAGE MSOP-10 (TOP VIEW) DIN 10 SCLK 1 9 DOUT/DRDY CS 2 8 VDD GND 3 7 AIN3 AIN0 4 6 AIN2 SCLK 1 10 DIN CS 2 9 DOUT/DRDY GND 3 8 VDD AIN0 4 7 AIN3 AIN1 5 6 AIN2 5 AIN1 PIN DESCRIPTIONS PIN # PIN NAME ANALOG/ DIGITAL INPUT/ OUTPUT 1 SCLK Digital input Serial clock input 2 CS Digital input Chip select; active low 3 GND Analog 4 AIN0 Analog input Differential channel 1: positive input or single-ended channel 1 input 5 AIN1 Analog input Differential channel 1: negative input or single-ended channel 2 input 6 AIN2 Analog input Differential channel 2: positive input or single-ended channel 3 input 7 AIN3 Analog input Differential channel 2: negative input or single-ended channel 4 input 8 VDD Analog 9 DOUT/DRDY Digital output Serial data out combined with data ready; active low 10 DIN Digital input Serial data input DESCRIPTION Ground Power supply: 2V to 5.5V Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 5 ADS1118 SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 www.ti.com SPI TIMING CHARACTERISTICS tCSH CS tSCLK tCSSC tSPWH tSCCS SCLK tDIHD tDIST tSPWL tSCSC DIN tCSDOD tDOHD tDOPD tCSDOZ Hi-Z Hi-Z DOUT Figure 1. Serial Interface Timing TIMING REQUIREMENTS: SERIAL INTERFACE TIMING At TA = –40°C to +125°C and VDD = 2V to 5.5V, unless otherwise noted. SYMBOL (1) (2) (3) 6 DESCRIPTION MIN MAX UNIT tCSSC CS low to first SCLK: setup time (1) 100 ns tSCLK SCLK period 250 ns tSPWH SCLK pulse width: high 100 ns tSPWL SCLK pulse width: low (2) tDIST Valid DIN to SCLK falling edge: setup time 50 50 100 ns 28 tDIHD Valid DIN to SCLK falling edge: hold time tDOPD SCLK rising edge to valid new DOUT: propagation delay (3) tDOHD SCLK rising edge to DOUT invalid: hold time tCSDOD tCSDOZ ms ns ns 50 ns 0 ns CS low to DOUT driven: propagation delay 100 ns CS high to DOUT Hi-Z: propagation delay 100 ns tCSH CS high pulse 200 ns tSCCS Final SCLK falling edge to CS high 100 ns CS can be tied low. Holding SCLK low longer than 28ms resets the SPI interface. DOUT load = 20pF || 100kΩ to DGND. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS At TA = +25°C and VDD = 3.3V, unless otherwise noted. TOTAL ERROR vs INPUT SIGNAL DATA RATE vs TEMPERATURE 4 4 VDD = 2V VDD = 3.3V VDD = 5V 3 2 2 Data Rate Error (%) Total Error (mV) Includes noise, offset, and gain error. 3 1 0 -1 -2 FS = ±2.048V Data Rate = 860SPS Differential Inputs -3 -4 -2.048 0 -1.024 1 0 −1 −2 −3 1.024 −4 −60 −40 −20 2.048 0 Input Signal (V) 20 40 60 80 Temperature (°C) Figure 2. 100 120 140 G028 Figure 3. NOISE vs INPUT SIGNAL NOISE vs SUPPLY VOLTAGE 10 35 FS = ±0.512V FS = ±2.048V DR = 860SPS DR = 860SPS 30 RMS Noise (µV) RMS Noise (µV) 8 6 4 DR = 128SPS 25 20 15 DR = 128SPS 10 DR = 8SPS DR = 8SPS 2 5 0 −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 Input Voltage (V) 0.3 0.4 0 2.0 0.5 2.5 3.0 G017 3.5 4.0 4.5 Supply Voltage (V) Figure 4. NOISE vs TEMPERATURE G018 INL vs SUPPLY VOLTAGE (1) 15 Integral Nonlinearity (ppm) FS = ±2.048V Data Rate = 8SPS 8 RMS Noise (µV) 5.5 Figure 5. 10 9 5.0 7 6 5 4 3 12.5 FS = ±0.256V FS = ±0.512V FS = ±2.048V FS = ±6.144V 10 7.5 5 2.5 2 1 −40 −20 0 20 40 60 Temperature (°C) 80 100 120 0 2.0 G019 Figure 6. (1) 2.5 3.0 3.5 4.0 4.5 Supply Voltage (V) 5.0 5.5 G010 Figure 7. This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3V be applied to this device. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 7 ADS1118 SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C and VDD = 3.3V, unless otherwise noted. INL vs INPUT SIGNAL INL vs INPUT SIGNAL 5 10 FS = ±2.048V VDD = 3.3V DR = 8SPS Best Fit 3 2 1 0 −1 −2 −40°C +25°C +125°C −3 −4 −5 −2 −1.5 −40°C +25°C +125°C 8 Integral Nonlinearity (ppm) Integral Nonlinearity (ppm) 4 6 4 2 0 −2 −4 FS = ±0.512V VDD = 3.3V DR = 8SPS Best Fit −6 −8 −1 −0.5 0 0.5 Input Signal (V) 1 1.5 −10 −0.5 2 −0.4 −0.2 G011 Figure 8. INL vs INPUT SIGNAL 3 2 Integral Nonlinearity (ppm) Integral Nonlinearity (ppm) G012 1 0 −1 −2 −40°C +25°C +125°C −3 −2 −1.5 −40°C +25°C +125°C 8 6 4 2 0 −2 −4 FS = ±0.512V VDD = 5V DR = 8SPS Best Fit −6 −8 −1 −0.5 0 0.5 Input Signal (V) 1 1.5 −10 −0.5 2 −0.4 −0.2 G013 Figure 10. −0.1 0 0.1 Input Signal (V) 0.2 0.4 0.5 G014 Figure 11. INL vs TEMPERATURE INL vs DATA RATE 12 16 FS = ±2.048V DR = 8SPS Best Fit VDD = 2V VDD = 3.3V VDD = 5V 8 6 4 2 0 −60 −40 −20 FS = ±2.048V Best Fit 14 Integral Nonlinearity (ppm) Integral Nonlinearity (ppm) 0.5 INL vs INPUT SIGNAL FS = ±2.048V VDD = 5V DR = 8SPS Best Fit −4 −40°C +25°C +125°C 12 10 8 6 4 2 0 20 40 60 80 Temperature (°C) 100 120 140 0 8 G015 Figure 12. 8 0.4 10 4 10 0.2 Figure 9. 5 −5 −0.1 0 0.1 Input Signal (V) 16 32 64 128 250 Data Rate (SPS) 475 860 G016 Figure 13. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) At TA = +25°C and VDD = 3.3V, unless otherwise noted. SINGLE-ENDED OFFSET vs TEMPERATURE SINGLE-ENDED OFFSET vs SUPPLY 60 60 AIN0 to GND AIN1 to GND AIN2 to GND AIN3 to GND AIN0 to GND AIN1 to GND AIN2 to GND AIN3 to GND 40 Offset Voltage (µV) Offset Voltage (µV) 40 20 0 −20 −40 20 0 −20 −40 FS = ±2.048V −60 −40 −20 FS = ±2.048V 0 20 40 60 Temperature (°C) 80 100 −60 120 2 2.5 3 3.5 4 Supply Voltage (V) G004 Figure 14. DIFFERENTIAL OFFSET vs TEMPERATURE G005 DIFFERENTIAL OFFSET vs SUPPLY 40 AIN0 to AIN1 AIN0 to AIN3 AIN1 to AIN3 AIN2 to AIN3 20 AIN0 to AIN1 AIN0 to AIN3 AIN1 to AIN3 AIN2 to AIN3 30 Offset Voltage (µV) 30 Offset Voltage (µV) 5 Figure 15. 40 10 0 −10 −20 −30 20 10 0 −10 −20 −30 FS = ±2.048V −40 −40 −20 FS = ±2.048V 0 20 40 60 Temperature (°C) 80 100 −40 120 2 2.5 G006 Figure 16. 3 3.5 4 Supply Voltage (V) 4.5 5 G007 Figure 17. OFFSET DRIFT HISTOGRAM OFFSET HISTOGRAM 15 200 Offset Drift from −40°C to +125°C FS = ±2.048V, MUX = AIN0 to AIN3 30 units from one production lot 540 units from 3 production lots FS = ±2.048V Number of Occurrences Number of Occurrences 4.5 10 5 100 50 Offset Drift (LSB/°C) −10 −8 −6 −4 −2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 0.005 0.004 0.003 0.002 0.001 0 −0.001 −0.002 −0.003 −0.004 0 −0.005 0 150 Offset (µV) G046 Figure 18. G000 Figure 19. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 9 ADS1118 SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C and VDD = 3.3V, unless otherwise noted. GAIN ERROR vs TEMPERATURE GAIN ERROR vs SUPPLY 0.05 0.15 0.04 0.10 0.02 Gain Error (%) Gain Error (%) 0.03 0.01 0 FS = ±0.256V FS = ±0.512V FS = ±1.024V FS = ±2.048V FS = ±4.096V FS = ±6.144V −0.01 −0.02 −0.03 −0.04 −0.05 −40 −20 0 20 40 60 80 Temperature (°C) 100 120 0.05 FS = ±256mV 0 FS = ±2.048V -0.05 -0.10 -0.15 140 2.0 2.5 3.0 3.5 G008 Figure 20. 4.5 5.0 5.5 Figure 21. GAIN ERROR HISTOGRAM OPERATING CURRENT vs TEMPERATURE 200 300 540 units from 3 production lots FS = ±2.048V 250 Operating Current (mA) Number of Occurrences 4.0 Supply Voltage (V) 150 100 50 VDD = 5V 200 150 VDD = 3.3V VDD = 2V 100 50 0 Gain Error (%) 0.05 0.04 0.045 0.03 0.035 0.02 0.025 0.01 0.015 0 0.005 −0.01 −0.005 −0.015 −0.02 0 -40 -20 0 VDD = 2V VDD = 3.3V VDD = 5V 120 140 Data Rate = 8SPS -10 -20 3.5 Gain (dB) Shutdown Current (µA) 100 FREQUENCY RESPONSE 0 3 2.5 2 1.5 -30 -40 -50 -60 1 -70 0.5 −20 0 20 40 60 80 Temperature (°C) 100 120 140 -80 1 G003 Figure 24. 10 80 Figure 23. SHUTDOWN CURRENT vs TEMPERATURE 0 −40 60 G000 5 4 40 Temperature (°C) Figure 22. 4.5 20 10 100 1k 10k Input Frequency (Hz) Figure 25. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) At TA = +25°C and VDD = 3.3V, unless otherwise noted. TEMPERATURE SENSOR ERROR vs AMBIENT TEMPERATURE (MSOP) TEMPERATURE SENSOR ERROR HISTOGRAM (MSOP) 1 40 Average Temperature Error Average ± 3 sigma Average ± 6 sigma 0.6 35 Number of Occurrences 0.4 0.2 0 −0.2 −0.4 −0.6 Ambient temperature = −40°C 48 units from 3 production lots 30 25 20 15 10 5 −0.8 G023 0.5 0.4 0.3 0.2 0 120 0.1 100 0 80 −0.1 20 40 60 Temperature (°C) −0.2 0 −0.3 −20 −0.5 −1 −40 −0.4 Temperature Error (°C) 0.8 Temperature Error (°C) Figure 27. TEMPERATURE SENSOR ERROR HISTOGRAM (MSOP) TEMPERATURE SENSOR ERROR HISTOGRAM (MSOP) 15 Temperature Error (°C) 0.5 0.4 0.3 −0.5 0.5 0.4 0.3 0.2 0.1 0 −0.1 −0.2 0 −0.3 0 −0.4 5 0.2 10 5 0.1 10 20 0 15 25 −0.1 20 30 −0.2 25 Ambient temperature = 25°C 48 units from 3 production lots −0.3 Number of Occurrences 35 30 −0.5 Temperature Error (°C) G040 G042 Figure 28. Figure 29. TEMPERATURE SENSOR ERROR HISTOGRAM (MSOP) TEMPERATURE SENSOR ERROR HISTOGRAM (MSOP) 35 15 Temperature Error (°C) G043 Figure 30. 0.5 −0.5 0.5 0.4 0.3 0.2 0.1 0 −0.1 −0.2 0 −0.3 0 −0.4 5 −0.5 5 0.4 10 0.3 10 20 0.2 15 25 0.1 20 0 25 30 −0.1 30 Ambient temperature = 125°C 48 units from 3 production lots −0.2 Number of Occurrences 35 40 Ambient temperature = 70°C 48 units from 3 production lots −0.3 40 −0.4 Number of Occurrences 35 40 Ambient temperature = 0°C 48 units from 3 production lots −0.4 40 Number of Occurrences G040 Figure 26. Temperature Error (°C) G045 Figure 31. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 11 ADS1118 SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C and VDD = 3.3V, unless otherwise noted. TEMPERATURE SENSOR ERROR vs AMBIENT TEMPERATURE (QFN) 1 0.8 80 0.6 70 Number of Occurrences 0.4 0.2 0 -0.2 -0.4 -0.6 $PELHQW WHPSHUDWXUH í 94 units from production °C 60 50 40 30 20 10 -0.8 -1 C007 0.5 0.4 0.3 0.2 120 0.1 100 0 80 -0.1 20 40 60 Temperature (ƒC) -0.2 0 -0.3 -20 -0.5 0 -40 -0.4 Temperature Error (ƒC) TEMPERATURE SENSOR ERROR HISTOGRAM (QFN) Average Temperature Error Average “ 3 sigma Average “ 6 sigma Temperature Error (ƒC) Figure 33. TEMPERATURE SENSOR ERROR HISTOGRAM (QFN) TEMPERATURE SENSOR ERROR HISTOGRAM (QFN) 30 Temperature Error (ƒC) 0.5 0.4 0.3 -0.5 0.5 0.4 0.3 0.2 0.1 0 -0.1 0 -0.2 0 -0.3 10 -0.4 10 0.2 20 0.1 20 40 0 30 50 -0.1 40 60 -0.2 50 Ambient temperature = 25°C 94 units from production -0.3 Number of Occurrences 70 60 -0.5 Number of Occurences 70 80 Ambient temperature = 0°C 94 units from production -0.4 80 Temperature Error (ƒC) C002 C003 Figure 34. Figure 35. TEMPERATURE SENSOR ERROR HISTOGRAM (QFN) TEMPERATURE SENSOR ERROR HISTOGRAM (QFN) 60 90 80 Ambient temperature = 70°C 94 units from production 50 70 Number of Occurrences Number of Occurrences C001 Figure 32. 60 50 40 30 20 Ambient temperature = 125°C 94 units from production 40 30 20 10 10 Temperature Error (ƒC) C004 Figure 36. 12 Temperature Error (ƒC) 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0 -0.5 0 C006 Figure 37. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 OVERVIEW The ADS1118 is a very small, low-power, 16-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC). The ADS1118 is extremely easy to configure and design into a wide variety of applications, and allows precise measurements to be obtained with very little effort. Both experienced and novice users of data converters find designing with the ADS1118 family to be intuitive and problem-free. The ADS1118 consists of a ΔΣ analog-to-digital (A/D) core with adjustable gain, an internal voltage reference, a clock oscillator, and an SPI. This device is also a highly linear and accurate temperature sensor. All of these features are intended to reduce required external circuitry and improve performance. Figure 38 shows the ADS1118 functional block diagram. VDD Device Voltage Reference MUX AIN0 Gain = 2/3, 1, 2, 4, 8, or 16 CS SCLK AIN1 16-Bit DS ADC PGA SPI Interface DIN DOUT/DRDY AIN2 Oscillator AIN3 Temperature Sensor GND Figure 38. ADS1118 Functional Block Diagram The ADS1118 A/D core measures a differential signal, VIN, that is the difference of AINP and AINN. The converter core consists of a differential, switched-capacitor ΔΣ modulator followed by a digital filter. This architecture results in a very strong attenuation in any common-mode signals. Input signals are compared to the internal voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the input voltage. The ADS1118 has two available conversion modes: single-shot mode and continuous conversion mode. In single-shot mode, the ADC performs one conversion of the input signal upon request and stores the value to an internal conversion register. The device then enters a low-power shutdown mode. This mode is intended to provide significant power savings in systems that require only periodic conversions or when there are long idle periods between conversions. In continuous conversion mode, the ADC automatically begins a conversion of the input signal as soon as the previous conversion is completed. The rate of continuous conversion is equal to the programmed data rate. Data can be read at any time and always reflect the most recent completed conversion. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 13 ADS1118 SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 www.ti.com MULTIPLEXER The ADS1118 contains an input multiplexer, as shown in Figure 39. Either four single-ended or two differential signals can be measured. Additionally, AIN0 and AIN1 may be measured differentially to AIN3. The multiplexer is configured by three bits in the Config Register. When single-ended signals are measured, the negative input of the ADC is internally connected to GND by a switch within the multiplexer. VDD Device AIN0 VDD GND AINP AIN1 AINN VDD GND AIN2 VDD GND AIN3 GND GND Figure 39. ADS1118 MUX When measuring single-ended inputs, it is important to note that the negative range of the output codes are not used. These codes are for measuring negative differential signals, such as (AINP – AINN) < 0. Electrostatic discharge (ESD) diodes to VDD and GND protect the inputs. To prevent the ESD diodes from turning on, the absolute voltage on any input must stay within the range of Equation 1: GND – 0.3V < AINx < VDD + 0.3V (1) If it is possible that the voltages on the input pins may violate these conditions, external Schottky clamp diodes and/or series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings table). While the analog inputs can support signals marginally above supply, under no circumstances should any analog or digital input or output be driven to greater than 5.5V with respect to the GND pin. Also, overdriving one unused input on the ADS1118 may affect conversions taking place on other input pins. If overdrive on unused inputs is possible, it is recommended to clamp the signal with external Schottky diodes. 14 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 ANALOG INPUTS The ADS1118 uses a switched-capacitor input stage where capacitors are continuously charged and then discharged to measure the voltage between AINP and AINN. The capacitors used are small, and to external circuitry, the average loading appears resistive. This structure is shown in Figure 40. The resistance is set by the capacitor values and the rate at which they are switched. Figure 41 shows the on/off setting of the switches illustrated in Figure 40. During the sampling phase, switches S1 are closed. This event charges CA1 to AINP, CA2 to AINN, and CB to (AINP – AINN). During the discharge phase, S1 is first opened and then S2 is closed. Both CA1 and CA2 then discharge to approximately 0.7V and CB discharges to 0V. This charging draws a very small transient current from the source driving the ADS1118 analog inputs. The average value of this current can be used to calculate the effective impedance (Reff), where Reff = VIN/IAVERAGE. 0.7V CA1 AINP S1 ZCM S2 0.7V Equivalent Circuit AINP CB S1 ZDIFF S2 AINN AINN 0.7V ZCM CA2 fCLK = 250kHz 0.7V Figure 40. Simplified Analog Input Circuit tSAMPLE ON S1 OFF ON S2 OFF Figure 41. S1 and S2 Switch Timing for Figure 40 The common-mode input impedance is measured by applying a common-mode signal to the shorted AINP and AINN inputs and measuring the average current consumed by each pin. The common-mode input impedance changes depending on the PGA gain setting, but is approximately 6MΩ for the default PGA gain setting. In Figure 40, the common-mode input impedance is ZCM. The differential input impedance is measured by applying a differential signal to AINP and AINN inputs where one input is held at 0.7V. The current that flows through the pin connected to 0.7V is the differential current and scales with the PGA gain setting. In Figure 40, the differential input impedance is ZDIFF. Table 1 describes the typical differential input impedance. Table 1. Differential Input Impedance FS (V) (1) (1) ±6.144V (1) DIFFERENTIAL INPUT IMPEDANCE 22MΩ ±4.096V(1) (1) 15MΩ ±2.048V 4.9MΩ ±1.024V 2.4MΩ ±0.512V 710kΩ ±0.256V 710kΩ This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3V be applied to this device. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 15 ADS1118 SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 www.ti.com The typical value of the input impedance cannot be neglected. Unless the input source has a low impedance, the ADS1118 input impedance may affect the measurement accuracy. For sources with high output impedance, buffering may be necessary. Note that active buffers introduce noise, and also introduce offset and gain errors. All of these factors should be considered in high-accuracy applications. Because the clock oscillator frequency drifts slightly with temperature, the input impedances also drift. For many applications, this input impedance drift can be ignored, and the values given in Table 1 for typical input impedance are valid. FULL-SCALE INPUT A PGA is implemented before the ΔΣ core of the ADS1118. The PGA can be set to gains of 2/3, 1, 2, 4, 8, and 16. Table 2 shows the corresponding full-scale (FS) ranges. The PGA is configured by three bits in the Config register. The PGA = 2/3 setting allows input measurement to extend up to the supply voltage when VDD is larger than 4V. Note, however, in this case (as well as for PGA = 1 and VDD < 4V) that it is not possible to reach a fullscale output code on the ADC. Analog input voltages may never exceed the analog input voltage limits given in the Electrical Characteristics table. Table 2. PGA Gain Full-Scale Range (1) 16 PGA SETTING FS (V) 2/3 ±6.144V(1) (1) 1 ±4.096V(1) 2 ±2.048V 4 ±1.024V 8 ±0.512V 16 ±0.256V This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3V be applied to this device. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 DATA FORMAT The ADS1118 provides 16 bits of data in binary twos complement format. The positive full-scale input produces an output code of 7FFFh and the negative full-scale input produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale. Table 3 summarizes the ideal output codes for different input signals. Figure 42 shows code transitions versus input voltage. Table 3. Input Signal versus Ideal Output Code INPUT SIGNAL, VIN (AINP – AINN) 15 ≥ FS (2 IDEAL OUTPUT CODE (1) 15 – 1)/2 7FFFh +FS/215 0001h 0 0 15 –FS/2 FFFFh ≤ –FS (1) 8000h Excludes the effects of noise, INL, offset, and gain errors. 0x7FFF 0x0001 0x0000 0xFFFF ¼ Output Code ¼ 0x7FFE 0x8001 0x8000 ¼ -FS 2 15 0 Input Voltage (AINP - AINN) -1 -FS 2 FS ¼ 15 2 15 FS 2 -1 15 Figure 42. ADS1118 Code Transition Diagram Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 17 ADS1118 SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 www.ti.com TEMPERATURE SENSOR The temperature measurement mode of the ADS1118 is configured as a 14-bit result when enabled. Two bytes must be read to obtain data. The first byte is the most significant byte (MSB), followed by a second byte, the least significant byte (LSB). The first 14 bits are used to indicate temperature. That is, the 14-bit temperature result is left-justified within the 16-bit result register and the last two bits always read back as '0'. One 14-bit LSB equals 0.03125°C. Negative numbers are represented in binary twos complement format. Table 4. 14-bit Temperature Data Format TEMPERATURE (°C) DIGITAL OUTPUT (BINARY) HEX 128 01 0000 0000 0000 1000 127.96875 00 1111 1111 1111 0FFF 100 00 1100 1000 0000 0C80 80 00 1010 0000 0000 0A00 75 00 1001 0110 0000 0960 50 00 0110 0100 0000 0640 25 00 0011 0010 0000 0320 0.25 00 0000 0000 1000 0008 0 00 0000 0000 0000 0000 –0.25 11 1111 1111 1000 3FF8 –25 11 1100 1110 0000 3CE0 –55 11 1001 0010 0000 3920 Converting from Temperature to Digital Codes For positive temperatures (for example, +50°C): Twos complement is not performed on positive numbers. Therefore, simply convert the number to binary code in a 14-bit left justified format with the MSB = 0 to denote the positive sign. Example: (+50°C)/(0.03125°C/count) = 1600 = 0640h = 00 0110 0100 0000 For negative temperatures (for example –25°C): Generate the twos complement of a negative number by complementing the absolute binary number and adding 1. Then denote the negative sign with the MSB = 1. Example:(|–25°C|)/(0.03125°C/count) = 800 = 0320h = 00 0011 0010 0000 Twos complement format: 11 1100 1101 1111 + 1 = 11 1100 1110 0000 Converting from Digital Codes to Temperature To convert from digital codes to temperature, first check whether the MSB is a '0' or a '1'. If the MSB is a '0', simply multiply the decimal code by 0.03125°C to obtain the result. If the MSB = 1, subtract '1' from the result and complement all of the bits. Then multiply the result by –0.03125°C. Example: ADS1118 reads back 0960h: 0960h has an MSB = 0. (0960h)(0.03125°C) = (2400)(0.03125°C) = +75°C Example: ADS1118 reads back 3CE0h: 3CE0h has an MSB = 1. Complement the result: 3CE0h → 0320h (0320h)(–0.03125°C) = (800)(–0.03125°C) = –25°C 18 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 ALIASING As with any data converter, if the input signal contains frequencies greater than half the data rate, aliasing occurs. To prevent aliasing, the input signal must be bandlimited. Some signals are inherently bandlimited; for example, the output of a thermocouple has a limited rate of change. Nevertheless, these signals can contain noise and interference components. These components can fold back into the sampling band in the same way as with any other signal. The ADS1118 digital filter provides some attenuation of high-frequency noise, but the digital sinc filter frequency response cannot completely replace an anti-aliasing filter. For some applications, some external filtering may be needed; in such instances, a simple RC filter is adequate. When designing an input filter circuit, be sure to take into account the interaction between the filter network and the input impedance of the ADS1118. OPERATING MODES The ADS1118 operates in one of two modes: continuous conversion or single-shot. In continuous conversion mode, the ADS1118 continuously performs conversions. Once a conversion has been completed, the ADS1118 places the result in the Conversion Register and immediately begins another conversion. In single-shot mode, the ADS1118 waits until the OS bit is set high. Once asserted, the bit is set to '0', indicating that a conversion is currently in progress. Once conversion data are ready, the OS bit reasserts and the device powers down. Writing a '1' to the OS bit during a conversion has no effect. RESET AND POWER-UP When the ADS1118 powers up, a reset is performed. As part of the reset process, the ADS1118 sets all of the bits in the Config Register to the respective default settings. By default, the ADS1118 enters into a power-down state at start-up. The device interface and digital are active, but no conversion occurs until the Config Register is written to. The initial power-down state of the ADS1118 is intended to relieve systems with tight power-supply requirements from encountering a surge during power-up. DUTY CYCLING FOR LOW POWER For many applications, improved performance at low data rates may not be required. For these applications, the ADS1118 supports duty cycling that can yield significant power savings by periodically requesting high data rate readings at an effectively lower data rate. For example, an ADS1118 in power-down mode with a data rate set to 860SPS could be operated by a microcontroller that instructs a single-shot conversion every 125ms (8SPS). Because a conversion at 860SPS only requires about 1.2ms, the ADS1118 enters power-down mode for the remaining 123.8ms. In this configuration, the ADS1118 consumes about 1/100th the power of the ADS1118 operated in continuous conversion mode. The rate of duty cycling is completely arbitrary and is defined by the master controller. SERIAL INTERFACE The SPI-compatible serial interface consists of either four signals: CS, SCLK, DIN, and DOUT/DRDY; or three signals, in which case CS may be tied low. The interface is used to read conversion data, read and write registers, and control the ADS1118 operation. CHIP SELECT (CS) The chip select (CS) selects the ADS1118 for SPI communication. This feature is useful when multiple devices share the serial bus. CS must remain low for the duration of the serial communication. When CS is taken high, the serial interface is reset, SCLK is ignored, and DOUT/DRDY enters a high-impedance state; as such, DOUT/DRDY cannot provide indication of data ready. In situations where multiple devices are present and DOUT/DRDY must be monitored; by periodically lowering CS, the DOUT/DRDY pin either immediately goes high to indicate that no new data are available, or it immediately goes low, to indicate that new data are present in the Config Register and are available for transfer. New data can be transferred at anytime without concern of data corruption. When a transmission starts, the current result is locked into the output shift register and does not change until the communication is completed. This system avoids any possibility of data corruption. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 19 ADS1118 SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 www.ti.com SERIAL CLOCK (SCLK) The serial clock (SCLK) features a Schmitt-triggered input and is used to clock data on the DIN and DOUT/DRDY pins into and out of the ADS1118. Even though the input has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. If SCLK is held low for 28ms, the serial interface resets and the next SCLK pulse starts a new communication cycle. This timeout feature can be used to recover communication when a serial interface transmission is interrupted. When the serial interface is idle, hold SCLK low. DATA INPUT (DIN) The data input pin (DIN) is used along with SCLK to send data to the ADS1118 (op code commands and register data). The device latches data on DIN on the falling edge of SCLK. The ADS1118 never drives the DIN pin. DATA OUTPUT AND DATA READY (DOUT/DRDY) The data output and data ready pin (DOUT/DRDY) are used with SCLK to read conversion and register data from the ADS1118. In Read Data Continuous mode, DOUT/DRDY goes low when conversion data are ready and goes high 8µs before the data ready signal. Data on DOUT/DRDY are shifted out on the rising edge of SCLK. By default DOUT/DRDY goes to a high-impedance state when CS is high. Alternatively, the ADS1118 DOUT/DRDY pin can be configured as a weak pull-up if CS is high. This feature is intended to reduce the risk of DOUT/DRDY floating near midsupply and causing leakage current in the master. If the ADS1118 does not share the serial bus with another device, CS may be tied low. POWER-DOWN MODE When the PWDN bit in the Config Register is set to '1', the ADS1118 enters a lower power standby state. This condition is also the default state the ADS1118 enters when power is first supplied. In this mode, the ADS1118 uses no more than 2μA of current. During this time, the device responds to commands, but does not perform any data conversion. To exit this mode, simply write a '0' to the PWDN bit in the Config Register. 20 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 REGISTERS The ADS1118 has two registers that are accessible via the SPI port. The Conversion Register contains the result of the last conversion. The Config Register allows the modification of the ADS1118 operating modes and the ability to query the status of the device. Conversion Register This 16-bit register contains the result of the last conversion in binary twos complement format. Following powerup, the Conversion Register is cleared to '0', and remains '0' until the first conversion is completed. The register format is shown in Table 5. Table 5. Conversion Register (Read-Only) BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Config Register The 16-bit register can be used to control the ADS1118 operating mode, input selection, data rate, PGA settings, and comparator modes. The register format is shown in Table 6. Table 6. Config Register (Read/Write) BIT 15 14 13 12 NAME OS MUX2 MUX1 MUX0 11 10 9 8 PGA2 PGA1 PGA0 MODE blank BIT 7 6 5 4 3 2 1 0 NAME DR2 DR1 DR0 TS_MODE PULL_UP_ EN NOP1 NOP2 CNV_RDY_FL Default = 8583h. Bit 15 OS: Operational status/single-shot conversion start This bit determines the operational status of the device. This bit can only be written when in power-down mode. For a write status: 0 : No effect 1 : Begin a single conversion (when in power-down mode) For a read status: 0 : Device is currently performing a conversion 1 : Device is not currently performing a conversion Bits[14:12] MUX[2:0]: Input multiplexer configuration These bits configure the input multiplexer. No effect when in temperature sensor mode. 000 : AINP = AIN0 and AINN = AIN1 (default) 001 : AINP = AIN0 and AINN = AIN3 010 : AINP = AIN1 and AINN = AIN3 011 : AINP = AIN2 and AINN = AIN3 Bits[11:9] 100 : AINP = AIN0 and AINN = GND 101 : AINP = AIN1 and AINN = GND 110 : AINP = AIN2 and AINN = GND 111 : AINP = AIN3 and AINN = GND PGA[2:0]: Programmable gain amplifier configuration These bits configure the programmable gain amplifier. No effect when in temperature sensor mode. 000 : FS = ±6.144V (1) 001 : FS = ±4.096V (1) 010 : FS = ±2.048V (default) 011 : FS = ±1.024V Bit 8 100 : FS = ±0.512V 101 : FS = ±0.256V 110 : FS = ±0.256V 111 : FS = ±0.256V MODE: Device operating mode This bit controls the current operational mode of the ADS1118. 0 : Continuous conversion mode 1 : Power-down single-shot mode (default) (1) This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3V be applied to this device. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 21 ADS1118 SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 Bits[7:5] www.ti.com DR[2:0]: Data rate These bits control the data rate setting. 000 : 8SPS 001 : 16SPS 010 : 32SPS 011 : 64SPS Bit 4 100 : 128SPS (default) 101 : 250SPS 110 : 475SPS 111 : 860SPS TS_MODE: Temperature sensor mode This bit configures the ADC to convert temperature or input signals. 0 : ADC mode (default) 1 : Temperature sensor mode Bit 3 PULL_UP_EN: Pull-up enable This bit enables a weak pull-up resistor on the DOUT pin when CS is high. When enabled, a 400kΩ resistor connects the bus line to supply when CS is high. When disabled, the DOUT pin floats when CS is high. 0 : Pull-up resistor disabled on DOUT pin (default) 1 : Pull-up resistor enabled on DOUT pin Bits[2:0] NOP: No operation The NOP bits control whether data are written to the Config Register or not. In order for data to be written to the Config Register, the NOP bits must be written as '01'. Any other value written to the NOP bits results in a NOP command. This means that DIN can be held high or low during SCLK pulses without data being written to the Config Register. 00 : Invalid data, do not update the contents of the Config Register. 01 : Valid data, update the Config Register (default) 10 : Invalid data, do not update the contents of the Config Register. 11: Invalid data, do not update the contents of the Config Register. Bit 0 CNV_RDY_FL: Conversion ready flag This bit is active low and indicates when data are ready from the converter. When it is high, a conversion is not yet ready and is in process. The purpose of the conversion ready flag bit is to return the DOUT pin line to a high state to prepare for the falling edge from new data. 0 : Data ready, no conversion in progress 1 : Data not ready, conversion in progress (default) 22 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 DATA RETRIEVAL Data may be read in one of two modes: Single-Shot and Continuous Conversion mode. The mode is selected by writing to the OS bit in the Config Register. Continuous Conversion Mode In Continuous Conversion mode, the conversion data are read from the device without an op code command. When DOUT/DRDY asserts low (indicating that new conversion data are ready), the conversion data are read by shifting the data out on DOUT. The MSB of the data (bit 15) on DOUT/DRDY is clocked out on the first rising edge of SCLK. As shown in Figure 43, the data consist of two bytes for the conversion result and an additional two bytes for the Config Register readback. The data read operation must be completed 16/fCLK cycles before DOUT asserts again. (1) CS 1 9 17 25 SCLK DOUT Hi-Z DIN DATA MSB DATA LSB CONFIG MSB CONFIG LSB CONFIG MSB CONFIG LSB CONFIG MSB CONFIG LSB Next Data Ready (1) CS may be held low. If CS is low, DOUT/DRDY asserts low indicating new data. Figure 43. Continuous Conversion Mode Timing One-Shot Mode In One-Shot mode, the conversion data are buffered, holding the current data until new conversion data replace it. The conversion data are read by writing a '1' to the OS bit, followed by shifting the conversion data out. The data consist of two bytes for the conversion result and two bytes for the Config Register; see Figure 44. In contrast to the Continuous Conversion mode, DOUT does not assert low in one-shot mode. (1) CS 1 9 17 25 tUPDATE SCLK DOUT DIN Hi-Z Data Ready DATA MSB DATA LSB CONFIG MSB CONFIG LSB CONFIG MSB CONFIG LSB CONFIG MSB CONFIG LSB Next Data Ready (1) CS may be held low. If CS is low, DOUT/DRDY asserts low indicating new data. Figure 44. One-Shot Mode Timing Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 23 ADS1118 SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 www.ti.com APPLICATION INFORMATION The following sections give example circuits and suggestions for using the ADS1118 in various situations. BASIC CONNECTIONS AND LAYOUT CONSIDERATIONS For many applications, connecting the ADS1118 is simple. A basic connection diagram for the ADS1118 is shown in Figure 45. Most microcontroller SPI peripherals can operate with the ADS1118. The interface operates in SPI mode 1 where CPOL = 0 and CPHA = 1. In SPI mode 1, SCLK idles low and data launch or are changed only on rising edges of SCLK and data are latched or read by the master and slave on falling edges of SCLK. Details of the SPI communication protocol employed by the ADS1118 can be found in the SPI Timing Characteristics section. Although it is not required, it is a good practice to place 49.9Ω resistors in series with all of the digital pins. This resistance smooths sharp transitions, suppresses overshoot, and offers some overvoltage protection. Device 10 VDD DIN Microcontroller or Microprocessor with SPI Port 1 SCLK DOUT/DRDY 9 2 CS VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 0.1mF (typ) AIN1 5 DOUT DIN Inputs Selected from Configuration Register CS SCLK Figure 45. Typical Connections of the ADS1118 The fully differential voltage input of the ADS1118 is ideal for connection to differential sources with moderately low source impedance, such as thermocouples and thermistors. Although the ADS1118 can read bipolar differential signals, it cannot accept negative voltages on either input because every pin on the ADS1118 employs the use of ESD protection diodes. In the event that an input exceeds supply or drops below ground, these diodes begin to turn on. Therefore, it may be helpful to think of the ADS1118 positive voltage input as noninverting, and of the negative input as inverting. When the ADS1118 is converting data, it draws current in short spikes. The 0.1μF bypass capacitor supplies the momentary bursts of extra current needed from the supply. This bypass capacitor should be placed as close to the device as possible. For very sensitive systems, or systems in harsh noise environments, avoiding the use of vias for connecting the bypass capacitor may offer superior bypass and noise immunity. 24 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 It is recommended to employ best design practices when laying out a printed circuit board (PCB) for both analog and digital components. This recommendation generally means that the layout should separate analog components [such as ADCs, op amps, references, digital-to-analog converters (DACs), and analog MUXs] from digital components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio frequency (RF) tranceivers, universal serial bus (USB) tranceivers, and switching regulators]. An example of good component placement is shown in Figure 46. While Figure 46 provides a good example of component placement, the best placement for each application is unique to the geometries, components, and PCB fabrication capabilities being employed. That is, there is no single layout that is perfect for every design and careful consideration must always be used when designing with any analog components. ADS1118 Ground fill or Ground plane Supply Generation Interface Tranceiver Microprocessor Optional: Split Ground Cut Signal Conditioning (RC filters and amplifiers) Ground fill or Ground plane Optional: Split Ground Cut Ground fill or Ground plane Connector or Antenna Ground fill or Ground plane Figure 46. System Component Placement The usage of split analog and digital ground planes is not necessary for improved noise performance (although for thermal isolation it is a worthwhile consideration). However, the use of a solid ground plane or ground fill in PCB areas with no components is essential for optimum performance. If the system being used employs a split digital and analog ground plane, it is generally recommended that the ground planes be connected as close to the ADS1118 as possible. It is also strongly recommended that digital components, especially RF portions, be kept as far as practically possible from analog circuitry in a given system. Additionally, minimize the distance that digital control traces run through analog areas and avoid allowing these traces to be near sensitive analog components. Digital return currents usually flow through a ground path that is as close to the digital path as possible. If a solid ground connection to a plane is not available, these currents may find paths back to the source that interfere with analog performance. The implications that layout has on the temperature sensing functions are much more significant than they are for the ADC functions. Details on layout considerations for the temperature sensor can be found in the Thermocouple Measurement with Cold Junction Compensation section. For a detailed layout example, refer to the ADS1118EVM User's Guide (SBAU184). Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 25 ADS1118 SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 www.ti.com CONNECTING MULTIPLE DEVICES Connecting multiple ADS1118s to a single bus is simple. Using a dedicated chip-select (CS) for each SPI enabled device, SCLK, DIN, and DOUT/DRDY can be safely shared. By default, when CS goes high for the ADS1118, DOUT/DRDY enters a 3-state mode. If the PULL_UP_EN bit is enabled, the DOUT/DRDY pin is pulled up to the supply of the ADS1118 by a weak 400kΩ resistor. This feature is intended to prevent DOUT/DRDY from floating near mid-rail and causing excess current leakage on a microcontroller input. The ADS1118 cannot issue a data ready pulse on DOUT/DRDY when CS is high. In order to evaluate when a new conversion is ready from the ADS1118 when using multiple devices, the master can periodically drop CS to the ADS1118. When CS lowers, the DOUT/DRDY pin immediately drives either high or low. If the DOUT/DRDY line drives low on a low CS, new data are currently available for clocking out at any time. If the DOUT/DRDY line drives high, no new data are available and the ADS1118 returns the last read conversion result. Valid data can be retrieved from the ADS1118 at anytime without concern of data corruption. When SCLK rises, the current result is locked into DOUT/DRDY the output shift register. If a new conversion becomes available during data transmission, it is not avialable for readback until a new SPI transmission is initiated. Microcontroller or Microprocessor ADS1118 SCLK DIN 10 DIN 1 SCLK DOUT/DRDY 9 2 CS VDD 8 DOUT 3 GND AIN3 7 CS1 4 AIN0 AIN2 6 AIN1 5 CS2 ADS1118 10 DIN 1 SCLK DOUT/DRDY 9 2 CS VDD 8 3 GND AIN3 7 AIN2 6 4 AIN0 AIN1 5 NOTE: Power and input connections omitted for clarity. Figure 47. Connecting Multiple ADS1118s 26 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 USING GPIO PORTS FOR COMMUNICATION Most microcontrollers have programmable input/output (I/O) pins that can be set in software to act as inputs or outputs. If an SPI controller is not available, the ADS1118 can be connected to GPIO pins and the SPI bus protocol can be simulated. Using GPIO pins to generate the SPI interface only requires that the pins be configured as push/pull inputs or outputs. Furthermore, if the SCLK line is held low for more than 28ms, the communication times out. This condition means that the GPIO ports must be capable of providing SCLK pulses with no more than 28ms between pulses. SINGLE-ENDED INPUTS Although the ADS1118 has two differential inputs, the device can easily measure four single-ended signals. Figure 48 shows a single-ended connection scheme. The ADS1118 is configured for single-ended measurement by configuring the MUX to measure each channel with respect to ground. Data are then read out of one input based on the selection in the Config Register. The single-ended signal can range from 0V to supply. The ADS1118 loses no linearity anywhere within the input range. Negative voltages cannot be applied to this circuit because the ADS1118 can only accept positive voltages. The ADS1118 input range is bipolar differential. The single-ended circuit shown in Figure 48 covers only half the ADS1118 input scale because it does not produce differentially negative inputs; therefore, one bit of resolution is lost. For optimal noise performance, it is recommended to use differential configurations whenever possible. Differential configurations maximize the dynamic range of the ADC and provide strong attenuation of commonmode noise. VDD Device 10 DIN 1 SCLK DOUT/DRDY 9 2 CS VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 0.1mF (typ) AIN1 5 Inputs Selected from Configuration Register NOTE: Digital pin connections omitted for clarity. Figure 48. Measuring Single-Ended Inputs The ADS1118 is also designed to allow AIN3 to serve as a common point for measurements by adjusting the MUX configuration. AIN0, AIN1, and AIN2 can all be measured with respect to AIN3. In this configuration the ADS1118 can operate with inputs where AIN3 serves as the common point. This ability improves the usable range over the single-ended configuration because it allows negative voltages; however, it does not offer attenuation of common-mode noise. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 27 ADS1118 SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 www.ti.com THERMOCOUPLE MEASUREMENT WITH COLD JUNCTION COMPENSATION For an independent, two-channel thermocouple system, Figure 49 shows the basic connections. This circuit contains a simple low-pass, anti-aliasing filter, mid-point bias, and open detection. While the digital filter of the ADS1118 strongly attenuates high-frequency components of noise, it is generally recommended to provide a first-order passive RC filter to further improve this performance. The differential RC filter formed by the 500Ω resistors (RDIFFA and RDIFFB) and the 1µF (CDIFF) capacitor offers a cutoff frequency of approximately 320Hz. Additional filtering can be achieved by increasing the differential capacitor or the resistance values. However, avoid increasing the filter resistance beyond 1kΩ because the effects of the interaction with ADCs input impedance begin to affect the linearity and gain error of the ADS1118. Because of the high sampling rates supported by the ADS1118, simple post digital filtering in a microcontroller can alleviate the requirements of the analog filter and can also offer the flexibility to implement filter notches at 50Hz or 60Hz. Two 0.1µF (CCMA and CCMB) capacitors are also added to offer attenuation of high-frequency common-mode noise components. Because mismatches in the common-mode capacitors cause differential noise, it is recommended that the differential capacitor be at least an order of magnitude (10x) larger than the common-mode capacitors. 3.3V 0.1 F GND 3.3V RPU = 1Mȍ GND CCMA = 0.1 F 500ȍ AIN0 VDD RDIFFA CDIFF = 1 F AIN1 RDIFFB RPD = 1Mȍ 500ȍ (PGA Gain = 16) ±256mV FS CCMB = 0.1 F Voltage Reference SCLK GND GND PGA GND 3.3V RPU = 1Mȍ MUX Digital Filter and Interface 16-bit Ȉǻ ADC DIN CCMA = 0.1 F 500ȍ CS DOUT/DRDY AIN2 RDIFFA CDIFF = 1 F RPD = 1Mȍ GND Oscillator AIN3 RDIFFB 500ȍ Temp Sensor GND CCMB = 0.1 F GND GND Figure 49. Two-Channel Thermocouple System 28 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 The two 1MΩ resistors (RPU and RPD) serve two purposes. The first purpose is to offer a common-mode bias near midsupply. While the ADS1118 does offer the ability to float the common-mode of a signal or connect any of the inputs to a common point such as ground or supply, it is generally recommended to avoid such situations. Connecting one of the inputs to a common point decreases performance by converting common-mode noise into differential signal noise that is not strongly attenuated. The second purpose of the 1MΩ resistors is to offer a weak pull-up and pull-down for sensor open detection. In the event that a sensor is disconnected, the inputs to the ADC extend to supply and ground and yield a full-scale readout, indicating a sensor disconnection. The procedure to actually achieve cold junction compensation is simple and can be done in several ways. One way is to interleave readings between the thermocouple inputs and the temperature sensor. That is, acquire one on-chip temperature result for every thermocouple ADC voltage measured. If the cold junction is in a very stable environment, more periodic cold junction measurements may be sufficient. These operations yield two results for every thermocouple measurement and cold junction measurement cycle: the thermocouple voltage or VTC and the on-chip temperature or TCJC. In order to account for the cold junction, the temperature sensor within the ADS1118 must first be converted to a voltage proportional to the thermocouple currently being used yielding VCJC. This conversion is generally accomplished by performing a reverse lookup on the table being used for the thermocouple voltage to temperature conversion. Then, adding the two voltages yields the thermocouple compensated voltage VActual where VCJC + VTC = VActual. VActual is then converted to temperature using the same lookup table from before, yielding TActual. Thermocouple manufacturers usually supply a lookup table with their thermocouples that offer excellent accuracy for linearization of a specific type of thermocouple. The granularity on these lookup tables is generally very precise (at around 1°C for each lookup value). To save microcontroller memory and development time, an interpolation technique applied to these values can be used. By choosing 16 to 32 equally-spaced values from the manufacturer's lookup tables over a desired temperature range, using a simple linear approximation of intervals between is generally very precise. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 29 ADS1118 SBAS457B – OCTOBER 2010 – REVISED AUGUST 2012 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (July 2011) to Revision B Page • Added (MSOP) to titles of Figure 26 to Figure 31 .............................................................................................................. 11 • Added Figure 32 to Figure 37 ............................................................................................................................................. 12 30 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: ADS1118 PACKAGE OPTION ADDENDUM www.ti.com 17-Sep-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ADS1118IDGSR ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1118IDGST ACTIVE MSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1118IRUGR ACTIVE X2QFN RUG 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS1118IRUGT ACTIVE X2QFN RUG 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1118IDGSR MSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 ADS1118IDGST MSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1118IDGSR MSOP DGS 10 2500 370.0 355.0 55.0 ADS1118IDGST MSOP DGS 10 250 195.0 200.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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