Intersil ISL62884CHRTZ Single-phase pwm regulator for imvp-6â ¢ mobile cpus Datasheet

ISL62884C
Features
The ISL62884C is a single-phase PWM buck regulator for
miroprocessor core power supply. It uses an integrated
gate drivers to provide a complete solution. The PWM
modulator of ISL62884C is based on Intersil's Robust
Ripple Regulator (R3™) technology. Compared with
traditional modulators, the R3™ modulator commands
variable switching frequency during load transients,
achieving faster transient response. With the same
modulator, the switching frequency is reduced at light
load, increasing the regulator efficiency.
• Precision Core Voltage Regulation
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
The ISL62884C is fully compliant with IMVP-6™
specifications. It responds to DPRSLPVR signals by
entering/exiting diode emulation mode. It reports the
regulator output current through the IMON pin. It senses
the current by using either discrete resistor or inductor
DCR whose variation over-temperature can be thermally
compensated by a single NTC thermistor. It uses
differential remote voltage sensing to accurately regulate
the processor die voltage. The adaptive body diode
conduction time reduction function minimizes the body
diode conduction loss in diode emulation mode.
User-selectable overshoot reduction function offers an
option to aggressively reduce the output capacitors as
well as the option to disable it for users concerned about
increased system thermal stress.
• Voltage Identification Input
- 7-Bit VID Input, 0V to 1.500V in 12.5mV Steps
- Supports VID Changes On-The-Fly
• Supports Multiple Current Sensing Methods
- Lossless Inductor DCR Current Sensing
- Precision Resistor Current Sensing
• Superior Noise Immunity and Transient Response
• Current Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Integrated Gate Driver
• Adaptive Body Diode Conduction Time Reduction
• User-selectable Overshoot Reduction Function
• Small Footprint 28 Ld 4x4 TQFN Package
• Pb-Free (RoHS Compliant)
Applications*(see page 29)
• Notebook Core Voltage Regulator
• Notebook GPU Voltage Regulator
Related Literature*(see page 29)
• See AN1545 for Evaluation Board Application Note
“ISL62884CEVAL2Z Evaluation User Guide”
Load Line Regulation
0.91
VIN = 19V
0.90
0.89
VOUT (V)
0.88
0.87
0.86
0.85
0.84
0.83
VIN = 12V
0.82
VIN = 8V
0.81
0.80
0
March 16, 2010
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1
2
4
6
8
10 12 14
IOUT (A)
16
18
20
22
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL62884C
Single-Phase PWM Regulator for IMVP-6™ Mobile
CPUs
ISL62884C
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL62884CHRTZ
62884C HRTZ
-10 to +100
28 Ld 4x4 TQFN
L28.4x4
ISL62884CIRTZ
62884C IRTZ
-40 to +100
28 Ld 4x4 TQFN
L28.4x4
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62884C. For more information on MSL please
see techbrief TB363.
Pin Configuration
VID2
VID3
VID4
VID5
VID6
DPRSLPVR
VR_ON
ISL62884C
(28 LD TQFN)
TOP VIEW
28 27 26 25 24 23 22
CLK_EN# 1
21 VID1
PGOOD 2
20 VID0
19 VCCP
RBIAS 3
VW
PD
(BOTTOM)
4
18 LGATE
17 VSSP
COMP 5
FB
2
VSEN 7
15 UGATE
BOOT
DPRSTP#
VIN
10 11 12 13 14
VDD
9
ISUM+
8
RTN
16 PHASE
ISUM-
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Pin Function Description
PIN
NUMBER
SYMBOL
DESCRIPTION
1
CLK_EN#
Open drain output to enable system PLL clock. It goes low 13 switching cycles after VCORE is within
10% of VBOOT.
2
PGOOD
Power-Good open-drain output indicating when the regulator is able to supply regulated voltage.
Pull-up externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
3
RBIAS
A resistor to GND sets internal current reference. A 147kΩ resistor sets the controller for CPU core
application and a 47kΩ resistor sets the controller for GPU core application.
4
VW
5
COMP
6
FB
7
VSEN
8
RTN
9, 10
ISUM- and
ISUM+
11
VDD
5V bias power.
12
VIN
Power stage supply voltage, used for feed-forward.
13
DPRSTP#
A mode signal from the CPU. Combined with the DPRSLPVR signal, it determines the operational
mode of the controller.
14
BOOT
Connect an MLCC capacitor across the BOOT and the PHASE pin. The boot capacitor is charged
through an internal boot diode connected from the VCCP pin to the BOOT pin, each time the PHASE
pin drops below VCCP minus the voltage dropped across the internal boot diode.
15
UGATE
Output of the high-side MOSFET gate driver. Connect the UGATE pin to the gate of the high-side
MOSFET.
16
PHASE
Current return path for the high-side MOSFET gate driver. Connect the PHASE pin to the node
consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor.
17
VSSP
Current return path for the low-side MOSFET gate driver. Connect the VSSP pin to the source of the
low-side MOSFET through a low impedance path, preferably in parallel with the traces connecting
the LGATE pins to the gates of the low-side MOSFET.
18
LGATE
Output of the low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of the Phase-1
low-side MOSFET.
19
VCCP
Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at
least 1µF of an MLCC capacitor to the VSSP pin.
20 thru 26
VID0 thru
VID6
27
VR_ON
28
DPRSLPVR
Deeper sleep enable signal. A high level logic signal on this pin indicates that the microprocessor
is in deeper sleep mode. It also programs the output voltage slew rate at 10mV/µs for
DPRSLPVR = 0 and 2.5mV/µs for DPRSLPVR = 1.
Pad
PD
The bottom pad is electrically connected to the GND pin inside the IC. It should also be used as the
thermal pad for heat removal.
A resistor from this pin to COMP programs the switching frequency (8kΩ gives approximately
300kHz).
This pin is the output of the error amplifier. Also, a resistor across this pin and GND adjusts the
overcurrent threshold.
This pin is the inverting input of the error amplifier.
Remote core voltage sense input. Connect to microprocessor die.
Remote voltage sensing return. Connect to ground at microprocessor die.
Droop current sense input.
VID input with VID0 = LSB and VID6 = MSB.
Voltage regulator enable input. A high level logic signal on this pin enables the regulator.
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Block Diagram
VIN VSEN
VDD
PGOOD CLK_EN#
VR_ON
PGOOD AND
CLK_EN#
LOGIC
MODE
CONTROL
DPRSTP#
DPRSLPVR
RBIAS
PROTECTION
FLT
VID0
VID1
WOC OC
VIN
VID2
DAC
AND
SOFTSTART
VID3
CLOCK
VDAC
COMP
VID4
VW
VID5
VID6
+
RTN
Σ
+
+
BOOT
E/A
VIN
COMP
PWM CONTROL LOGIC
-
FB
VDAC
MODULATOR
VW
IDROOP
+
-
+
ISUM-
-
CURRENT
SENSE
COMP
CURRENT
COMPARATORS
2.5X
ISUM+
WOC
+
-
60µA
UGATE
PHASE
SHOOT-THROUGH
PROTECTION
VCCP
DRIVER
LGATE
VSSP
OC
+
4
DRIVER
Σ
+
ADJ. OCP
THRESHOLD
COMP
GND
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Table of Contents
Ordering Information ......................................................................................................................... 2
Pin Configuration ................................................................................................................................ 2
Pin Function Description ..................................................................................................................... 3
Block Diagram .................................................................................................................................... 4
Absolute Maximum Ratings ................................................................................................................ 6
Thermal Information .......................................................................................................................... 6
Recommended Operating Conditions .................................................................................................. 6
Electrical Specifiactions ...................................................................................................................... 6
Gate Driver Timing Diagram ............................................................................................................... 9
Simplified Application Circuits ............................................................................................................ 9
Theory of Operation .......................................................................................................................... 11
Multiphase R3™ Modulator ............................................................................................................... 11
Diode Emulation and Period Stretching ............................................................................................... 12
Start-Up Timing .............................................................................................................................. 12
Voltage Regulation and Load Line Implementation ............................................................................... 12
Differential Sensing ......................................................................................................................... 15
CCM Switching Frequency ................................................................................................................ 15
Modes of Operation ......................................................................................................................... 15
Dynamic Operation .......................................................................................................................... 15
Protections ..................................................................................................................................... 15
Adaptive Body Diode Conduction Time Reduction ................................................................................. 16
Overshoot Reduction Function ........................................................................................................... 16
Key Component Selection ................................................................................................................. 17
RBIAS ............................................................................................................................................
Inductor DCR Current-Sensing Network ..............................................................................................
Resistor Current-Sensing Network .....................................................................................................
Overcurrent Protection .....................................................................................................................
Load Line Slope ..............................................................................................................................
Compensator ..................................................................................................................................
Optional Slew Rate Compensation Circuit For 1-Tick VID Transition ........................................................
17
17
19
19
20
20
21
Layout Guidelines ............................................................................................................................. 22
Reference Design Bill of Materials .................................................................................................... 25
Typical Performance ......................................................................................................................... 26
Revision History ............................................................................................................................... 29
Products ........................................................................................................................................... 29
Package Outline Drawing ................................................................................................................. 30
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Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . .-0.3V to +7V
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . +28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE) . . . . -0.3V to +7V(DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns)
Phase Voltage (PHASE) . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . PHASE-0.3V (DC) to BOOT
. . . . . . . . . PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT
LGATE, LGATEa and LGATEb Voltage
. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V (DC) to VDD+0.3V
LGATEa and LGATEb
. . . . . . . . . -2.5V (<20ns Pulse Width, 2.5µJ) to VDD+0.3V
LGATE
. . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD + 0.3V
All Other Pins. . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Open Drain Outputs, PGOOD, VR_TT#, CLK_EN#
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7V
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . 200V
Latch Up (per JESD-78B; Class 2, Level B, Note 6) . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
28 Ld TQFN Package (Notes 4, 5) . .
42
5
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD .
Battery Voltage, VIN .
Ambient Temperature
ISL62884CHRTZ. . .
ISL62884CIRTZ . . .
Junction Temperature
ISL62884CHRTZ. . .
ISL62884CIRTZ . . .
. . . . . . . . . . . . . . . . . . . . +5V ±5%
. . . . . . . . . . . . . . . . . . +4.5V to 25V
. . . . . . . . . . . . . . . -10°C to +100°C
. . . . . . . . . . . . . . . -40°C to +100°C
. . . . . . . . . . . . . . . -10°C to +125°C
. . . . . . . . . . . . . . . -40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. Jedec Class II pulse conditions and failure criterion uses. Level B exception is using a minimum negative pulse of -1.2V on the
DPRSLPVR pin (#28).
Electrical Specifications
PARAMETER
Operating Conditions: VDD = 5V, TA = -40°C to +100°C, fSW = 300kHz, unless otherwise
noted. Boldface limits apply over the operating temperature range, -40°C to
+100°C.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
3.2
4.0
mA
INPUT POWER SUPPLY
+5V Supply Current
IVDD
VR_ON = 0V
1
µA
Battery Supply Current
IVIN
VR_ON = 0V
1
µA
VIN Input Resistance
RVIN
VR_ON = 1V
900
Power-On-Reset Threshold
PORr
VDD rising
4.35
PORf
VDD falling
VR_ON = 1V
4.00
kΩ
4.5
4.15
V
V
SYSTEM AND REFERENCES
ISL62884CHRTZ System
Accuracy
ISL62884CIRTZ System
Accuracy
%Error (VCC_CORE) No load; closed loop, active mode range
VID = 0.75V to 1.50V
-0.5
+0.5
%
VID = 0.5V to 0.7375V
-8
+8
mV
VID = 0.3V to 0.4875V
-15
+15
mV
-0.8
+0.8
%
VID = 0.5V to 0.7375V
-10
+10
mV
VID = 0.3V to 0.4875V
-18
+18
mV
1.2
1.206
V
1.2
1.2096
V
%Error (VCC_CORE) No load; closed loop, active mode range
VID = 0.75V to 1.50V
Boot Supply Voltage
Maximum Output Voltage
6
VBOOT
ISL62884CHRTZ
1.194
ISL62884CIRTZ
1.1904
VCC_CORE(max)
VID = [0000000]
1.500
V
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Electrical Specifications
PARAMETER
Operating Conditions: VDD = 5V, TA = -40°C to +100°C, fSW = 300kHz, unless otherwise
noted. Boldface limits apply over the operating temperature range, -40°C to
+100°C. (Continued)
SYMBOL
Minimum Output Voltage
(Note 7)
VCC_CORE(min)
RBIAS Voltage
TEST CONDITIONS
MIN
VID = [1111111]
RBIAS = 147kΩ
TYP
MAX
0
1.45
1.47
295
310
UNITS
V
1.49
V
CHANNEL FREQUENCY
Nominal Channel Frequency
fSW(nom)
RFSET = 7kΩ, VCOMP = 1V
Adjustment Range
325
kHz
200
500
kHz
-0.15
+0.15
mV
AMPLIFIERS
Current-Sense Amplifier
Input Offset
IFB = 0A
Error Amp DC Gain (Note 7)
Av0
Error Amp Gain-Bandwidth
Product (Note 7)
GBW
CL = 20pF
90
dB
18
MHz
POWER GOOD AND PROTECTION MONITORS
VOL
IPGOOD = 4mA
PGOOD Leakage Current
IOH
PGOOD = 3.3V
PGOOD Delay
tpgd
CLK_ENABLE# LOW to PGOOD HIGH
PGOOD Low Voltage
0.26
0.4
1
µA
7.6
8.9
ms
1.0
1.5
Ω
-1
6.3
V
UGATE DRIVER
UGATE Pull-Up Resistance
(Note 7)
RUGPU
200mA Source Current
UGATE Source Current
(Note 7)
IUGSRC
BOOT - UGATE = 2.5V
UGATE Sink Resistance
(Note 7)
RUGPD
250mA Sink Current
UGATE Sink Current (Note 7)
IUGSNK
UGATE - PHASE = 2.5V
LGATE Pull-Up Resistance
(Note 7)
RLGPU
250mA Source Current
LGATE Source Current
(Note 7)
ILGSRC
VCCP - LGATE = 2.5V
LGATE Sink Resistance
(Note 7)
RLGPD
250mA Sink Current
LGATE Sink Current (Note 7)
ILGSNK
LGATE - VSSP = 2.5V
4.0
A
UGATE to LGATE Deadtime
tUGFLGR
UGATE falling to LGATE rising, no load
23
ns
LGATE to UGATE Deadtime
tLGFUGR
LGATE falling to UGATE rising, no load
28
ns
0.58
V
0.2
µA
2.0
1.0
A
1.5
2.0
Ω
A
LGATE DRIVER
1.0
1.5
2.0
0.5
Ω
A
0.9
Ω
BOOTSTRAP DIODE
Forward Voltage
VF
PVCC = 5V, IF = 2mA
Reverse Leakage
IR
VR = 25V
PROTECTION
Overvoltage Threshold
OVH
Severe Overvoltage
Threshold
OVHS
OC Threshold Offset
Undervoltage Threshold
UVf
VSEN rising above setpoint for >1ms
VSEN rising for >2µs
150
200
240
mV
1.675
1.7
1.725
V
ISUM- pin current, RCOMP open circuit
28
30
32
µA
VSEN falling below setpoint for >1.2ms
-355
-295
-235
mV
0.3
V
LOGIC THRESHOLDS
VR_ON Input Low
VIL(1.0V)
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Electrical Specifications
PARAMETER
Operating Conditions: VDD = 5V, TA = -40°C to +100°C, fSW = 300kHz, unless otherwise
noted. Boldface limits apply over the operating temperature range, -40°C to
+100°C. (Continued)
SYMBOL
VR_ON Input High
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VIH(1.0V)
ISL62884CHRTZ
0.7
V
VIH(1.0V)
ISL62884CIRTZ
0.75
V
VID0-VID6 and DPRSTP#
Input Low
VIL(1.0V)
VID0-VID6 and DPRSTP#
Input High
VIH(1.0V)
DPRSLPVR Input Low
VIL(3.3V)
DPRSLPVR Input High
VIH(3.3V)
0.3
0.7
V
V
1
V
2.3
V
CLK_EN# OUTPUT LEVELS
CLK_EN# Low Output
Voltage
VOL
I = 4mA
CLK_EN# Leakage Current
IOH
CLK_EN# = 3.3V
-1
VR_ON = 0V
-1
0
-1
0
0.26
0.4
V
1
µA
INPUTS
VR_ON Leakage Current
IVR_ON
VR_ON = 1V
VIDx Leakage Current
IVIDx
VIDx = 0V
0
VIDx = 1V
DPRSLPVR Leakage Current
IDPRSLPVR
DPRSLPVR = 0V
0.45
-1
DPRSLPVR = 3.3V
DPRSTP# Leakage Current
IDPRSTP#
DPRSTP# = 0V
-1
1
µA
µA
1
µA
1.2
µA
1
µA
0
0.9
DPRSTP# = 1V
µA
µA
0
0.45
µA
SLEW RATE
Slew Rate (For VID Change)
SR
10
mV/µs
NOTES:
7. Limits established by characterization and are not production tested.
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Gate Driver Timing Diagram
PWM
tLGFUGR
tFU
tRU
1V
UGATE
1V
LGATE
tFL
tRL
tUGFLGR
Simplified Application Circuits
V+5
R B IA S
V+5
V IN
VDD VCCP
V IN
R B IA S
PGOOD
C LK _ E N #
V ID < 0:6 >
D P R S LP V R
D P R S TP #
V R _O N
PGOOD
C LK _ E N #
V ID S
D P R S LP V R
DPRSTP#
V R _O N
VW
ISL 6 2 8 8 4C
BOOT
RFSET
V IN
UGATE
L
PHASE
COM P
FB
LG A TE
V SS P
VO
R SUM
R DROOP
V SE N
IS U M +
V C C S EN S E
V S S S EN S E
RN
R TN
CN
°C
RI
IS U M (B O TT O M P A D )
VSS
FIGURE 1. ISL62884C TYPICAL APPLICATION CIRCUIT USING DCR SENSING
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ISL62884C
Simplified Application Circuits (Continued)
V+5
V+5
VIN
VDD VCCP VIN
R BIAS
RBIAS
PGOOD
CLK_EN#
VID<0:6>
DPRSLPVR
DPRSTP#
VR_ON
PGOOD
CLK_EN#
VIDS
DPRSLPVR
DPRSTP#
VR_ON
VW
ISL62884C
RFSET
BOOT
VIN
UGATE
L
RSEN
PHASE
COMP
FB
VO
LGATE
VSSP
R DROOP
VSEN
R SUM
ISUM+
VCC SENSE
VSS SENSE
RTN
CN
RI
ISUM(BOTTOM PAD)
VSS
FIGURE 2. ISL62884C TYPICAL APPLICATION CIRCUIT USING RESISTOR SENSING
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Theory of Operation
The ISL62884C is a single-phase regulator implementing
Intel® IMVP-6™ protocol. It uses Intersil patented
R3™(Robust Ripple Regulator™) modulator. The R3™
modulator combines the best features of fixed frequency
PWM and hysteretic PWM while eliminating many of their
shortcomings. Figure 3 conceptually shows the
ISL62884C R3™ modulator circuit, and Figure 4 shows
the operation principles.
Multiphase R3™ Modulator
MASTER CLOCK CIRCUIT
VW
MASTER
CLOCK
COMP
VCRM
CLOCK
CRM
GMVO
SLAVE CIRCUIT
VW
CLOCK
VCRS
S PWM
Q
R
PHASE
L
IL
VO
CO
GM
CRS
FIGURE 3. R3™ MODULATOR CIRCUIT
VW
H Y S T E R E T IC
W IN D O W
VCRM
COM P
C LO C K
PW M
VW
VCRS
FIGURE 4. R3™ MODULATOR OPERATION PRINCIPLES
IN STEADY STATE
A current source flows from the VW pin to the COMP pin,
creating a voltage window set by the resistor between
the two pins. This voltage window is called VW window in
the following discussion.
Inside the IC, the modulator uses the master clock circuit
to generate the clocks for the slave circuit. The
modulator discharges the ripple capacitor Crm with a
current source equal to gmVo, where gm is a gain factor.
Crm voltage Vcrm is a sawtooth waveform traversing
between the VW and COMP voltages. It resets to VW
when it hits COMP, and generates a one-shot clock
signal.
The slave circuit has its own ripple capacitor Crs, whose
voltage mimics the inductor ripple current. A gm
amplifier converts the inductor voltage into a current
source to charge and discharge Crs. The slave circuit
turns on its PWM pulse upon receiving the clock signal,
and the current source charges Crs. When Crs voltage
Vcrs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges Crs.
Since the ISL62884C works with Vcrs, which is
large-amplitude and noise-free synthesized signal, the
ISL62884C achieves lower phase jitter than conventional
hysteretic mode and fixed PWM mode controllers. Unlike
conventional hysteretic mode converters, the ISL62884C
has an error amplifier that allows the controller to
maintain a 0.5% output voltage accuracy.
Figure 5 shows the operation principles during load
insertion response. The COMP voltage rises during load
insertion, generating the clock signal more quickly, so the
PWM pulse turns on earlier, increasing the effective
switching frequency, which allows for higher control loop
bandwidth than conventional fixed frequency PWM
controllers. The VW voltage rises as the COMP voltage
rises, making the PWM pulse wider. During load release
response, the COMP voltage falls. It takes the master
clock circuit longer to generate the next clock signal so
the PWM pulse is held off until needed. The VW voltage
falls as the VW voltage falls, reducing the current PWM
pulse width. This kind of behavior gives the ISL62884C
excellent response speed.
VW
COMP
VCRM
CLOCK
PWM
VW
VCRS
FIGURE 5. R3™ MODULATOR OPERATION PRINCIPLES
IN LOAD INSERTION RESPONSE
11
FN7591.0
March 16, 2010
ISL62884C
Diode Emulation and Period Stretching
VDD
10mV/µs
VR_ON
2.5mV/µs
90%VBOOT
800µs
PHASE
VID
COMMAND
VOLTAGE
DAC
UGATE
13 SWITCHING CYCLES
LGATE
CLK_EN#
PGOOD
IL
FIGURE 6. DIODE EMULATION
ISL62884C can operate in diode emulation (DE) mode to
improve light load efficiency. In DE mode, the low-side
MOSFET conducts when the current is flowing from
source to drain and doesn’t not allow reverse current,
emulating a diode. As shown in Figure 6, when LGATE is
on, the low-side MOSFET carries current, creating
negative voltage on the phase node due to the voltage
drop across the ON-resistance. The ISL62884C monitors
the current through monitoring the phase node voltage.
It turns off LGATE when the phase node voltage reaches
zero to prevent the inductor current from reversing the
direction and creating unnecessary power loss.
If the load current is light enough, as Figure 7 shows, the
inductor current will reach and stay at zero before the
next phase node pulse, and the regulator is in
discontinuous conduction mode (DCM). If the load
current is heavy enough, the inductor current will never
reach 0A, and the regulator is in CCM although the
controller is in DE mode.
CCM/DCM BOUNDARY
VW
VCRS
IL
VW
LIGHT DCM
FIGURE 8. SOFT-START WAVEFORMS FOR CPU VR
APPLICATION
Figure 7 shows the operation principle in diode emulation
mode at light load. The load gets incrementally lighter in
the three cases from top to bottom. The PWM on-time is
determined by the VW window size, therefore is the
same, making the inductor current triangle the same in
the three cases. The ISL62884C clamps the ripple
capacitor voltage Vcrs in DE mode to make it mimic the
inductor current. It takes the COMP voltage longer to hit
Vcrs, naturally stretching the switching period. The
inductor current triangles move further apart from each
other such that the inductor current average value is
equal to the load current. The reduced switching
frequency helps increase light load efficiency.
Start-Up Timing
With the controller's VDD voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 1.1V logic high threshold.
Figure 8 shows the typical start-up timing. The
ISL62884C uses digital soft-start to ramp up DAC to the
boot voltage of 1.2V at about 2.5mV/µs. Once the output
voltage is within 10% of the boot voltage for 13 PWM
cycles (43µs for frequency = 300kHz), CLK_EN# is
pulled low and DAC slews at 10mV/µs to the voltage set
by the VID pins. PGOOD is asserted high in
approximately 7ms. Similar results occur if VR_ON is tied
to VDD, with the soft-start sequence starting 120µs after
VDD crosses the POR threshold.
Voltage Regulation and Load Line
Implementation
VCRS
IL
VW
~7ms
DEEP DCM
VCRS
After the start sequence, the ISL62884C regulates the
output voltage to the value set by the VID inputs per
Table 1. The ISL62884C will control the no-load output
voltage to an accuracy of ±0.5% over the range of
0.75V to 1.5V. A differential amplifier allows voltage
sensing for precise voltage regulation at the
microprocessor die.
IL
FIGURE 7. PERIOD STRETCHING
12
FN7591.0
March 16, 2010
ISL62884C
TABLE 1. VID TABLE (Continued)
TABLE 1. VID TABLE
VID6 VID5 VID4 VID3 VID2 VID1 VID0
VO
(V)
VID6 VID5 VID4 VID3 VID2 VID1 VID0
VO
(V)
0
0
0
0
0
0
0
1.5000
0
1
0
1
0
1
0
0.9750
0
0
0
0
0
0
1
1.4875
0
1
0
1
0
1
1
0.9625
0
0
0
0
0
1
0
1.4750
0
1
0
1
1
0
0
0.9500
0
0
0
0
0
1
1
1.4625
0
1
0
1
1
0
1
0.9375
0
0
0
0
1
0
0
1.4500
0
1
0
1
1
1
0
0.9250
0
0
0
0
1
0
1
1.4375
0
1
0
1
1
1
1
0.9125
0
0
0
0
1
1
0
1.4250
0
1
1
0
0
0
0
0.9000
0
0
0
0
1
1
1
1.4125
0
1
1
0
0
0
1
0.8875
0
0
0
1
0
0
0
1.4000
0
1
1
0
0
1
0
0.8750
0
0
0
1
0
0
1
1.3875
0
1
1
0
0
1
1
0.8625
0
0
0
1
0
1
0
1.3750
0
1
1
0
1
0
0
0.8500
0
0
0
1
0
1
1
1.3625
0
1
1
0
1
0
1
0.8375
0
0
0
1
1
0
0
1.3500
0
1
1
0
1
1
0
0.8250
0
0
0
1
1
0
1
1.3375
0
1
1
0
1
1
1
0.8125
0
0
0
1
1
1
0
1.3250
0
1
1
1
0
0
0
0.8000
0
0
0
1
1
1
1
1.3125
0
1
1
1
0
0
1
0.7875
0
0
1
0
0
0
0
1.3000
0
1
1
1
0
1
0
0.7750
0
0
1
0
0
0
1
1.2875
0
1
1
1
0
1
1
0.7625
0
0
1
0
0
1
0
1.2750
0
1
1
1
1
0
0
0.7500
0
0
1
0
0
1
1
1.2625
0
1
1
1
1
0
1
0.7375
0
0
1
0
1
0
0
1.2500
0
1
1
1
1
1
0
0.7250
0
0
1
0
1
0
1
1.2375
0
1
1
1
1
1
1
0.7125
0
0
1
0
1
1
0
1.2250
1
0
0
0
0
0
0
0.7000
0
0
1
0
1
1
1
1.2125
1
0
0
0
0
0
1
0.6875
0
0
1
1
0
0
0
1.2000
1
0
0
0
0
1
0
0.6750
0
0
1
1
0
0
1
1.1875
1
0
0
0
0
1
1
0.6625
0
0
1
1
0
1
0
1.1750
1
0
0
0
1
0
0
0.6500
0
0
1
1
0
1
1
1.1625
1
0
0
0
1
0
1
0.6375
0
0
1
1
1
0
0
1.1500
1
0
0
0
1
1
0
0.6250
0
0
1
1
1
0
1
1.1375
1
0
0
0
1
1
1
0.6125
0
0
1
1
1
1
0
1.1250
1
0
0
1
0
0
0
0.6000
0
0
1
1
1
1
1
1.1125
1
0
0
1
0
0
1
0.5875
0
1
0
0
0
0
0
1.1000
1
0
0
1
0
1
0
0.5750
0
1
0
0
0
0
1
1.0875
1
0
0
1
0
1
1
0.5625
0
1
0
0
0
1
0
1.0750
1
0
0
1
1
0
0
0.5500
0
1
0
0
0
1
1
1.0625
1
0
0
1
1
0
1
0.5375
0
1
0
0
1
0
0
1.0500
1
0
0
1
1
1
0
0.5250
0
1
0
0
1
0
1
1.0375
1
0
0
1
1
1
1
0.5125
0
1
0
0
1
1
0
1.0250
1
0
1
0
0
0
0
0.5000
0
1
0
0
1
1
1
1.0125
1
0
1
0
0
0
1
0.4875
0
1
0
1
0
0
0
1.0000
1
0
1
0
0
1
0
0.4750
0
1
0
1
0
0
1
0.9875
1
0
1
0
0
1
1
0.4625
13
FN7591.0
March 16, 2010
ISL62884C
TABLE 1. VID TABLE (Continued)
VID6 VID5 VID4 VID3 VID2 VID1 VID0
TABLE 1. VID TABLE (Continued)
VO
(V)
VO
(V)
VID6 VID5 VID4 VID3 VID2 VID1 VID0
1
0
1
0
1
0
0
0.4500
1
1
1
1
1
0
0
0.0000
1
0
1
0
1
0
1
0.4375
1
1
1
1
1
0
1
0.0000
1
0
1
0
1
1
0
0.4250
1
1
1
1
1
1
0
0.0000
1
0
1
0
1
1
1
0.4125
1
1
1
1
1
1
1
0.0000
1
0
1
1
0
0
0
0.4000
1
0
1
1
0
0
1
0.3875
1
0
1
1
0
1
0
0.3750
1
0
1
1
0
1
1
0.3625
1
0
1
1
1
0
0
0.3500
1
0
1
1
1
0
1
0.3375
1
0
1
1
1
1
0
0.3250
1
0
1
1
1
1
1
0.3125
1
1
0
0
0
0
0
0.3000
R DROOP
VCC SENSE
FB
VDROOP
VR LOCAL VO
“CATCH”
RESISTOR
IDROOP
COMP
E/A
Σ
VIDS
VDAC
DAC
RTN
INTERNAL TO IC
X1
VID<0:6>
VSSSENSE
VSS
1
1
0
0
0
0
1
0.2875
1
1
0
0
0
1
0
0.2750
1
1
0
0
0
1
1
0.2625
1
1
0
0
1
0
0
0.2500
1
1
0
0
1
0
1
0.2375
1
1
0
0
1
1
0
0.2250
1
1
0
0
1
1
1
0.2125
1
1
0
1
0
0
0
0.2000
1
1
0
1
0
0
1
0.1875
1
1
0
1
0
1
0
0.1750
1
1
0
1
0
1
1
0.1625
1
1
0
1
1
0
0
0.1500
1
1
0
1
1
0
1
0.1375
1
1
0
1
1
1
0
0.1250
1
1
0
1
1
1
1
0.1125
1
1
1
0
0
0
0
0.1000
1
1
1
0
0
0
1
0.0875
1
1
1
0
0
1
0
0.0750
1
1
1
0
0
1
1
0.0625
1
1
1
0
1
0
0
0.0500
1
1
1
0
1
0
1
0.0375
1
1
1
0
1
1
0
0.0250
1
1
1
0
1
1
1
0.0125
Idroop flows through resistor Rdroop and creates a
voltage drop as shown in Equation 2.
1
1
1
1
0
0
0
0.0000
V DROOP = R DROOP × I DROOP
1
1
1
1
0
0
1
0.0000
1
1
1
1
0
1
0
0.0000
1
1
1
1
0
1
1
0.0000
14
“CATCH”
RESISTOR
FIGURE 9. DIFFERENTIAL SENSING AND LOAD LINE
IMPLEMENTATION
As the load current increases from zero, the output
voltage will droop from the VID table value by an amount
proportional to the load current to achieve the load line.
The ISL62884C can sense the inductor current through
the intrinsic DC Resistance (DCR) of the inductors as
shown in Figure 1 or through a resistor in series with the
inductors as shown in Figure 2. In both methods,
capacitor Cn voltage represents the inductor total
currents. A droop amplifier converts Cn voltage into an
internal current source with the gain set by resistor Ri.
The current source is used for load line implementation,
current monitor and overcurrent protection.
Figure 9 shows the load line implementation. The
ISL62884C drives a current source Idroop out of the FB
pin, described by Equation 1.
2xV Cn
I DROOP = -----------------Ri
(EQ. 1)
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding thus sustaining the load
line accuracy with reduced cost.
(EQ. 2)
VDROOP is the droop voltage required to implement load
line. Changing Rdroop or scaling IDROOP can both change
the load line slope. Since Idroop also sets the overcurrent
protection level, it is recommended to first scale Idroop
based on OCP requirement, then select an appropriate
Rdroop value to obtain the desired load line slope.
FN7591.0
March 16, 2010
ISL62884C
Differential Sensing
Figure 9 also shows the differential voltage sensing
scheme. VCCSENSE and VSSSENSE are the remote
voltage sensing signals from the processor die. A unity
gain differential amplifier senses the VSSSENSE voltage
and adds it to the DAC output. The error amplifier
regulates the inverting and the non-inverting input
voltages to be equal, therefore:
VCC SENSE + V
DROOP
= V DAC + VSS SENSE
(EQ. 3)
Rewriting Equation 3 and substituting Equation 2 gives:
VCC SENSE – VSS SENSE = V DAC – R DROOP × I DROOP
(EQ. 4)
Equation 4 is the exact equation required for load line
implementation.
The VCCSENSE and VSSSENSE signals come from the
processor die. The feedback will be open circuit in the
absence of the processor. As shown in Figure 9, it is
recommended to add a “catch” resistor to feed the VR
local output voltage back to the compensator, and add
another “catch” resistor to connect the VR local output
ground to the RTN pin. These resistors, typically
10Ω ~100Ω, will provide voltage feedback if the system is
powered up without a processor installed.
CCM Switching Frequency
The RFSET resistor between the COMP and the VW pins
sets the VW windows size, which therefore sets the
switching frequency. When the ISL62884C is in
continuous conduction mode (CCM), the switching
frequency is not absolutely constant due to the nature of
the R3™ modulator. As explained in “Multiphase R3™
Modulator” on page 11, the effective switching frequency
will increase during load insertion and will decrease
during load release to achieve fast response. On the
other hand, the switching frequency is relatively constant
at steady state. Variation is expected when the power
stage condition, such as input voltage, output voltage,
load, etc. changes. The variation is usually less than 15%
and doesn’t have any significant effect on output voltage
ripple magnitude. Equation 5 gives an estimate of the
frequency-setting resistor RFSET value. 8kΩ RFSET gives
approximately 300kHz switching frequency. Lower
resistance gives higher switching frequency.
R FSET ( kΩ ) = ( Period ( μs ) – 0.29 ) × 2.65
(EQ. 5)
Modes of Operation
TABLE 2. ISL62884C MODES OF OPERATION
DPRSTP# DPRSLPVR OPERATIONAL MODE
SLEW RATE
(mV/µs)
0
0
1-phase CCM
10
0
1
1-phase DE
2.5
1
0
1-phase CCM
10
1
1
1-phase CCM
2.5
15
Table 2 shows the ISL62884C operational modes,
programmed by the logic status of the DPRSLPVR pin and
the DPRSTP# pin. The ISL62884C enters 1-phase DE
mode when there is DPRSLPVR = 0 and DPRSLPVR = 1.
DPRSLPVR logic status also controls the output voltage
slew rate.
Dynamic Operation
The ISL62884C responds to VID changes by slewing to
the new voltage at a slew rate programmed by the logic
status on the DPRSLPVR pin, as Table 2 shows. The slew
rate is 10mV/µs for DPRSLPVR = 0 and is 1/4 of that for
DPRSLPVR = 1. As the output approaches the VID
command voltage, the dv/dt moderates to prevent
overshoot.
When the ISL62884C is in DE mode, it will actively drive
the output voltage up when the VID changes to a higher
value. Thus, will resume DE mode operation after
reaching the new voltage level. If the load is light enough
to warrant DCM, it will enter DCM after the inductor
current has crossed zero for four consecutive cycles. The
ISL62884C will remain in DE mode when the VID
changes to a lower value. The output voltage will decay
to the new value and the load will determine the slew
rate.
During load insertion response, the Fast Clock function
increases the PWM pulse response speed. The
ISL62884C monitors the VSEN pin voltage and compares
it to 100ns-filtered version. When the unfiltered version
is 20mV below the filtered version, the controller knows
there is a fast voltage dip due to load insertion, hence
issues an additional master clock signal to deliver a PWM
pulse immediately.
The R3™ modulator intrinsically has voltage feed
forward. The output voltage is insensitive to a fast slew
rate input voltage change.
Protections
The ISL62884C provides overcurrent, undervoltage,
and overvoltage protections.
The ISL62884C determines overcurrent protection
(OCP) by comparing the average value of the droop
current IDROOP with an internal current source
threshold. It declares OCP when IDROOP is above the
threshold for 120µs. A resistor Rcomp from the COMP
pin to GND programs the OCP current source threshold,
as well as the overshoot reduction function (to be
discussed in later sections), as Table 3 shows. It is
recommended to use the nominal Rcomp value. The
ISL62884C detects the Rcomp value at the beginning of
start-up, and sets the internal OCP threshold
accordingly. It remembers the Rcomp value until the
VR_ON signal drops below the POR threshold.
FN7591.0
March 16, 2010
ISL62884C
TABLE 3. ISL62884C OCP THRESHOLD AND
OVERSHOOT REDUCTION FUNCTION
Rcomp
NOMINAL
(kΩ)
MAX
(kΩ)
OCP
THRESHOLD
(µA)
OVERSHOOT
REDUCTION
FUNCTION
none
none
60
Disabled
305
400
410
68
205
235
240
62
155
165
170
54
104
120
130
60
78
85
90
68
62
66
68
45
50
55
MIN
(kΩ)
Table 4 summarizes the fault protections.
TABLE 4. FAULT PROTECTION SUMMARY
FAULT TYPE
Enabled
FAULT
DURATION
BEFORE
PROTECTION FAULT
PROTECTION
ACTION
RESET
Overcurrent
120µs
<2µs
62
Way-Overcurrent
(2.5xOC)
54
Overvoltage +200mV
1ms
The default OCP threshold is the value when Rcomp is
not populated. It is recommended to scale the droop
current IDROOP such that the default OCP threshold
gives approximately the desired OCP level, then use
Rcomp to fine tune the OCP level if necessary.
For overcurrent condition above 2.5x the OCP level, the
PWM output will immediately shut off and PGOOD will go
low to maximize protection. This protection is also
referred to as way-overcurrent protection or
fast-overcurrent protection, for short-circuit protections.
The ISL62884C will declare undervoltage (UV) fault and
latch off if the output voltage is less than the VID set
value by 300mV or more for 1ms. Thus, will turn off the
PWM output and de-assert PGOOD.
The ISL62884C has two levels of overvoltage
protections. The first level of overvoltage protection is
referred to as PGOOD overvoltage protection. If the
output voltage exceeds the VID set value by +200mV for
1ms, the ISL62884C will declare a fault and de-assert
PGOOD.
The ISL62884C takes the same actions for all of the
above fault protections: de-assertion of PGOOD and
turn-off of the high-side and low-side power MOSFETs.
Any residual inductor current will decay through the
MOSFET body diodes. These fault conditions can be reset
by bringing VR_ON low or by bringing VDD below the
POR threshold. When VR_ON and VDD return to their
high operating levels, a soft-start will occur.
The second level of overvoltage protection is different. If
the output voltage exceeds 1.7V, the ISL62884C will
immediately declare an OV fault, de-assert PGOOD, and
turn on the low-side power MOSFETs. The low-side power
MOSFETs remain on until the output voltage is pulled
down below 0.85V when all power MOSFETs are turned
off. If the output voltage rises above 1.7V again, the
protection process is repeated. This behavior provides
the maximum amount of protection against shorted
high-side power MOSFETs while preventing output
ringing below ground. Resetting VR_ON cannot clear the
1.7V OVP. Only resetting VDD will clear it. The 1.7V OVP
is active all the time when the controller is enabled, even
16
if one of the other faults have been declared. This
ensures that the processor is protected against high-side
power MOSFET leakage while the MOSFETs are
commanded off.
PWM tri-state, VR_ON
PGOOD latched toggle
or VDD
low
toggle
Undervoltage -300mV
Overvoltage 1.7V
Immediately
Low-side
VDD
MOSFET on
toggle
until Vcore
<0.85V, then
PWM tri-state,
PGOOD latched
low.
Adaptive Body Diode Conduction Time
Reduction
In DCM, the controller turns off the low-side MOSFET
when the inductor current approaches zero. During
on-time of the low-side MOSFET, phase voltage is negative
and the amount is the MOSFET rDS(ON) voltage drop,
which is proportional to the inductor current. A phase
comparator inside the controller monitors the phase
voltage during on-time of the low-side MOSFET and
compares it with a threshold to determine the
zero-crossing point of the inductor current. If the inductor
current has not reached zero when the low-side MOSFET
turns off, it’ll flow through the low-side MOSFET body
diode, causing the phase node to have a larger voltage
drop until it decays to zero. If the inductor current has
crossed zero and reversed the direction when the low-side
MOSFET turns off, it’ll flow through the high-side MOSFET
body diode, causing the phase node to have a spike until it
decays to zero. The controller continues monitoring the
phase voltage after turning off the low-side MOSFET and
adjusts the phase comparator threshold voltage
accordingly in iterative steps such that the low-side
MOSFET body diode conducts for approximately 40ns to
minimize the body diode-related loss.
Overshoot Reduction Function
The ISL62884C has an optional overshoot reduction
function, enabled or disabled by the resistor from the
COMP pin to GND, as shown in Table 3.
When a load release occurs, the energy stored in the
inductors will dump to the output capacitor, causing
output voltage overshoot. The inductor current
freewheels through the low-side MOSFET during this
period of time. The overshoot reduction function turns off
the low-side MOSFET during the output voltage
FN7591.0
March 16, 2010
ISL62884C
overshoot, forcing the inductor current to freewheel
through the low-side MOSFET body diode. Since the body
diode voltage drop is much higher than MOSFET rDS(ON)
voltage drop, more energy is dissipated on the low-side
MOSFET therefore the output voltage overshoot is lower.
If the overshoot reduction function is enabled, the
ISL62884C monitors the COMP pin voltage to determine
the output voltage overshoot condition. The COMP
voltage will fall and hit the clamp voltage when the
output voltage overshoots. The ISL62884C will turn off
LGATE when COMP is being clamped. The low-side
MOSFET in the power stage will be turned off. When the
output voltage has reached its peak and starts to come
down, the COMP voltage starts to rise and is no longer
clamped. The ISL62884C will resume normal PWM
operation.
While the overshoot reduction function reduces the
output voltage overshoot, energy is dissipated on the
low-side MOSFET, causing additional power loss. The
more frequent the transient event, the more the power
loss dissipated on the low-side MOSFET. The MOSFET
may face severe thermal stress when transient events
occur at a high repetitive rate. User discretion is advised
when this function is enabled.
Key Component Selection
RBIAS
The ISL62884C uses a resistor (1% or better tolerance is
recommended) from the RBIAS pin to GND to establish
highly accurate reference current sources inside the IC.
Using RBIAS = 147kΩ. Do not connect any other
components to this pin. Do not connect any capacitor to
the RBIAS pin as it will create instability.
Care should be taken in layout that the resistor is placed
very close to the RBIAS pin and that a good quality
signal ground is connected to the opposite side of the
RBIAS resistor.
Figure 10 shows the inductor DCR current-sensing
network. An inductor current flows through the DCR and
creates a voltage drop. The inductor has a resistors in
Rsum connected to the phase-node-side pad and a PCB
trace connected to the output-side pad to accurately
sense the inductor current by sensing the DCR voltage
drop. The sensed current information is fed to the NTC
network (consisting of Rntcs, Rntc and Rp) and capacitor
Cn. Rntc is a negative temperature coefficient (NTC)
thermistor, used to temperature-compensate the
inductor DCR change. The inductor current information is
presented to the capacitor Cn.
17
Inductor DCR Current-Sensing Network
PHASE
ISUM+
RSUM
L
RNTCS
RP
DCR
+
CN VCN
-
RNTC
RI
ISUM-
IO
FIGURE 10. DCR CURRENT-SENSING NETWORK
Equations 6 through 10 describe the frequency-domain
relationship between inductor total current Io(s) and Cn
voltage VCn(s):
R ntcnet
⎛
⎞
V Cn ( s ) = ⎜ ------------------------------------------ × DCR⎟ × I o ( s ) × A cs ( s )
R
+
R
⎝ ntcnet
⎠
sum
(EQ. 6)
( R ntcs + R ntc ) × R p
R ntcnet = ---------------------------------------------------R ntcs + R ntc + R p
(EQ. 7)
s
1 + ------ωL
A cs ( s ) = ----------------------s
1 + ------------ω sns
(EQ. 8)
DCR
ω L = ------------L
(EQ. 9)
1
ω sns = -------------------------------------------------------R ntcnet × R sum
------------------------------------------ × C n
R ntcnet + R sum
(EQ. 10)
Transfer function Acs(s) always has unity gain at DC. The
inductor DCR value increases as the winding temperature
increases, giving higher reading of the inductor DC
current. The NTC Rntc values decreases as its
temperature decreases. Proper selections of Rsum, Rntcs,
Rp and Rntc parameters ensure that VCn represents the
inductor total DC current over the temperature range of
interest.
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the
NTC network and the Rsum resistors form a voltage
divider, Vcn is always a fraction of the inductor DCR
voltage. It is recommended to have a higher ratio of Vcn
to the inductor DCR voltage, so the droop circuit has
higher signal level to work with.
FN7591.0
March 16, 2010
ISL62884C
A typical set of parameters that provide good
temperature compensation are: Rsum = 1.82kΩ,
Rp = 11kΩ, Rntcs = 2.61kΩ and Rntc = 10kΩ
(ERT-J1VR103J). The NTC network parameters may need
to be fine tuned on actual boards. One can apply full load
DC current and record the output voltage reading
immediately; then record the output voltage reading
again when the board has reached the thermal steady
state. A good NTC network can limit the output voltage
drift to within 2mV. It is recommended to follow the
Intersil evaluation board layout and current-sensing
network parameters to minimize engineering time.
VCn(s) also needs to represent real-time Io(s) for the
controller to achieve good transient response. Transfer
function Acs(s) has a pole ωsns and a zero ωL. One needs
to match ωL and ωsns so Acs(s) is unity gain at all
frequencies. By forcing ωL equal to ωsns and solving for
the solution, Equation 11 gives Cn value.
L
C n = --------------------------------------------------------------R ntcnet × R sum
------------------------------------------ × DCR
R ntcnet + R sum
(EQ. 11)
io
Vo
FIGURE 11. DESIRED LOAD TRANSIENT RESPONSE
WAVEFORMS
io
Vo
FIGURE 12. LOAD TRANSIENT RESPONSE WHEN Cn IS
TOO SMALL
io
Vo
For example, given Rsum = 1.82kΩ, Rp = 11kΩ,
Rntcs = 2.61kΩ, Rntc = 10kΩ, DCR = 19.7mΩ and
L = 1.5µH, Equation 11 gives Cn = 0.055µF.
Assuming the compensator design is correct, Figure 11
shows the expected load transient response waveforms if
Cn is correctly selected. When the load current Icore has
a square change, the output voltage Vcore also has a
square response.
If Cn value is too large or too small, VCn(s) will not
accurately represent real-time Io(s) and will worsen the
transient response. Figure 12 shows the load transient
response when Cn is too small. Vcore will sag excessively
upon load insertion and may create a system failure.
Figure 13 shows the transient response when Cn is too
large. Vcore is sluggish in drooping to its final value.
There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU
reliability.
Figure 14 shows the output voltage ring back problem
during load transient response. The load current io has a
fast step change, but the inductor current iL cannot
accurately follow. Instead, iL responds in first order
system fashion due to the nature of current loop. The
ESR and ESL effect of the output capacitors makes the
output voltage Vo dip quickly upon load current change.
However, the controller regulates Vo according to the
droop current idroop, which is a real-time representation
of iL; therefore it pulls Vo back to the level dictated by iL,
causing the ring back problem. This phenomenon is not
observed when the output capacitors have very low ESR
and ESL, such as all ceramic capacitors.
Figure 15 shows two optional circuits for reduction of the
ring back. Rip and Cip form an R-C branch in parallel with
Ri, providing a lower impedance path than Ri at the
beginning of io change. Rip and Cip do not have any
effect at steady state. Through proper selection of Rip
and Cip values, idroop can resemble io rather than iL, and
Vo will not ring back. The recommended value for Rip is
100Ω. Cip should be determined through tuning the load
transient response waveforms on an actual board. The
recommended range for Cip is 100pF~2000pF. However,
it should be noted that the Rip -Cip branch may distort
the idroop waveform. Instead of being triangular as the
real inductor current, idroop may have sharp spikes,
which may adversely affect idroop average value
detection and therefore may affect OCP accuracy. User
discretion is advised.
iO
iL
FIGURE 13. LOAD TRANSIENT RESPONSE WHEN Cn IS
TOO LARGE
VO
RING
BACK
FIGURE 14. OUTPUT VOLTAGE RING BACK PROBLEM
18
FN7591.0
March 16, 2010
ISL62884C
ISUM+
Rntcs
Cn.1
Rp
Rntc
Rn
+
Cn.2 Vcn
-
Ri
OPTIONAL
ISUM-
Rip Cip
OPTIONAL
FIGURE 15. OPTIONAL CIRCUITS FOR RING BACK
REDUCTION
Cn is the capacitor used to match the inductor time
constant. It usually takes the parallel of two (or more)
capacitors to get the desired value. Figure 15 shows
that two capacitors Cn.1 and Cn.2 are in parallel.
Resistor Rn is an optional component to reduce the Vo
ring back. At steady state, Cn.1 + Cn.2 provides the
desired Cn capacitance. At the beginning of io change,
the effective capacitance is less because Rn increases
the impedance of the Cn.1 branch. As Figure 12
explains, Vo tends to dip when Cn is too small, and this
effect will reduce the Vo ring back. This effect is more
pronounced when Cn.1 is much larger than Cn.2. It is
also more pronounced when Rn is bigger. However, the
presence of Rn increases the ripple of the Vn signal if
Cn.2 is too small. It is recommended to keep Cn.2
greater than 2200pF. Rn value usually is a few ohms.
Cn.1, Cn.2 and Rn values should be determined
through tuning the load transient response waveforms
on an actual board.
Resistor Current-Sensing Network
V Cn ( s ) = R sen × I o ( s ) × A Rsen ( s )
(EQ. 12)
1
A Rsen ( s ) = ----------------------s
1 + ------------ω sns
(EQ. 13)
(EQ. 14)
1
ω Rsen = ----------------------------R sum × C n
Transfer function ARsen(s) always has unity gain at DC.
Current-sensing resistor Rsen value will not have
significant variation over-temperature, so there is no
need for the NTC network.
The recommended values are Rsum = 1kΩ and
Cn = 5600pF.
Overcurrent Protection
Referring to Equation 1 and Figures 9, 10 and 16, resistor
Ri sets the droop current Idroop. Table 3 shows the
internal OCP threshold. It is recommended to design
Idroop without using the Rcomp resistor.
For example, the OCP threshold is 60µA. We will design
Idroop to be 50µA at full load, so the OCP trip level is 1.2x
of the full load current.
For inductor DCR sensing, Equation 15 gives the DC
relationship of Vcn(s) and Io(s).
R ntcnet
⎛
⎞
V Cn = ⎜ ------------------------------------------ × DCR⎟ × I o
⎝ R ntcnet + R sum
⎠
(EQ. 15)
Substitution of Equation 15 into Equation 1 gives
Equation 16:
R ntcnet
2
I droop = ----- × ------------------------------------------ × DCR × I o
R i R ntcnet + R sum
(EQ. 16)
Therefore:
2R ntcnet × DCR × I o
R i = ---------------------------------------------------------------------( R ntcnet + R sum ) × I droop
PHASE
(EQ. 17)
Substitution of Equation 7 and application of the OCP
condition in Equation 17 gives Equation 18:
L
DCR
ISUM+
RSUM
RSEN
Figure 16 shows the resistor current-sensing network.
The inductor has a series current-sensing resistor Rsen.
Rsum and is connected to the Rsen pad to accurately
capture the inductor current information. The Rsum feeds
the sensed information to capacitor Cn. Rsum and Cn
form a a filter for noise attenuation. Equations 12
through 14 gives VCn(s) expressions:
Vcn
Cn
Ri
ISUM-
Io
FIGURE 16. RESISTOR CURRENT-SENSING NETWORK
19
( R ntcs + R ntc ) × R p
2 × ---------------------------------------------------- × DCR × I omax
R ntcs + R ntc + R p
R i = -----------------------------------------------------------------------------------------------------------------⎛ ( R ntcs + R ntc ) × R p
⎞
⎜ ---------------------------------------------------- + R sum⎟ × I droopmax
⎝ R ntcs + R ntc + R p
⎠
(EQ. 18)
where Iomax is the full load current, Idroopmax is the
corresponding droop current. For example, given
Rsum = 1.82kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ, Rntc = 10kΩ,
DCR = 19.7mΩ, Iomax = 5A and Idroopmax = 50µA,
Equation 18 gives Ri = 3.01kΩ.
For resistor sensing, Equation 19 gives the DC
relationship of Vcn(s) and Io(s).
V Cn = R sen × I o
(EQ. 19)
FN7591.0
March 16, 2010
ISL62884C
Substitution of Equation 19 into Equation 1 gives
Equation 20:
2
I droop = ----- × R sen × I o
Ri
(EQ. 20)
Therefore:
2R sen × I o
R i = ---------------------------I droop
equivalent to a voltage source (= VID) and output
impedance Zout(s). If Zout(s) is equal to the load line
slope LL, i.e., constant output impedance in the entire
frequency range, Vo will have square response when Io
has a square change.
Zout(s) = LL
(EQ. 21)
Substitution of Equation 21 and application of the OCP
condition in Equation 17 gives Equation 22:
2R sen × I omax
R i = --------------------------------------I droopmax
iO
VR
VID
+
VO
-
LOAD
(EQ. 22)
where Iomax is the full load current, Idroopmax is the
corresponding droop current. For example, given
Rsen = 1mΩ, Iomax = 5A and Idroopmax = 50µA,
Equation 22 gives Ri = 200Ω.
A resistor from COMP to GND can adjust the internal OCP
threshold, providing another dimension of fine-tune
flexibility. Table 3 shows the detail. It is recommended to
scale Idroop such that the default OCP threshold gives
approximately the desired OCP level, then use Rcomp to
fine tune the OCP level if necessary.
Load Line Slope
Refer to Figure 9.
For inductor DCR sensing, substitution of Equation 16
into Equation 2 gives the load line slope expression in
Equation 23.
V droop
2R droop
R ntcnet
LL = ------------------- = ----------------------- × ------------------------------------------ × DCR
Io
Ri
R ntcnet + R sum
(EQ. 23)
For resistor sensing, substitution of Equation 20 into
Equation 2 gives the load line slope expression in
Equation 24:
2R sen × R droop
V droop
LL = ------------------- = ------------------------------------------Io
Ri
(EQ. 24)
Substitution of Equation 17 and rewriting Equation 23,
or substitution of Equation 21 and rewriting Equation 24
gives the same result in Equation 25:
Io
R droop = ---------------- × LL
I droop
FIGURE 17. VOLTAGE REGULATOR EQUIVALENT
CIRCUIT
A VR with active droop function is a dual-loop system
consisting of a voltage loop and a droop loop which is a
current loop. However, neither loop alone is sufficient to
describe the entire system. The spreadsheet (see
Figure 21) shows two loop gain transfer functions, T1(s)
and T2(s), that describe the entire system. Figure 18
conceptually shows T1(s) measurement set-up and
Figure 19 conceptually shows T2(s) measurement
set-up. The VR senses the inductor current, multiplies it
by a gain of the load line slope, then adds it on top of the
sensed output voltage and feeds it to the compensator.
T(1) is measured after the summing node, and T2(s) is
measured in the voltage loop before the summing node.
The spreadsheet (see Figure 21) gives both T1(s) and
T2(s) plots. However, only T2(s) can be actually
measured on an ISL62884C regulator.
T1(s) is the total loop gain of the voltage loop and the
droop loop. It always has a higher crossover frequency
than T2(s) and has more meaning of system stability.
T2(s) is the voltage loop gain with closed droop loop. It
has more meaning of output voltage response.
Design the compensator to get stable T1(s) and T2(s)
with sufficient phase margin, and output impedance
equal or smaller than the load line slope.
L
(EQ. 25)
VIN
One can use the full load condition to calculate Rdroop.
For example, given Iomax = 5A, Idroopmax = 50µA and
LL = 5.7mΩ, Equation 25 gives Rdroop = 0.57kΩ.
It is recommended to start with the Rdroop value
calculated by Equation 25, and fine tune it on the actual
board to get accurate load line slope. One should record
the output voltage readings at no load and at full load for
load line slope calculation. Reading the output voltage at
lighter load instead of full load will increase the
measurement error.
Compensator
Figure 11 shows the desired load transient response
waveforms. Figure 17 shows the equivalent circuit of a
voltage regulator (VR) with the droop function. A VR is
20
VO
Q1
GATE Q2
DRIVER
IO
COUT
LOAD LINE SLOPE
MOD
EA
+
COMP
LOOP GAIN =
CHANNEL B
20 Ω
VID
+
+
ISOLATION
TRANSFORMER
CHANNEL A
CHANNEL A
NETWORK
ANALYZER
CHANNEL B
EXCITATION OUTPUT
FIGURE 18. LOOP GAIN T1(s) MEASUREMENT SET-UP
FN7591.0
March 16, 2010
ISL62884C
L
Figure 20 shows the waveforms of 1-tick VID transition.
During 1-tick VID transition, the DAC output changes at
approximately 15mV/µs slew rate, but the DAC cannot
step through multiple VIDs to control the slew rate.
Instead, the control loop response speed determines
Vcore slew rate. Ideally, Vcore will follow the FB pin
voltage slew rate. However, the controller senses the
inductor current increase during the up transition, as the
Idroop_vid waveform shows, and will droop the output
voltage Vcore accordingly, making Vcore slew rate slow.
Similar behavior occurs during the down transition.
VO
Q1
VIN
IO
COUT
GATE Q2
DRIVER
LOAD LINE SLOPE
+
MOD
COMP
LOOP GAIN =
EA
+
+
20 Ω
VID
ISOLATION
TRANSFORMER
CHANNEL B
CHANNEL A
CHANNEL A
NETWORK
ANALYZER
CHANNEL B
EXCITATION OUTPUT
FIGURE 19. LOOP GAIN T2(s) MEASUREMENT SET-UP
Optional Slew Rate Compensation Circuit
For 1-Tick VID Transition
Rdroop
Rvid
Vcore
Ivid
E/A
Σ VDACDAC
VIDs
RTN
X1
INTERNAL TO
IC
–t
---------------------------⎞
C out × LL dV core ⎛
C
× LL⎟
I droop ( t ) = -------------------------- × ------------------- × ⎜ 1 – e out
⎜
⎟
dt
R droop
⎝
⎠
(EQ. 26)
where Cout is the total output capacitance.
In the meantime, the Rvid-Cvid branch current Ivid time
domain expression is shown in Equation 27:
--------------------------------⎞
dV fb ⎛
R
× C vid⎟
I vid ( t ) = C vid × ------------ × ⎜ 1 – e vid
⎜
⎟
dt
⎝
⎠
(EQ. 27)
It is desired to let Ivid(t) cancel Idroop_vid(t). So there
are Equation 28:
Idroop_vid
COMP
When Vcore increases, the time domain expression of the
induced Idroop change is as shown in Equation 26:
–t
Cvid
OPTIONAL
FB
To control Vcore slew rate during 1-tick VID transition,
one can add the Rvid-Cvid branch, whose current Ivid
cancels Idroop_vid.
VID<0:6>
VSSSENSE
VSS
dV fb
C out × LL dV core
C vid × ------------ = -------------------------- × ------------------R droop
dt
dt
(EQ. 28)
and Equation 29:
R vid × C vid = C out × LL
(EQ. 29)
The result is Equation 30:
VID<0:6>
R vid = R droop
(EQ. 30)
and Equation 31:
Vfb
dV core
C out × LL -----------------dt
C vid = -------------------------- × ------------------R droop
dV fb
-----------dt
Ivid
(EQ. 31)
For example: given LL = 5.7mΩ, Rdroop = 0.57kΩ,
Cout = 410µF, dVcore/dt = 10mV/µs and
dVfb/dt = 15mV/µs, Equation 30 gives Rvid = 0.57kΩ
and Equation 31 gives Cvid = 2730pF.
Vcore
Idroop_vid
FIGURE 20. OPTIONAL SLEW RATE COMPENSATION
CIRCUIT FOR1-TICK VID TRANSITION
During a large VID transition, the DAC steps through the
VIDs at a controlled slew rate, such as 1.25µs per tick
(12.5mV), controlling output voltage Vcore slew rate at
10mV/µs.
21
It’s recommended to select the calculated Rvid value and
start with the calculated Cvid value and tweak it on the
actual board to get the best performance.
During normal transient response, the FB pin voltage is
held constant, therefore is virtual ground in small signal
sense. The Rvid-Cvid network is between the virtual
ground and the real ground, and hence has no effect on
transient response.
FN7591.0
March 16, 2010
ISL62884C
Layout Guidelines
Table 5 shows the layout considerations. The designators
refer to the reference designs shown in Figure 22.
TABLE 5. LAYOUT CONSIDERATIONS
NAME
LAYOUT CONSIDERATION
GND
Create analog ground plane underneath the controller and the analog signal processing components. Don’t let the
power ground plane overlap with the analog ground plane. Avoid noisy planes/traces (e.g.: phase node) from
crossing over/overlapping with the analog plane.
CLK_EN#
No special consideration.
PGOOD
No special consideration.
RBIAS
Place the RBIAS resistor (R16) in general proximity of the controller. Low impedance connection to the analog ground
plane.
VW
COMP
Place capacitor (C4) across VW and COMP in close proximity of the controller.
Place compensator components (C3, C5, C6 R7, R11, R10 and C11) in general proximity of the controller.
FB
VSEN
Place the VSEN/RTN filter (C12, C13) in close proximity of the controller for good decoupling.
RTN
VDD
DPRSTP#
ISUMISUM+
A capacitor (C16) decouples it to GND. Place it in close proximity of the controller.
No special consideration.
Place the current sensing circuit in general proximity of the controller.
Place C82 very close to the controller.
Place NTC thermistors R42 next to inductor (L1) so it senses the inductor temperature correctly.
The power stage sends a pair of VSUM+ and VSUM- signals to the controller. Run these two signal traces in parallel
fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads.
Route R63 to the phase-node side pad of inductor L1. Route the other current sensing trace to the output side pad
of inductor L1.
If possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to
the center of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of
the inductor. The following drawings show the two preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENTSENSING TRACES
VIN
CURRENTSENSING TRACES
A capacitor (C17) decouples it to GND. Place it in close proximity of the controller.
BOOT
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
UGATE
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE trace to the high-side MOSFET (Q2 and Q8) source pins
instead of general phase node copper.
PHASE
VSSP
LGATE
VCCP
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing VSSP to the low-side MOSFET (Q3) source pins instead of general
power ground plane for better performance.
A capacitor (C22) decouples it to GND. Place it in close proximity of the controller.
VID0~6
No special consideration.
VR_ON
No special consideration.
DPRSLPVR No special consideration.
Phase Node Minimize phase node copper area. Don’t let the phase node copper overlap with/getting close to other sensitive
traces. Cut the power ground plane to avoid overlapping with phase node copper.
Minimize the loop consisting of input capacitor, high-side MOSFETs and low-side MOSFETs (e.g.: C27, C33, Q2, Q3).
22
FN7591.0
March 16, 2010
Compensation & Current Sensing Network Design for Intersil Multiphase R^3 Regulators for IMVP-6.5
Jia Wei, [email protected], 919-405-3605
Attention: 1. "Analysis ToolPak" Add-in is required. To turn on, go to Tools--Add-Ins, and check "Analysis ToolPak"
2. Green cells require user input
Compensator Parameters
Operation Parameters
Controller Part Number: ISL6288x
§
s · §
s ·
¸
¸ ˜ ¨1 KZi ˜ Zi ˜ ¨¨1 Phase Number:
3
2Sf z1 ¸¹ ¨©
2Sf z 2 ¸¹
©
AV ( s )
Vin:
12 volts
§
·
§
·
s ¸ ¨
s ¸
Vo:
1.15 volts
˜ 1
s ˜ ¨1 ¨
2Sf p1 ¸¹ ¨©
2Sf p 2 ¸¹
©
Full Load Current:
51 Amps
23
Estimated Full-Load Efficiency:
Number of Output Bulk Capacitors:
Capacitance of Each Output Bulk Capacitor:
ESR of Each Output Bulk Capacitor:
ESL of Each Output Bulk Capacitor:
Number of Output Ceramic Capacitors:
Capacitance of Each Output Ceramic Capacitor:
ESR of Each Output Ceramic Capacitor:
ESL of Each Output Ceramic Capacitor:
Switching Frequency:
Inductance Per Phase:
CPU Socket Resistance:
Desired Load-Line Slope:
Desired ISUM- Pin Current at Full Load:
(This sets the over-current protection level)
87
4
270
4.5
0.6
24
10
3
3
300
0.36
0.9
1.9
40.9
%
uF
m:
nH
Recommended Value
R1
2.369 k :
R2
338.213 k :
R3
0.530 k :
C1
148.140 pF
C2
455.369 pF
C3
40.069 pF
uF
m:
nH
kHz
uH
m:
m:
uA
User-Selected Value
R1
2.37 k :
R2
324 k :
R3
0.536 k :
C1
150 pF
C2
390 pF
C3
39 pF
Use User-Selected Value (Y/N)?
N
Performance and Stability
T1 Bandwidth: 212kHz
T2 Bandwidth: 66kHz
T1 Phase Margin: 58.9°
T2 Phase Margin: 89.3°
1.3
Loop Gain, Gain Curve
0DJQLWXGH PRKP
(
3KDVH GHJUHH
(
(
(
)UHTXHQF\ +]
(
(
(
Loop Gain, Phase Curve
7 V
7 V
FN7591.0
March 16, 2010
(
(
(
)UHTXHQF\ +]
(
(
(
(
(
)UHTXHQF\ +]
(
(
(
3KDVH GHJUHH
*DLQ G%
Recommended Value
Cn
0.406 uF
Ri 606.036 :
7 V
7 V
Output Impedance, Gain Curve
Operation Parameters
Inductor DCR
0.88 m :
Rsum
3.65 k :
Rntc
10 k :
Rntcs
2.61 k :
Rp
11 k :
Output Impedance, Phase Curve
(
(
(
(
)UHTXHQF\ +]
(
(
FIGURE 21. SCREENSHOT OF THE COMPENSATOR DESIGN SPREADSHEET
User Selected Value
Cn
0.406 uF
Ri
604 :
ISL62884C
Changing the settings in red requires deep understanding of control loop design
Place the 2nd compensator pole fp2 at:
2.2 xfs (Switching Frequency)
Tune Ki to get the desired loop gain bandwidth
Tune the compensator gain factor Ki:
(Recommended Ki range is 0.8~2)
Current Sensing Network Parameters
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VR_ON
DPRSLPVR
IN
IN
IN
IN
IN
IN
IN
+3.3V
IN
IN
IN
C61
C60
10UF
C59
10UF
C56
10UF
C55
10UF
C54
10UF
C41
10UF
C40
10UF
C52
330UF
4MOHM
C52
DNP
Q3
OUT
VCORE
10UF
10UF
C27
10UF
C33
56UF
C24
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
0.22UF
1.5UH
11MOHM
1UF
DPRSTP#
+5V
VIN
R41
10K 2.61K
NTC
-----> R42
11K
R38
0.1UF
----
DNP DNP
-----------OPTIONAL
C20
C15
R30
1.91K
-----------C81 R109
----
0.1UF
R63
R26
10
IN
0
0.22UF
R18
----
IN
R40
C18
IN
1
DNP
VSSSENSE
IN
R37
1UF
C17
IN
0
+5V
IRF7832
1.82K
PLACE NEAR L1
FIGURE 22. REFERENCE DESIGN
LAYOUT NOTE:
ROUTE UGATE TRACE IN PARALLEL
WITH THE PHASE TRACE GOING TO
THE SOURCE OF Q2
ROUTE LGATE TRACE IN PARALLEL
WITH THE VSSP TRACE GOING TO
THE SOURCE OF Q3
ISL62884C
VCCSENSE
0
C82
10
C30
R20
C16
R17
R56
LGATE
VSSP
PHASE
UGATE
ISL62884C
C22
R11
576
OPTIONAL
----
IN
RTN
ISUMISUM+
VDD
VIN
DPRSTP#
BOOT
C4
IN
VSEN
EP
C11
IRF7821
Q2
L1
VID1
VID0
VCCP
U6
DNP DNP
VCORE
R7
191K
IN
1.91K
R19
150PF
VW
COMP
FB
255 2700PF
----C12
C3
R10
C13
----
C6
82PF
PGOOD
RBIAS
R16
147K
1000PF 330PF
-----
C83 R110
DNP
DNP
--------
--------
OPTIONAL
----
CLK_EN#
1000PF
----
OUT
OUT
10K
DNP
------R6
------R4
24
CLK_EN#
PGOOD
OPTIONAL
----
1.91K
R23
VIN
FN7591.0
March 16, 2010
ISL62884C
Reference Design Bill of Materials
QTY
REFERENCE
1
C11
1
C12
1
C13
2
C16, C22
1µF
Multilayer Cap, 16V, 20%
GENERIC
H1045-00105-16V20
SM0603
1
C18
0.1µF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00104-16V10
SM0603
0.1µF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00104-16V10
SM0603
0.22µF Multilayer Cap, 25V, 10%
GENERIC
H1045-00224-25V10
SM0603
1
C20
2
C17, C30
VALUE
DESCRIPTION
2700pF Multilayer Cap, 16V, 10%
330pF
MANUFACTURER
GENERIC
PART NUMBER
PACKAGE
H1045-00272-16V10
SM0603
Multilayer Cap, 16V, 10%
GENERIC
H1045-00331-16V10
SM0603
1000pF Multilayer Cap, 16V, 10%
GENERIC
H1045-00102-16V10
SM0603
1
C24
56µF
Radial SP Series Cap, 25V, 20% SANYO
25SP56M
CASE-CC
2
C27, C33
10µF
Multilayer Cap, 25V, 20%
H1065-00106-25V20
SM1206
SM0603
GENERIC
1
C3
150pF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00151-16V10
1
C52
330µF
SPCAP, 2V, 4MΩ
PANASONIC
EEXSX0D331E4
POLYMER CAP, 2.5V, 4.5MΩ
KEMET
T520V337M2R5A(1)E4R5-6666
1
C4
GENERIC
H1045-00102-16V10
SM0603
8
C40, C41, C54C56, C59-C61
10µF
TAIYO
MURATA
Kyocera
TDK
JMK212BJ106MG-T
SM0805
C6
82pF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00820-16V10
SM0603
0
C82
DNP
0
C39, C81, C83
DNP
1
L1
1.5µH
Inductor, Inductance 20%,
DCR 10%
PANASONIC
ETQP3M1R5YFN
6.5mm x
6.5mm
1
Q2
N-Channel Power MOSFET
IR
IRF7821
PWRPAKSO8
1
Q3
N-Channel Power MOSFET
IR
IRF7832
PWRPAKSO8
1
R10
255
Thick Film Chip Resistor, 1%
GENERIC
H2511-02550-1/16W1
SM0603
1
R11
576
Thick Film Chip Resistor, 1%
GENERIC
H2511-05760-1/16W1
SM0603
1
R16
147k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01473-1/16W1
SM0603
2
R17, R18
10
Thick Film Chip Resistor, 1%
GENERIC
H2511-00100-1/16W1
SM0603
2
R19, R23
1.91k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01911-1/16W1
SM0603
1
R26
82.5
Thick Film Chip Resistor, 1%
GENERIC
H2511-082R5-1/16W1
SM0603
3
R20, R40, R56
0
Thick Film Chip Resistor, 1%
GENERIC
H2511-00R00-1/16W1
SM0603
1
R30
1.91k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01911-1/16W1
SM0603
1
R37
1
Thick Film Chip Resistor, 1%
GENERIC
H2511-01R00-1/16W1
SM0603
1
R38
11k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01102-1/16W1
SM0603
2.61k
Thick Film Chip Resistor, 1%
GENERIC
H2511-02611-1/16W1
SM0603
PANASONIC
ERT-J1VR103J
SM0603
1
1
R41
1
R42
1000pF Multilayer Cap, 16V, 10%
Multilayer Cap, 6.3V, 20%
10k NTC Thermistor, 10k NTC
GRM21BR60J106ME19
CM21X5R106M06AT
C2012X5R0J106MT009N
1
R6
10k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01002-1/16W1
SM0603
1
R63
1.82k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01821-1/16W1
SM0805
1
R7
191k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01913-1/16W1
SM0603
0
R109, R110,
R4, R8, R9
DNP
1
U6
IMVP-6 PWM Controller
INTERSIL
ISL62884CHRTZ
QFN-28
25
FN7591.0
March 16, 2010
ISL62884C
100
90
90
80
70
VIN = 12V
60
VIN = 19V
VIN = 8V
50
80
VIN = 12V
70
60
VIN = 8V
VIN = 19V
50
40
40
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IOUT(A)
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IOUT(A)
FIGURE 23. ISL62884CEVAL2Z EVALUATION BOARD
CCM EFFICIENCY, VID = 1.2375V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
VOUT(V)
EFFICIENCY (%)
100
FIGURE 24. ISL62884CEVAL2Z EVALUATION BOARD DE
MODE EFFICIENCY, VID = 1.2375V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
1.27
1.27
1.26
1.26
1.25
1.25
VIN = 19V
1.24
1.23
1.22
1.21
VIN = 12V
1.20
VIN = 8V
VIN = 19VV
1.24
1.23
1.22
1.21
VIN = 12V
1.20
VIN = 8V
1.19
1.19
1.18
VOUT(V)
EFFICIENCY(%)
Typical Performance
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IOUT(A)
1.18
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IOUT(A)
FIGURE 25. ISL62884CEVAL2Z EVALUATION BOARD
CCM LOAD LINE, VID = 1.2375V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 26. ISL62884CEVAL2Z EVALUATION BOARD DE
MODE LOAD LINE, VID = 1.2375V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 27. SOFT-START, VIN = 12V, IO = 1A,
VID = 1.2375V, CH1: PHASE, CH2: VO
FIGURE 28. SHUT DOWN, VIN = 12V, IO = 1A,
VID = 1.2375V, CH1: PHASE, CH2: VO
26
FN7591.0
March 16, 2010
ISL62884C
Typical Performance (Continued)
FIGURE 29. CCM STEADY STATE, VIN = 12V, IO = 5A,
VID = 1.2375V, CH1: PHASE, CH2: VO
FIGURE 30. DCM STEADY STATE, VIN = 12V, IO = 0.5A,
VID = 1.2375V, CH1: PHASE, CH2: VO
Phase Margin
Gain
FIGURE 31. REFERENCE DESIGN LOOP GAIN T2(s)
MEASUREMENT RESULT
FIGURE 32. CLK_EN# DELAY, VIN = 12V, IO = 1A,
VID = 1.2375V, Ch1: PHASE, Ch3: CLK_EN#
FIGURE 33. LOAD TRANSIENT RESPONSE WITH
OVERSHOOT REDUCTION FUNCTION
DISABLED, VIN = 12V, VID = 1.2375V,
IO = 5A/0A, Ch1: VO
FIGURE 34. LOAD TRANSIENT RESPONSE WITH
OVERSHOOT REDUCTION FUNCTION
DISABLED, VIN = 12V, VID = 1.2375V,
IO = 5A/0A, Ch1: VO
27
FN7591.0
March 16, 2010
ISL62884C
Typical Performance (Continued)
FIGURE 35. LOAD TRANSIENT RESPONSE WITH
OVERSHOOT REDUCTION FUNCTION
DISABLED, VIN = 12V, VID = 1.2375V,
IO = 5A/0A, CH1: VO
FIGURE 36. LOAD TRANSIENT RESPONSE WITH
OVERSHOOT REDUCTION FUNCTION
DISABLED, VIN = 12V, VID = 1.2375V,
IO = 5A/0A, CH1: VO
FIGURE 37. VID TRANSITION, IO = 0.2A, DPRSLPVR =
0, DPRSTP# = 0, VID = 1.2375V/1.0375V,
CH1: PHASE, CH2: VO, CH3: VID4
FIGURE 38. VID TRANSITION, IO = 0.2A, DPRSLPVR =
1, DPRSTP# = 0, VID = 1.2375V/1.0375V,
CH1: PHASE, CH2: VO, CH3: VID4
FIGURE 39. VID TRANSITION, IO = 0.2A,
DPRSLPVR = 0, DPRSTP# = 1,
VID = 1.2375V/1.0375V, CH1: PHASE,
CH2: VO, CH3: VID4
FIGURE 40. VID TRANSITION, IO = 0.2A,
DPRSLPVR = 1, DPRSTP#=1,
VID = 1.2375V/1.0375V, CH1: PHASE,
CH2: VO, CH3: VID4
28
FN7591.0
March 16, 2010
ISL62884C
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
3/16/10
FN7591.0
CHANGE
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL62884C
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
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patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
29
FN7591.0
March 16, 2010
ISL62884C
Package Outline Drawing
L28.4x4
28 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 9/06
A
4 . 00
2 . 50
PIN #1 INDEX AREA
CHAMFER 0 . 400 X 45¬
0 . 40
22
28
1
0 . 40
15
3 . 20
2 . 50
4 . 00
21
0 . 4 x 6 = 2.40 REF
B
PIN 1
INDEX AREA
7
0 . 10
2X
14
8
0 . 20 ±0 . 0
0 . 10 M C A B
0 . 4 x 6 = 2 . 40 REF
TOP VIEW
3 . 20
BOTTOM VIEW
SEE DETAIL X''
0 . 10 C
(3 . 20)
C
PACKAGE BOUNDARY
MAX. 0 . 80
SEATING PLANE
(28X 0 . 20)
0 . 00 - 0 . 05
0 . 08 C
0 . 20 REF
(3 . 20)
(2 . 50)
SIDE VIEW
(0 . 40)
C
(0 . 40)
0 . 20 REF
5
0 ~ 0 . 05
(2 . 50)
(28X 0 . 60)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Controlling dimensions are in mm.
Dimensions in ( ) for reference only.
2. Unless otherwise specified, tolerance : Decimal ±0.05
Angular ±2°
3. Dimensioning and tolerancing conform to AMSE Y14.5M-1994.
4. Bottom side Pin#1 ID is diepad chamfer as shown.
5. Tiebar shown (if present) is a non-functional feature.
30
FN7591.0
March 16, 2010
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