PD - 95552B
IRLR2908PbF
IRLU2908PbF
HEXFET® Power MOSFET
Features
l
l
l
l
l
l
l
Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
D
VDSS = 80V
RDS(on) = 28mΩ
G
ID = 30A
S
Description
This HEXFET ® Power MOSFET utilizes the latest processing techniques
to achieve extremely low on-resistance per silicon area. Additional features
of this HEXFET power MOSFET are a 175°C junction operating temperature,
low RθJC, fast switching speed and improved repetitive avalanche rating.
These features combine to make this design an extremely efficient and
reliable device for use in a wide variety of applications.
The D-Pak is designed for surface mounting using vapor phase, infrared,
or wave soldering techniques. The straight lead version (IRFU series) is
for through-hole mounting applications. Power dissipation levels up to 1.5
watts are possible in typical surface mount applications.
I-Pak
D-Pak
IRLR2908PbF IRLU2908PbF
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
39
A
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V (See Fig. 9)
28
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Package Limited)
30
IDM
Pulsed Drain Current
150
PD @TC = 25°C
Maximum Power Dissipation
120
W
VGS
Linear Derating Factor
Gate-to-Source Voltage
0.77
± 16
W/°C
V
180
mJ
EAS
c
EAS (tested)
Single Pulse Avalanche Energy (Thermally Limited)
Single Pulse Avalanche Energy Tested Value
IAR
Avalanche Current
EAR
dv/dt
TJ
TSTG
i
c
See Fig.12a,12b,15,16
h
Peak Diode Recovery dv/dt e
A
mJ
V/ns
°C
2.3
-55 to + 175
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Parameter
RθJA
Junction-to-Case
Junction-to-Ambient (PCB Mount)
RθJA
Junction-to-Ambient
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250
Repetitive Avalanche Energy
Thermal Resistance
RθJC
d
j
300 (1.6mm from case )
Typ.
Max.
Units
–––
1.3
°C/W
–––
40
–––
110
1
10/01/10
IRLR/U2908PbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
80
–––
–––
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.085
–––
V/°C Reference to 25°C, ID = 1mA
RDS(on)
Static Drain-to-Source On-Resistance
–––
22.5
28
mΩ
–––
25
30
V
VGS = 0V, ID = 250µA
VGS = 10V, ID = 23A
VGS = 4.5V, ID = 20A
f
f
VGS(th)
Gate Threshold Voltage
1.0
–––
2.5
V
VDS = VGS, ID = 250µA
gfs
IDSS
Forward Transconductance
35
–––
–––
S
VDS = 25V, ID = 23A
Drain-to-Source Leakage Current
–––
–––
20
µA
VDS = 80V, VGS = 0V
–––
–––
250
–––
–––
200
nA
VGS = 16V
nC
ID = 23A
IGSS
Gate-to-Source Forward Leakage
VDS = 80V, VGS = 0V, TJ = 125°C
VGS = -16V
Gate-to-Source Reverse Leakage
–––
–––
-200
Qg
Total Gate Charge
–––
22
33
Qgs
Gate-to-Source Charge
–––
6.0
9.1
VDS = 64V
Qgd
Gate-to-Drain ("Miller") Charge
–––
11
17
VGS = 4.5V
td(on)
Turn-On Delay Time
–––
12
–––
tr
Rise Time
–––
95
–––
ID = 23A
td(off)
Turn-Off Delay Time
–––
36
–––
RG = 8.3Ω
tf
Fall Time
–––
55
–––
LD
Internal Drain Inductance
–––
4.5
–––
LS
Internal Source Inductance
–––
7.5
–––
6mm (0.25in.)
from package
and center of die contact
VGS = 0V
ns
VDD = 40V
VGS = 4.5V
nH
f
Between lead,
D
G
S
Ciss
Input Capacitance
–––
1890
–––
Coss
Output Capacitance
–––
260
–––
VDS = 25V
Crss
Reverse Transfer Capacitance
–––
35
–––
ƒ = 1.0MHz, See Fig. 5
Coss
Output Capacitance
–––
1920
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss
Output Capacitance
–––
170
–––
VGS = 0V, VDS = 64V, ƒ = 1.0MHz
Coss eff.
Effective Output Capacitance
–––
310
–––
VGS = 0V, VDS = 0V to 64V
pF
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
ISM
(Body Diode)
Pulsed Source Current
VSD
(Body Diode)
Diode Forward Voltage
–––
trr
Reverse Recovery Time
–––
Qrr
Reverse Recovery Charge
–––
ton
Forward Turn-On Time
c
–––
–––
39
D
150
showing the
integral reverse
–––
1.3
V
p-n junction diode.
TJ = 25°C, IS = 23A, VGS = 0V
75
110
ns
210
310
nC
A
–––
Conditions
MOSFET symbol
–––
G
TJ = 25°C, IF = 23A, VDD = 25V
di/dt = 100A/µs
S
f
f
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes through are on page 11
HEXFET® is a registered trademark of International Rectifier.
2
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IRLR/U2908PbF
1000
1000
100
BOTTOM
10
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
4.5V
4.0V
3.5V
3.0V
2.7V
2.5V
2.5V
1
0.1
100
BOTTOM
VGS
15V
10V
4.5V
4.0V
3.5V
3.0V
2.7V
2.5V
2.5V
10
1
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
0.1
0.01
0.01
0.1
1
10
0.01
100
1
10
100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
60
G FS , Forward Transconductance (S)
ID, Drain-to-Source Current (Α)
0.1
100
T J = 175°C
T J = 25°C
10
VDS = 25V
20µs PULSE WIDTH
1
2
3
4
VGS , Gate-to-Source Voltage (V)
5
TJ = 25°C
50
40
T J = 175°C
30
20
10
VDS = 10V
20µs PULSE WIDTH
0
0
10
20
30
40
50
60
ID, Drain-to-Source Current (A)
Fig 3. Typical Transfer Characteristics
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Fig 4. Typical Forward Transconductance
vs. Drain Current
3
IRLR/U2908PbF
100000
VGS , Gate-to-Source Voltage (V)
ID= 23A
Coss = Cds + Cgd
10000
C, Capacitance(pF)
5.0
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = Cgd
Ciss
1000
Coss
100
Crss
4.0
VDS= 16V
3.0
2.0
1.0
0.0
10
1
10
0
100
10
15
20
25
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
1000
100.00
ID, Drain-to-Source Current (A)
1000.00
ISD, Reverse Drain Current (A)
5
Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
T J = 25°C
1.00
VGS = 0V
0.10
0.2
0.4
0.6
0.8
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
T J = 175°C
10.00
1.0
1.2
1.4
1.6
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
VDS= 64V
VDS= 40V
1.8
100µsec
10
1msec
1
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRLR/U2908PbF
40
35
ID, Drain Current (A)
30
25
20
15
10
5
ID = 38A
2.5
VGS = 4.5V
2.0
(Normalized)
RDS(on) , Drain-to-Source On Resistance
3.0
0
1.5
1.0
0.5
0.0
25
50
75
100
125
150
175
-60 -40 -20 0
T C , Case Temperature (°C)
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Normalized On-Resistance
vs. Temperature
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.10
0.1
0.05
0.02
0.01
P DM
t1
0.01
SINGLE PULSE
( THERMAL RESPONSE )
t2
Notes:
1. Duty factor D =
2. Peak T
t1/ t 2
J = P DM x Z thJC
+T C
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLR/U2908PbF
DRIVER
L
VDS
D.U.T
RG
20V
VGS
+
V
- DD
IAS
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
400
15V
ID
9.3A
16A
BOTTOM 23A
TOP
300
200
100
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
QGS
QGD
2.5
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
VGS(th) Gate threshold Voltage (V)
10 V
2.0
1.5
ID = 250µA
1.0
0.5
-75 -50 -25
VGS
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage vs. Temperature
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IRLR/U2908PbF
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
100
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses
0.01
10
0.05
0.10
1
0.1
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
200
TOP
Single Pulse
BOTTOM 10% Duty Cycle
ID = 23A
150
100
50
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
vs. Temperature
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175
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRLR/U2908PbF
D.U.T
Driver Gate Drive
+
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D=
Period
P.W.
+
VDD
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
VDS
VGS
RG
RD
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRLR/U2908PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFR120
WIT H ASS EMBLY
LOT CODE 1234
ASS EMBLED ON WW 16, 2001
IN T HE AS SEMB LY LINE "A"
PART NUMBER
INT ERNAT IONAL
RECT IFIER
LOGO
Note: "P" in assembly line position
indicates "Lead-Free"
IRFR120
116A
12
34
AS SEMB LY
LOT CODE
DAT E CODE
YEAR 1 = 2001
WEEK 16
LINE A
"P" in assembly line position indicates
"Lead-Free" qualification to the cons umer-level
OR
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
IRFR120
12
AS SEMB LY
LOT CODE
34
DAT E CODE
P = DESIGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
P = DESIGNAT ES LEAD-FREE
PRODUCT QUALIFIED T O T HE
CONS UMER LEVEL (OPT IONAL)
YEAR 1 = 2001
WEEK 16
A = AS SEMB LY S IT E CODE
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
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9
IRLR/U2908PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
E XAMPLE: T HIS IS AN IRF U120
WIT H AS SEMBLY
LOT CODE 5678
ASS EMBLED ON WW 19, 2001
IN T HE AS SEMBLY LINE "A"
INT ERNAT IONAL
RE CT IF IER
LOGO
PART NUMBER
IRF U120
119A
56
78
ASSE MBLY
LOT CODE
Note: "P" in as s embly line pos ition
indicates Lead-Free"
DAT E CODE
YE AR 1 = 2001
WEEK 19
LINE A
OR
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
IRF U120
56
ASS EMBLY
LOT CODE
78
DAT E CODE
P = DESIGNAT ES LE AD-FREE
PRODUCT (OPT IONAL)
YEAR 1 = 2001
WEEK 19
A = ASS EMBLY SIT E CODE
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
10
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IRLR/U2908PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.71mH, RG = 25Ω, IAS = 23A, VGS =10V. Part not recommended for use above
this value.
ISD ≤ 23A, di/dt ≤ 400A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS .
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance.
This value determined from sample failure population. 100% tested to this value in production.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer
to application note #AN-994.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 10/2010
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11